atomic.h revision 334762
1/*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/i386/include/atomic.h 334762 2018-06-07 07:42:48Z hselasky $ 27 */ 28#ifndef _MACHINE_ATOMIC_H_ 29#define _MACHINE_ATOMIC_H_ 30 31#ifndef _SYS_CDEFS_H_ 32#error this file needs sys/cdefs.h as a prerequisite 33#endif 34 35#include <sys/atomic_common.h> 36 37#ifdef _KERNEL 38#include <machine/md_var.h> 39#include <machine/specialreg.h> 40#endif 41 42#ifndef __OFFSETOF_MONITORBUF 43/* 44 * __OFFSETOF_MONITORBUF == __pcpu_offset(pc_monitorbuf). 45 * 46 * The open-coded number is used instead of the symbolic expression to 47 * avoid a dependency on sys/pcpu.h in machine/atomic.h consumers. 48 * An assertion in i386/vm_machdep.c ensures that the value is correct. 49 */ 50#define __OFFSETOF_MONITORBUF 0x180 51 52static __inline void 53__mbk(void) 54{ 55 56 __asm __volatile("lock; addl $0,%%fs:%0" 57 : "+m" (*(u_int *)__OFFSETOF_MONITORBUF) : : "memory", "cc"); 58} 59 60static __inline void 61__mbu(void) 62{ 63 64 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory", "cc"); 65} 66#endif 67 68/* 69 * Various simple operations on memory, each of which is atomic in the 70 * presence of interrupts and multiple processors. 71 * 72 * atomic_set_char(P, V) (*(u_char *)(P) |= (V)) 73 * atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V)) 74 * atomic_add_char(P, V) (*(u_char *)(P) += (V)) 75 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V)) 76 * 77 * atomic_set_short(P, V) (*(u_short *)(P) |= (V)) 78 * atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V)) 79 * atomic_add_short(P, V) (*(u_short *)(P) += (V)) 80 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V)) 81 * 82 * atomic_set_int(P, V) (*(u_int *)(P) |= (V)) 83 * atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V)) 84 * atomic_add_int(P, V) (*(u_int *)(P) += (V)) 85 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V)) 86 * atomic_swap_int(P, V) (return (*(u_int *)(P)); *(u_int *)(P) = (V);) 87 * atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;) 88 * 89 * atomic_set_long(P, V) (*(u_long *)(P) |= (V)) 90 * atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V)) 91 * atomic_add_long(P, V) (*(u_long *)(P) += (V)) 92 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V)) 93 * atomic_swap_long(P, V) (return (*(u_long *)(P)); *(u_long *)(P) = (V);) 94 * atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;) 95 */ 96 97/* 98 * The above functions are expanded inline in the statically-linked 99 * kernel. Lock prefixes are generated if an SMP kernel is being 100 * built. 101 * 102 * Kernel modules call real functions which are built into the kernel. 103 * This allows kernel modules to be portable between UP and SMP systems. 104 */ 105#if defined(KLD_MODULE) || !defined(__GNUCLIKE_ASM) 106#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 107void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \ 108void atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 109 110int atomic_cmpset_char(volatile u_char *dst, u_char expect, u_char src); 111int atomic_cmpset_short(volatile u_short *dst, u_short expect, u_short src); 112int atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src); 113int atomic_fcmpset_char(volatile u_char *dst, u_char *expect, u_char src); 114int atomic_fcmpset_short(volatile u_short *dst, u_short *expect, 115 u_short src); 116int atomic_fcmpset_int(volatile u_int *dst, u_int *expect, u_int src); 117u_int atomic_fetchadd_int(volatile u_int *p, u_int v); 118int atomic_testandset_int(volatile u_int *p, u_int v); 119int atomic_testandclear_int(volatile u_int *p, u_int v); 120void atomic_thread_fence_acq(void); 121void atomic_thread_fence_acq_rel(void); 122void atomic_thread_fence_rel(void); 123void atomic_thread_fence_seq_cst(void); 124 125#define ATOMIC_LOAD(TYPE) \ 126u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p) 127#define ATOMIC_STORE(TYPE) \ 128void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 129 130int atomic_cmpset_64(volatile uint64_t *, uint64_t, uint64_t); 131uint64_t atomic_load_acq_64(volatile uint64_t *); 132void atomic_store_rel_64(volatile uint64_t *, uint64_t); 133uint64_t atomic_swap_64(volatile uint64_t *, uint64_t); 134uint64_t atomic_fetchadd_64(volatile uint64_t *, uint64_t); 135void atomic_add_64(volatile uint64_t *, uint64_t); 136void atomic_subtract_64(volatile uint64_t *, uint64_t); 137 138#else /* !KLD_MODULE && __GNUCLIKE_ASM */ 139 140/* 141 * For userland, always use lock prefixes so that the binaries will run 142 * on both SMP and !SMP systems. 143 */ 144#if defined(SMP) || !defined(_KERNEL) 145#define MPLOCKED "lock ; " 146#else 147#define MPLOCKED 148#endif 149 150/* 151 * The assembly is volatilized to avoid code chunk removal by the compiler. 152 * GCC aggressively reorders operations and memory clobbering is necessary 153 * in order to avoid that for memory barriers. 154 */ 155#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 156static __inline void \ 157atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 158{ \ 159 __asm __volatile(MPLOCKED OP \ 160 : "+m" (*p) \ 161 : CONS (V) \ 162 : "cc"); \ 163} \ 164 \ 165static __inline void \ 166atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 167{ \ 168 __asm __volatile(MPLOCKED OP \ 169 : "+m" (*p) \ 170 : CONS (V) \ 171 : "memory", "cc"); \ 172} \ 173struct __hack 174 175/* 176 * Atomic compare and set, used by the mutex functions. 177 * 178 * cmpset: 179 * if (*dst == expect) 180 * *dst = src 181 * 182 * fcmpset: 183 * if (*dst == *expect) 184 * *dst = src 185 * else 186 * *expect = *dst 187 * 188 * Returns 0 on failure, non-zero on success. 189 */ 190#define ATOMIC_CMPSET(TYPE, CONS) \ 191static __inline int \ 192atomic_cmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE expect, u_##TYPE src) \ 193{ \ 194 u_char res; \ 195 \ 196 __asm __volatile( \ 197 " " MPLOCKED " " \ 198 " cmpxchg %3,%1 ; " \ 199 " sete %0 ; " \ 200 "# atomic_cmpset_" #TYPE " " \ 201 : "=q" (res), /* 0 */ \ 202 "+m" (*dst), /* 1 */ \ 203 "+a" (expect) /* 2 */ \ 204 : CONS (src) /* 3 */ \ 205 : "memory", "cc"); \ 206 return (res); \ 207} \ 208 \ 209static __inline int \ 210atomic_fcmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE *expect, u_##TYPE src) \ 211{ \ 212 u_char res; \ 213 \ 214 __asm __volatile( \ 215 " " MPLOCKED " " \ 216 " cmpxchg %3,%1 ; " \ 217 " sete %0 ; " \ 218 "# atomic_fcmpset_" #TYPE " " \ 219 : "=q" (res), /* 0 */ \ 220 "+m" (*dst), /* 1 */ \ 221 "+a" (*expect) /* 2 */ \ 222 : CONS (src) /* 3 */ \ 223 : "memory", "cc"); \ 224 return (res); \ 225} 226 227ATOMIC_CMPSET(char, "q"); 228ATOMIC_CMPSET(short, "r"); 229ATOMIC_CMPSET(int, "r"); 230 231/* 232 * Atomically add the value of v to the integer pointed to by p and return 233 * the previous value of *p. 234 */ 235static __inline u_int 236atomic_fetchadd_int(volatile u_int *p, u_int v) 237{ 238 239 __asm __volatile( 240 " " MPLOCKED " " 241 " xaddl %0,%1 ; " 242 "# atomic_fetchadd_int" 243 : "+r" (v), /* 0 */ 244 "+m" (*p) /* 1 */ 245 : : "cc"); 246 return (v); 247} 248 249static __inline int 250atomic_testandset_int(volatile u_int *p, u_int v) 251{ 252 u_char res; 253 254 __asm __volatile( 255 " " MPLOCKED " " 256 " btsl %2,%1 ; " 257 " setc %0 ; " 258 "# atomic_testandset_int" 259 : "=q" (res), /* 0 */ 260 "+m" (*p) /* 1 */ 261 : "Ir" (v & 0x1f) /* 2 */ 262 : "cc"); 263 return (res); 264} 265 266static __inline int 267atomic_testandclear_int(volatile u_int *p, u_int v) 268{ 269 u_char res; 270 271 __asm __volatile( 272 " " MPLOCKED " " 273 " btrl %2,%1 ; " 274 " setc %0 ; " 275 "# atomic_testandclear_int" 276 : "=q" (res), /* 0 */ 277 "+m" (*p) /* 1 */ 278 : "Ir" (v & 0x1f) /* 2 */ 279 : "cc"); 280 return (res); 281} 282 283/* 284 * We assume that a = b will do atomic loads and stores. Due to the 285 * IA32 memory model, a simple store guarantees release semantics. 286 * 287 * However, a load may pass a store if they are performed on distinct 288 * addresses, so we need Store/Load barrier for sequentially 289 * consistent fences in SMP kernels. We use "lock addl $0,mem" for a 290 * Store/Load barrier, as recommended by the AMD Software Optimization 291 * Guide, and not mfence. In the kernel, we use a private per-cpu 292 * cache line for "mem", to avoid introducing false data 293 * dependencies. In user space, we use the word at the top of the 294 * stack. 295 * 296 * For UP kernels, however, the memory of the single processor is 297 * always consistent, so we only need to stop the compiler from 298 * reordering accesses in a way that violates the semantics of acquire 299 * and release. 300 */ 301 302#if defined(_KERNEL) 303#if defined(SMP) 304#define __storeload_barrier() __mbk() 305#else /* _KERNEL && UP */ 306#define __storeload_barrier() __compiler_membar() 307#endif /* SMP */ 308#else /* !_KERNEL */ 309#define __storeload_barrier() __mbu() 310#endif /* _KERNEL*/ 311 312#define ATOMIC_LOAD(TYPE) \ 313static __inline u_##TYPE \ 314atomic_load_acq_##TYPE(volatile u_##TYPE *p) \ 315{ \ 316 u_##TYPE res; \ 317 \ 318 res = *p; \ 319 __compiler_membar(); \ 320 return (res); \ 321} \ 322struct __hack 323 324#define ATOMIC_STORE(TYPE) \ 325static __inline void \ 326atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \ 327{ \ 328 \ 329 __compiler_membar(); \ 330 *p = v; \ 331} \ 332struct __hack 333 334static __inline void 335atomic_thread_fence_acq(void) 336{ 337 338 __compiler_membar(); 339} 340 341static __inline void 342atomic_thread_fence_rel(void) 343{ 344 345 __compiler_membar(); 346} 347 348static __inline void 349atomic_thread_fence_acq_rel(void) 350{ 351 352 __compiler_membar(); 353} 354 355static __inline void 356atomic_thread_fence_seq_cst(void) 357{ 358 359 __storeload_barrier(); 360} 361 362#ifdef _KERNEL 363 364#ifdef WANT_FUNCTIONS 365int atomic_cmpset_64_i386(volatile uint64_t *, uint64_t, uint64_t); 366int atomic_cmpset_64_i586(volatile uint64_t *, uint64_t, uint64_t); 367uint64_t atomic_load_acq_64_i386(volatile uint64_t *); 368uint64_t atomic_load_acq_64_i586(volatile uint64_t *); 369void atomic_store_rel_64_i386(volatile uint64_t *, uint64_t); 370void atomic_store_rel_64_i586(volatile uint64_t *, uint64_t); 371uint64_t atomic_swap_64_i386(volatile uint64_t *, uint64_t); 372uint64_t atomic_swap_64_i586(volatile uint64_t *, uint64_t); 373#endif 374 375/* I486 does not support SMP or CMPXCHG8B. */ 376static __inline int 377atomic_cmpset_64_i386(volatile uint64_t *dst, uint64_t expect, uint64_t src) 378{ 379 volatile uint32_t *p; 380 u_char res; 381 382 p = (volatile uint32_t *)dst; 383 __asm __volatile( 384 " pushfl ; " 385 " cli ; " 386 " xorl %1,%%eax ; " 387 " xorl %2,%%edx ; " 388 " orl %%edx,%%eax ; " 389 " jne 1f ; " 390 " movl %4,%1 ; " 391 " movl %5,%2 ; " 392 "1: " 393 " sete %3 ; " 394 " popfl" 395 : "+A" (expect), /* 0 */ 396 "+m" (*p), /* 1 */ 397 "+m" (*(p + 1)), /* 2 */ 398 "=q" (res) /* 3 */ 399 : "r" ((uint32_t)src), /* 4 */ 400 "r" ((uint32_t)(src >> 32)) /* 5 */ 401 : "memory", "cc"); 402 return (res); 403} 404 405static __inline uint64_t 406atomic_load_acq_64_i386(volatile uint64_t *p) 407{ 408 volatile uint32_t *q; 409 uint64_t res; 410 411 q = (volatile uint32_t *)p; 412 __asm __volatile( 413 " pushfl ; " 414 " cli ; " 415 " movl %1,%%eax ; " 416 " movl %2,%%edx ; " 417 " popfl" 418 : "=&A" (res) /* 0 */ 419 : "m" (*q), /* 1 */ 420 "m" (*(q + 1)) /* 2 */ 421 : "memory"); 422 return (res); 423} 424 425static __inline void 426atomic_store_rel_64_i386(volatile uint64_t *p, uint64_t v) 427{ 428 volatile uint32_t *q; 429 430 q = (volatile uint32_t *)p; 431 __asm __volatile( 432 " pushfl ; " 433 " cli ; " 434 " movl %%eax,%0 ; " 435 " movl %%edx,%1 ; " 436 " popfl" 437 : "=m" (*q), /* 0 */ 438 "=m" (*(q + 1)) /* 1 */ 439 : "A" (v) /* 2 */ 440 : "memory"); 441} 442 443static __inline uint64_t 444atomic_swap_64_i386(volatile uint64_t *p, uint64_t v) 445{ 446 volatile uint32_t *q; 447 uint64_t res; 448 449 q = (volatile uint32_t *)p; 450 __asm __volatile( 451 " pushfl ; " 452 " cli ; " 453 " movl %1,%%eax ; " 454 " movl %2,%%edx ; " 455 " movl %4,%2 ; " 456 " movl %3,%1 ; " 457 " popfl" 458 : "=&A" (res), /* 0 */ 459 "+m" (*q), /* 1 */ 460 "+m" (*(q + 1)) /* 2 */ 461 : "r" ((uint32_t)v), /* 3 */ 462 "r" ((uint32_t)(v >> 32))); /* 4 */ 463 return (res); 464} 465 466static __inline int 467atomic_cmpset_64_i586(volatile uint64_t *dst, uint64_t expect, uint64_t src) 468{ 469 u_char res; 470 471 __asm __volatile( 472 " " MPLOCKED " " 473 " cmpxchg8b %1 ; " 474 " sete %0" 475 : "=q" (res), /* 0 */ 476 "+m" (*dst), /* 1 */ 477 "+A" (expect) /* 2 */ 478 : "b" ((uint32_t)src), /* 3 */ 479 "c" ((uint32_t)(src >> 32)) /* 4 */ 480 : "memory", "cc"); 481 return (res); 482} 483 484static __inline uint64_t 485atomic_load_acq_64_i586(volatile uint64_t *p) 486{ 487 uint64_t res; 488 489 __asm __volatile( 490 " movl %%ebx,%%eax ; " 491 " movl %%ecx,%%edx ; " 492 " " MPLOCKED " " 493 " cmpxchg8b %1" 494 : "=&A" (res), /* 0 */ 495 "+m" (*p) /* 1 */ 496 : : "memory", "cc"); 497 return (res); 498} 499 500static __inline void 501atomic_store_rel_64_i586(volatile uint64_t *p, uint64_t v) 502{ 503 504 __asm __volatile( 505 " movl %%eax,%%ebx ; " 506 " movl %%edx,%%ecx ; " 507 "1: " 508 " " MPLOCKED " " 509 " cmpxchg8b %0 ; " 510 " jne 1b" 511 : "+m" (*p), /* 0 */ 512 "+A" (v) /* 1 */ 513 : : "ebx", "ecx", "memory", "cc"); 514} 515 516static __inline uint64_t 517atomic_swap_64_i586(volatile uint64_t *p, uint64_t v) 518{ 519 520 __asm __volatile( 521 " movl %%eax,%%ebx ; " 522 " movl %%edx,%%ecx ; " 523 "1: " 524 " " MPLOCKED " " 525 " cmpxchg8b %0 ; " 526 " jne 1b" 527 : "+m" (*p), /* 0 */ 528 "+A" (v) /* 1 */ 529 : : "ebx", "ecx", "memory", "cc"); 530 return (v); 531} 532 533static __inline int 534atomic_cmpset_64(volatile uint64_t *dst, uint64_t expect, uint64_t src) 535{ 536 537 if ((cpu_feature & CPUID_CX8) == 0) 538 return (atomic_cmpset_64_i386(dst, expect, src)); 539 else 540 return (atomic_cmpset_64_i586(dst, expect, src)); 541} 542 543static __inline uint64_t 544atomic_load_acq_64(volatile uint64_t *p) 545{ 546 547 if ((cpu_feature & CPUID_CX8) == 0) 548 return (atomic_load_acq_64_i386(p)); 549 else 550 return (atomic_load_acq_64_i586(p)); 551} 552 553static __inline void 554atomic_store_rel_64(volatile uint64_t *p, uint64_t v) 555{ 556 557 if ((cpu_feature & CPUID_CX8) == 0) 558 atomic_store_rel_64_i386(p, v); 559 else 560 atomic_store_rel_64_i586(p, v); 561} 562 563static __inline uint64_t 564atomic_swap_64(volatile uint64_t *p, uint64_t v) 565{ 566 567 if ((cpu_feature & CPUID_CX8) == 0) 568 return (atomic_swap_64_i386(p, v)); 569 else 570 return (atomic_swap_64_i586(p, v)); 571} 572 573static __inline uint64_t 574atomic_fetchadd_64(volatile uint64_t *p, uint64_t v) 575{ 576 577 for (;;) { 578 uint64_t t = *p; 579 if (atomic_cmpset_64(p, t, t + v)) 580 return (t); 581 } 582} 583 584static __inline void 585atomic_add_64(volatile uint64_t *p, uint64_t v) 586{ 587 uint64_t t; 588 589 for (;;) { 590 t = *p; 591 if (atomic_cmpset_64(p, t, t + v)) 592 break; 593 } 594} 595 596static __inline void 597atomic_subtract_64(volatile uint64_t *p, uint64_t v) 598{ 599 uint64_t t; 600 601 for (;;) { 602 t = *p; 603 if (atomic_cmpset_64(p, t, t - v)) 604 break; 605 } 606} 607 608#endif /* _KERNEL */ 609 610#endif /* KLD_MODULE || !__GNUCLIKE_ASM */ 611 612ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v); 613ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v); 614ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v); 615ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v); 616 617ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v); 618ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v); 619ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v); 620ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v); 621 622ATOMIC_ASM(set, int, "orl %1,%0", "ir", v); 623ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v); 624ATOMIC_ASM(add, int, "addl %1,%0", "ir", v); 625ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v); 626 627ATOMIC_ASM(set, long, "orl %1,%0", "ir", v); 628ATOMIC_ASM(clear, long, "andl %1,%0", "ir", ~v); 629ATOMIC_ASM(add, long, "addl %1,%0", "ir", v); 630ATOMIC_ASM(subtract, long, "subl %1,%0", "ir", v); 631 632#define ATOMIC_LOADSTORE(TYPE) \ 633 ATOMIC_LOAD(TYPE); \ 634 ATOMIC_STORE(TYPE) 635 636ATOMIC_LOADSTORE(char); 637ATOMIC_LOADSTORE(short); 638ATOMIC_LOADSTORE(int); 639ATOMIC_LOADSTORE(long); 640 641#undef ATOMIC_ASM 642#undef ATOMIC_LOAD 643#undef ATOMIC_STORE 644#undef ATOMIC_LOADSTORE 645 646#ifndef WANT_FUNCTIONS 647 648static __inline int 649atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src) 650{ 651 652 return (atomic_cmpset_int((volatile u_int *)dst, (u_int)expect, 653 (u_int)src)); 654} 655 656static __inline u_long 657atomic_fetchadd_long(volatile u_long *p, u_long v) 658{ 659 660 return (atomic_fetchadd_int((volatile u_int *)p, (u_int)v)); 661} 662 663static __inline int 664atomic_testandset_long(volatile u_long *p, u_int v) 665{ 666 667 return (atomic_testandset_int((volatile u_int *)p, v)); 668} 669 670static __inline int 671atomic_testandclear_long(volatile u_long *p, u_int v) 672{ 673 674 return (atomic_testandclear_int((volatile u_int *)p, v)); 675} 676 677/* Read the current value and store a new value in the destination. */ 678#ifdef __GNUCLIKE_ASM 679 680static __inline u_int 681atomic_swap_int(volatile u_int *p, u_int v) 682{ 683 684 __asm __volatile( 685 " xchgl %1,%0 ; " 686 "# atomic_swap_int" 687 : "+r" (v), /* 0 */ 688 "+m" (*p)); /* 1 */ 689 return (v); 690} 691 692static __inline u_long 693atomic_swap_long(volatile u_long *p, u_long v) 694{ 695 696 return (atomic_swap_int((volatile u_int *)p, (u_int)v)); 697} 698 699#else /* !__GNUCLIKE_ASM */ 700 701u_int atomic_swap_int(volatile u_int *p, u_int v); 702u_long atomic_swap_long(volatile u_long *p, u_long v); 703 704#endif /* __GNUCLIKE_ASM */ 705 706#define atomic_set_acq_char atomic_set_barr_char 707#define atomic_set_rel_char atomic_set_barr_char 708#define atomic_clear_acq_char atomic_clear_barr_char 709#define atomic_clear_rel_char atomic_clear_barr_char 710#define atomic_add_acq_char atomic_add_barr_char 711#define atomic_add_rel_char atomic_add_barr_char 712#define atomic_subtract_acq_char atomic_subtract_barr_char 713#define atomic_subtract_rel_char atomic_subtract_barr_char 714#define atomic_cmpset_acq_char atomic_cmpset_char 715#define atomic_cmpset_rel_char atomic_cmpset_char 716#define atomic_fcmpset_acq_char atomic_fcmpset_char 717#define atomic_fcmpset_rel_char atomic_fcmpset_char 718 719#define atomic_set_acq_short atomic_set_barr_short 720#define atomic_set_rel_short atomic_set_barr_short 721#define atomic_clear_acq_short atomic_clear_barr_short 722#define atomic_clear_rel_short atomic_clear_barr_short 723#define atomic_add_acq_short atomic_add_barr_short 724#define atomic_add_rel_short atomic_add_barr_short 725#define atomic_subtract_acq_short atomic_subtract_barr_short 726#define atomic_subtract_rel_short atomic_subtract_barr_short 727#define atomic_cmpset_acq_short atomic_cmpset_short 728#define atomic_cmpset_rel_short atomic_cmpset_short 729#define atomic_fcmpset_acq_short atomic_fcmpset_short 730#define atomic_fcmpset_rel_short atomic_fcmpset_short 731 732#define atomic_set_acq_int atomic_set_barr_int 733#define atomic_set_rel_int atomic_set_barr_int 734#define atomic_clear_acq_int atomic_clear_barr_int 735#define atomic_clear_rel_int atomic_clear_barr_int 736#define atomic_add_acq_int atomic_add_barr_int 737#define atomic_add_rel_int atomic_add_barr_int 738#define atomic_subtract_acq_int atomic_subtract_barr_int 739#define atomic_subtract_rel_int atomic_subtract_barr_int 740#define atomic_cmpset_acq_int atomic_cmpset_int 741#define atomic_cmpset_rel_int atomic_cmpset_int 742#define atomic_fcmpset_acq_int atomic_fcmpset_int 743#define atomic_fcmpset_rel_int atomic_fcmpset_int 744 745#define atomic_set_acq_long atomic_set_barr_long 746#define atomic_set_rel_long atomic_set_barr_long 747#define atomic_clear_acq_long atomic_clear_barr_long 748#define atomic_clear_rel_long atomic_clear_barr_long 749#define atomic_add_acq_long atomic_add_barr_long 750#define atomic_add_rel_long atomic_add_barr_long 751#define atomic_subtract_acq_long atomic_subtract_barr_long 752#define atomic_subtract_rel_long atomic_subtract_barr_long 753#define atomic_cmpset_acq_long atomic_cmpset_long 754#define atomic_cmpset_rel_long atomic_cmpset_long 755#define atomic_fcmpset_acq_long atomic_fcmpset_long 756#define atomic_fcmpset_rel_long atomic_fcmpset_long 757 758#define atomic_readandclear_int(p) atomic_swap_int(p, 0) 759#define atomic_readandclear_long(p) atomic_swap_long(p, 0) 760 761/* Operations on 8-bit bytes. */ 762#define atomic_set_8 atomic_set_char 763#define atomic_set_acq_8 atomic_set_acq_char 764#define atomic_set_rel_8 atomic_set_rel_char 765#define atomic_clear_8 atomic_clear_char 766#define atomic_clear_acq_8 atomic_clear_acq_char 767#define atomic_clear_rel_8 atomic_clear_rel_char 768#define atomic_add_8 atomic_add_char 769#define atomic_add_acq_8 atomic_add_acq_char 770#define atomic_add_rel_8 atomic_add_rel_char 771#define atomic_subtract_8 atomic_subtract_char 772#define atomic_subtract_acq_8 atomic_subtract_acq_char 773#define atomic_subtract_rel_8 atomic_subtract_rel_char 774#define atomic_load_acq_8 atomic_load_acq_char 775#define atomic_store_rel_8 atomic_store_rel_char 776#define atomic_cmpset_8 atomic_cmpset_char 777#define atomic_cmpset_acq_8 atomic_cmpset_acq_char 778#define atomic_cmpset_rel_8 atomic_cmpset_rel_char 779#define atomic_fcmpset_8 atomic_fcmpset_char 780#define atomic_fcmpset_acq_8 atomic_fcmpset_acq_char 781#define atomic_fcmpset_rel_8 atomic_fcmpset_rel_char 782 783/* Operations on 16-bit words. */ 784#define atomic_set_16 atomic_set_short 785#define atomic_set_acq_16 atomic_set_acq_short 786#define atomic_set_rel_16 atomic_set_rel_short 787#define atomic_clear_16 atomic_clear_short 788#define atomic_clear_acq_16 atomic_clear_acq_short 789#define atomic_clear_rel_16 atomic_clear_rel_short 790#define atomic_add_16 atomic_add_short 791#define atomic_add_acq_16 atomic_add_acq_short 792#define atomic_add_rel_16 atomic_add_rel_short 793#define atomic_subtract_16 atomic_subtract_short 794#define atomic_subtract_acq_16 atomic_subtract_acq_short 795#define atomic_subtract_rel_16 atomic_subtract_rel_short 796#define atomic_load_acq_16 atomic_load_acq_short 797#define atomic_store_rel_16 atomic_store_rel_short 798#define atomic_cmpset_16 atomic_cmpset_short 799#define atomic_cmpset_acq_16 atomic_cmpset_acq_short 800#define atomic_cmpset_rel_16 atomic_cmpset_rel_short 801#define atomic_fcmpset_16 atomic_fcmpset_short 802#define atomic_fcmpset_acq_16 atomic_fcmpset_acq_short 803#define atomic_fcmpset_rel_16 atomic_fcmpset_rel_short 804 805/* Operations on 32-bit double words. */ 806#define atomic_set_32 atomic_set_int 807#define atomic_set_acq_32 atomic_set_acq_int 808#define atomic_set_rel_32 atomic_set_rel_int 809#define atomic_clear_32 atomic_clear_int 810#define atomic_clear_acq_32 atomic_clear_acq_int 811#define atomic_clear_rel_32 atomic_clear_rel_int 812#define atomic_add_32 atomic_add_int 813#define atomic_add_acq_32 atomic_add_acq_int 814#define atomic_add_rel_32 atomic_add_rel_int 815#define atomic_subtract_32 atomic_subtract_int 816#define atomic_subtract_acq_32 atomic_subtract_acq_int 817#define atomic_subtract_rel_32 atomic_subtract_rel_int 818#define atomic_load_acq_32 atomic_load_acq_int 819#define atomic_store_rel_32 atomic_store_rel_int 820#define atomic_cmpset_32 atomic_cmpset_int 821#define atomic_cmpset_acq_32 atomic_cmpset_acq_int 822#define atomic_cmpset_rel_32 atomic_cmpset_rel_int 823#define atomic_fcmpset_32 atomic_fcmpset_int 824#define atomic_fcmpset_acq_32 atomic_fcmpset_acq_int 825#define atomic_fcmpset_rel_32 atomic_fcmpset_rel_int 826#define atomic_swap_32 atomic_swap_int 827#define atomic_readandclear_32 atomic_readandclear_int 828#define atomic_fetchadd_32 atomic_fetchadd_int 829#define atomic_testandset_32 atomic_testandset_int 830#define atomic_testandclear_32 atomic_testandclear_int 831 832/* Operations on 64-bit quad words. */ 833#define atomic_cmpset_acq_64 atomic_cmpset_64 834#define atomic_cmpset_rel_64 atomic_cmpset_64 835#define atomic_fetchadd_acq_64 atomic_fetchadd_64 836#define atomic_fetchadd_rel_64 atomic_fetchadd_64 837#define atomic_add_acq_64 atomic_add_64 838#define atomic_add_rel_64 atomic_add_64 839#define atomic_subtract_acq_64 atomic_subtract_64 840#define atomic_subtract_rel_64 atomic_subtract_64 841 842/* Operations on pointers. */ 843#define atomic_set_ptr(p, v) \ 844 atomic_set_int((volatile u_int *)(p), (u_int)(v)) 845#define atomic_set_acq_ptr(p, v) \ 846 atomic_set_acq_int((volatile u_int *)(p), (u_int)(v)) 847#define atomic_set_rel_ptr(p, v) \ 848 atomic_set_rel_int((volatile u_int *)(p), (u_int)(v)) 849#define atomic_clear_ptr(p, v) \ 850 atomic_clear_int((volatile u_int *)(p), (u_int)(v)) 851#define atomic_clear_acq_ptr(p, v) \ 852 atomic_clear_acq_int((volatile u_int *)(p), (u_int)(v)) 853#define atomic_clear_rel_ptr(p, v) \ 854 atomic_clear_rel_int((volatile u_int *)(p), (u_int)(v)) 855#define atomic_add_ptr(p, v) \ 856 atomic_add_int((volatile u_int *)(p), (u_int)(v)) 857#define atomic_add_acq_ptr(p, v) \ 858 atomic_add_acq_int((volatile u_int *)(p), (u_int)(v)) 859#define atomic_add_rel_ptr(p, v) \ 860 atomic_add_rel_int((volatile u_int *)(p), (u_int)(v)) 861#define atomic_subtract_ptr(p, v) \ 862 atomic_subtract_int((volatile u_int *)(p), (u_int)(v)) 863#define atomic_subtract_acq_ptr(p, v) \ 864 atomic_subtract_acq_int((volatile u_int *)(p), (u_int)(v)) 865#define atomic_subtract_rel_ptr(p, v) \ 866 atomic_subtract_rel_int((volatile u_int *)(p), (u_int)(v)) 867#define atomic_load_acq_ptr(p) \ 868 atomic_load_acq_int((volatile u_int *)(p)) 869#define atomic_store_rel_ptr(p, v) \ 870 atomic_store_rel_int((volatile u_int *)(p), (v)) 871#define atomic_cmpset_ptr(dst, old, new) \ 872 atomic_cmpset_int((volatile u_int *)(dst), (u_int)(old), (u_int)(new)) 873#define atomic_cmpset_acq_ptr(dst, old, new) \ 874 atomic_cmpset_acq_int((volatile u_int *)(dst), (u_int)(old), \ 875 (u_int)(new)) 876#define atomic_cmpset_rel_ptr(dst, old, new) \ 877 atomic_cmpset_rel_int((volatile u_int *)(dst), (u_int)(old), \ 878 (u_int)(new)) 879#define atomic_fcmpset_ptr(dst, old, new) \ 880 atomic_fcmpset_int((volatile u_int *)(dst), (u_int *)(old), (u_int)(new)) 881#define atomic_fcmpset_acq_ptr(dst, old, new) \ 882 atomic_fcmpset_acq_int((volatile u_int *)(dst), (u_int *)(old), \ 883 (u_int)(new)) 884#define atomic_fcmpset_rel_ptr(dst, old, new) \ 885 atomic_fcmpset_rel_int((volatile u_int *)(dst), (u_int *)(old), \ 886 (u_int)(new)) 887#define atomic_swap_ptr(p, v) \ 888 atomic_swap_int((volatile u_int *)(p), (u_int)(v)) 889#define atomic_readandclear_ptr(p) \ 890 atomic_readandclear_int((volatile u_int *)(p)) 891 892#endif /* !WANT_FUNCTIONS */ 893 894#if defined(_KERNEL) 895#define mb() __mbk() 896#define wmb() __mbk() 897#define rmb() __mbk() 898#else 899#define mb() __mbu() 900#define wmb() __mbu() 901#define rmb() __mbu() 902#endif 903 904#endif /* !_MACHINE_ATOMIC_H_ */ 905