pmap.c revision 338419
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/11/sys/i386/i386/pmap.c 338419 2018-09-01 09:59:46Z kib $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_apic.h" 100#include "opt_cpu.h" 101#include "opt_pmap.h" 102#include "opt_smp.h" 103#include "opt_vm.h" 104#include "opt_xbox.h" 105 106#include <sys/param.h> 107#include <sys/systm.h> 108#include <sys/kernel.h> 109#include <sys/ktr.h> 110#include <sys/lock.h> 111#include <sys/malloc.h> 112#include <sys/mman.h> 113#include <sys/msgbuf.h> 114#include <sys/mutex.h> 115#include <sys/proc.h> 116#include <sys/rwlock.h> 117#include <sys/sf_buf.h> 118#include <sys/sx.h> 119#include <sys/vmmeter.h> 120#include <sys/sched.h> 121#include <sys/sysctl.h> 122#include <sys/smp.h> 123 124#include <vm/vm.h> 125#include <vm/vm_param.h> 126#include <vm/vm_kern.h> 127#include <vm/vm_page.h> 128#include <vm/vm_map.h> 129#include <vm/vm_object.h> 130#include <vm/vm_extern.h> 131#include <vm/vm_pageout.h> 132#include <vm/vm_pager.h> 133#include <vm/vm_phys.h> 134#include <vm/vm_radix.h> 135#include <vm/vm_reserv.h> 136#include <vm/uma.h> 137 138#ifdef DEV_APIC 139#include <sys/bus.h> 140#include <machine/intr_machdep.h> 141#include <x86/apicvar.h> 142#endif 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#ifndef PMAP_SHPGPERPROC 157#define PMAP_SHPGPERPROC 200 158#endif 159 160#if !defined(DIAGNOSTIC) 161#ifdef __GNUC_GNU_INLINE__ 162#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 163#else 164#define PMAP_INLINE extern inline 165#endif 166#else 167#define PMAP_INLINE 168#endif 169 170#ifdef PV_STATS 171#define PV_STAT(x) do { x ; } while (0) 172#else 173#define PV_STAT(x) do { } while (0) 174#endif 175 176#define pa_index(pa) ((pa) >> PDRSHIFT) 177#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 178 179/* 180 * Get PDEs and PTEs for user/kernel address space 181 */ 182#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 183#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 184 185#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 186#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 187#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 188#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 189#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 190 191#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 192 atomic_clear_int((u_int *)(pte), PG_W)) 193#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 194 195struct pmap kernel_pmap_store; 196LIST_HEAD(pmaplist, pmap); 197static struct pmaplist allpmaps; 198static struct mtx allpmaps_lock; 199 200vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 201vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 202int pgeflag = 0; /* PG_G or-in */ 203int pseflag = 0; /* PG_PS or-in */ 204 205static int nkpt = NKPT; 206vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 207extern u_int32_t KERNend; 208extern u_int32_t KPTphys; 209 210#if defined(PAE) || defined(PAE_TABLES) 211pt_entry_t pg_nx; 212static uma_zone_t pdptzone; 213#endif 214 215static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 216 217static int pat_works = 1; 218SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1, 219 "Is page attribute table fully functional?"); 220 221static int pg_ps_enabled = 1; 222SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 223 &pg_ps_enabled, 0, "Are large page mappings enabled?"); 224 225#define PAT_INDEX_SIZE 8 226static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 227 228/* 229 * pmap_mapdev support pre initialization (i.e. console) 230 */ 231#define PMAP_PREINIT_MAPPING_COUNT 8 232static struct pmap_preinit_mapping { 233 vm_paddr_t pa; 234 vm_offset_t va; 235 vm_size_t sz; 236 int mode; 237} pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 238static int pmap_initialized; 239 240static struct rwlock_padalign pvh_global_lock; 241 242/* 243 * Data for the pv entry allocation mechanism 244 */ 245static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 246static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 247static struct md_page *pv_table; 248static int shpgperproc = PMAP_SHPGPERPROC; 249 250struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 251int pv_maxchunks; /* How many chunks we have KVA for */ 252vm_offset_t pv_vafree; /* freelist stored in the PTE */ 253 254/* 255 * All those kernel PT submaps that BSD is so fond of 256 */ 257pt_entry_t *CMAP3; 258static pd_entry_t *KPTD; 259caddr_t ptvmmap = 0; 260caddr_t CADDR3; 261struct msgbuf *msgbufp = NULL; 262 263/* 264 * Crashdump maps. 265 */ 266static caddr_t crashdumpmap; 267 268static pt_entry_t *PMAP1 = NULL, *PMAP2; 269static pt_entry_t *PADDR1 = NULL, *PADDR2; 270#ifdef SMP 271static int PMAP1cpu; 272static int PMAP1changedcpu; 273SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 274 &PMAP1changedcpu, 0, 275 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 276#endif 277static int PMAP1changed; 278SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 279 &PMAP1changed, 0, 280 "Number of times pmap_pte_quick changed PMAP1"); 281static int PMAP1unchanged; 282SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 283 &PMAP1unchanged, 0, 284 "Number of times pmap_pte_quick didn't change PMAP1"); 285static struct mtx PMAP2mutex; 286 287int pti; 288 289static void free_pv_chunk(struct pv_chunk *pc); 290static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 291static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 292static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 293static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 294#if VM_NRESERVLEVEL > 0 295static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 296#endif 297static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 298static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 299 vm_offset_t va); 300static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 301 302static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 303static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 304 vm_prot_t prot); 305static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 306 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 307static void pmap_flush_page(vm_page_t m); 308static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 309static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, 310 pd_entry_t pde); 311static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 312static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 313static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 314static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 315static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 316static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 317#if VM_NRESERVLEVEL > 0 318static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 319#endif 320static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 321 vm_prot_t prot); 322static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 323static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 324 struct spglist *free); 325static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 326 struct spglist *free); 327static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va); 328static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 329 struct spglist *free); 330static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 331 vm_offset_t va); 332static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 333static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 334 vm_page_t m); 335static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 336 pd_entry_t newpde); 337static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 338 339static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 340 341static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags); 342static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free); 343static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 344static void pmap_pte_release(pt_entry_t *pte); 345static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *); 346#if defined(PAE) || defined(PAE_TABLES) 347static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 348 int wait); 349#endif 350static void pmap_set_pg(void); 351 352static __inline void pagezero(void *page); 353 354CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 355CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 356 357/* 358 * If you get an error here, then you set KVA_PAGES wrong! See the 359 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 360 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 361 */ 362CTASSERT(KERNBASE % (1 << 24) == 0); 363 364/* 365 * Bootstrap the system enough to run with virtual memory. 366 * 367 * On the i386 this is called after mapping has already been enabled 368 * and just syncs the pmap module with what has already been done. 369 * [We can't call it easily with mapping off since the kernel is not 370 * mapped with PA == VA, hence we would have to relocate every address 371 * from the linked base (virtual) address "KERNBASE" to the actual 372 * (physical) address starting relative to 0] 373 */ 374void 375pmap_bootstrap(vm_paddr_t firstaddr) 376{ 377 vm_offset_t va; 378 pt_entry_t *pte, *unused; 379 struct pcpu *pc; 380 int i; 381 382 /* 383 * Add a physical memory segment (vm_phys_seg) corresponding to the 384 * preallocated kernel page table pages so that vm_page structures 385 * representing these pages will be created. The vm_page structures 386 * are required for promotion of the corresponding kernel virtual 387 * addresses to superpage mappings. 388 */ 389 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt)); 390 391 /* 392 * Initialize the first available kernel virtual address. However, 393 * using "firstaddr" may waste a few pages of the kernel virtual 394 * address space, because locore may not have mapped every physical 395 * page that it allocated. Preferably, locore would provide a first 396 * unused virtual address in addition to "firstaddr". 397 */ 398 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 399 400 virtual_end = VM_MAX_KERNEL_ADDRESS; 401 402 /* 403 * Initialize the kernel pmap (which is statically allocated). 404 */ 405 PMAP_LOCK_INIT(kernel_pmap); 406 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 407#if defined(PAE) || defined(PAE_TABLES) 408 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 409#endif 410 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 411 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 412 413 /* 414 * Initialize the global pv list lock. 415 */ 416 rw_init(&pvh_global_lock, "pmap pv global"); 417 418 LIST_INIT(&allpmaps); 419 420 /* 421 * Request a spin mutex so that changes to allpmaps cannot be 422 * preempted by smp_rendezvous_cpus(). Otherwise, 423 * pmap_update_pde_kernel() could access allpmaps while it is 424 * being changed. 425 */ 426 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 427 mtx_lock_spin(&allpmaps_lock); 428 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 429 mtx_unlock_spin(&allpmaps_lock); 430 431 /* 432 * Reserve some special page table entries/VA space for temporary 433 * mapping of pages. 434 */ 435#define SYSMAP(c, p, v, n) \ 436 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 437 438 va = virtual_avail; 439 pte = vtopte(va); 440 441 442 /* 443 * Initialize temporary map objects on the current CPU for use 444 * during early boot. 445 * CMAP1/CMAP2 are used for zeroing and copying pages. 446 * CMAP3 is used for the idle process page zeroing. 447 */ 448 pc = get_pcpu(); 449 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 450 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1) 451 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1) 452 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1) 453 454 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 455 456 /* 457 * Crashdump maps. 458 */ 459 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 460 461 /* 462 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 463 */ 464 SYSMAP(caddr_t, unused, ptvmmap, 1) 465 466 /* 467 * msgbufp is used to map the system message buffer. 468 */ 469 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 470 471 /* 472 * KPTmap is used by pmap_kextract(). 473 * 474 * KPTmap is first initialized by locore. However, that initial 475 * KPTmap can only support NKPT page table pages. Here, a larger 476 * KPTmap is created that can support KVA_PAGES page table pages. 477 */ 478 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 479 480 for (i = 0; i < NKPT; i++) 481 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 482 483 /* 484 * Adjust the start of the KPTD and KPTmap so that the implementation 485 * of pmap_kextract() and pmap_growkernel() can be made simpler. 486 */ 487 KPTD -= KPTDI; 488 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 489 490 /* 491 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 492 * respectively. 493 */ 494 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 495 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 496 497 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 498 499 virtual_avail = va; 500 501 /* 502 * Leave in place an identity mapping (virt == phys) for the low 1 MB 503 * physical memory region that is used by the ACPI wakeup code. This 504 * mapping must not have PG_G set. 505 */ 506#ifdef XBOX 507 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 508 * an early stadium, we cannot yet neatly map video memory ... :-( 509 * Better fixes are very welcome! */ 510 if (!arch_i386_is_xbox) 511#endif 512 for (i = 1; i < NKPT; i++) 513 PTD[i] = 0; 514 515 /* 516 * Initialize the PAT MSR if present. 517 * pmap_init_pat() clears and sets CR4_PGE, which, as a 518 * side-effect, invalidates stale PG_G TLB entries that might 519 * have been created in our pre-boot environment. We assume 520 * that PAT support implies PGE and in reverse, PGE presence 521 * comes with PAT. Both features were added for Pentium Pro. 522 */ 523 pmap_init_pat(); 524 525 /* Turn on PG_G on kernel page(s) */ 526 pmap_set_pg(); 527} 528 529static void 530pmap_init_reserved_pages(void) 531{ 532 struct pcpu *pc; 533 vm_offset_t pages; 534 int i; 535 536 CPU_FOREACH(i) { 537 pc = pcpu_find(i); 538 /* 539 * Skip if the mapping has already been initialized, 540 * i.e. this is the BSP. 541 */ 542 if (pc->pc_cmap_addr1 != 0) 543 continue; 544 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 545 pages = kva_alloc(PAGE_SIZE * 3); 546 if (pages == 0) 547 panic("%s: unable to allocate KVA", __func__); 548 pc->pc_cmap_pte1 = vtopte(pages); 549 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE); 550 pc->pc_cmap_addr1 = (caddr_t)pages; 551 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE); 552 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2); 553 } 554} 555 556SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL); 557 558/* 559 * Setup the PAT MSR. 560 */ 561void 562pmap_init_pat(void) 563{ 564 int pat_table[PAT_INDEX_SIZE]; 565 uint64_t pat_msr; 566 u_long cr0, cr4; 567 int i; 568 569 /* Set default PAT index table. */ 570 for (i = 0; i < PAT_INDEX_SIZE; i++) 571 pat_table[i] = -1; 572 pat_table[PAT_WRITE_BACK] = 0; 573 pat_table[PAT_WRITE_THROUGH] = 1; 574 pat_table[PAT_UNCACHEABLE] = 3; 575 pat_table[PAT_WRITE_COMBINING] = 3; 576 pat_table[PAT_WRITE_PROTECTED] = 3; 577 pat_table[PAT_UNCACHED] = 3; 578 579 /* 580 * Bail if this CPU doesn't implement PAT. 581 * We assume that PAT support implies PGE. 582 */ 583 if ((cpu_feature & CPUID_PAT) == 0) { 584 for (i = 0; i < PAT_INDEX_SIZE; i++) 585 pat_index[i] = pat_table[i]; 586 pat_works = 0; 587 return; 588 } 589 590 /* 591 * Due to some Intel errata, we can only safely use the lower 4 592 * PAT entries. 593 * 594 * Intel Pentium III Processor Specification Update 595 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 596 * or Mode C Paging) 597 * 598 * Intel Pentium IV Processor Specification Update 599 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 600 */ 601 if (cpu_vendor_id == CPU_VENDOR_INTEL && 602 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) 603 pat_works = 0; 604 605 /* Initialize default PAT entries. */ 606 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 607 PAT_VALUE(1, PAT_WRITE_THROUGH) | 608 PAT_VALUE(2, PAT_UNCACHED) | 609 PAT_VALUE(3, PAT_UNCACHEABLE) | 610 PAT_VALUE(4, PAT_WRITE_BACK) | 611 PAT_VALUE(5, PAT_WRITE_THROUGH) | 612 PAT_VALUE(6, PAT_UNCACHED) | 613 PAT_VALUE(7, PAT_UNCACHEABLE); 614 615 if (pat_works) { 616 /* 617 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 618 * Program 5 and 6 as WP and WC. 619 * Leave 4 and 7 as WB and UC. 620 */ 621 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 622 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 623 PAT_VALUE(6, PAT_WRITE_COMBINING); 624 pat_table[PAT_UNCACHED] = 2; 625 pat_table[PAT_WRITE_PROTECTED] = 5; 626 pat_table[PAT_WRITE_COMBINING] = 6; 627 } else { 628 /* 629 * Just replace PAT Index 2 with WC instead of UC-. 630 */ 631 pat_msr &= ~PAT_MASK(2); 632 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 633 pat_table[PAT_WRITE_COMBINING] = 2; 634 } 635 636 /* Disable PGE. */ 637 cr4 = rcr4(); 638 load_cr4(cr4 & ~CR4_PGE); 639 640 /* Disable caches (CD = 1, NW = 0). */ 641 cr0 = rcr0(); 642 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 643 644 /* Flushes caches and TLBs. */ 645 wbinvd(); 646 invltlb(); 647 648 /* Update PAT and index table. */ 649 wrmsr(MSR_PAT, pat_msr); 650 for (i = 0; i < PAT_INDEX_SIZE; i++) 651 pat_index[i] = pat_table[i]; 652 653 /* Flush caches and TLBs again. */ 654 wbinvd(); 655 invltlb(); 656 657 /* Restore caches and PGE. */ 658 load_cr0(cr0); 659 load_cr4(cr4); 660} 661 662/* 663 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 664 */ 665static void 666pmap_set_pg(void) 667{ 668 pt_entry_t *pte; 669 vm_offset_t va, endva; 670 671 if (pgeflag == 0) 672 return; 673 674 endva = KERNBASE + KERNend; 675 676 if (pseflag) { 677 va = KERNBASE + KERNLOAD; 678 while (va < endva) { 679 pdir_pde(PTD, va) |= pgeflag; 680 invltlb(); /* Flush non-PG_G entries. */ 681 va += NBPDR; 682 } 683 } else { 684 va = (vm_offset_t)btext; 685 while (va < endva) { 686 pte = vtopte(va); 687 if (*pte) 688 *pte |= pgeflag; 689 invltlb(); /* Flush non-PG_G entries. */ 690 va += PAGE_SIZE; 691 } 692 } 693} 694 695/* 696 * Initialize a vm_page's machine-dependent fields. 697 */ 698void 699pmap_page_init(vm_page_t m) 700{ 701 702 TAILQ_INIT(&m->md.pv_list); 703 m->md.pat_mode = PAT_WRITE_BACK; 704} 705 706#if defined(PAE) || defined(PAE_TABLES) 707static void * 708pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait) 709{ 710 711 /* Inform UMA that this allocator uses kernel_map/object. */ 712 *flags = UMA_SLAB_KERNEL; 713 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL, 714 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 715} 716#endif 717 718/* 719 * Abuse the pte nodes for unmapped kva to thread a kva freelist through. 720 * Requirements: 721 * - Must deal with pages in order to ensure that none of the PG_* bits 722 * are ever set, PG_V in particular. 723 * - Assumes we can write to ptes without pte_store() atomic ops, even 724 * on PAE systems. This should be ok. 725 * - Assumes nothing will ever test these addresses for 0 to indicate 726 * no mapping instead of correctly checking PG_V. 727 * - Assumes a vm_offset_t will fit in a pte (true for i386). 728 * Because PG_V is never set, there can be no mappings to invalidate. 729 */ 730static vm_offset_t 731pmap_ptelist_alloc(vm_offset_t *head) 732{ 733 pt_entry_t *pte; 734 vm_offset_t va; 735 736 va = *head; 737 if (va == 0) 738 panic("pmap_ptelist_alloc: exhausted ptelist KVA"); 739 pte = vtopte(va); 740 *head = *pte; 741 if (*head & PG_V) 742 panic("pmap_ptelist_alloc: va with PG_V set!"); 743 *pte = 0; 744 return (va); 745} 746 747static void 748pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 749{ 750 pt_entry_t *pte; 751 752 if (va & PG_V) 753 panic("pmap_ptelist_free: freeing va with PG_V set!"); 754 pte = vtopte(va); 755 *pte = *head; /* virtual! PG_V is 0 though */ 756 *head = va; 757} 758 759static void 760pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 761{ 762 int i; 763 vm_offset_t va; 764 765 *head = 0; 766 for (i = npages - 1; i >= 0; i--) { 767 va = (vm_offset_t)base + i * PAGE_SIZE; 768 pmap_ptelist_free(head, va); 769 } 770} 771 772 773/* 774 * Initialize the pmap module. 775 * Called by vm_init, to initialize any structures that the pmap 776 * system needs to map virtual memory. 777 */ 778void 779pmap_init(void) 780{ 781 struct pmap_preinit_mapping *ppim; 782 vm_page_t mpte; 783 vm_size_t s; 784 int i, pv_npg; 785 786 /* 787 * Initialize the vm page array entries for the kernel pmap's 788 * page table pages. 789 */ 790 PMAP_LOCK(kernel_pmap); 791 for (i = 0; i < NKPT; i++) { 792 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 793 KASSERT(mpte >= vm_page_array && 794 mpte < &vm_page_array[vm_page_array_size], 795 ("pmap_init: page table page is out of range")); 796 mpte->pindex = i + KPTDI; 797 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 798 mpte->wire_count = 1; 799 if (pseflag != 0 && 800 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend && 801 pmap_insert_pt_page(kernel_pmap, mpte)) 802 panic("pmap_init: pmap_insert_pt_page failed"); 803 } 804 PMAP_UNLOCK(kernel_pmap); 805 atomic_add_int(&vm_cnt.v_wire_count, NKPT); 806 807 /* 808 * Initialize the address space (zone) for the pv entries. Set a 809 * high water mark so that the system can recover from excessive 810 * numbers of pv entries. 811 */ 812 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 813 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 814 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 815 pv_entry_max = roundup(pv_entry_max, _NPCPV); 816 pv_entry_high_water = 9 * (pv_entry_max / 10); 817 818 /* 819 * If the kernel is running on a virtual machine, then it must assume 820 * that MCA is enabled by the hypervisor. Moreover, the kernel must 821 * be prepared for the hypervisor changing the vendor and family that 822 * are reported by CPUID. Consequently, the workaround for AMD Family 823 * 10h Erratum 383 is enabled if the processor's feature set does not 824 * include at least one feature that is only supported by older Intel 825 * or newer AMD processors. 826 */ 827 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 && 828 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 829 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 830 AMDID2_FMA4)) == 0) 831 workaround_erratum383 = 1; 832 833 /* 834 * Are large page mappings supported and enabled? 835 */ 836 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 837 if (pseflag == 0) 838 pg_ps_enabled = 0; 839 else if (pg_ps_enabled) { 840 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 841 ("pmap_init: can't assign to pagesizes[1]")); 842 pagesizes[1] = NBPDR; 843 } 844 845 /* 846 * Calculate the size of the pv head table for superpages. 847 * Handle the possibility that "vm_phys_segs[...].end" is zero. 848 */ 849 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end - 850 PAGE_SIZE) / NBPDR + 1; 851 852 /* 853 * Allocate memory for the pv head table for superpages. 854 */ 855 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 856 s = round_page(s); 857 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 858 M_WAITOK | M_ZERO); 859 for (i = 0; i < pv_npg; i++) 860 TAILQ_INIT(&pv_table[i].pv_list); 861 862 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 863 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 864 if (pv_chunkbase == NULL) 865 panic("pmap_init: not enough kvm for pv chunks"); 866 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 867#if defined(PAE) || defined(PAE_TABLES) 868 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 869 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 870 UMA_ZONE_VM | UMA_ZONE_NOFREE); 871 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 872#endif 873 874 pmap_initialized = 1; 875 if (!bootverbose) 876 return; 877 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 878 ppim = pmap_preinit_mapping + i; 879 if (ppim->va == 0) 880 continue; 881 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i, 882 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode); 883 } 884} 885 886 887SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 888 "Max number of PV entries"); 889SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 890 "Page share factor per proc"); 891 892static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 893 "2/4MB page mapping counters"); 894 895static u_long pmap_pde_demotions; 896SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 897 &pmap_pde_demotions, 0, "2/4MB page demotions"); 898 899static u_long pmap_pde_mappings; 900SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 901 &pmap_pde_mappings, 0, "2/4MB page mappings"); 902 903static u_long pmap_pde_p_failures; 904SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 905 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 906 907static u_long pmap_pde_promotions; 908SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 909 &pmap_pde_promotions, 0, "2/4MB page promotions"); 910 911/*************************************************** 912 * Low level helper routines..... 913 ***************************************************/ 914 915/* 916 * Determine the appropriate bits to set in a PTE or PDE for a specified 917 * caching mode. 918 */ 919int 920pmap_cache_bits(int mode, boolean_t is_pde) 921{ 922 int cache_bits, pat_flag, pat_idx; 923 924 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0) 925 panic("Unknown caching mode %d\n", mode); 926 927 /* The PAT bit is different for PTE's and PDE's. */ 928 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 929 930 /* Map the caching mode to a PAT index. */ 931 pat_idx = pat_index[mode]; 932 933 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 934 cache_bits = 0; 935 if (pat_idx & 0x4) 936 cache_bits |= pat_flag; 937 if (pat_idx & 0x2) 938 cache_bits |= PG_NC_PCD; 939 if (pat_idx & 0x1) 940 cache_bits |= PG_NC_PWT; 941 return (cache_bits); 942} 943 944/* 945 * The caller is responsible for maintaining TLB consistency. 946 */ 947static void 948pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 949{ 950 pd_entry_t *pde; 951 pmap_t pmap; 952 boolean_t PTD_updated; 953 954 PTD_updated = FALSE; 955 mtx_lock_spin(&allpmaps_lock); 956 LIST_FOREACH(pmap, &allpmaps, pm_list) { 957 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 958 PG_FRAME)) 959 PTD_updated = TRUE; 960 pde = pmap_pde(pmap, va); 961 pde_store(pde, newpde); 962 } 963 mtx_unlock_spin(&allpmaps_lock); 964 KASSERT(PTD_updated, 965 ("pmap_kenter_pde: current page table is not in allpmaps")); 966} 967 968/* 969 * After changing the page size for the specified virtual address in the page 970 * table, flush the corresponding entries from the processor's TLB. Only the 971 * calling processor's TLB is affected. 972 * 973 * The calling thread must be pinned to a processor. 974 */ 975static void 976pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 977{ 978 u_long cr4; 979 980 if ((newpde & PG_PS) == 0) 981 /* Demotion: flush a specific 2MB page mapping. */ 982 invlpg(va); 983 else if ((newpde & PG_G) == 0) 984 /* 985 * Promotion: flush every 4KB page mapping from the TLB 986 * because there are too many to flush individually. 987 */ 988 invltlb(); 989 else { 990 /* 991 * Promotion: flush every 4KB page mapping from the TLB, 992 * including any global (PG_G) mappings. 993 */ 994 cr4 = rcr4(); 995 load_cr4(cr4 & ~CR4_PGE); 996 /* 997 * Although preemption at this point could be detrimental to 998 * performance, it would not lead to an error. PG_G is simply 999 * ignored if CR4.PGE is clear. Moreover, in case this block 1000 * is re-entered, the load_cr4() either above or below will 1001 * modify CR4.PGE flushing the TLB. 1002 */ 1003 load_cr4(cr4 | CR4_PGE); 1004 } 1005} 1006 1007void 1008invltlb_glob(void) 1009{ 1010 uint64_t cr4; 1011 1012 if (pgeflag == 0) { 1013 invltlb(); 1014 } else { 1015 cr4 = rcr4(); 1016 load_cr4(cr4 & ~CR4_PGE); 1017 load_cr4(cr4 | CR4_PGE); 1018 } 1019} 1020 1021 1022#ifdef SMP 1023/* 1024 * For SMP, these functions have to use the IPI mechanism for coherence. 1025 * 1026 * N.B.: Before calling any of the following TLB invalidation functions, 1027 * the calling processor must ensure that all stores updating a non- 1028 * kernel page table are globally performed. Otherwise, another 1029 * processor could cache an old, pre-update entry without being 1030 * invalidated. This can happen one of two ways: (1) The pmap becomes 1031 * active on another processor after its pm_active field is checked by 1032 * one of the following functions but before a store updating the page 1033 * table is globally performed. (2) The pmap becomes active on another 1034 * processor before its pm_active field is checked but due to 1035 * speculative loads one of the following functions stills reads the 1036 * pmap as inactive on the other processor. 1037 * 1038 * The kernel page table is exempt because its pm_active field is 1039 * immutable. The kernel page table is always active on every 1040 * processor. 1041 */ 1042void 1043pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1044{ 1045 cpuset_t *mask, other_cpus; 1046 u_int cpuid; 1047 1048 sched_pin(); 1049 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1050 invlpg(va); 1051 mask = &all_cpus; 1052 } else { 1053 cpuid = PCPU_GET(cpuid); 1054 other_cpus = all_cpus; 1055 CPU_CLR(cpuid, &other_cpus); 1056 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1057 invlpg(va); 1058 CPU_AND(&other_cpus, &pmap->pm_active); 1059 mask = &other_cpus; 1060 } 1061 smp_masked_invlpg(*mask, va, pmap); 1062 sched_unpin(); 1063} 1064 1065/* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */ 1066#define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE) 1067 1068void 1069pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1070{ 1071 cpuset_t *mask, other_cpus; 1072 vm_offset_t addr; 1073 u_int cpuid; 1074 1075 if (eva - sva >= PMAP_INVLPG_THRESHOLD) { 1076 pmap_invalidate_all(pmap); 1077 return; 1078 } 1079 1080 sched_pin(); 1081 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1082 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1083 invlpg(addr); 1084 mask = &all_cpus; 1085 } else { 1086 cpuid = PCPU_GET(cpuid); 1087 other_cpus = all_cpus; 1088 CPU_CLR(cpuid, &other_cpus); 1089 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1090 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1091 invlpg(addr); 1092 CPU_AND(&other_cpus, &pmap->pm_active); 1093 mask = &other_cpus; 1094 } 1095 smp_masked_invlpg_range(*mask, sva, eva, pmap); 1096 sched_unpin(); 1097} 1098 1099void 1100pmap_invalidate_all(pmap_t pmap) 1101{ 1102 cpuset_t *mask, other_cpus; 1103 u_int cpuid; 1104 1105 sched_pin(); 1106 if (pmap == kernel_pmap) { 1107 invltlb_glob(); 1108 mask = &all_cpus; 1109 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) { 1110 invltlb(); 1111 mask = &all_cpus; 1112 } else { 1113 cpuid = PCPU_GET(cpuid); 1114 other_cpus = all_cpus; 1115 CPU_CLR(cpuid, &other_cpus); 1116 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1117 invltlb(); 1118 CPU_AND(&other_cpus, &pmap->pm_active); 1119 mask = &other_cpus; 1120 } 1121 smp_masked_invltlb(*mask, pmap); 1122 sched_unpin(); 1123} 1124 1125void 1126pmap_invalidate_cache(void) 1127{ 1128 1129 sched_pin(); 1130 wbinvd(); 1131 smp_cache_flush(); 1132 sched_unpin(); 1133} 1134 1135struct pde_action { 1136 cpuset_t invalidate; /* processors that invalidate their TLB */ 1137 vm_offset_t va; 1138 pd_entry_t *pde; 1139 pd_entry_t newpde; 1140 u_int store; /* processor that updates the PDE */ 1141}; 1142 1143static void 1144pmap_update_pde_kernel(void *arg) 1145{ 1146 struct pde_action *act = arg; 1147 pd_entry_t *pde; 1148 pmap_t pmap; 1149 1150 if (act->store == PCPU_GET(cpuid)) { 1151 1152 /* 1153 * Elsewhere, this operation requires allpmaps_lock for 1154 * synchronization. Here, it does not because it is being 1155 * performed in the context of an all_cpus rendezvous. 1156 */ 1157 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1158 pde = pmap_pde(pmap, act->va); 1159 pde_store(pde, act->newpde); 1160 } 1161 } 1162} 1163 1164static void 1165pmap_update_pde_user(void *arg) 1166{ 1167 struct pde_action *act = arg; 1168 1169 if (act->store == PCPU_GET(cpuid)) 1170 pde_store(act->pde, act->newpde); 1171} 1172 1173static void 1174pmap_update_pde_teardown(void *arg) 1175{ 1176 struct pde_action *act = arg; 1177 1178 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1179 pmap_update_pde_invalidate(act->va, act->newpde); 1180} 1181 1182/* 1183 * Change the page size for the specified virtual address in a way that 1184 * prevents any possibility of the TLB ever having two entries that map the 1185 * same virtual address using different page sizes. This is the recommended 1186 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1187 * machine check exception for a TLB state that is improperly diagnosed as a 1188 * hardware error. 1189 */ 1190static void 1191pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1192{ 1193 struct pde_action act; 1194 cpuset_t active, other_cpus; 1195 u_int cpuid; 1196 1197 sched_pin(); 1198 cpuid = PCPU_GET(cpuid); 1199 other_cpus = all_cpus; 1200 CPU_CLR(cpuid, &other_cpus); 1201 if (pmap == kernel_pmap) 1202 active = all_cpus; 1203 else 1204 active = pmap->pm_active; 1205 if (CPU_OVERLAP(&active, &other_cpus)) { 1206 act.store = cpuid; 1207 act.invalidate = active; 1208 act.va = va; 1209 act.pde = pde; 1210 act.newpde = newpde; 1211 CPU_SET(cpuid, &active); 1212 smp_rendezvous_cpus(active, 1213 smp_no_rendezvous_barrier, pmap == kernel_pmap ? 1214 pmap_update_pde_kernel : pmap_update_pde_user, 1215 pmap_update_pde_teardown, &act); 1216 } else { 1217 if (pmap == kernel_pmap) 1218 pmap_kenter_pde(va, newpde); 1219 else 1220 pde_store(pde, newpde); 1221 if (CPU_ISSET(cpuid, &active)) 1222 pmap_update_pde_invalidate(va, newpde); 1223 } 1224 sched_unpin(); 1225} 1226#else /* !SMP */ 1227/* 1228 * Normal, non-SMP, 486+ invalidation functions. 1229 * We inline these within pmap.c for speed. 1230 */ 1231PMAP_INLINE void 1232pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1233{ 1234 1235 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1236 invlpg(va); 1237} 1238 1239PMAP_INLINE void 1240pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1241{ 1242 vm_offset_t addr; 1243 1244 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1245 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1246 invlpg(addr); 1247} 1248 1249PMAP_INLINE void 1250pmap_invalidate_all(pmap_t pmap) 1251{ 1252 1253 if (pmap == kernel_pmap) 1254 invltlb_glob(); 1255 else if (!CPU_EMPTY(&pmap->pm_active)) 1256 invltlb(); 1257} 1258 1259PMAP_INLINE void 1260pmap_invalidate_cache(void) 1261{ 1262 1263 wbinvd(); 1264} 1265 1266static void 1267pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1268{ 1269 1270 if (pmap == kernel_pmap) 1271 pmap_kenter_pde(va, newpde); 1272 else 1273 pde_store(pde, newpde); 1274 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1275 pmap_update_pde_invalidate(va, newpde); 1276} 1277#endif /* !SMP */ 1278 1279static void 1280pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1281{ 1282 1283 /* 1284 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was 1285 * created by a promotion that did not invalidate the 512 or 1024 4KB 1286 * page mappings that might exist in the TLB. Consequently, at this 1287 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for 1288 * the address range [va, va + NBPDR). Therefore, the entire range 1289 * must be invalidated here. In contrast, when PG_PROMOTED is clear, 1290 * the TLB will not hold any 4KB page mappings for the address range 1291 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the 1292 * 2- or 4MB page mapping from the TLB. 1293 */ 1294 if ((pde & PG_PROMOTED) != 0) 1295 pmap_invalidate_range(pmap, va, va + NBPDR - 1); 1296 else 1297 pmap_invalidate_page(pmap, va); 1298} 1299 1300#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 1301 1302void 1303pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force) 1304{ 1305 1306 if (force) { 1307 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1); 1308 } else { 1309 KASSERT((sva & PAGE_MASK) == 0, 1310 ("pmap_invalidate_cache_range: sva not page-aligned")); 1311 KASSERT((eva & PAGE_MASK) == 0, 1312 ("pmap_invalidate_cache_range: eva not page-aligned")); 1313 } 1314 1315 if ((cpu_feature & CPUID_SS) != 0 && !force) 1316 ; /* If "Self Snoop" is supported and allowed, do nothing. */ 1317 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 && 1318 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1319#ifdef DEV_APIC 1320 /* 1321 * XXX: Some CPUs fault, hang, or trash the local APIC 1322 * registers if we use CLFLUSH on the local APIC 1323 * range. The local APIC is always uncached, so we 1324 * don't need to flush for that range anyway. 1325 */ 1326 if (pmap_kextract(sva) == lapic_paddr) 1327 return; 1328#endif 1329 /* 1330 * Otherwise, do per-cache line flush. Use the sfence 1331 * instruction to insure that previous stores are 1332 * included in the write-back. The processor 1333 * propagates flush to other processors in the cache 1334 * coherence domain. 1335 */ 1336 sfence(); 1337 for (; sva < eva; sva += cpu_clflush_line_size) 1338 clflushopt(sva); 1339 sfence(); 1340 } else if ((cpu_feature & CPUID_CLFSH) != 0 && 1341 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1342#ifdef DEV_APIC 1343 if (pmap_kextract(sva) == lapic_paddr) 1344 return; 1345#endif 1346 /* 1347 * Writes are ordered by CLFLUSH on Intel CPUs. 1348 */ 1349 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1350 mfence(); 1351 for (; sva < eva; sva += cpu_clflush_line_size) 1352 clflush(sva); 1353 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1354 mfence(); 1355 } else { 1356 1357 /* 1358 * No targeted cache flush methods are supported by CPU, 1359 * or the supplied range is bigger than 2MB. 1360 * Globally invalidate cache. 1361 */ 1362 pmap_invalidate_cache(); 1363 } 1364} 1365 1366void 1367pmap_invalidate_cache_pages(vm_page_t *pages, int count) 1368{ 1369 int i; 1370 1371 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 1372 (cpu_feature & CPUID_CLFSH) == 0) { 1373 pmap_invalidate_cache(); 1374 } else { 1375 for (i = 0; i < count; i++) 1376 pmap_flush_page(pages[i]); 1377 } 1378} 1379 1380/* 1381 * Are we current address space or kernel? 1382 */ 1383static __inline int 1384pmap_is_current(pmap_t pmap) 1385{ 1386 1387 return (pmap == kernel_pmap || pmap == 1388 vmspace_pmap(curthread->td_proc->p_vmspace)); 1389} 1390 1391/* 1392 * If the given pmap is not the current or kernel pmap, the returned pte must 1393 * be released by passing it to pmap_pte_release(). 1394 */ 1395pt_entry_t * 1396pmap_pte(pmap_t pmap, vm_offset_t va) 1397{ 1398 pd_entry_t newpf; 1399 pd_entry_t *pde; 1400 1401 pde = pmap_pde(pmap, va); 1402 if (*pde & PG_PS) 1403 return (pde); 1404 if (*pde != 0) { 1405 /* are we current address space or kernel? */ 1406 if (pmap_is_current(pmap)) 1407 return (vtopte(va)); 1408 mtx_lock(&PMAP2mutex); 1409 newpf = *pde & PG_FRAME; 1410 if ((*PMAP2 & PG_FRAME) != newpf) { 1411 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1412 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1413 } 1414 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1415 } 1416 return (NULL); 1417} 1418 1419/* 1420 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1421 * being NULL. 1422 */ 1423static __inline void 1424pmap_pte_release(pt_entry_t *pte) 1425{ 1426 1427 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1428 mtx_unlock(&PMAP2mutex); 1429} 1430 1431/* 1432 * NB: The sequence of updating a page table followed by accesses to the 1433 * corresponding pages is subject to the situation described in the "AMD64 1434 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23, 1435 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG 1436 * right after modifying the PTE bits is crucial. 1437 */ 1438static __inline void 1439invlcaddr(void *caddr) 1440{ 1441 1442 invlpg((u_int)caddr); 1443} 1444 1445/* 1446 * Super fast pmap_pte routine best used when scanning 1447 * the pv lists. This eliminates many coarse-grained 1448 * invltlb calls. Note that many of the pv list 1449 * scans are across different pmaps. It is very wasteful 1450 * to do an entire invltlb for checking a single mapping. 1451 * 1452 * If the given pmap is not the current pmap, pvh_global_lock 1453 * must be held and curthread pinned to a CPU. 1454 */ 1455static pt_entry_t * 1456pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1457{ 1458 pd_entry_t newpf; 1459 pd_entry_t *pde; 1460 1461 pde = pmap_pde(pmap, va); 1462 if (*pde & PG_PS) 1463 return (pde); 1464 if (*pde != 0) { 1465 /* are we current address space or kernel? */ 1466 if (pmap_is_current(pmap)) 1467 return (vtopte(va)); 1468 rw_assert(&pvh_global_lock, RA_WLOCKED); 1469 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1470 newpf = *pde & PG_FRAME; 1471 if ((*PMAP1 & PG_FRAME) != newpf) { 1472 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1473#ifdef SMP 1474 PMAP1cpu = PCPU_GET(cpuid); 1475#endif 1476 invlcaddr(PADDR1); 1477 PMAP1changed++; 1478 } else 1479#ifdef SMP 1480 if (PMAP1cpu != PCPU_GET(cpuid)) { 1481 PMAP1cpu = PCPU_GET(cpuid); 1482 invlcaddr(PADDR1); 1483 PMAP1changedcpu++; 1484 } else 1485#endif 1486 PMAP1unchanged++; 1487 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1488 } 1489 return (0); 1490} 1491 1492/* 1493 * Routine: pmap_extract 1494 * Function: 1495 * Extract the physical page address associated 1496 * with the given map/virtual_address pair. 1497 */ 1498vm_paddr_t 1499pmap_extract(pmap_t pmap, vm_offset_t va) 1500{ 1501 vm_paddr_t rtval; 1502 pt_entry_t *pte; 1503 pd_entry_t pde; 1504 1505 rtval = 0; 1506 PMAP_LOCK(pmap); 1507 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1508 if (pde != 0) { 1509 if ((pde & PG_PS) != 0) 1510 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1511 else { 1512 pte = pmap_pte(pmap, va); 1513 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1514 pmap_pte_release(pte); 1515 } 1516 } 1517 PMAP_UNLOCK(pmap); 1518 return (rtval); 1519} 1520 1521/* 1522 * Routine: pmap_extract_and_hold 1523 * Function: 1524 * Atomically extract and hold the physical page 1525 * with the given pmap and virtual address pair 1526 * if that mapping permits the given protection. 1527 */ 1528vm_page_t 1529pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1530{ 1531 pd_entry_t pde; 1532 pt_entry_t pte, *ptep; 1533 vm_page_t m; 1534 vm_paddr_t pa; 1535 1536 pa = 0; 1537 m = NULL; 1538 PMAP_LOCK(pmap); 1539retry: 1540 pde = *pmap_pde(pmap, va); 1541 if (pde != 0) { 1542 if (pde & PG_PS) { 1543 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1544 if (vm_page_pa_tryrelock(pmap, (pde & 1545 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1546 goto retry; 1547 m = PHYS_TO_VM_PAGE(pa); 1548 } 1549 } else { 1550 ptep = pmap_pte(pmap, va); 1551 pte = *ptep; 1552 pmap_pte_release(ptep); 1553 if (pte != 0 && 1554 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1555 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1556 &pa)) 1557 goto retry; 1558 m = PHYS_TO_VM_PAGE(pa); 1559 } 1560 } 1561 if (m != NULL) 1562 vm_page_hold(m); 1563 } 1564 PA_UNLOCK_COND(pa); 1565 PMAP_UNLOCK(pmap); 1566 return (m); 1567} 1568 1569/*************************************************** 1570 * Low level mapping routines..... 1571 ***************************************************/ 1572 1573/* 1574 * Add a wired page to the kva. 1575 * Note: not SMP coherent. 1576 * 1577 * This function may be used before pmap_bootstrap() is called. 1578 */ 1579PMAP_INLINE void 1580pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1581{ 1582 pt_entry_t *pte; 1583 1584 pte = vtopte(va); 1585 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1586} 1587 1588static __inline void 1589pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1590{ 1591 pt_entry_t *pte; 1592 1593 pte = vtopte(va); 1594 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1595} 1596 1597/* 1598 * Remove a page from the kernel pagetables. 1599 * Note: not SMP coherent. 1600 * 1601 * This function may be used before pmap_bootstrap() is called. 1602 */ 1603PMAP_INLINE void 1604pmap_kremove(vm_offset_t va) 1605{ 1606 pt_entry_t *pte; 1607 1608 pte = vtopte(va); 1609 pte_clear(pte); 1610} 1611 1612/* 1613 * Used to map a range of physical addresses into kernel 1614 * virtual address space. 1615 * 1616 * The value passed in '*virt' is a suggested virtual address for 1617 * the mapping. Architectures which can support a direct-mapped 1618 * physical to virtual region can return the appropriate address 1619 * within that region, leaving '*virt' unchanged. Other 1620 * architectures should map the pages starting at '*virt' and 1621 * update '*virt' with the first usable address after the mapped 1622 * region. 1623 */ 1624vm_offset_t 1625pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1626{ 1627 vm_offset_t va, sva; 1628 vm_paddr_t superpage_offset; 1629 pd_entry_t newpde; 1630 1631 va = *virt; 1632 /* 1633 * Does the physical address range's size and alignment permit at 1634 * least one superpage mapping to be created? 1635 */ 1636 superpage_offset = start & PDRMASK; 1637 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) { 1638 /* 1639 * Increase the starting virtual address so that its alignment 1640 * does not preclude the use of superpage mappings. 1641 */ 1642 if ((va & PDRMASK) < superpage_offset) 1643 va = (va & ~PDRMASK) + superpage_offset; 1644 else if ((va & PDRMASK) > superpage_offset) 1645 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset; 1646 } 1647 sva = va; 1648 while (start < end) { 1649 if ((start & PDRMASK) == 0 && end - start >= NBPDR && 1650 pseflag) { 1651 KASSERT((va & PDRMASK) == 0, 1652 ("pmap_map: misaligned va %#x", va)); 1653 newpde = start | PG_PS | pgeflag | PG_RW | PG_V; 1654 pmap_kenter_pde(va, newpde); 1655 va += NBPDR; 1656 start += NBPDR; 1657 } else { 1658 pmap_kenter(va, start); 1659 va += PAGE_SIZE; 1660 start += PAGE_SIZE; 1661 } 1662 } 1663 pmap_invalidate_range(kernel_pmap, sva, va); 1664 *virt = va; 1665 return (sva); 1666} 1667 1668 1669/* 1670 * Add a list of wired pages to the kva 1671 * this routine is only used for temporary 1672 * kernel mappings that do not need to have 1673 * page modification or references recorded. 1674 * Note that old mappings are simply written 1675 * over. The page *must* be wired. 1676 * Note: SMP coherent. Uses a ranged shootdown IPI. 1677 */ 1678void 1679pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1680{ 1681 pt_entry_t *endpte, oldpte, pa, *pte; 1682 vm_page_t m; 1683 1684 oldpte = 0; 1685 pte = vtopte(sva); 1686 endpte = pte + count; 1687 while (pte < endpte) { 1688 m = *ma++; 1689 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 1690 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1691 oldpte |= *pte; 1692 pte_store(pte, pa | pgeflag | PG_RW | PG_V); 1693 } 1694 pte++; 1695 } 1696 if (__predict_false((oldpte & PG_V) != 0)) 1697 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1698 PAGE_SIZE); 1699} 1700 1701/* 1702 * This routine tears out page mappings from the 1703 * kernel -- it is meant only for temporary mappings. 1704 * Note: SMP coherent. Uses a ranged shootdown IPI. 1705 */ 1706void 1707pmap_qremove(vm_offset_t sva, int count) 1708{ 1709 vm_offset_t va; 1710 1711 va = sva; 1712 while (count-- > 0) { 1713 pmap_kremove(va); 1714 va += PAGE_SIZE; 1715 } 1716 pmap_invalidate_range(kernel_pmap, sva, va); 1717} 1718 1719/*************************************************** 1720 * Page table page management routines..... 1721 ***************************************************/ 1722static __inline void 1723pmap_free_zero_pages(struct spglist *free) 1724{ 1725 vm_page_t m; 1726 int count; 1727 1728 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) { 1729 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1730 /* Preserve the page's PG_ZERO setting. */ 1731 vm_page_free_toq(m); 1732 } 1733 atomic_subtract_int(&vm_cnt.v_wire_count, count); 1734} 1735 1736/* 1737 * Schedule the specified unused page table page to be freed. Specifically, 1738 * add the page to the specified list of pages that will be released to the 1739 * physical memory manager after the TLB has been updated. 1740 */ 1741static __inline void 1742pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1743 boolean_t set_PG_ZERO) 1744{ 1745 1746 if (set_PG_ZERO) 1747 m->flags |= PG_ZERO; 1748 else 1749 m->flags &= ~PG_ZERO; 1750 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1751} 1752 1753/* 1754 * Inserts the specified page table page into the specified pmap's collection 1755 * of idle page table pages. Each of a pmap's page table pages is responsible 1756 * for mapping a distinct range of virtual addresses. The pmap's collection is 1757 * ordered by this virtual address range. 1758 */ 1759static __inline int 1760pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1761{ 1762 1763 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1764 return (vm_radix_insert(&pmap->pm_root, mpte)); 1765} 1766 1767/* 1768 * Removes the page table page mapping the specified virtual address from the 1769 * specified pmap's collection of idle page table pages, and returns it. 1770 * Otherwise, returns NULL if there is no page table page corresponding to the 1771 * specified virtual address. 1772 */ 1773static __inline vm_page_t 1774pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 1775{ 1776 1777 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1778 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT)); 1779} 1780 1781/* 1782 * Decrements a page table page's wire count, which is used to record the 1783 * number of valid page table entries within the page. If the wire count 1784 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1785 * page table page was unmapped and FALSE otherwise. 1786 */ 1787static inline boolean_t 1788pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1789{ 1790 1791 --m->wire_count; 1792 if (m->wire_count == 0) { 1793 _pmap_unwire_ptp(pmap, m, free); 1794 return (TRUE); 1795 } else 1796 return (FALSE); 1797} 1798 1799static void 1800_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1801{ 1802 vm_offset_t pteva; 1803 1804 /* 1805 * unmap the page table page 1806 */ 1807 pmap->pm_pdir[m->pindex] = 0; 1808 --pmap->pm_stats.resident_count; 1809 1810 /* 1811 * Do an invltlb to make the invalidated mapping 1812 * take effect immediately. 1813 */ 1814 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1815 pmap_invalidate_page(pmap, pteva); 1816 1817 /* 1818 * Put page on a list so that it is released after 1819 * *ALL* TLB shootdown is done 1820 */ 1821 pmap_add_delayed_free_list(m, free, TRUE); 1822} 1823 1824/* 1825 * After removing a page table entry, this routine is used to 1826 * conditionally free the page, and manage the hold/wire counts. 1827 */ 1828static int 1829pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free) 1830{ 1831 pd_entry_t ptepde; 1832 vm_page_t mpte; 1833 1834 if (va >= VM_MAXUSER_ADDRESS) 1835 return (0); 1836 ptepde = *pmap_pde(pmap, va); 1837 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1838 return (pmap_unwire_ptp(pmap, mpte, free)); 1839} 1840 1841/* 1842 * Initialize the pmap for the swapper process. 1843 */ 1844void 1845pmap_pinit0(pmap_t pmap) 1846{ 1847 1848 PMAP_LOCK_INIT(pmap); 1849 /* 1850 * Since the page table directory is shared with the kernel pmap, 1851 * which is already included in the list "allpmaps", this pmap does 1852 * not need to be inserted into that list. 1853 */ 1854 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1855#if defined(PAE) || defined(PAE_TABLES) 1856 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1857#endif 1858 pmap->pm_root.rt_root = 0; 1859 CPU_ZERO(&pmap->pm_active); 1860 TAILQ_INIT(&pmap->pm_pvchunk); 1861 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1862 pmap_activate_boot(pmap); 1863} 1864 1865/* 1866 * Initialize a preallocated and zeroed pmap structure, 1867 * such as one in a vmspace structure. 1868 */ 1869int 1870pmap_pinit(pmap_t pmap) 1871{ 1872 vm_page_t m, ptdpg[NPGPTD]; 1873 vm_paddr_t pa; 1874 int i; 1875 1876 /* 1877 * No need to allocate page table space yet but we do need a valid 1878 * page directory table. 1879 */ 1880 if (pmap->pm_pdir == NULL) { 1881 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1882 if (pmap->pm_pdir == NULL) 1883 return (0); 1884#if defined(PAE) || defined(PAE_TABLES) 1885 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1886 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1887 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1888 ("pmap_pinit: pdpt misaligned")); 1889 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1890 ("pmap_pinit: pdpt above 4g")); 1891#endif 1892 pmap->pm_root.rt_root = 0; 1893 } 1894 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1895 ("pmap_pinit: pmap has reserved page table page(s)")); 1896 1897 /* 1898 * allocate the page directory page(s) 1899 */ 1900 for (i = 0; i < NPGPTD;) { 1901 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1902 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1903 if (m == NULL) 1904 VM_WAIT; 1905 else { 1906 ptdpg[i++] = m; 1907 } 1908 } 1909 1910 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1911 1912 for (i = 0; i < NPGPTD; i++) 1913 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1914 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1915 1916 mtx_lock_spin(&allpmaps_lock); 1917 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1918 /* Copy the kernel page table directory entries. */ 1919 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1920 mtx_unlock_spin(&allpmaps_lock); 1921 1922 /* install self-referential address mapping entry(s) */ 1923 for (i = 0; i < NPGPTD; i++) { 1924 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1925 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1926#if defined(PAE) || defined(PAE_TABLES) 1927 pmap->pm_pdpt[i] = pa | PG_V; 1928#endif 1929 } 1930 1931 CPU_ZERO(&pmap->pm_active); 1932 TAILQ_INIT(&pmap->pm_pvchunk); 1933 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1934 1935 return (1); 1936} 1937 1938/* 1939 * this routine is called if the page table page is not 1940 * mapped correctly. 1941 */ 1942static vm_page_t 1943_pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags) 1944{ 1945 vm_paddr_t ptepa; 1946 vm_page_t m; 1947 1948 /* 1949 * Allocate a page table page. 1950 */ 1951 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1952 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1953 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1954 PMAP_UNLOCK(pmap); 1955 rw_wunlock(&pvh_global_lock); 1956 VM_WAIT; 1957 rw_wlock(&pvh_global_lock); 1958 PMAP_LOCK(pmap); 1959 } 1960 1961 /* 1962 * Indicate the need to retry. While waiting, the page table 1963 * page may have been allocated. 1964 */ 1965 return (NULL); 1966 } 1967 if ((m->flags & PG_ZERO) == 0) 1968 pmap_zero_page(m); 1969 1970 /* 1971 * Map the pagetable page into the process address space, if 1972 * it isn't already there. 1973 */ 1974 1975 pmap->pm_stats.resident_count++; 1976 1977 ptepa = VM_PAGE_TO_PHYS(m); 1978 pmap->pm_pdir[ptepindex] = 1979 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1980 1981 return (m); 1982} 1983 1984static vm_page_t 1985pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1986{ 1987 u_int ptepindex; 1988 pd_entry_t ptepa; 1989 vm_page_t m; 1990 1991 /* 1992 * Calculate pagetable page index 1993 */ 1994 ptepindex = va >> PDRSHIFT; 1995retry: 1996 /* 1997 * Get the page directory entry 1998 */ 1999 ptepa = pmap->pm_pdir[ptepindex]; 2000 2001 /* 2002 * This supports switching from a 4MB page to a 2003 * normal 4K page. 2004 */ 2005 if (ptepa & PG_PS) { 2006 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 2007 ptepa = pmap->pm_pdir[ptepindex]; 2008 } 2009 2010 /* 2011 * If the page table page is mapped, we just increment the 2012 * hold count, and activate it. 2013 */ 2014 if (ptepa) { 2015 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 2016 m->wire_count++; 2017 } else { 2018 /* 2019 * Here if the pte page isn't mapped, or if it has 2020 * been deallocated. 2021 */ 2022 m = _pmap_allocpte(pmap, ptepindex, flags); 2023 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 2024 goto retry; 2025 } 2026 return (m); 2027} 2028 2029 2030/*************************************************** 2031* Pmap allocation/deallocation routines. 2032 ***************************************************/ 2033 2034/* 2035 * Release any resources held by the given physical map. 2036 * Called when a pmap initialized by pmap_pinit is being released. 2037 * Should only be called if the map contains no valid mappings. 2038 */ 2039void 2040pmap_release(pmap_t pmap) 2041{ 2042 vm_page_t m, ptdpg[NPGPTD]; 2043 int i; 2044 2045 KASSERT(pmap->pm_stats.resident_count == 0, 2046 ("pmap_release: pmap resident count %ld != 0", 2047 pmap->pm_stats.resident_count)); 2048 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2049 ("pmap_release: pmap has reserved page table page(s)")); 2050 KASSERT(CPU_EMPTY(&pmap->pm_active), 2051 ("releasing active pmap %p", pmap)); 2052 2053 mtx_lock_spin(&allpmaps_lock); 2054 LIST_REMOVE(pmap, pm_list); 2055 mtx_unlock_spin(&allpmaps_lock); 2056 2057 for (i = 0; i < NPGPTD; i++) 2058 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 2059 PG_FRAME); 2060 2061 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 2062 sizeof(*pmap->pm_pdir)); 2063 2064 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2065 2066 for (i = 0; i < NPGPTD; i++) { 2067 m = ptdpg[i]; 2068#if defined(PAE) || defined(PAE_TABLES) 2069 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2070 ("pmap_release: got wrong ptd page")); 2071#endif 2072 m->wire_count--; 2073 vm_page_free_zero(m); 2074 } 2075 atomic_subtract_int(&vm_cnt.v_wire_count, NPGPTD); 2076} 2077 2078static int 2079kvm_size(SYSCTL_HANDLER_ARGS) 2080{ 2081 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2082 2083 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2084} 2085SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2086 0, 0, kvm_size, "IU", "Size of KVM"); 2087 2088static int 2089kvm_free(SYSCTL_HANDLER_ARGS) 2090{ 2091 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2092 2093 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2094} 2095SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2096 0, 0, kvm_free, "IU", "Amount of KVM free"); 2097 2098/* 2099 * grow the number of kernel page table entries, if needed 2100 */ 2101void 2102pmap_growkernel(vm_offset_t addr) 2103{ 2104 vm_paddr_t ptppaddr; 2105 vm_page_t nkpg; 2106 pd_entry_t newpdir; 2107 2108 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2109 addr = roundup2(addr, NBPDR); 2110 if (addr - 1 >= kernel_map->max_offset) 2111 addr = kernel_map->max_offset; 2112 while (kernel_vm_end < addr) { 2113 if (pdir_pde(PTD, kernel_vm_end)) { 2114 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2115 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2116 kernel_vm_end = kernel_map->max_offset; 2117 break; 2118 } 2119 continue; 2120 } 2121 2122 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2123 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2124 VM_ALLOC_ZERO); 2125 if (nkpg == NULL) 2126 panic("pmap_growkernel: no memory to grow kernel"); 2127 2128 nkpt++; 2129 2130 if ((nkpg->flags & PG_ZERO) == 0) 2131 pmap_zero_page(nkpg); 2132 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2133 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2134 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2135 2136 pmap_kenter_pde(kernel_vm_end, newpdir); 2137 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2138 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2139 kernel_vm_end = kernel_map->max_offset; 2140 break; 2141 } 2142 } 2143} 2144 2145 2146/*************************************************** 2147 * page management routines. 2148 ***************************************************/ 2149 2150CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2151CTASSERT(_NPCM == 11); 2152CTASSERT(_NPCPV == 336); 2153 2154static __inline struct pv_chunk * 2155pv_to_chunk(pv_entry_t pv) 2156{ 2157 2158 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2159} 2160 2161#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2162 2163#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2164#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2165 2166static const uint32_t pc_freemask[_NPCM] = { 2167 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2168 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2169 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2170 PC_FREE0_9, PC_FREE10 2171}; 2172 2173SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2174 "Current number of pv entries"); 2175 2176#ifdef PV_STATS 2177static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2178 2179SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2180 "Current number of pv entry chunks"); 2181SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2182 "Current number of pv entry chunks allocated"); 2183SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2184 "Current number of pv entry chunks frees"); 2185SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2186 "Number of times tried to get a chunk page but failed."); 2187 2188static long pv_entry_frees, pv_entry_allocs; 2189static int pv_entry_spare; 2190 2191SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2192 "Current number of pv entry frees"); 2193SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2194 "Current number of pv entry allocs"); 2195SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2196 "Current number of spare pv entries"); 2197#endif 2198 2199/* 2200 * We are in a serious low memory condition. Resort to 2201 * drastic measures to free some pages so we can allocate 2202 * another pv entry chunk. 2203 */ 2204static vm_page_t 2205pmap_pv_reclaim(pmap_t locked_pmap) 2206{ 2207 struct pch newtail; 2208 struct pv_chunk *pc; 2209 struct md_page *pvh; 2210 pd_entry_t *pde; 2211 pmap_t pmap; 2212 pt_entry_t *pte, tpte; 2213 pv_entry_t pv; 2214 vm_offset_t va; 2215 vm_page_t m, m_pc; 2216 struct spglist free; 2217 uint32_t inuse; 2218 int bit, field, freed; 2219 2220 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2221 pmap = NULL; 2222 m_pc = NULL; 2223 SLIST_INIT(&free); 2224 TAILQ_INIT(&newtail); 2225 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 2226 SLIST_EMPTY(&free))) { 2227 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2228 if (pmap != pc->pc_pmap) { 2229 if (pmap != NULL) { 2230 pmap_invalidate_all(pmap); 2231 if (pmap != locked_pmap) 2232 PMAP_UNLOCK(pmap); 2233 } 2234 pmap = pc->pc_pmap; 2235 /* Avoid deadlock and lock recursion. */ 2236 if (pmap > locked_pmap) 2237 PMAP_LOCK(pmap); 2238 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2239 pmap = NULL; 2240 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2241 continue; 2242 } 2243 } 2244 2245 /* 2246 * Destroy every non-wired, 4 KB page mapping in the chunk. 2247 */ 2248 freed = 0; 2249 for (field = 0; field < _NPCM; field++) { 2250 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2251 inuse != 0; inuse &= ~(1UL << bit)) { 2252 bit = bsfl(inuse); 2253 pv = &pc->pc_pventry[field * 32 + bit]; 2254 va = pv->pv_va; 2255 pde = pmap_pde(pmap, va); 2256 if ((*pde & PG_PS) != 0) 2257 continue; 2258 pte = pmap_pte(pmap, va); 2259 tpte = *pte; 2260 if ((tpte & PG_W) == 0) 2261 tpte = pte_load_clear(pte); 2262 pmap_pte_release(pte); 2263 if ((tpte & PG_W) != 0) 2264 continue; 2265 KASSERT(tpte != 0, 2266 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2267 pmap, va)); 2268 if ((tpte & PG_G) != 0) 2269 pmap_invalidate_page(pmap, va); 2270 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2271 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2272 vm_page_dirty(m); 2273 if ((tpte & PG_A) != 0) 2274 vm_page_aflag_set(m, PGA_REFERENCED); 2275 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2276 if (TAILQ_EMPTY(&m->md.pv_list) && 2277 (m->flags & PG_FICTITIOUS) == 0) { 2278 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2279 if (TAILQ_EMPTY(&pvh->pv_list)) { 2280 vm_page_aflag_clear(m, 2281 PGA_WRITEABLE); 2282 } 2283 } 2284 pc->pc_map[field] |= 1UL << bit; 2285 pmap_unuse_pt(pmap, va, &free); 2286 freed++; 2287 } 2288 } 2289 if (freed == 0) { 2290 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2291 continue; 2292 } 2293 /* Every freed mapping is for a 4 KB page. */ 2294 pmap->pm_stats.resident_count -= freed; 2295 PV_STAT(pv_entry_frees += freed); 2296 PV_STAT(pv_entry_spare += freed); 2297 pv_entry_count -= freed; 2298 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2299 for (field = 0; field < _NPCM; field++) 2300 if (pc->pc_map[field] != pc_freemask[field]) { 2301 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2302 pc_list); 2303 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2304 2305 /* 2306 * One freed pv entry in locked_pmap is 2307 * sufficient. 2308 */ 2309 if (pmap == locked_pmap) 2310 goto out; 2311 break; 2312 } 2313 if (field == _NPCM) { 2314 PV_STAT(pv_entry_spare -= _NPCPV); 2315 PV_STAT(pc_chunk_count--); 2316 PV_STAT(pc_chunk_frees++); 2317 /* Entire chunk is free; return it. */ 2318 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2319 pmap_qremove((vm_offset_t)pc, 1); 2320 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2321 break; 2322 } 2323 } 2324out: 2325 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2326 if (pmap != NULL) { 2327 pmap_invalidate_all(pmap); 2328 if (pmap != locked_pmap) 2329 PMAP_UNLOCK(pmap); 2330 } 2331 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) { 2332 m_pc = SLIST_FIRST(&free); 2333 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2334 /* Recycle a freed page table page. */ 2335 m_pc->wire_count = 1; 2336 } 2337 pmap_free_zero_pages(&free); 2338 return (m_pc); 2339} 2340 2341/* 2342 * free the pv_entry back to the free list 2343 */ 2344static void 2345free_pv_entry(pmap_t pmap, pv_entry_t pv) 2346{ 2347 struct pv_chunk *pc; 2348 int idx, field, bit; 2349 2350 rw_assert(&pvh_global_lock, RA_WLOCKED); 2351 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2352 PV_STAT(pv_entry_frees++); 2353 PV_STAT(pv_entry_spare++); 2354 pv_entry_count--; 2355 pc = pv_to_chunk(pv); 2356 idx = pv - &pc->pc_pventry[0]; 2357 field = idx / 32; 2358 bit = idx % 32; 2359 pc->pc_map[field] |= 1ul << bit; 2360 for (idx = 0; idx < _NPCM; idx++) 2361 if (pc->pc_map[idx] != pc_freemask[idx]) { 2362 /* 2363 * 98% of the time, pc is already at the head of the 2364 * list. If it isn't already, move it to the head. 2365 */ 2366 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2367 pc)) { 2368 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2369 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2370 pc_list); 2371 } 2372 return; 2373 } 2374 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2375 free_pv_chunk(pc); 2376} 2377 2378static void 2379free_pv_chunk(struct pv_chunk *pc) 2380{ 2381 vm_page_t m; 2382 2383 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2384 PV_STAT(pv_entry_spare -= _NPCPV); 2385 PV_STAT(pc_chunk_count--); 2386 PV_STAT(pc_chunk_frees++); 2387 /* entire chunk is free, return it */ 2388 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2389 pmap_qremove((vm_offset_t)pc, 1); 2390 vm_page_unwire(m, PQ_NONE); 2391 vm_page_free(m); 2392 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2393} 2394 2395/* 2396 * get a new pv_entry, allocating a block from the system 2397 * when needed. 2398 */ 2399static pv_entry_t 2400get_pv_entry(pmap_t pmap, boolean_t try) 2401{ 2402 static const struct timeval printinterval = { 60, 0 }; 2403 static struct timeval lastprint; 2404 int bit, field; 2405 pv_entry_t pv; 2406 struct pv_chunk *pc; 2407 vm_page_t m; 2408 2409 rw_assert(&pvh_global_lock, RA_WLOCKED); 2410 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2411 PV_STAT(pv_entry_allocs++); 2412 pv_entry_count++; 2413 if (pv_entry_count > pv_entry_high_water) 2414 if (ratecheck(&lastprint, &printinterval)) 2415 printf("Approaching the limit on PV entries, consider " 2416 "increasing either the vm.pmap.shpgperproc or the " 2417 "vm.pmap.pv_entry_max tunable.\n"); 2418retry: 2419 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2420 if (pc != NULL) { 2421 for (field = 0; field < _NPCM; field++) { 2422 if (pc->pc_map[field]) { 2423 bit = bsfl(pc->pc_map[field]); 2424 break; 2425 } 2426 } 2427 if (field < _NPCM) { 2428 pv = &pc->pc_pventry[field * 32 + bit]; 2429 pc->pc_map[field] &= ~(1ul << bit); 2430 /* If this was the last item, move it to tail */ 2431 for (field = 0; field < _NPCM; field++) 2432 if (pc->pc_map[field] != 0) { 2433 PV_STAT(pv_entry_spare--); 2434 return (pv); /* not full, return */ 2435 } 2436 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2437 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2438 PV_STAT(pv_entry_spare--); 2439 return (pv); 2440 } 2441 } 2442 /* 2443 * Access to the ptelist "pv_vafree" is synchronized by the pvh 2444 * global lock. If "pv_vafree" is currently non-empty, it will 2445 * remain non-empty until pmap_ptelist_alloc() completes. 2446 */ 2447 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2448 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2449 if (try) { 2450 pv_entry_count--; 2451 PV_STAT(pc_chunk_tryfail++); 2452 return (NULL); 2453 } 2454 m = pmap_pv_reclaim(pmap); 2455 if (m == NULL) 2456 goto retry; 2457 } 2458 PV_STAT(pc_chunk_count++); 2459 PV_STAT(pc_chunk_allocs++); 2460 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2461 pmap_qenter((vm_offset_t)pc, &m, 1); 2462 pc->pc_pmap = pmap; 2463 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2464 for (field = 1; field < _NPCM; field++) 2465 pc->pc_map[field] = pc_freemask[field]; 2466 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2467 pv = &pc->pc_pventry[0]; 2468 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2469 PV_STAT(pv_entry_spare += _NPCPV - 1); 2470 return (pv); 2471} 2472 2473static __inline pv_entry_t 2474pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2475{ 2476 pv_entry_t pv; 2477 2478 rw_assert(&pvh_global_lock, RA_WLOCKED); 2479 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2480 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2481 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2482 break; 2483 } 2484 } 2485 return (pv); 2486} 2487 2488static void 2489pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2490{ 2491 struct md_page *pvh; 2492 pv_entry_t pv; 2493 vm_offset_t va_last; 2494 vm_page_t m; 2495 2496 rw_assert(&pvh_global_lock, RA_WLOCKED); 2497 KASSERT((pa & PDRMASK) == 0, 2498 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2499 2500 /* 2501 * Transfer the 4mpage's pv entry for this mapping to the first 2502 * page's pv list. 2503 */ 2504 pvh = pa_to_pvh(pa); 2505 va = trunc_4mpage(va); 2506 pv = pmap_pvh_remove(pvh, pmap, va); 2507 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2508 m = PHYS_TO_VM_PAGE(pa); 2509 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2510 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2511 va_last = va + NBPDR - PAGE_SIZE; 2512 do { 2513 m++; 2514 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2515 ("pmap_pv_demote_pde: page %p is not managed", m)); 2516 va += PAGE_SIZE; 2517 pmap_insert_entry(pmap, va, m); 2518 } while (va < va_last); 2519} 2520 2521#if VM_NRESERVLEVEL > 0 2522static void 2523pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2524{ 2525 struct md_page *pvh; 2526 pv_entry_t pv; 2527 vm_offset_t va_last; 2528 vm_page_t m; 2529 2530 rw_assert(&pvh_global_lock, RA_WLOCKED); 2531 KASSERT((pa & PDRMASK) == 0, 2532 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2533 2534 /* 2535 * Transfer the first page's pv entry for this mapping to the 2536 * 4mpage's pv list. Aside from avoiding the cost of a call 2537 * to get_pv_entry(), a transfer avoids the possibility that 2538 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2539 * removes one of the mappings that is being promoted. 2540 */ 2541 m = PHYS_TO_VM_PAGE(pa); 2542 va = trunc_4mpage(va); 2543 pv = pmap_pvh_remove(&m->md, pmap, va); 2544 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2545 pvh = pa_to_pvh(pa); 2546 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2547 /* Free the remaining NPTEPG - 1 pv entries. */ 2548 va_last = va + NBPDR - PAGE_SIZE; 2549 do { 2550 m++; 2551 va += PAGE_SIZE; 2552 pmap_pvh_free(&m->md, pmap, va); 2553 } while (va < va_last); 2554} 2555#endif /* VM_NRESERVLEVEL > 0 */ 2556 2557static void 2558pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2559{ 2560 pv_entry_t pv; 2561 2562 pv = pmap_pvh_remove(pvh, pmap, va); 2563 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2564 free_pv_entry(pmap, pv); 2565} 2566 2567static void 2568pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2569{ 2570 struct md_page *pvh; 2571 2572 rw_assert(&pvh_global_lock, RA_WLOCKED); 2573 pmap_pvh_free(&m->md, pmap, va); 2574 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) { 2575 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2576 if (TAILQ_EMPTY(&pvh->pv_list)) 2577 vm_page_aflag_clear(m, PGA_WRITEABLE); 2578 } 2579} 2580 2581/* 2582 * Create a pv entry for page at pa for 2583 * (pmap, va). 2584 */ 2585static void 2586pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2587{ 2588 pv_entry_t pv; 2589 2590 rw_assert(&pvh_global_lock, RA_WLOCKED); 2591 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2592 pv = get_pv_entry(pmap, FALSE); 2593 pv->pv_va = va; 2594 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2595} 2596 2597/* 2598 * Conditionally create a pv entry. 2599 */ 2600static boolean_t 2601pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2602{ 2603 pv_entry_t pv; 2604 2605 rw_assert(&pvh_global_lock, RA_WLOCKED); 2606 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2607 if (pv_entry_count < pv_entry_high_water && 2608 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2609 pv->pv_va = va; 2610 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2611 return (TRUE); 2612 } else 2613 return (FALSE); 2614} 2615 2616/* 2617 * Create the pv entries for each of the pages within a superpage. 2618 */ 2619static boolean_t 2620pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2621{ 2622 struct md_page *pvh; 2623 pv_entry_t pv; 2624 2625 rw_assert(&pvh_global_lock, RA_WLOCKED); 2626 if (pv_entry_count < pv_entry_high_water && 2627 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2628 pv->pv_va = va; 2629 pvh = pa_to_pvh(pa); 2630 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2631 return (TRUE); 2632 } else 2633 return (FALSE); 2634} 2635 2636/* 2637 * Fills a page table page with mappings to consecutive physical pages. 2638 */ 2639static void 2640pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2641{ 2642 pt_entry_t *pte; 2643 2644 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2645 *pte = newpte; 2646 newpte += PAGE_SIZE; 2647 } 2648} 2649 2650/* 2651 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2652 * 2- or 4MB page mapping is invalidated. 2653 */ 2654static boolean_t 2655pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2656{ 2657 pd_entry_t newpde, oldpde; 2658 pt_entry_t *firstpte, newpte; 2659 vm_paddr_t mptepa; 2660 vm_page_t mpte; 2661 struct spglist free; 2662 vm_offset_t sva; 2663 2664 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2665 oldpde = *pde; 2666 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2667 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2668 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) == 2669 NULL) { 2670 KASSERT((oldpde & PG_W) == 0, 2671 ("pmap_demote_pde: page table page for a wired mapping" 2672 " is missing")); 2673 2674 /* 2675 * Invalidate the 2- or 4MB page mapping and return 2676 * "failure" if the mapping was never accessed or the 2677 * allocation of the new page table page fails. 2678 */ 2679 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2680 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2681 VM_ALLOC_WIRED)) == NULL) { 2682 SLIST_INIT(&free); 2683 sva = trunc_4mpage(va); 2684 pmap_remove_pde(pmap, pde, sva, &free); 2685 if ((oldpde & PG_G) == 0) 2686 pmap_invalidate_pde_page(pmap, sva, oldpde); 2687 pmap_free_zero_pages(&free); 2688 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2689 " in pmap %p", va, pmap); 2690 return (FALSE); 2691 } 2692 if (va < VM_MAXUSER_ADDRESS) 2693 pmap->pm_stats.resident_count++; 2694 } 2695 mptepa = VM_PAGE_TO_PHYS(mpte); 2696 2697 /* 2698 * If the page mapping is in the kernel's address space, then the 2699 * KPTmap can provide access to the page table page. Otherwise, 2700 * temporarily map the page table page (mpte) into the kernel's 2701 * address space at either PADDR1 or PADDR2. 2702 */ 2703 if (va >= KERNBASE) 2704 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2705 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) { 2706 if ((*PMAP1 & PG_FRAME) != mptepa) { 2707 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2708#ifdef SMP 2709 PMAP1cpu = PCPU_GET(cpuid); 2710#endif 2711 invlcaddr(PADDR1); 2712 PMAP1changed++; 2713 } else 2714#ifdef SMP 2715 if (PMAP1cpu != PCPU_GET(cpuid)) { 2716 PMAP1cpu = PCPU_GET(cpuid); 2717 invlcaddr(PADDR1); 2718 PMAP1changedcpu++; 2719 } else 2720#endif 2721 PMAP1unchanged++; 2722 firstpte = PADDR1; 2723 } else { 2724 mtx_lock(&PMAP2mutex); 2725 if ((*PMAP2 & PG_FRAME) != mptepa) { 2726 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2727 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2728 } 2729 firstpte = PADDR2; 2730 } 2731 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2732 KASSERT((oldpde & PG_A) != 0, 2733 ("pmap_demote_pde: oldpde is missing PG_A")); 2734 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2735 ("pmap_demote_pde: oldpde is missing PG_M")); 2736 newpte = oldpde & ~PG_PS; 2737 if ((newpte & PG_PDE_PAT) != 0) 2738 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2739 2740 /* 2741 * If the page table page is new, initialize it. 2742 */ 2743 if (mpte->wire_count == 1) { 2744 mpte->wire_count = NPTEPG; 2745 pmap_fill_ptp(firstpte, newpte); 2746 } 2747 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2748 ("pmap_demote_pde: firstpte and newpte map different physical" 2749 " addresses")); 2750 2751 /* 2752 * If the mapping has changed attributes, update the page table 2753 * entries. 2754 */ 2755 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2756 pmap_fill_ptp(firstpte, newpte); 2757 2758 /* 2759 * Demote the mapping. This pmap is locked. The old PDE has 2760 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2761 * set. Thus, there is no danger of a race with another 2762 * processor changing the setting of PG_A and/or PG_M between 2763 * the read above and the store below. 2764 */ 2765 if (workaround_erratum383) 2766 pmap_update_pde(pmap, va, pde, newpde); 2767 else if (pmap == kernel_pmap) 2768 pmap_kenter_pde(va, newpde); 2769 else 2770 pde_store(pde, newpde); 2771 if (firstpte == PADDR2) 2772 mtx_unlock(&PMAP2mutex); 2773 2774 /* 2775 * Invalidate the recursive mapping of the page table page. 2776 */ 2777 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2778 2779 /* 2780 * Demote the pv entry. This depends on the earlier demotion 2781 * of the mapping. Specifically, the (re)creation of a per- 2782 * page pv entry might trigger the execution of pmap_collect(), 2783 * which might reclaim a newly (re)created per-page pv entry 2784 * and destroy the associated mapping. In order to destroy 2785 * the mapping, the PDE must have already changed from mapping 2786 * the 2mpage to referencing the page table page. 2787 */ 2788 if ((oldpde & PG_MANAGED) != 0) 2789 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2790 2791 pmap_pde_demotions++; 2792 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2793 " in pmap %p", va, pmap); 2794 return (TRUE); 2795} 2796 2797/* 2798 * Removes a 2- or 4MB page mapping from the kernel pmap. 2799 */ 2800static void 2801pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2802{ 2803 pd_entry_t newpde; 2804 vm_paddr_t mptepa; 2805 vm_page_t mpte; 2806 2807 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2808 mpte = pmap_remove_pt_page(pmap, va); 2809 if (mpte == NULL) 2810 panic("pmap_remove_kernel_pde: Missing pt page."); 2811 2812 mptepa = VM_PAGE_TO_PHYS(mpte); 2813 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V; 2814 2815 /* 2816 * Initialize the page table page. 2817 */ 2818 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]); 2819 2820 /* 2821 * Remove the mapping. 2822 */ 2823 if (workaround_erratum383) 2824 pmap_update_pde(pmap, va, pde, newpde); 2825 else 2826 pmap_kenter_pde(va, newpde); 2827 2828 /* 2829 * Invalidate the recursive mapping of the page table page. 2830 */ 2831 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2832} 2833 2834/* 2835 * pmap_remove_pde: do the things to unmap a superpage in a process 2836 */ 2837static void 2838pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2839 struct spglist *free) 2840{ 2841 struct md_page *pvh; 2842 pd_entry_t oldpde; 2843 vm_offset_t eva, va; 2844 vm_page_t m, mpte; 2845 2846 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2847 KASSERT((sva & PDRMASK) == 0, 2848 ("pmap_remove_pde: sva is not 4mpage aligned")); 2849 oldpde = pte_load_clear(pdq); 2850 if (oldpde & PG_W) 2851 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2852 2853 /* 2854 * Machines that don't support invlpg, also don't support 2855 * PG_G. 2856 */ 2857 if ((oldpde & PG_G) != 0) 2858 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 2859 2860 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2861 if (oldpde & PG_MANAGED) { 2862 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2863 pmap_pvh_free(pvh, pmap, sva); 2864 eva = sva + NBPDR; 2865 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2866 va < eva; va += PAGE_SIZE, m++) { 2867 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2868 vm_page_dirty(m); 2869 if (oldpde & PG_A) 2870 vm_page_aflag_set(m, PGA_REFERENCED); 2871 if (TAILQ_EMPTY(&m->md.pv_list) && 2872 TAILQ_EMPTY(&pvh->pv_list)) 2873 vm_page_aflag_clear(m, PGA_WRITEABLE); 2874 } 2875 } 2876 if (pmap == kernel_pmap) { 2877 pmap_remove_kernel_pde(pmap, pdq, sva); 2878 } else { 2879 mpte = pmap_remove_pt_page(pmap, sva); 2880 if (mpte != NULL) { 2881 pmap->pm_stats.resident_count--; 2882 KASSERT(mpte->wire_count == NPTEPG, 2883 ("pmap_remove_pde: pte page wire count error")); 2884 mpte->wire_count = 0; 2885 pmap_add_delayed_free_list(mpte, free, FALSE); 2886 } 2887 } 2888} 2889 2890/* 2891 * pmap_remove_pte: do the things to unmap a page in a process 2892 */ 2893static int 2894pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 2895 struct spglist *free) 2896{ 2897 pt_entry_t oldpte; 2898 vm_page_t m; 2899 2900 rw_assert(&pvh_global_lock, RA_WLOCKED); 2901 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2902 oldpte = pte_load_clear(ptq); 2903 KASSERT(oldpte != 0, 2904 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2905 if (oldpte & PG_W) 2906 pmap->pm_stats.wired_count -= 1; 2907 /* 2908 * Machines that don't support invlpg, also don't support 2909 * PG_G. 2910 */ 2911 if (oldpte & PG_G) 2912 pmap_invalidate_page(kernel_pmap, va); 2913 pmap->pm_stats.resident_count -= 1; 2914 if (oldpte & PG_MANAGED) { 2915 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2916 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2917 vm_page_dirty(m); 2918 if (oldpte & PG_A) 2919 vm_page_aflag_set(m, PGA_REFERENCED); 2920 pmap_remove_entry(pmap, m, va); 2921 } 2922 return (pmap_unuse_pt(pmap, va, free)); 2923} 2924 2925/* 2926 * Remove a single page from a process address space 2927 */ 2928static void 2929pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free) 2930{ 2931 pt_entry_t *pte; 2932 2933 rw_assert(&pvh_global_lock, RA_WLOCKED); 2934 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2935 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2936 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2937 return; 2938 pmap_remove_pte(pmap, pte, va, free); 2939 pmap_invalidate_page(pmap, va); 2940} 2941 2942/* 2943 * Remove the given range of addresses from the specified map. 2944 * 2945 * It is assumed that the start and end are properly 2946 * rounded to the page size. 2947 */ 2948void 2949pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2950{ 2951 vm_offset_t pdnxt; 2952 pd_entry_t ptpaddr; 2953 pt_entry_t *pte; 2954 struct spglist free; 2955 int anyvalid; 2956 2957 /* 2958 * Perform an unsynchronized read. This is, however, safe. 2959 */ 2960 if (pmap->pm_stats.resident_count == 0) 2961 return; 2962 2963 anyvalid = 0; 2964 SLIST_INIT(&free); 2965 2966 rw_wlock(&pvh_global_lock); 2967 sched_pin(); 2968 PMAP_LOCK(pmap); 2969 2970 /* 2971 * special handling of removing one page. a very 2972 * common operation and easy to short circuit some 2973 * code. 2974 */ 2975 if ((sva + PAGE_SIZE == eva) && 2976 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2977 pmap_remove_page(pmap, sva, &free); 2978 goto out; 2979 } 2980 2981 for (; sva < eva; sva = pdnxt) { 2982 u_int pdirindex; 2983 2984 /* 2985 * Calculate index for next page table. 2986 */ 2987 pdnxt = (sva + NBPDR) & ~PDRMASK; 2988 if (pdnxt < sva) 2989 pdnxt = eva; 2990 if (pmap->pm_stats.resident_count == 0) 2991 break; 2992 2993 pdirindex = sva >> PDRSHIFT; 2994 ptpaddr = pmap->pm_pdir[pdirindex]; 2995 2996 /* 2997 * Weed out invalid mappings. Note: we assume that the page 2998 * directory table is always allocated, and in kernel virtual. 2999 */ 3000 if (ptpaddr == 0) 3001 continue; 3002 3003 /* 3004 * Check for large page. 3005 */ 3006 if ((ptpaddr & PG_PS) != 0) { 3007 /* 3008 * Are we removing the entire large page? If not, 3009 * demote the mapping and fall through. 3010 */ 3011 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3012 /* 3013 * The TLB entry for a PG_G mapping is 3014 * invalidated by pmap_remove_pde(). 3015 */ 3016 if ((ptpaddr & PG_G) == 0) 3017 anyvalid = 1; 3018 pmap_remove_pde(pmap, 3019 &pmap->pm_pdir[pdirindex], sva, &free); 3020 continue; 3021 } else if (!pmap_demote_pde(pmap, 3022 &pmap->pm_pdir[pdirindex], sva)) { 3023 /* The large page mapping was destroyed. */ 3024 continue; 3025 } 3026 } 3027 3028 /* 3029 * Limit our scan to either the end of the va represented 3030 * by the current page table page, or to the end of the 3031 * range being removed. 3032 */ 3033 if (pdnxt > eva) 3034 pdnxt = eva; 3035 3036 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3037 sva += PAGE_SIZE) { 3038 if (*pte == 0) 3039 continue; 3040 3041 /* 3042 * The TLB entry for a PG_G mapping is invalidated 3043 * by pmap_remove_pte(). 3044 */ 3045 if ((*pte & PG_G) == 0) 3046 anyvalid = 1; 3047 if (pmap_remove_pte(pmap, pte, sva, &free)) 3048 break; 3049 } 3050 } 3051out: 3052 sched_unpin(); 3053 if (anyvalid) 3054 pmap_invalidate_all(pmap); 3055 rw_wunlock(&pvh_global_lock); 3056 PMAP_UNLOCK(pmap); 3057 pmap_free_zero_pages(&free); 3058} 3059 3060/* 3061 * Routine: pmap_remove_all 3062 * Function: 3063 * Removes this physical page from 3064 * all physical maps in which it resides. 3065 * Reflects back modify bits to the pager. 3066 * 3067 * Notes: 3068 * Original versions of this routine were very 3069 * inefficient because they iteratively called 3070 * pmap_remove (slow...) 3071 */ 3072 3073void 3074pmap_remove_all(vm_page_t m) 3075{ 3076 struct md_page *pvh; 3077 pv_entry_t pv; 3078 pmap_t pmap; 3079 pt_entry_t *pte, tpte; 3080 pd_entry_t *pde; 3081 vm_offset_t va; 3082 struct spglist free; 3083 3084 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3085 ("pmap_remove_all: page %p is not managed", m)); 3086 SLIST_INIT(&free); 3087 rw_wlock(&pvh_global_lock); 3088 sched_pin(); 3089 if ((m->flags & PG_FICTITIOUS) != 0) 3090 goto small_mappings; 3091 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3092 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3093 va = pv->pv_va; 3094 pmap = PV_PMAP(pv); 3095 PMAP_LOCK(pmap); 3096 pde = pmap_pde(pmap, va); 3097 (void)pmap_demote_pde(pmap, pde, va); 3098 PMAP_UNLOCK(pmap); 3099 } 3100small_mappings: 3101 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3102 pmap = PV_PMAP(pv); 3103 PMAP_LOCK(pmap); 3104 pmap->pm_stats.resident_count--; 3105 pde = pmap_pde(pmap, pv->pv_va); 3106 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3107 " a 4mpage in page %p's pv list", m)); 3108 pte = pmap_pte_quick(pmap, pv->pv_va); 3109 tpte = pte_load_clear(pte); 3110 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 3111 pmap, pv->pv_va)); 3112 if (tpte & PG_W) 3113 pmap->pm_stats.wired_count--; 3114 if (tpte & PG_A) 3115 vm_page_aflag_set(m, PGA_REFERENCED); 3116 3117 /* 3118 * Update the vm_page_t clean and reference bits. 3119 */ 3120 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3121 vm_page_dirty(m); 3122 pmap_unuse_pt(pmap, pv->pv_va, &free); 3123 pmap_invalidate_page(pmap, pv->pv_va); 3124 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3125 free_pv_entry(pmap, pv); 3126 PMAP_UNLOCK(pmap); 3127 } 3128 vm_page_aflag_clear(m, PGA_WRITEABLE); 3129 sched_unpin(); 3130 rw_wunlock(&pvh_global_lock); 3131 pmap_free_zero_pages(&free); 3132} 3133 3134/* 3135 * pmap_protect_pde: do the things to protect a 4mpage in a process 3136 */ 3137static boolean_t 3138pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3139{ 3140 pd_entry_t newpde, oldpde; 3141 vm_offset_t eva, va; 3142 vm_page_t m; 3143 boolean_t anychanged; 3144 3145 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3146 KASSERT((sva & PDRMASK) == 0, 3147 ("pmap_protect_pde: sva is not 4mpage aligned")); 3148 anychanged = FALSE; 3149retry: 3150 oldpde = newpde = *pde; 3151 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) == 3152 (PG_MANAGED | PG_M | PG_RW)) { 3153 eva = sva + NBPDR; 3154 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3155 va < eva; va += PAGE_SIZE, m++) 3156 vm_page_dirty(m); 3157 } 3158 if ((prot & VM_PROT_WRITE) == 0) 3159 newpde &= ~(PG_RW | PG_M); 3160#if defined(PAE) || defined(PAE_TABLES) 3161 if ((prot & VM_PROT_EXECUTE) == 0) 3162 newpde |= pg_nx; 3163#endif 3164 if (newpde != oldpde) { 3165 /* 3166 * As an optimization to future operations on this PDE, clear 3167 * PG_PROMOTED. The impending invalidation will remove any 3168 * lingering 4KB page mappings from the TLB. 3169 */ 3170 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED)) 3171 goto retry; 3172 if ((oldpde & PG_G) != 0) 3173 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 3174 else 3175 anychanged = TRUE; 3176 } 3177 return (anychanged); 3178} 3179 3180/* 3181 * Set the physical protection on the 3182 * specified range of this map as requested. 3183 */ 3184void 3185pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3186{ 3187 vm_offset_t pdnxt; 3188 pd_entry_t ptpaddr; 3189 pt_entry_t *pte; 3190 boolean_t anychanged, pv_lists_locked; 3191 3192 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 3193 if (prot == VM_PROT_NONE) { 3194 pmap_remove(pmap, sva, eva); 3195 return; 3196 } 3197 3198#if defined(PAE) || defined(PAE_TABLES) 3199 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3200 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3201 return; 3202#else 3203 if (prot & VM_PROT_WRITE) 3204 return; 3205#endif 3206 3207 if (pmap_is_current(pmap)) 3208 pv_lists_locked = FALSE; 3209 else { 3210 pv_lists_locked = TRUE; 3211resume: 3212 rw_wlock(&pvh_global_lock); 3213 sched_pin(); 3214 } 3215 anychanged = FALSE; 3216 3217 PMAP_LOCK(pmap); 3218 for (; sva < eva; sva = pdnxt) { 3219 pt_entry_t obits, pbits; 3220 u_int pdirindex; 3221 3222 pdnxt = (sva + NBPDR) & ~PDRMASK; 3223 if (pdnxt < sva) 3224 pdnxt = eva; 3225 3226 pdirindex = sva >> PDRSHIFT; 3227 ptpaddr = pmap->pm_pdir[pdirindex]; 3228 3229 /* 3230 * Weed out invalid mappings. Note: we assume that the page 3231 * directory table is always allocated, and in kernel virtual. 3232 */ 3233 if (ptpaddr == 0) 3234 continue; 3235 3236 /* 3237 * Check for large page. 3238 */ 3239 if ((ptpaddr & PG_PS) != 0) { 3240 /* 3241 * Are we protecting the entire large page? If not, 3242 * demote the mapping and fall through. 3243 */ 3244 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3245 /* 3246 * The TLB entry for a PG_G mapping is 3247 * invalidated by pmap_protect_pde(). 3248 */ 3249 if (pmap_protect_pde(pmap, 3250 &pmap->pm_pdir[pdirindex], sva, prot)) 3251 anychanged = TRUE; 3252 continue; 3253 } else { 3254 if (!pv_lists_locked) { 3255 pv_lists_locked = TRUE; 3256 if (!rw_try_wlock(&pvh_global_lock)) { 3257 if (anychanged) 3258 pmap_invalidate_all( 3259 pmap); 3260 PMAP_UNLOCK(pmap); 3261 goto resume; 3262 } 3263 sched_pin(); 3264 } 3265 if (!pmap_demote_pde(pmap, 3266 &pmap->pm_pdir[pdirindex], sva)) { 3267 /* 3268 * The large page mapping was 3269 * destroyed. 3270 */ 3271 continue; 3272 } 3273 } 3274 } 3275 3276 if (pdnxt > eva) 3277 pdnxt = eva; 3278 3279 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3280 sva += PAGE_SIZE) { 3281 vm_page_t m; 3282 3283retry: 3284 /* 3285 * Regardless of whether a pte is 32 or 64 bits in 3286 * size, PG_RW, PG_A, and PG_M are among the least 3287 * significant 32 bits. 3288 */ 3289 obits = pbits = *pte; 3290 if ((pbits & PG_V) == 0) 3291 continue; 3292 3293 if ((prot & VM_PROT_WRITE) == 0) { 3294 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3295 (PG_MANAGED | PG_M | PG_RW)) { 3296 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3297 vm_page_dirty(m); 3298 } 3299 pbits &= ~(PG_RW | PG_M); 3300 } 3301#if defined(PAE) || defined(PAE_TABLES) 3302 if ((prot & VM_PROT_EXECUTE) == 0) 3303 pbits |= pg_nx; 3304#endif 3305 3306 if (pbits != obits) { 3307#if defined(PAE) || defined(PAE_TABLES) 3308 if (!atomic_cmpset_64(pte, obits, pbits)) 3309 goto retry; 3310#else 3311 if (!atomic_cmpset_int((u_int *)pte, obits, 3312 pbits)) 3313 goto retry; 3314#endif 3315 if (obits & PG_G) 3316 pmap_invalidate_page(pmap, sva); 3317 else 3318 anychanged = TRUE; 3319 } 3320 } 3321 } 3322 if (anychanged) 3323 pmap_invalidate_all(pmap); 3324 if (pv_lists_locked) { 3325 sched_unpin(); 3326 rw_wunlock(&pvh_global_lock); 3327 } 3328 PMAP_UNLOCK(pmap); 3329} 3330 3331#if VM_NRESERVLEVEL > 0 3332/* 3333 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3334 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3335 * For promotion to occur, two conditions must be met: (1) the 4KB page 3336 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3337 * mappings must have identical characteristics. 3338 * 3339 * Managed (PG_MANAGED) mappings within the kernel address space are not 3340 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3341 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3342 * pmap. 3343 */ 3344static void 3345pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3346{ 3347 pd_entry_t newpde; 3348 pt_entry_t *firstpte, oldpte, pa, *pte; 3349 vm_offset_t oldpteva; 3350 vm_page_t mpte; 3351 3352 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3353 3354 /* 3355 * Examine the first PTE in the specified PTP. Abort if this PTE is 3356 * either invalid, unused, or does not map the first 4KB physical page 3357 * within a 2- or 4MB page. 3358 */ 3359 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3360setpde: 3361 newpde = *firstpte; 3362 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3363 pmap_pde_p_failures++; 3364 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3365 " in pmap %p", va, pmap); 3366 return; 3367 } 3368 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3369 pmap_pde_p_failures++; 3370 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3371 " in pmap %p", va, pmap); 3372 return; 3373 } 3374 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3375 /* 3376 * When PG_M is already clear, PG_RW can be cleared without 3377 * a TLB invalidation. 3378 */ 3379 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3380 ~PG_RW)) 3381 goto setpde; 3382 newpde &= ~PG_RW; 3383 } 3384 3385 /* 3386 * Examine each of the other PTEs in the specified PTP. Abort if this 3387 * PTE maps an unexpected 4KB physical page or does not have identical 3388 * characteristics to the first PTE. 3389 */ 3390 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3391 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3392setpte: 3393 oldpte = *pte; 3394 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3395 pmap_pde_p_failures++; 3396 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3397 " in pmap %p", va, pmap); 3398 return; 3399 } 3400 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3401 /* 3402 * When PG_M is already clear, PG_RW can be cleared 3403 * without a TLB invalidation. 3404 */ 3405 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3406 oldpte & ~PG_RW)) 3407 goto setpte; 3408 oldpte &= ~PG_RW; 3409 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3410 (va & ~PDRMASK); 3411 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3412 " in pmap %p", oldpteva, pmap); 3413 } 3414 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3415 pmap_pde_p_failures++; 3416 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3417 " in pmap %p", va, pmap); 3418 return; 3419 } 3420 pa -= PAGE_SIZE; 3421 } 3422 3423 /* 3424 * Save the page table page in its current state until the PDE 3425 * mapping the superpage is demoted by pmap_demote_pde() or 3426 * destroyed by pmap_remove_pde(). 3427 */ 3428 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3429 KASSERT(mpte >= vm_page_array && 3430 mpte < &vm_page_array[vm_page_array_size], 3431 ("pmap_promote_pde: page table page is out of range")); 3432 KASSERT(mpte->pindex == va >> PDRSHIFT, 3433 ("pmap_promote_pde: page table page's pindex is wrong")); 3434 if (pmap_insert_pt_page(pmap, mpte)) { 3435 pmap_pde_p_failures++; 3436 CTR2(KTR_PMAP, 3437 "pmap_promote_pde: failure for va %#x in pmap %p", va, 3438 pmap); 3439 return; 3440 } 3441 3442 /* 3443 * Promote the pv entries. 3444 */ 3445 if ((newpde & PG_MANAGED) != 0) 3446 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3447 3448 /* 3449 * Propagate the PAT index to its proper position. 3450 */ 3451 if ((newpde & PG_PTE_PAT) != 0) 3452 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3453 3454 /* 3455 * Map the superpage. 3456 */ 3457 if (workaround_erratum383) 3458 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3459 else if (pmap == kernel_pmap) 3460 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde); 3461 else 3462 pde_store(pde, PG_PROMOTED | PG_PS | newpde); 3463 3464 pmap_pde_promotions++; 3465 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3466 " in pmap %p", va, pmap); 3467} 3468#endif /* VM_NRESERVLEVEL > 0 */ 3469 3470/* 3471 * Insert the given physical page (p) at 3472 * the specified virtual address (v) in the 3473 * target physical map with the protection requested. 3474 * 3475 * If specified, the page will be wired down, meaning 3476 * that the related pte can not be reclaimed. 3477 * 3478 * NB: This is the only routine which MAY NOT lazy-evaluate 3479 * or lose information. That is, this routine must actually 3480 * insert this page into the given map NOW. 3481 */ 3482int 3483pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3484 u_int flags, int8_t psind) 3485{ 3486 pd_entry_t *pde; 3487 pt_entry_t *pte; 3488 pt_entry_t newpte, origpte; 3489 pv_entry_t pv; 3490 vm_paddr_t opa, pa; 3491 vm_page_t mpte, om; 3492 boolean_t invlva, wired; 3493 3494 va = trunc_page(va); 3495 mpte = NULL; 3496 wired = (flags & PMAP_ENTER_WIRED) != 0; 3497 3498 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3499 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3500 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3501 va)); 3502 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3503 VM_OBJECT_ASSERT_LOCKED(m->object); 3504 3505 rw_wlock(&pvh_global_lock); 3506 PMAP_LOCK(pmap); 3507 sched_pin(); 3508 3509 pde = pmap_pde(pmap, va); 3510 if (va < VM_MAXUSER_ADDRESS) { 3511 /* 3512 * va is for UVA. 3513 * In the case that a page table page is not resident, 3514 * we are creating it here. pmap_allocpte() handles 3515 * demotion. 3516 */ 3517 mpte = pmap_allocpte(pmap, va, flags); 3518 if (mpte == NULL) { 3519 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 3520 ("pmap_allocpte failed with sleep allowed")); 3521 sched_unpin(); 3522 rw_wunlock(&pvh_global_lock); 3523 PMAP_UNLOCK(pmap); 3524 return (KERN_RESOURCE_SHORTAGE); 3525 } 3526 } else { 3527 /* 3528 * va is for KVA, so pmap_demote_pde() will never fail 3529 * to install a page table page. PG_V is also 3530 * asserted by pmap_demote_pde(). 3531 */ 3532 KASSERT(pde != NULL && (*pde & PG_V) != 0, 3533 ("KVA %#x invalid pde pdir %#jx", va, 3534 (uintmax_t)pmap->pm_pdir[PTDPTDI])); 3535 if ((*pde & PG_PS) != 0) 3536 pmap_demote_pde(pmap, pde, va); 3537 } 3538 pte = pmap_pte_quick(pmap, va); 3539 3540 /* 3541 * Page Directory table entry is not valid, which should not 3542 * happen. We should have either allocated the page table 3543 * page or demoted the existing mapping above. 3544 */ 3545 if (pte == NULL) { 3546 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3547 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3548 } 3549 3550 pa = VM_PAGE_TO_PHYS(m); 3551 om = NULL; 3552 origpte = *pte; 3553 opa = origpte & PG_FRAME; 3554 3555 /* 3556 * Mapping has not changed, must be protection or wiring change. 3557 */ 3558 if (origpte && (opa == pa)) { 3559 /* 3560 * Wiring change, just update stats. We don't worry about 3561 * wiring PT pages as they remain resident as long as there 3562 * are valid mappings in them. Hence, if a user page is wired, 3563 * the PT page will be also. 3564 */ 3565 if (wired && ((origpte & PG_W) == 0)) 3566 pmap->pm_stats.wired_count++; 3567 else if (!wired && (origpte & PG_W)) 3568 pmap->pm_stats.wired_count--; 3569 3570 /* 3571 * Remove extra pte reference 3572 */ 3573 if (mpte) 3574 mpte->wire_count--; 3575 3576 if (origpte & PG_MANAGED) { 3577 om = m; 3578 pa |= PG_MANAGED; 3579 } 3580 goto validate; 3581 } 3582 3583 pv = NULL; 3584 3585 /* 3586 * Mapping has changed, invalidate old range and fall through to 3587 * handle validating new mapping. 3588 */ 3589 if (opa) { 3590 if (origpte & PG_W) 3591 pmap->pm_stats.wired_count--; 3592 if (origpte & PG_MANAGED) { 3593 om = PHYS_TO_VM_PAGE(opa); 3594 pv = pmap_pvh_remove(&om->md, pmap, va); 3595 } 3596 if (mpte != NULL) { 3597 mpte->wire_count--; 3598 KASSERT(mpte->wire_count > 0, 3599 ("pmap_enter: missing reference to page table page," 3600 " va: 0x%x", va)); 3601 } 3602 } else 3603 pmap->pm_stats.resident_count++; 3604 3605 /* 3606 * Enter on the PV list if part of our managed memory. 3607 */ 3608 if ((m->oflags & VPO_UNMANAGED) == 0) { 3609 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3610 ("pmap_enter: managed mapping within the clean submap")); 3611 if (pv == NULL) 3612 pv = get_pv_entry(pmap, FALSE); 3613 pv->pv_va = va; 3614 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3615 pa |= PG_MANAGED; 3616 } else if (pv != NULL) 3617 free_pv_entry(pmap, pv); 3618 3619 /* 3620 * Increment counters 3621 */ 3622 if (wired) 3623 pmap->pm_stats.wired_count++; 3624 3625validate: 3626 /* 3627 * Now validate mapping with desired protection/wiring. 3628 */ 3629 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3630 if ((prot & VM_PROT_WRITE) != 0) { 3631 newpte |= PG_RW; 3632 if ((newpte & PG_MANAGED) != 0) 3633 vm_page_aflag_set(m, PGA_WRITEABLE); 3634 } 3635#if defined(PAE) || defined(PAE_TABLES) 3636 if ((prot & VM_PROT_EXECUTE) == 0) 3637 newpte |= pg_nx; 3638#endif 3639 if (wired) 3640 newpte |= PG_W; 3641 if (va < VM_MAXUSER_ADDRESS) 3642 newpte |= PG_U; 3643 if (pmap == kernel_pmap) 3644 newpte |= pgeflag; 3645 3646 /* 3647 * if the mapping or permission bits are different, we need 3648 * to update the pte. 3649 */ 3650 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3651 newpte |= PG_A; 3652 if ((flags & VM_PROT_WRITE) != 0) 3653 newpte |= PG_M; 3654 if (origpte & PG_V) { 3655 invlva = FALSE; 3656 origpte = pte_load_store(pte, newpte); 3657 if (origpte & PG_A) { 3658 if (origpte & PG_MANAGED) 3659 vm_page_aflag_set(om, PGA_REFERENCED); 3660 if (opa != VM_PAGE_TO_PHYS(m)) 3661 invlva = TRUE; 3662#if defined(PAE) || defined(PAE_TABLES) 3663 if ((origpte & PG_NX) == 0 && 3664 (newpte & PG_NX) != 0) 3665 invlva = TRUE; 3666#endif 3667 } 3668 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3669 if ((origpte & PG_MANAGED) != 0) 3670 vm_page_dirty(om); 3671 if ((prot & VM_PROT_WRITE) == 0) 3672 invlva = TRUE; 3673 } 3674 if ((origpte & PG_MANAGED) != 0 && 3675 TAILQ_EMPTY(&om->md.pv_list) && 3676 ((om->flags & PG_FICTITIOUS) != 0 || 3677 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3678 vm_page_aflag_clear(om, PGA_WRITEABLE); 3679 if (invlva) 3680 pmap_invalidate_page(pmap, va); 3681 } else 3682 pte_store(pte, newpte); 3683 } 3684 3685#if VM_NRESERVLEVEL > 0 3686 /* 3687 * If both the page table page and the reservation are fully 3688 * populated, then attempt promotion. 3689 */ 3690 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3691 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3692 vm_reserv_level_iffullpop(m) == 0) 3693 pmap_promote_pde(pmap, pde, va); 3694#endif 3695 3696 sched_unpin(); 3697 rw_wunlock(&pvh_global_lock); 3698 PMAP_UNLOCK(pmap); 3699 return (KERN_SUCCESS); 3700} 3701 3702/* 3703 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3704 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3705 * blocking, (2) a mapping already exists at the specified virtual address, or 3706 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3707 */ 3708static boolean_t 3709pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3710{ 3711 pd_entry_t *pde, newpde; 3712 3713 rw_assert(&pvh_global_lock, RA_WLOCKED); 3714 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3715 pde = pmap_pde(pmap, va); 3716 if (*pde != 0) { 3717 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3718 " in pmap %p", va, pmap); 3719 return (FALSE); 3720 } 3721 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3722 PG_PS | PG_V; 3723 if ((m->oflags & VPO_UNMANAGED) == 0) { 3724 newpde |= PG_MANAGED; 3725 3726 /* 3727 * Abort this mapping if its PV entry could not be created. 3728 */ 3729 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3730 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3731 " in pmap %p", va, pmap); 3732 return (FALSE); 3733 } 3734 } 3735#if defined(PAE) || defined(PAE_TABLES) 3736 if ((prot & VM_PROT_EXECUTE) == 0) 3737 newpde |= pg_nx; 3738#endif 3739 if (va < VM_MAXUSER_ADDRESS) 3740 newpde |= PG_U; 3741 3742 /* 3743 * Increment counters. 3744 */ 3745 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3746 3747 /* 3748 * Map the superpage. (This is not a promoted mapping; there will not 3749 * be any lingering 4KB page mappings in the TLB.) 3750 */ 3751 pde_store(pde, newpde); 3752 3753 pmap_pde_mappings++; 3754 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3755 " in pmap %p", va, pmap); 3756 return (TRUE); 3757} 3758 3759/* 3760 * Maps a sequence of resident pages belonging to the same object. 3761 * The sequence begins with the given page m_start. This page is 3762 * mapped at the given virtual address start. Each subsequent page is 3763 * mapped at a virtual address that is offset from start by the same 3764 * amount as the page is offset from m_start within the object. The 3765 * last page in the sequence is the page with the largest offset from 3766 * m_start that can be mapped at a virtual address less than the given 3767 * virtual address end. Not every virtual page between start and end 3768 * is mapped; only those for which a resident page exists with the 3769 * corresponding offset from m_start are mapped. 3770 */ 3771void 3772pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3773 vm_page_t m_start, vm_prot_t prot) 3774{ 3775 vm_offset_t va; 3776 vm_page_t m, mpte; 3777 vm_pindex_t diff, psize; 3778 3779 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3780 3781 psize = atop(end - start); 3782 mpte = NULL; 3783 m = m_start; 3784 rw_wlock(&pvh_global_lock); 3785 PMAP_LOCK(pmap); 3786 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3787 va = start + ptoa(diff); 3788 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3789 m->psind == 1 && pg_ps_enabled && 3790 pmap_enter_pde(pmap, va, m, prot)) 3791 m = &m[NBPDR / PAGE_SIZE - 1]; 3792 else 3793 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3794 mpte); 3795 m = TAILQ_NEXT(m, listq); 3796 } 3797 rw_wunlock(&pvh_global_lock); 3798 PMAP_UNLOCK(pmap); 3799} 3800 3801/* 3802 * this code makes some *MAJOR* assumptions: 3803 * 1. Current pmap & pmap exists. 3804 * 2. Not wired. 3805 * 3. Read access. 3806 * 4. No page table pages. 3807 * but is *MUCH* faster than pmap_enter... 3808 */ 3809 3810void 3811pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3812{ 3813 3814 rw_wlock(&pvh_global_lock); 3815 PMAP_LOCK(pmap); 3816 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3817 rw_wunlock(&pvh_global_lock); 3818 PMAP_UNLOCK(pmap); 3819} 3820 3821static vm_page_t 3822pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3823 vm_prot_t prot, vm_page_t mpte) 3824{ 3825 pt_entry_t *pte; 3826 vm_paddr_t pa; 3827 struct spglist free; 3828 3829 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3830 (m->oflags & VPO_UNMANAGED) != 0, 3831 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3832 rw_assert(&pvh_global_lock, RA_WLOCKED); 3833 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3834 3835 /* 3836 * In the case that a page table page is not 3837 * resident, we are creating it here. 3838 */ 3839 if (va < VM_MAXUSER_ADDRESS) { 3840 u_int ptepindex; 3841 pd_entry_t ptepa; 3842 3843 /* 3844 * Calculate pagetable page index 3845 */ 3846 ptepindex = va >> PDRSHIFT; 3847 if (mpte && (mpte->pindex == ptepindex)) { 3848 mpte->wire_count++; 3849 } else { 3850 /* 3851 * Get the page directory entry 3852 */ 3853 ptepa = pmap->pm_pdir[ptepindex]; 3854 3855 /* 3856 * If the page table page is mapped, we just increment 3857 * the hold count, and activate it. 3858 */ 3859 if (ptepa) { 3860 if (ptepa & PG_PS) 3861 return (NULL); 3862 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3863 mpte->wire_count++; 3864 } else { 3865 mpte = _pmap_allocpte(pmap, ptepindex, 3866 PMAP_ENTER_NOSLEEP); 3867 if (mpte == NULL) 3868 return (mpte); 3869 } 3870 } 3871 } else { 3872 mpte = NULL; 3873 } 3874 3875 /* 3876 * This call to vtopte makes the assumption that we are 3877 * entering the page into the current pmap. In order to support 3878 * quick entry into any pmap, one would likely use pmap_pte_quick. 3879 * But that isn't as quick as vtopte. 3880 */ 3881 pte = vtopte(va); 3882 if (*pte) { 3883 if (mpte != NULL) { 3884 mpte->wire_count--; 3885 mpte = NULL; 3886 } 3887 return (mpte); 3888 } 3889 3890 /* 3891 * Enter on the PV list if part of our managed memory. 3892 */ 3893 if ((m->oflags & VPO_UNMANAGED) == 0 && 3894 !pmap_try_insert_pv_entry(pmap, va, m)) { 3895 if (mpte != NULL) { 3896 SLIST_INIT(&free); 3897 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3898 pmap_invalidate_page(pmap, va); 3899 pmap_free_zero_pages(&free); 3900 } 3901 3902 mpte = NULL; 3903 } 3904 return (mpte); 3905 } 3906 3907 /* 3908 * Increment counters 3909 */ 3910 pmap->pm_stats.resident_count++; 3911 3912 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3913#if defined(PAE) || defined(PAE_TABLES) 3914 if ((prot & VM_PROT_EXECUTE) == 0) 3915 pa |= pg_nx; 3916#endif 3917 3918 /* 3919 * Now validate mapping with RO protection 3920 */ 3921 if ((m->oflags & VPO_UNMANAGED) != 0) 3922 pte_store(pte, pa | PG_V | PG_U); 3923 else 3924 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3925 return (mpte); 3926} 3927 3928/* 3929 * Make a temporary mapping for a physical address. This is only intended 3930 * to be used for panic dumps. 3931 */ 3932void * 3933pmap_kenter_temporary(vm_paddr_t pa, int i) 3934{ 3935 vm_offset_t va; 3936 3937 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3938 pmap_kenter(va, pa); 3939 invlpg(va); 3940 return ((void *)crashdumpmap); 3941} 3942 3943/* 3944 * This code maps large physical mmap regions into the 3945 * processor address space. Note that some shortcuts 3946 * are taken, but the code works. 3947 */ 3948void 3949pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3950 vm_pindex_t pindex, vm_size_t size) 3951{ 3952 pd_entry_t *pde; 3953 vm_paddr_t pa, ptepa; 3954 vm_page_t p; 3955 int pat_mode; 3956 3957 VM_OBJECT_ASSERT_WLOCKED(object); 3958 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3959 ("pmap_object_init_pt: non-device object")); 3960 if (pseflag && 3961 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3962 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3963 return; 3964 p = vm_page_lookup(object, pindex); 3965 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3966 ("pmap_object_init_pt: invalid page %p", p)); 3967 pat_mode = p->md.pat_mode; 3968 3969 /* 3970 * Abort the mapping if the first page is not physically 3971 * aligned to a 2/4MB page boundary. 3972 */ 3973 ptepa = VM_PAGE_TO_PHYS(p); 3974 if (ptepa & (NBPDR - 1)) 3975 return; 3976 3977 /* 3978 * Skip the first page. Abort the mapping if the rest of 3979 * the pages are not physically contiguous or have differing 3980 * memory attributes. 3981 */ 3982 p = TAILQ_NEXT(p, listq); 3983 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3984 pa += PAGE_SIZE) { 3985 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3986 ("pmap_object_init_pt: invalid page %p", p)); 3987 if (pa != VM_PAGE_TO_PHYS(p) || 3988 pat_mode != p->md.pat_mode) 3989 return; 3990 p = TAILQ_NEXT(p, listq); 3991 } 3992 3993 /* 3994 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3995 * "size" is a multiple of 2/4M, adding the PAT setting to 3996 * "pa" will not affect the termination of this loop. 3997 */ 3998 PMAP_LOCK(pmap); 3999 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 4000 size; pa += NBPDR) { 4001 pde = pmap_pde(pmap, addr); 4002 if (*pde == 0) { 4003 pde_store(pde, pa | PG_PS | PG_M | PG_A | 4004 PG_U | PG_RW | PG_V); 4005 pmap->pm_stats.resident_count += NBPDR / 4006 PAGE_SIZE; 4007 pmap_pde_mappings++; 4008 } 4009 /* Else continue on if the PDE is already valid. */ 4010 addr += NBPDR; 4011 } 4012 PMAP_UNLOCK(pmap); 4013 } 4014} 4015 4016/* 4017 * Clear the wired attribute from the mappings for the specified range of 4018 * addresses in the given pmap. Every valid mapping within that range 4019 * must have the wired attribute set. In contrast, invalid mappings 4020 * cannot have the wired attribute set, so they are ignored. 4021 * 4022 * The wired attribute of the page table entry is not a hardware feature, 4023 * so there is no need to invalidate any TLB entries. 4024 */ 4025void 4026pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 4027{ 4028 vm_offset_t pdnxt; 4029 pd_entry_t *pde; 4030 pt_entry_t *pte; 4031 boolean_t pv_lists_locked; 4032 4033 if (pmap_is_current(pmap)) 4034 pv_lists_locked = FALSE; 4035 else { 4036 pv_lists_locked = TRUE; 4037resume: 4038 rw_wlock(&pvh_global_lock); 4039 sched_pin(); 4040 } 4041 PMAP_LOCK(pmap); 4042 for (; sva < eva; sva = pdnxt) { 4043 pdnxt = (sva + NBPDR) & ~PDRMASK; 4044 if (pdnxt < sva) 4045 pdnxt = eva; 4046 pde = pmap_pde(pmap, sva); 4047 if ((*pde & PG_V) == 0) 4048 continue; 4049 if ((*pde & PG_PS) != 0) { 4050 if ((*pde & PG_W) == 0) 4051 panic("pmap_unwire: pde %#jx is missing PG_W", 4052 (uintmax_t)*pde); 4053 4054 /* 4055 * Are we unwiring the entire large page? If not, 4056 * demote the mapping and fall through. 4057 */ 4058 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 4059 /* 4060 * Regardless of whether a pde (or pte) is 32 4061 * or 64 bits in size, PG_W is among the least 4062 * significant 32 bits. 4063 */ 4064 atomic_clear_int((u_int *)pde, PG_W); 4065 pmap->pm_stats.wired_count -= NBPDR / 4066 PAGE_SIZE; 4067 continue; 4068 } else { 4069 if (!pv_lists_locked) { 4070 pv_lists_locked = TRUE; 4071 if (!rw_try_wlock(&pvh_global_lock)) { 4072 PMAP_UNLOCK(pmap); 4073 /* Repeat sva. */ 4074 goto resume; 4075 } 4076 sched_pin(); 4077 } 4078 if (!pmap_demote_pde(pmap, pde, sva)) 4079 panic("pmap_unwire: demotion failed"); 4080 } 4081 } 4082 if (pdnxt > eva) 4083 pdnxt = eva; 4084 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 4085 sva += PAGE_SIZE) { 4086 if ((*pte & PG_V) == 0) 4087 continue; 4088 if ((*pte & PG_W) == 0) 4089 panic("pmap_unwire: pte %#jx is missing PG_W", 4090 (uintmax_t)*pte); 4091 4092 /* 4093 * PG_W must be cleared atomically. Although the pmap 4094 * lock synchronizes access to PG_W, another processor 4095 * could be setting PG_M and/or PG_A concurrently. 4096 * 4097 * PG_W is among the least significant 32 bits. 4098 */ 4099 atomic_clear_int((u_int *)pte, PG_W); 4100 pmap->pm_stats.wired_count--; 4101 } 4102 } 4103 if (pv_lists_locked) { 4104 sched_unpin(); 4105 rw_wunlock(&pvh_global_lock); 4106 } 4107 PMAP_UNLOCK(pmap); 4108} 4109 4110 4111/* 4112 * Copy the range specified by src_addr/len 4113 * from the source map to the range dst_addr/len 4114 * in the destination map. 4115 * 4116 * This routine is only advisory and need not do anything. 4117 */ 4118 4119void 4120pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4121 vm_offset_t src_addr) 4122{ 4123 struct spglist free; 4124 vm_offset_t addr; 4125 vm_offset_t end_addr = src_addr + len; 4126 vm_offset_t pdnxt; 4127 4128 if (dst_addr != src_addr) 4129 return; 4130 4131 if (!pmap_is_current(src_pmap)) 4132 return; 4133 4134 rw_wlock(&pvh_global_lock); 4135 if (dst_pmap < src_pmap) { 4136 PMAP_LOCK(dst_pmap); 4137 PMAP_LOCK(src_pmap); 4138 } else { 4139 PMAP_LOCK(src_pmap); 4140 PMAP_LOCK(dst_pmap); 4141 } 4142 sched_pin(); 4143 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 4144 pt_entry_t *src_pte, *dst_pte; 4145 vm_page_t dstmpte, srcmpte; 4146 pd_entry_t srcptepaddr; 4147 u_int ptepindex; 4148 4149 KASSERT(addr < UPT_MIN_ADDRESS, 4150 ("pmap_copy: invalid to pmap_copy page tables")); 4151 4152 pdnxt = (addr + NBPDR) & ~PDRMASK; 4153 if (pdnxt < addr) 4154 pdnxt = end_addr; 4155 ptepindex = addr >> PDRSHIFT; 4156 4157 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 4158 if (srcptepaddr == 0) 4159 continue; 4160 4161 if (srcptepaddr & PG_PS) { 4162 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4163 continue; 4164 if (dst_pmap->pm_pdir[ptepindex] == 0 && 4165 ((srcptepaddr & PG_MANAGED) == 0 || 4166 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 4167 PG_PS_FRAME))) { 4168 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 4169 ~PG_W; 4170 dst_pmap->pm_stats.resident_count += 4171 NBPDR / PAGE_SIZE; 4172 pmap_pde_mappings++; 4173 } 4174 continue; 4175 } 4176 4177 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 4178 KASSERT(srcmpte->wire_count > 0, 4179 ("pmap_copy: source page table page is unused")); 4180 4181 if (pdnxt > end_addr) 4182 pdnxt = end_addr; 4183 4184 src_pte = vtopte(addr); 4185 while (addr < pdnxt) { 4186 pt_entry_t ptetemp; 4187 ptetemp = *src_pte; 4188 /* 4189 * we only virtual copy managed pages 4190 */ 4191 if ((ptetemp & PG_MANAGED) != 0) { 4192 dstmpte = pmap_allocpte(dst_pmap, addr, 4193 PMAP_ENTER_NOSLEEP); 4194 if (dstmpte == NULL) 4195 goto out; 4196 dst_pte = pmap_pte_quick(dst_pmap, addr); 4197 if (*dst_pte == 0 && 4198 pmap_try_insert_pv_entry(dst_pmap, addr, 4199 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 4200 /* 4201 * Clear the wired, modified, and 4202 * accessed (referenced) bits 4203 * during the copy. 4204 */ 4205 *dst_pte = ptetemp & ~(PG_W | PG_M | 4206 PG_A); 4207 dst_pmap->pm_stats.resident_count++; 4208 } else { 4209 SLIST_INIT(&free); 4210 if (pmap_unwire_ptp(dst_pmap, dstmpte, 4211 &free)) { 4212 pmap_invalidate_page(dst_pmap, 4213 addr); 4214 pmap_free_zero_pages(&free); 4215 } 4216 goto out; 4217 } 4218 if (dstmpte->wire_count >= srcmpte->wire_count) 4219 break; 4220 } 4221 addr += PAGE_SIZE; 4222 src_pte++; 4223 } 4224 } 4225out: 4226 sched_unpin(); 4227 rw_wunlock(&pvh_global_lock); 4228 PMAP_UNLOCK(src_pmap); 4229 PMAP_UNLOCK(dst_pmap); 4230} 4231 4232static __inline void 4233pagezero(void *page) 4234{ 4235#if defined(I686_CPU) 4236 if (cpu_class == CPUCLASS_686) { 4237 if (cpu_feature & CPUID_SSE2) 4238 sse2_pagezero(page); 4239 else 4240 i686_pagezero(page); 4241 } else 4242#endif 4243 bzero(page, PAGE_SIZE); 4244} 4245 4246/* 4247 * pmap_zero_page zeros the specified hardware page by mapping 4248 * the page into KVM and using bzero to clear its contents. 4249 */ 4250void 4251pmap_zero_page(vm_page_t m) 4252{ 4253 pt_entry_t *cmap_pte2; 4254 struct pcpu *pc; 4255 4256 sched_pin(); 4257 pc = get_pcpu(); 4258 cmap_pte2 = pc->pc_cmap_pte2; 4259 mtx_lock(&pc->pc_cmap_lock); 4260 if (*cmap_pte2) 4261 panic("pmap_zero_page: CMAP2 busy"); 4262 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4263 pmap_cache_bits(m->md.pat_mode, 0); 4264 invlcaddr(pc->pc_cmap_addr2); 4265 pagezero(pc->pc_cmap_addr2); 4266 *cmap_pte2 = 0; 4267 4268 /* 4269 * Unpin the thread before releasing the lock. Otherwise the thread 4270 * could be rescheduled while still bound to the current CPU, only 4271 * to unpin itself immediately upon resuming execution. 4272 */ 4273 sched_unpin(); 4274 mtx_unlock(&pc->pc_cmap_lock); 4275} 4276 4277/* 4278 * pmap_zero_page_area zeros the specified hardware page by mapping 4279 * the page into KVM and using bzero to clear its contents. 4280 * 4281 * off and size may not cover an area beyond a single hardware page. 4282 */ 4283void 4284pmap_zero_page_area(vm_page_t m, int off, int size) 4285{ 4286 pt_entry_t *cmap_pte2; 4287 struct pcpu *pc; 4288 4289 sched_pin(); 4290 pc = get_pcpu(); 4291 cmap_pte2 = pc->pc_cmap_pte2; 4292 mtx_lock(&pc->pc_cmap_lock); 4293 if (*cmap_pte2) 4294 panic("pmap_zero_page_area: CMAP2 busy"); 4295 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4296 pmap_cache_bits(m->md.pat_mode, 0); 4297 invlcaddr(pc->pc_cmap_addr2); 4298 if (off == 0 && size == PAGE_SIZE) 4299 pagezero(pc->pc_cmap_addr2); 4300 else 4301 bzero(pc->pc_cmap_addr2 + off, size); 4302 *cmap_pte2 = 0; 4303 sched_unpin(); 4304 mtx_unlock(&pc->pc_cmap_lock); 4305} 4306 4307/* 4308 * pmap_zero_page_idle zeros the specified hardware page by mapping 4309 * the page into KVM and using bzero to clear its contents. This 4310 * is intended to be called from the vm_pagezero process only and 4311 * outside of Giant. 4312 */ 4313void 4314pmap_zero_page_idle(vm_page_t m) 4315{ 4316 4317 if (*CMAP3) 4318 panic("pmap_zero_page_idle: CMAP3 busy"); 4319 sched_pin(); 4320 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4321 pmap_cache_bits(m->md.pat_mode, 0); 4322 invlcaddr(CADDR3); 4323 pagezero(CADDR3); 4324 *CMAP3 = 0; 4325 sched_unpin(); 4326} 4327 4328/* 4329 * pmap_copy_page copies the specified (machine independent) 4330 * page by mapping the page into virtual memory and using 4331 * bcopy to copy the page, one machine dependent page at a 4332 * time. 4333 */ 4334void 4335pmap_copy_page(vm_page_t src, vm_page_t dst) 4336{ 4337 pt_entry_t *cmap_pte1, *cmap_pte2; 4338 struct pcpu *pc; 4339 4340 sched_pin(); 4341 pc = get_pcpu(); 4342 cmap_pte1 = pc->pc_cmap_pte1; 4343 cmap_pte2 = pc->pc_cmap_pte2; 4344 mtx_lock(&pc->pc_cmap_lock); 4345 if (*cmap_pte1) 4346 panic("pmap_copy_page: CMAP1 busy"); 4347 if (*cmap_pte2) 4348 panic("pmap_copy_page: CMAP2 busy"); 4349 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4350 pmap_cache_bits(src->md.pat_mode, 0); 4351 invlcaddr(pc->pc_cmap_addr1); 4352 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4353 pmap_cache_bits(dst->md.pat_mode, 0); 4354 invlcaddr(pc->pc_cmap_addr2); 4355 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE); 4356 *cmap_pte1 = 0; 4357 *cmap_pte2 = 0; 4358 sched_unpin(); 4359 mtx_unlock(&pc->pc_cmap_lock); 4360} 4361 4362int unmapped_buf_allowed = 1; 4363 4364void 4365pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4366 vm_offset_t b_offset, int xfersize) 4367{ 4368 vm_page_t a_pg, b_pg; 4369 char *a_cp, *b_cp; 4370 vm_offset_t a_pg_offset, b_pg_offset; 4371 pt_entry_t *cmap_pte1, *cmap_pte2; 4372 struct pcpu *pc; 4373 int cnt; 4374 4375 sched_pin(); 4376 pc = get_pcpu(); 4377 cmap_pte1 = pc->pc_cmap_pte1; 4378 cmap_pte2 = pc->pc_cmap_pte2; 4379 mtx_lock(&pc->pc_cmap_lock); 4380 if (*cmap_pte1 != 0) 4381 panic("pmap_copy_pages: CMAP1 busy"); 4382 if (*cmap_pte2 != 0) 4383 panic("pmap_copy_pages: CMAP2 busy"); 4384 while (xfersize > 0) { 4385 a_pg = ma[a_offset >> PAGE_SHIFT]; 4386 a_pg_offset = a_offset & PAGE_MASK; 4387 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4388 b_pg = mb[b_offset >> PAGE_SHIFT]; 4389 b_pg_offset = b_offset & PAGE_MASK; 4390 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4391 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A | 4392 pmap_cache_bits(a_pg->md.pat_mode, 0); 4393 invlcaddr(pc->pc_cmap_addr1); 4394 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A | 4395 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0); 4396 invlcaddr(pc->pc_cmap_addr2); 4397 a_cp = pc->pc_cmap_addr1 + a_pg_offset; 4398 b_cp = pc->pc_cmap_addr2 + b_pg_offset; 4399 bcopy(a_cp, b_cp, cnt); 4400 a_offset += cnt; 4401 b_offset += cnt; 4402 xfersize -= cnt; 4403 } 4404 *cmap_pte1 = 0; 4405 *cmap_pte2 = 0; 4406 sched_unpin(); 4407 mtx_unlock(&pc->pc_cmap_lock); 4408} 4409 4410/* 4411 * Returns true if the pmap's pv is one of the first 4412 * 16 pvs linked to from this page. This count may 4413 * be changed upwards or downwards in the future; it 4414 * is only necessary that true be returned for a small 4415 * subset of pmaps for proper page aging. 4416 */ 4417boolean_t 4418pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4419{ 4420 struct md_page *pvh; 4421 pv_entry_t pv; 4422 int loops = 0; 4423 boolean_t rv; 4424 4425 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4426 ("pmap_page_exists_quick: page %p is not managed", m)); 4427 rv = FALSE; 4428 rw_wlock(&pvh_global_lock); 4429 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4430 if (PV_PMAP(pv) == pmap) { 4431 rv = TRUE; 4432 break; 4433 } 4434 loops++; 4435 if (loops >= 16) 4436 break; 4437 } 4438 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4439 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4440 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4441 if (PV_PMAP(pv) == pmap) { 4442 rv = TRUE; 4443 break; 4444 } 4445 loops++; 4446 if (loops >= 16) 4447 break; 4448 } 4449 } 4450 rw_wunlock(&pvh_global_lock); 4451 return (rv); 4452} 4453 4454/* 4455 * pmap_page_wired_mappings: 4456 * 4457 * Return the number of managed mappings to the given physical page 4458 * that are wired. 4459 */ 4460int 4461pmap_page_wired_mappings(vm_page_t m) 4462{ 4463 int count; 4464 4465 count = 0; 4466 if ((m->oflags & VPO_UNMANAGED) != 0) 4467 return (count); 4468 rw_wlock(&pvh_global_lock); 4469 count = pmap_pvh_wired_mappings(&m->md, count); 4470 if ((m->flags & PG_FICTITIOUS) == 0) { 4471 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4472 count); 4473 } 4474 rw_wunlock(&pvh_global_lock); 4475 return (count); 4476} 4477 4478/* 4479 * pmap_pvh_wired_mappings: 4480 * 4481 * Return the updated number "count" of managed mappings that are wired. 4482 */ 4483static int 4484pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4485{ 4486 pmap_t pmap; 4487 pt_entry_t *pte; 4488 pv_entry_t pv; 4489 4490 rw_assert(&pvh_global_lock, RA_WLOCKED); 4491 sched_pin(); 4492 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4493 pmap = PV_PMAP(pv); 4494 PMAP_LOCK(pmap); 4495 pte = pmap_pte_quick(pmap, pv->pv_va); 4496 if ((*pte & PG_W) != 0) 4497 count++; 4498 PMAP_UNLOCK(pmap); 4499 } 4500 sched_unpin(); 4501 return (count); 4502} 4503 4504/* 4505 * Returns TRUE if the given page is mapped individually or as part of 4506 * a 4mpage. Otherwise, returns FALSE. 4507 */ 4508boolean_t 4509pmap_page_is_mapped(vm_page_t m) 4510{ 4511 boolean_t rv; 4512 4513 if ((m->oflags & VPO_UNMANAGED) != 0) 4514 return (FALSE); 4515 rw_wlock(&pvh_global_lock); 4516 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4517 ((m->flags & PG_FICTITIOUS) == 0 && 4518 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 4519 rw_wunlock(&pvh_global_lock); 4520 return (rv); 4521} 4522 4523/* 4524 * Remove all pages from specified address space 4525 * this aids process exit speeds. Also, this code 4526 * is special cased for current process only, but 4527 * can have the more generic (and slightly slower) 4528 * mode enabled. This is much faster than pmap_remove 4529 * in the case of running down an entire address space. 4530 */ 4531void 4532pmap_remove_pages(pmap_t pmap) 4533{ 4534 pt_entry_t *pte, tpte; 4535 vm_page_t m, mpte, mt; 4536 pv_entry_t pv; 4537 struct md_page *pvh; 4538 struct pv_chunk *pc, *npc; 4539 struct spglist free; 4540 int field, idx; 4541 int32_t bit; 4542 uint32_t inuse, bitmask; 4543 int allfree; 4544 4545 if (pmap != PCPU_GET(curpmap)) { 4546 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4547 return; 4548 } 4549 SLIST_INIT(&free); 4550 rw_wlock(&pvh_global_lock); 4551 PMAP_LOCK(pmap); 4552 sched_pin(); 4553 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4554 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 4555 pc->pc_pmap)); 4556 allfree = 1; 4557 for (field = 0; field < _NPCM; field++) { 4558 inuse = ~pc->pc_map[field] & pc_freemask[field]; 4559 while (inuse != 0) { 4560 bit = bsfl(inuse); 4561 bitmask = 1UL << bit; 4562 idx = field * 32 + bit; 4563 pv = &pc->pc_pventry[idx]; 4564 inuse &= ~bitmask; 4565 4566 pte = pmap_pde(pmap, pv->pv_va); 4567 tpte = *pte; 4568 if ((tpte & PG_PS) == 0) { 4569 pte = vtopte(pv->pv_va); 4570 tpte = *pte & ~PG_PTE_PAT; 4571 } 4572 4573 if (tpte == 0) { 4574 printf( 4575 "TPTE at %p IS ZERO @ VA %08x\n", 4576 pte, pv->pv_va); 4577 panic("bad pte"); 4578 } 4579 4580/* 4581 * We cannot remove wired pages from a process' mapping at this time 4582 */ 4583 if (tpte & PG_W) { 4584 allfree = 0; 4585 continue; 4586 } 4587 4588 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4589 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4590 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4591 m, (uintmax_t)m->phys_addr, 4592 (uintmax_t)tpte)); 4593 4594 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 4595 m < &vm_page_array[vm_page_array_size], 4596 ("pmap_remove_pages: bad tpte %#jx", 4597 (uintmax_t)tpte)); 4598 4599 pte_clear(pte); 4600 4601 /* 4602 * Update the vm_page_t clean/reference bits. 4603 */ 4604 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4605 if ((tpte & PG_PS) != 0) { 4606 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4607 vm_page_dirty(mt); 4608 } else 4609 vm_page_dirty(m); 4610 } 4611 4612 /* Mark free */ 4613 PV_STAT(pv_entry_frees++); 4614 PV_STAT(pv_entry_spare++); 4615 pv_entry_count--; 4616 pc->pc_map[field] |= bitmask; 4617 if ((tpte & PG_PS) != 0) { 4618 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4619 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4620 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4621 if (TAILQ_EMPTY(&pvh->pv_list)) { 4622 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4623 if (TAILQ_EMPTY(&mt->md.pv_list)) 4624 vm_page_aflag_clear(mt, PGA_WRITEABLE); 4625 } 4626 mpte = pmap_remove_pt_page(pmap, pv->pv_va); 4627 if (mpte != NULL) { 4628 pmap->pm_stats.resident_count--; 4629 KASSERT(mpte->wire_count == NPTEPG, 4630 ("pmap_remove_pages: pte page wire count error")); 4631 mpte->wire_count = 0; 4632 pmap_add_delayed_free_list(mpte, &free, FALSE); 4633 } 4634 } else { 4635 pmap->pm_stats.resident_count--; 4636 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4637 if (TAILQ_EMPTY(&m->md.pv_list) && 4638 (m->flags & PG_FICTITIOUS) == 0) { 4639 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4640 if (TAILQ_EMPTY(&pvh->pv_list)) 4641 vm_page_aflag_clear(m, PGA_WRITEABLE); 4642 } 4643 pmap_unuse_pt(pmap, pv->pv_va, &free); 4644 } 4645 } 4646 } 4647 if (allfree) { 4648 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4649 free_pv_chunk(pc); 4650 } 4651 } 4652 sched_unpin(); 4653 pmap_invalidate_all(pmap); 4654 rw_wunlock(&pvh_global_lock); 4655 PMAP_UNLOCK(pmap); 4656 pmap_free_zero_pages(&free); 4657} 4658 4659/* 4660 * pmap_is_modified: 4661 * 4662 * Return whether or not the specified physical page was modified 4663 * in any physical maps. 4664 */ 4665boolean_t 4666pmap_is_modified(vm_page_t m) 4667{ 4668 boolean_t rv; 4669 4670 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4671 ("pmap_is_modified: page %p is not managed", m)); 4672 4673 /* 4674 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4675 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4676 * is clear, no PTEs can have PG_M set. 4677 */ 4678 VM_OBJECT_ASSERT_WLOCKED(m->object); 4679 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4680 return (FALSE); 4681 rw_wlock(&pvh_global_lock); 4682 rv = pmap_is_modified_pvh(&m->md) || 4683 ((m->flags & PG_FICTITIOUS) == 0 && 4684 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4685 rw_wunlock(&pvh_global_lock); 4686 return (rv); 4687} 4688 4689/* 4690 * Returns TRUE if any of the given mappings were used to modify 4691 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4692 * mappings are supported. 4693 */ 4694static boolean_t 4695pmap_is_modified_pvh(struct md_page *pvh) 4696{ 4697 pv_entry_t pv; 4698 pt_entry_t *pte; 4699 pmap_t pmap; 4700 boolean_t rv; 4701 4702 rw_assert(&pvh_global_lock, RA_WLOCKED); 4703 rv = FALSE; 4704 sched_pin(); 4705 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4706 pmap = PV_PMAP(pv); 4707 PMAP_LOCK(pmap); 4708 pte = pmap_pte_quick(pmap, pv->pv_va); 4709 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4710 PMAP_UNLOCK(pmap); 4711 if (rv) 4712 break; 4713 } 4714 sched_unpin(); 4715 return (rv); 4716} 4717 4718/* 4719 * pmap_is_prefaultable: 4720 * 4721 * Return whether or not the specified virtual address is elgible 4722 * for prefault. 4723 */ 4724boolean_t 4725pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4726{ 4727 pd_entry_t *pde; 4728 pt_entry_t *pte; 4729 boolean_t rv; 4730 4731 rv = FALSE; 4732 PMAP_LOCK(pmap); 4733 pde = pmap_pde(pmap, addr); 4734 if (*pde != 0 && (*pde & PG_PS) == 0) { 4735 pte = vtopte(addr); 4736 rv = *pte == 0; 4737 } 4738 PMAP_UNLOCK(pmap); 4739 return (rv); 4740} 4741 4742/* 4743 * pmap_is_referenced: 4744 * 4745 * Return whether or not the specified physical page was referenced 4746 * in any physical maps. 4747 */ 4748boolean_t 4749pmap_is_referenced(vm_page_t m) 4750{ 4751 boolean_t rv; 4752 4753 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4754 ("pmap_is_referenced: page %p is not managed", m)); 4755 rw_wlock(&pvh_global_lock); 4756 rv = pmap_is_referenced_pvh(&m->md) || 4757 ((m->flags & PG_FICTITIOUS) == 0 && 4758 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4759 rw_wunlock(&pvh_global_lock); 4760 return (rv); 4761} 4762 4763/* 4764 * Returns TRUE if any of the given mappings were referenced and FALSE 4765 * otherwise. Both page and 4mpage mappings are supported. 4766 */ 4767static boolean_t 4768pmap_is_referenced_pvh(struct md_page *pvh) 4769{ 4770 pv_entry_t pv; 4771 pt_entry_t *pte; 4772 pmap_t pmap; 4773 boolean_t rv; 4774 4775 rw_assert(&pvh_global_lock, RA_WLOCKED); 4776 rv = FALSE; 4777 sched_pin(); 4778 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4779 pmap = PV_PMAP(pv); 4780 PMAP_LOCK(pmap); 4781 pte = pmap_pte_quick(pmap, pv->pv_va); 4782 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4783 PMAP_UNLOCK(pmap); 4784 if (rv) 4785 break; 4786 } 4787 sched_unpin(); 4788 return (rv); 4789} 4790 4791/* 4792 * Clear the write and modified bits in each of the given page's mappings. 4793 */ 4794void 4795pmap_remove_write(vm_page_t m) 4796{ 4797 struct md_page *pvh; 4798 pv_entry_t next_pv, pv; 4799 pmap_t pmap; 4800 pd_entry_t *pde; 4801 pt_entry_t oldpte, *pte; 4802 vm_offset_t va; 4803 4804 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4805 ("pmap_remove_write: page %p is not managed", m)); 4806 4807 /* 4808 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4809 * set by another thread while the object is locked. Thus, 4810 * if PGA_WRITEABLE is clear, no page table entries need updating. 4811 */ 4812 VM_OBJECT_ASSERT_WLOCKED(m->object); 4813 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4814 return; 4815 rw_wlock(&pvh_global_lock); 4816 sched_pin(); 4817 if ((m->flags & PG_FICTITIOUS) != 0) 4818 goto small_mappings; 4819 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4820 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4821 va = pv->pv_va; 4822 pmap = PV_PMAP(pv); 4823 PMAP_LOCK(pmap); 4824 pde = pmap_pde(pmap, va); 4825 if ((*pde & PG_RW) != 0) 4826 (void)pmap_demote_pde(pmap, pde, va); 4827 PMAP_UNLOCK(pmap); 4828 } 4829small_mappings: 4830 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4831 pmap = PV_PMAP(pv); 4832 PMAP_LOCK(pmap); 4833 pde = pmap_pde(pmap, pv->pv_va); 4834 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4835 " a 4mpage in page %p's pv list", m)); 4836 pte = pmap_pte_quick(pmap, pv->pv_va); 4837retry: 4838 oldpte = *pte; 4839 if ((oldpte & PG_RW) != 0) { 4840 /* 4841 * Regardless of whether a pte is 32 or 64 bits 4842 * in size, PG_RW and PG_M are among the least 4843 * significant 32 bits. 4844 */ 4845 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4846 oldpte & ~(PG_RW | PG_M))) 4847 goto retry; 4848 if ((oldpte & PG_M) != 0) 4849 vm_page_dirty(m); 4850 pmap_invalidate_page(pmap, pv->pv_va); 4851 } 4852 PMAP_UNLOCK(pmap); 4853 } 4854 vm_page_aflag_clear(m, PGA_WRITEABLE); 4855 sched_unpin(); 4856 rw_wunlock(&pvh_global_lock); 4857} 4858 4859/* 4860 * pmap_ts_referenced: 4861 * 4862 * Return a count of reference bits for a page, clearing those bits. 4863 * It is not necessary for every reference bit to be cleared, but it 4864 * is necessary that 0 only be returned when there are truly no 4865 * reference bits set. 4866 * 4867 * As an optimization, update the page's dirty field if a modified bit is 4868 * found while counting reference bits. This opportunistic update can be 4869 * performed at low cost and can eliminate the need for some future calls 4870 * to pmap_is_modified(). However, since this function stops after 4871 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 4872 * dirty pages. Those dirty pages will only be detected by a future call 4873 * to pmap_is_modified(). 4874 */ 4875int 4876pmap_ts_referenced(vm_page_t m) 4877{ 4878 struct md_page *pvh; 4879 pv_entry_t pv, pvf; 4880 pmap_t pmap; 4881 pd_entry_t *pde; 4882 pt_entry_t *pte; 4883 vm_paddr_t pa; 4884 int rtval = 0; 4885 4886 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4887 ("pmap_ts_referenced: page %p is not managed", m)); 4888 pa = VM_PAGE_TO_PHYS(m); 4889 pvh = pa_to_pvh(pa); 4890 rw_wlock(&pvh_global_lock); 4891 sched_pin(); 4892 if ((m->flags & PG_FICTITIOUS) != 0 || 4893 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 4894 goto small_mappings; 4895 pv = pvf; 4896 do { 4897 pmap = PV_PMAP(pv); 4898 PMAP_LOCK(pmap); 4899 pde = pmap_pde(pmap, pv->pv_va); 4900 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4901 /* 4902 * Although "*pde" is mapping a 2/4MB page, because 4903 * this function is called at a 4KB page granularity, 4904 * we only update the 4KB page under test. 4905 */ 4906 vm_page_dirty(m); 4907 } 4908 if ((*pde & PG_A) != 0) { 4909 /* 4910 * Since this reference bit is shared by either 1024 4911 * or 512 4KB pages, it should not be cleared every 4912 * time it is tested. Apply a simple "hash" function 4913 * on the physical page number, the virtual superpage 4914 * number, and the pmap address to select one 4KB page 4915 * out of the 1024 or 512 on which testing the 4916 * reference bit will result in clearing that bit. 4917 * This function is designed to avoid the selection of 4918 * the same 4KB page for every 2- or 4MB page mapping. 4919 * 4920 * On demotion, a mapping that hasn't been referenced 4921 * is simply destroyed. To avoid the possibility of a 4922 * subsequent page fault on a demoted wired mapping, 4923 * always leave its reference bit set. Moreover, 4924 * since the superpage is wired, the current state of 4925 * its reference bit won't affect page replacement. 4926 */ 4927 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 4928 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 4929 (*pde & PG_W) == 0) { 4930 atomic_clear_int((u_int *)pde, PG_A); 4931 pmap_invalidate_page(pmap, pv->pv_va); 4932 } 4933 rtval++; 4934 } 4935 PMAP_UNLOCK(pmap); 4936 /* Rotate the PV list if it has more than one entry. */ 4937 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4938 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4939 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4940 } 4941 if (rtval >= PMAP_TS_REFERENCED_MAX) 4942 goto out; 4943 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4944small_mappings: 4945 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4946 goto out; 4947 pv = pvf; 4948 do { 4949 pmap = PV_PMAP(pv); 4950 PMAP_LOCK(pmap); 4951 pde = pmap_pde(pmap, pv->pv_va); 4952 KASSERT((*pde & PG_PS) == 0, 4953 ("pmap_ts_referenced: found a 4mpage in page %p's pv list", 4954 m)); 4955 pte = pmap_pte_quick(pmap, pv->pv_va); 4956 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4957 vm_page_dirty(m); 4958 if ((*pte & PG_A) != 0) { 4959 atomic_clear_int((u_int *)pte, PG_A); 4960 pmap_invalidate_page(pmap, pv->pv_va); 4961 rtval++; 4962 } 4963 PMAP_UNLOCK(pmap); 4964 /* Rotate the PV list if it has more than one entry. */ 4965 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4966 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4967 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4968 } 4969 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval < 4970 PMAP_TS_REFERENCED_MAX); 4971out: 4972 sched_unpin(); 4973 rw_wunlock(&pvh_global_lock); 4974 return (rtval); 4975} 4976 4977/* 4978 * Apply the given advice to the specified range of addresses within the 4979 * given pmap. Depending on the advice, clear the referenced and/or 4980 * modified flags in each mapping and set the mapped page's dirty field. 4981 */ 4982void 4983pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4984{ 4985 pd_entry_t oldpde, *pde; 4986 pt_entry_t *pte; 4987 vm_offset_t va, pdnxt; 4988 vm_page_t m; 4989 boolean_t anychanged, pv_lists_locked; 4990 4991 if (advice != MADV_DONTNEED && advice != MADV_FREE) 4992 return; 4993 if (pmap_is_current(pmap)) 4994 pv_lists_locked = FALSE; 4995 else { 4996 pv_lists_locked = TRUE; 4997resume: 4998 rw_wlock(&pvh_global_lock); 4999 sched_pin(); 5000 } 5001 anychanged = FALSE; 5002 PMAP_LOCK(pmap); 5003 for (; sva < eva; sva = pdnxt) { 5004 pdnxt = (sva + NBPDR) & ~PDRMASK; 5005 if (pdnxt < sva) 5006 pdnxt = eva; 5007 pde = pmap_pde(pmap, sva); 5008 oldpde = *pde; 5009 if ((oldpde & PG_V) == 0) 5010 continue; 5011 else if ((oldpde & PG_PS) != 0) { 5012 if ((oldpde & PG_MANAGED) == 0) 5013 continue; 5014 if (!pv_lists_locked) { 5015 pv_lists_locked = TRUE; 5016 if (!rw_try_wlock(&pvh_global_lock)) { 5017 if (anychanged) 5018 pmap_invalidate_all(pmap); 5019 PMAP_UNLOCK(pmap); 5020 goto resume; 5021 } 5022 sched_pin(); 5023 } 5024 if (!pmap_demote_pde(pmap, pde, sva)) { 5025 /* 5026 * The large page mapping was destroyed. 5027 */ 5028 continue; 5029 } 5030 5031 /* 5032 * Unless the page mappings are wired, remove the 5033 * mapping to a single page so that a subsequent 5034 * access may repromote. Since the underlying page 5035 * table page is fully populated, this removal never 5036 * frees a page table page. 5037 */ 5038 if ((oldpde & PG_W) == 0) { 5039 pte = pmap_pte_quick(pmap, sva); 5040 KASSERT((*pte & PG_V) != 0, 5041 ("pmap_advise: invalid PTE")); 5042 pmap_remove_pte(pmap, pte, sva, NULL); 5043 anychanged = TRUE; 5044 } 5045 } 5046 if (pdnxt > eva) 5047 pdnxt = eva; 5048 va = pdnxt; 5049 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 5050 sva += PAGE_SIZE) { 5051 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V)) 5052 goto maybe_invlrng; 5053 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5054 if (advice == MADV_DONTNEED) { 5055 /* 5056 * Future calls to pmap_is_modified() 5057 * can be avoided by making the page 5058 * dirty now. 5059 */ 5060 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 5061 vm_page_dirty(m); 5062 } 5063 atomic_clear_int((u_int *)pte, PG_M | PG_A); 5064 } else if ((*pte & PG_A) != 0) 5065 atomic_clear_int((u_int *)pte, PG_A); 5066 else 5067 goto maybe_invlrng; 5068 if ((*pte & PG_G) != 0) { 5069 if (va == pdnxt) 5070 va = sva; 5071 } else 5072 anychanged = TRUE; 5073 continue; 5074maybe_invlrng: 5075 if (va != pdnxt) { 5076 pmap_invalidate_range(pmap, va, sva); 5077 va = pdnxt; 5078 } 5079 } 5080 if (va != pdnxt) 5081 pmap_invalidate_range(pmap, va, sva); 5082 } 5083 if (anychanged) 5084 pmap_invalidate_all(pmap); 5085 if (pv_lists_locked) { 5086 sched_unpin(); 5087 rw_wunlock(&pvh_global_lock); 5088 } 5089 PMAP_UNLOCK(pmap); 5090} 5091 5092/* 5093 * Clear the modify bits on the specified physical page. 5094 */ 5095void 5096pmap_clear_modify(vm_page_t m) 5097{ 5098 struct md_page *pvh; 5099 pv_entry_t next_pv, pv; 5100 pmap_t pmap; 5101 pd_entry_t oldpde, *pde; 5102 pt_entry_t oldpte, *pte; 5103 vm_offset_t va; 5104 5105 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5106 ("pmap_clear_modify: page %p is not managed", m)); 5107 VM_OBJECT_ASSERT_WLOCKED(m->object); 5108 KASSERT(!vm_page_xbusied(m), 5109 ("pmap_clear_modify: page %p is exclusive busied", m)); 5110 5111 /* 5112 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 5113 * If the object containing the page is locked and the page is not 5114 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 5115 */ 5116 if ((m->aflags & PGA_WRITEABLE) == 0) 5117 return; 5118 rw_wlock(&pvh_global_lock); 5119 sched_pin(); 5120 if ((m->flags & PG_FICTITIOUS) != 0) 5121 goto small_mappings; 5122 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5123 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5124 va = pv->pv_va; 5125 pmap = PV_PMAP(pv); 5126 PMAP_LOCK(pmap); 5127 pde = pmap_pde(pmap, va); 5128 oldpde = *pde; 5129 if ((oldpde & PG_RW) != 0) { 5130 if (pmap_demote_pde(pmap, pde, va)) { 5131 if ((oldpde & PG_W) == 0) { 5132 /* 5133 * Write protect the mapping to a 5134 * single page so that a subsequent 5135 * write access may repromote. 5136 */ 5137 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5138 PG_PS_FRAME); 5139 pte = pmap_pte_quick(pmap, va); 5140 oldpte = *pte; 5141 if ((oldpte & PG_V) != 0) { 5142 /* 5143 * Regardless of whether a pte is 32 or 64 bits 5144 * in size, PG_RW and PG_M are among the least 5145 * significant 32 bits. 5146 */ 5147 while (!atomic_cmpset_int((u_int *)pte, 5148 oldpte, 5149 oldpte & ~(PG_M | PG_RW))) 5150 oldpte = *pte; 5151 vm_page_dirty(m); 5152 pmap_invalidate_page(pmap, va); 5153 } 5154 } 5155 } 5156 } 5157 PMAP_UNLOCK(pmap); 5158 } 5159small_mappings: 5160 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5161 pmap = PV_PMAP(pv); 5162 PMAP_LOCK(pmap); 5163 pde = pmap_pde(pmap, pv->pv_va); 5164 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 5165 " a 4mpage in page %p's pv list", m)); 5166 pte = pmap_pte_quick(pmap, pv->pv_va); 5167 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5168 /* 5169 * Regardless of whether a pte is 32 or 64 bits 5170 * in size, PG_M is among the least significant 5171 * 32 bits. 5172 */ 5173 atomic_clear_int((u_int *)pte, PG_M); 5174 pmap_invalidate_page(pmap, pv->pv_va); 5175 } 5176 PMAP_UNLOCK(pmap); 5177 } 5178 sched_unpin(); 5179 rw_wunlock(&pvh_global_lock); 5180} 5181 5182/* 5183 * Miscellaneous support routines follow 5184 */ 5185 5186/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 5187static __inline void 5188pmap_pte_attr(pt_entry_t *pte, int cache_bits) 5189{ 5190 u_int opte, npte; 5191 5192 /* 5193 * The cache mode bits are all in the low 32-bits of the 5194 * PTE, so we can just spin on updating the low 32-bits. 5195 */ 5196 do { 5197 opte = *(u_int *)pte; 5198 npte = opte & ~PG_PTE_CACHE; 5199 npte |= cache_bits; 5200 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 5201} 5202 5203/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 5204static __inline void 5205pmap_pde_attr(pd_entry_t *pde, int cache_bits) 5206{ 5207 u_int opde, npde; 5208 5209 /* 5210 * The cache mode bits are all in the low 32-bits of the 5211 * PDE, so we can just spin on updating the low 32-bits. 5212 */ 5213 do { 5214 opde = *(u_int *)pde; 5215 npde = opde & ~PG_PDE_CACHE; 5216 npde |= cache_bits; 5217 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 5218} 5219 5220/* 5221 * Map a set of physical memory pages into the kernel virtual 5222 * address space. Return a pointer to where it is mapped. This 5223 * routine is intended to be used for mapping device memory, 5224 * NOT real memory. 5225 */ 5226void * 5227pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 5228{ 5229 struct pmap_preinit_mapping *ppim; 5230 vm_offset_t va, offset; 5231 vm_size_t tmpsize; 5232 int i; 5233 5234 offset = pa & PAGE_MASK; 5235 size = round_page(offset + size); 5236 pa = pa & PG_FRAME; 5237 5238 if (pa < KERNLOAD && pa + size <= KERNLOAD) 5239 va = KERNBASE + pa; 5240 else if (!pmap_initialized) { 5241 va = 0; 5242 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5243 ppim = pmap_preinit_mapping + i; 5244 if (ppim->va == 0) { 5245 ppim->pa = pa; 5246 ppim->sz = size; 5247 ppim->mode = mode; 5248 ppim->va = virtual_avail; 5249 virtual_avail += size; 5250 va = ppim->va; 5251 break; 5252 } 5253 } 5254 if (va == 0) 5255 panic("%s: too many preinit mappings", __func__); 5256 } else { 5257 /* 5258 * If we have a preinit mapping, re-use it. 5259 */ 5260 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5261 ppim = pmap_preinit_mapping + i; 5262 if (ppim->pa == pa && ppim->sz == size && 5263 ppim->mode == mode) 5264 return ((void *)(ppim->va + offset)); 5265 } 5266 va = kva_alloc(size); 5267 if (va == 0) 5268 panic("%s: Couldn't allocate KVA", __func__); 5269 } 5270 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 5271 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 5272 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 5273 pmap_invalidate_cache_range(va, va + size, FALSE); 5274 return ((void *)(va + offset)); 5275} 5276 5277void * 5278pmap_mapdev(vm_paddr_t pa, vm_size_t size) 5279{ 5280 5281 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 5282} 5283 5284void * 5285pmap_mapbios(vm_paddr_t pa, vm_size_t size) 5286{ 5287 5288 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 5289} 5290 5291void 5292pmap_unmapdev(vm_offset_t va, vm_size_t size) 5293{ 5294 struct pmap_preinit_mapping *ppim; 5295 vm_offset_t offset; 5296 int i; 5297 5298 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 5299 return; 5300 offset = va & PAGE_MASK; 5301 size = round_page(offset + size); 5302 va = trunc_page(va); 5303 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5304 ppim = pmap_preinit_mapping + i; 5305 if (ppim->va == va && ppim->sz == size) { 5306 if (pmap_initialized) 5307 return; 5308 ppim->pa = 0; 5309 ppim->va = 0; 5310 ppim->sz = 0; 5311 ppim->mode = 0; 5312 if (va + size == virtual_avail) 5313 virtual_avail = va; 5314 return; 5315 } 5316 } 5317 if (pmap_initialized) 5318 kva_free(va, size); 5319} 5320 5321/* 5322 * Sets the memory attribute for the specified page. 5323 */ 5324void 5325pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5326{ 5327 5328 m->md.pat_mode = ma; 5329 if ((m->flags & PG_FICTITIOUS) != 0) 5330 return; 5331 5332 /* 5333 * If "m" is a normal page, flush it from the cache. 5334 * See pmap_invalidate_cache_range(). 5335 * 5336 * First, try to find an existing mapping of the page by sf 5337 * buffer. sf_buf_invalidate_cache() modifies mapping and 5338 * flushes the cache. 5339 */ 5340 if (sf_buf_invalidate_cache(m)) 5341 return; 5342 5343 /* 5344 * If page is not mapped by sf buffer, but CPU does not 5345 * support self snoop, map the page transient and do 5346 * invalidation. In the worst case, whole cache is flushed by 5347 * pmap_invalidate_cache_range(). 5348 */ 5349 if ((cpu_feature & CPUID_SS) == 0) 5350 pmap_flush_page(m); 5351} 5352 5353static void 5354pmap_flush_page(vm_page_t m) 5355{ 5356 pt_entry_t *cmap_pte2; 5357 struct pcpu *pc; 5358 vm_offset_t sva, eva; 5359 bool useclflushopt; 5360 5361 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0; 5362 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) { 5363 sched_pin(); 5364 pc = get_pcpu(); 5365 cmap_pte2 = pc->pc_cmap_pte2; 5366 mtx_lock(&pc->pc_cmap_lock); 5367 if (*cmap_pte2) 5368 panic("pmap_flush_page: CMAP2 busy"); 5369 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 5370 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 5371 invlcaddr(pc->pc_cmap_addr2); 5372 sva = (vm_offset_t)pc->pc_cmap_addr2; 5373 eva = sva + PAGE_SIZE; 5374 5375 /* 5376 * Use mfence or sfence despite the ordering implied by 5377 * mtx_{un,}lock() because clflush on non-Intel CPUs 5378 * and clflushopt are not guaranteed to be ordered by 5379 * any other instruction. 5380 */ 5381 if (useclflushopt) 5382 sfence(); 5383 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5384 mfence(); 5385 for (; sva < eva; sva += cpu_clflush_line_size) { 5386 if (useclflushopt) 5387 clflushopt(sva); 5388 else 5389 clflush(sva); 5390 } 5391 if (useclflushopt) 5392 sfence(); 5393 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5394 mfence(); 5395 *cmap_pte2 = 0; 5396 sched_unpin(); 5397 mtx_unlock(&pc->pc_cmap_lock); 5398 } else 5399 pmap_invalidate_cache(); 5400} 5401 5402/* 5403 * Changes the specified virtual address range's memory type to that given by 5404 * the parameter "mode". The specified virtual address range must be 5405 * completely contained within either the kernel map. 5406 * 5407 * Returns zero if the change completed successfully, and either EINVAL or 5408 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 5409 * of the virtual address range was not mapped, and ENOMEM is returned if 5410 * there was insufficient memory available to complete the change. 5411 */ 5412int 5413pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 5414{ 5415 vm_offset_t base, offset, tmpva; 5416 pd_entry_t *pde; 5417 pt_entry_t *pte; 5418 int cache_bits_pte, cache_bits_pde; 5419 boolean_t changed; 5420 5421 base = trunc_page(va); 5422 offset = va & PAGE_MASK; 5423 size = round_page(offset + size); 5424 5425 /* 5426 * Only supported on kernel virtual addresses above the recursive map. 5427 */ 5428 if (base < VM_MIN_KERNEL_ADDRESS) 5429 return (EINVAL); 5430 5431 cache_bits_pde = pmap_cache_bits(mode, 1); 5432 cache_bits_pte = pmap_cache_bits(mode, 0); 5433 changed = FALSE; 5434 5435 /* 5436 * Pages that aren't mapped aren't supported. Also break down 5437 * 2/4MB pages into 4KB pages if required. 5438 */ 5439 PMAP_LOCK(kernel_pmap); 5440 for (tmpva = base; tmpva < base + size; ) { 5441 pde = pmap_pde(kernel_pmap, tmpva); 5442 if (*pde == 0) { 5443 PMAP_UNLOCK(kernel_pmap); 5444 return (EINVAL); 5445 } 5446 if (*pde & PG_PS) { 5447 /* 5448 * If the current 2/4MB page already has 5449 * the required memory type, then we need not 5450 * demote this page. Just increment tmpva to 5451 * the next 2/4MB page frame. 5452 */ 5453 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 5454 tmpva = trunc_4mpage(tmpva) + NBPDR; 5455 continue; 5456 } 5457 5458 /* 5459 * If the current offset aligns with a 2/4MB 5460 * page frame and there is at least 2/4MB left 5461 * within the range, then we need not break 5462 * down this page into 4KB pages. 5463 */ 5464 if ((tmpva & PDRMASK) == 0 && 5465 tmpva + PDRMASK < base + size) { 5466 tmpva += NBPDR; 5467 continue; 5468 } 5469 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 5470 PMAP_UNLOCK(kernel_pmap); 5471 return (ENOMEM); 5472 } 5473 } 5474 pte = vtopte(tmpva); 5475 if (*pte == 0) { 5476 PMAP_UNLOCK(kernel_pmap); 5477 return (EINVAL); 5478 } 5479 tmpva += PAGE_SIZE; 5480 } 5481 PMAP_UNLOCK(kernel_pmap); 5482 5483 /* 5484 * Ok, all the pages exist, so run through them updating their 5485 * cache mode if required. 5486 */ 5487 for (tmpva = base; tmpva < base + size; ) { 5488 pde = pmap_pde(kernel_pmap, tmpva); 5489 if (*pde & PG_PS) { 5490 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 5491 pmap_pde_attr(pde, cache_bits_pde); 5492 changed = TRUE; 5493 } 5494 tmpva = trunc_4mpage(tmpva) + NBPDR; 5495 } else { 5496 pte = vtopte(tmpva); 5497 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 5498 pmap_pte_attr(pte, cache_bits_pte); 5499 changed = TRUE; 5500 } 5501 tmpva += PAGE_SIZE; 5502 } 5503 } 5504 5505 /* 5506 * Flush CPU caches to make sure any data isn't cached that 5507 * shouldn't be, etc. 5508 */ 5509 if (changed) { 5510 pmap_invalidate_range(kernel_pmap, base, tmpva); 5511 pmap_invalidate_cache_range(base, tmpva, FALSE); 5512 } 5513 return (0); 5514} 5515 5516/* 5517 * perform the pmap work for mincore 5518 */ 5519int 5520pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5521{ 5522 pd_entry_t *pdep; 5523 pt_entry_t *ptep, pte; 5524 vm_paddr_t pa; 5525 int val; 5526 5527 PMAP_LOCK(pmap); 5528retry: 5529 pdep = pmap_pde(pmap, addr); 5530 if (*pdep != 0) { 5531 if (*pdep & PG_PS) { 5532 pte = *pdep; 5533 /* Compute the physical address of the 4KB page. */ 5534 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5535 PG_FRAME; 5536 val = MINCORE_SUPER; 5537 } else { 5538 ptep = pmap_pte(pmap, addr); 5539 pte = *ptep; 5540 pmap_pte_release(ptep); 5541 pa = pte & PG_FRAME; 5542 val = 0; 5543 } 5544 } else { 5545 pte = 0; 5546 pa = 0; 5547 val = 0; 5548 } 5549 if ((pte & PG_V) != 0) { 5550 val |= MINCORE_INCORE; 5551 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5552 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5553 if ((pte & PG_A) != 0) 5554 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5555 } 5556 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5557 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5558 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5559 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5560 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5561 goto retry; 5562 } else 5563 PA_UNLOCK_COND(*locked_pa); 5564 PMAP_UNLOCK(pmap); 5565 return (val); 5566} 5567 5568void 5569pmap_activate(struct thread *td) 5570{ 5571 pmap_t pmap, oldpmap; 5572 u_int cpuid; 5573 u_int32_t cr3; 5574 5575 critical_enter(); 5576 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5577 oldpmap = PCPU_GET(curpmap); 5578 cpuid = PCPU_GET(cpuid); 5579#if defined(SMP) 5580 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 5581 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5582#else 5583 CPU_CLR(cpuid, &oldpmap->pm_active); 5584 CPU_SET(cpuid, &pmap->pm_active); 5585#endif 5586#if defined(PAE) || defined(PAE_TABLES) 5587 cr3 = vtophys(pmap->pm_pdpt); 5588#else 5589 cr3 = vtophys(pmap->pm_pdir); 5590#endif 5591 /* 5592 * pmap_activate is for the current thread on the current cpu 5593 */ 5594 td->td_pcb->pcb_cr3 = cr3; 5595 load_cr3(cr3); 5596 PCPU_SET(curpmap, pmap); 5597 critical_exit(); 5598} 5599 5600void 5601pmap_activate_boot(pmap_t pmap) 5602{ 5603 u_int cpuid; 5604 5605 cpuid = PCPU_GET(cpuid); 5606#if defined(SMP) 5607 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5608#else 5609 CPU_SET(cpuid, &pmap->pm_active); 5610#endif 5611 PCPU_SET(curpmap, pmap); 5612} 5613 5614void 5615pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5616{ 5617} 5618 5619/* 5620 * Increase the starting virtual address of the given mapping if a 5621 * different alignment might result in more superpage mappings. 5622 */ 5623void 5624pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5625 vm_offset_t *addr, vm_size_t size) 5626{ 5627 vm_offset_t superpage_offset; 5628 5629 if (size < NBPDR) 5630 return; 5631 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5632 offset += ptoa(object->pg_color); 5633 superpage_offset = offset & PDRMASK; 5634 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5635 (*addr & PDRMASK) == superpage_offset) 5636 return; 5637 if ((*addr & PDRMASK) < superpage_offset) 5638 *addr = (*addr & ~PDRMASK) + superpage_offset; 5639 else 5640 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5641} 5642 5643vm_offset_t 5644pmap_quick_enter_page(vm_page_t m) 5645{ 5646 vm_offset_t qaddr; 5647 pt_entry_t *pte; 5648 5649 critical_enter(); 5650 qaddr = PCPU_GET(qmap_addr); 5651 pte = vtopte(qaddr); 5652 5653 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy")); 5654 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 5655 pmap_cache_bits(pmap_page_get_memattr(m), 0); 5656 invlpg(qaddr); 5657 5658 return (qaddr); 5659} 5660 5661void 5662pmap_quick_remove_page(vm_offset_t addr) 5663{ 5664 vm_offset_t qaddr; 5665 pt_entry_t *pte; 5666 5667 qaddr = PCPU_GET(qmap_addr); 5668 pte = vtopte(qaddr); 5669 5670 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use")); 5671 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address")); 5672 5673 *pte = 0; 5674 critical_exit(); 5675} 5676 5677#if defined(PMAP_DEBUG) 5678pmap_pid_dump(int pid) 5679{ 5680 pmap_t pmap; 5681 struct proc *p; 5682 int npte = 0; 5683 int index; 5684 5685 sx_slock(&allproc_lock); 5686 FOREACH_PROC_IN_SYSTEM(p) { 5687 if (p->p_pid != pid) 5688 continue; 5689 5690 if (p->p_vmspace) { 5691 int i,j; 5692 index = 0; 5693 pmap = vmspace_pmap(p->p_vmspace); 5694 for (i = 0; i < NPDEPTD; i++) { 5695 pd_entry_t *pde; 5696 pt_entry_t *pte; 5697 vm_offset_t base = i << PDRSHIFT; 5698 5699 pde = &pmap->pm_pdir[i]; 5700 if (pde && pmap_pde_v(pde)) { 5701 for (j = 0; j < NPTEPG; j++) { 5702 vm_offset_t va = base + (j << PAGE_SHIFT); 5703 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5704 if (index) { 5705 index = 0; 5706 printf("\n"); 5707 } 5708 sx_sunlock(&allproc_lock); 5709 return (npte); 5710 } 5711 pte = pmap_pte(pmap, va); 5712 if (pte && pmap_pte_v(pte)) { 5713 pt_entry_t pa; 5714 vm_page_t m; 5715 pa = *pte; 5716 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5717 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5718 va, pa, m->hold_count, m->wire_count, m->flags); 5719 npte++; 5720 index++; 5721 if (index >= 2) { 5722 index = 0; 5723 printf("\n"); 5724 } else { 5725 printf(" "); 5726 } 5727 } 5728 } 5729 } 5730 } 5731 } 5732 } 5733 sx_sunlock(&allproc_lock); 5734 return (npte); 5735} 5736#endif 5737