pmap.c revision 313862
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/11/sys/i386/i386/pmap.c 313862 2017-02-17 07:08:37Z jah $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_apic.h" 100#include "opt_cpu.h" 101#include "opt_pmap.h" 102#include "opt_smp.h" 103#include "opt_xbox.h" 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/kernel.h> 108#include <sys/ktr.h> 109#include <sys/lock.h> 110#include <sys/malloc.h> 111#include <sys/mman.h> 112#include <sys/msgbuf.h> 113#include <sys/mutex.h> 114#include <sys/proc.h> 115#include <sys/rwlock.h> 116#include <sys/sf_buf.h> 117#include <sys/sx.h> 118#include <sys/vmmeter.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/smp.h> 122 123#include <vm/vm.h> 124#include <vm/vm_param.h> 125#include <vm/vm_kern.h> 126#include <vm/vm_page.h> 127#include <vm/vm_map.h> 128#include <vm/vm_object.h> 129#include <vm/vm_extern.h> 130#include <vm/vm_pageout.h> 131#include <vm/vm_pager.h> 132#include <vm/vm_phys.h> 133#include <vm/vm_radix.h> 134#include <vm/vm_reserv.h> 135#include <vm/uma.h> 136 137#ifdef DEV_APIC 138#include <sys/bus.h> 139#include <machine/intr_machdep.h> 140#include <x86/apicvar.h> 141#endif 142#include <machine/cpu.h> 143#include <machine/cputypes.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146#include <machine/specialreg.h> 147#ifdef SMP 148#include <machine/smp.h> 149#endif 150 151#ifdef XBOX 152#include <machine/xbox.h> 153#endif 154 155#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 156#define CPU_ENABLE_SSE 157#endif 158 159#ifndef PMAP_SHPGPERPROC 160#define PMAP_SHPGPERPROC 200 161#endif 162 163#if !defined(DIAGNOSTIC) 164#ifdef __GNUC_GNU_INLINE__ 165#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 166#else 167#define PMAP_INLINE extern inline 168#endif 169#else 170#define PMAP_INLINE 171#endif 172 173#ifdef PV_STATS 174#define PV_STAT(x) do { x ; } while (0) 175#else 176#define PV_STAT(x) do { } while (0) 177#endif 178 179#define pa_index(pa) ((pa) >> PDRSHIFT) 180#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 181 182/* 183 * Get PDEs and PTEs for user/kernel address space 184 */ 185#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 186#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 187 188#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 189#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 190#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 191#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 192#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 193 194#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 195 atomic_clear_int((u_int *)(pte), PG_W)) 196#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 197 198struct pmap kernel_pmap_store; 199LIST_HEAD(pmaplist, pmap); 200static struct pmaplist allpmaps; 201static struct mtx allpmaps_lock; 202 203vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 204vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 205int pgeflag = 0; /* PG_G or-in */ 206int pseflag = 0; /* PG_PS or-in */ 207 208static int nkpt = NKPT; 209vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 210extern u_int32_t KERNend; 211extern u_int32_t KPTphys; 212 213#if defined(PAE) || defined(PAE_TABLES) 214pt_entry_t pg_nx; 215static uma_zone_t pdptzone; 216#endif 217 218static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 219 220static int pat_works = 1; 221SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1, 222 "Is page attribute table fully functional?"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 226 &pg_ps_enabled, 0, "Are large page mappings enabled?"); 227 228#define PAT_INDEX_SIZE 8 229static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 230 231/* 232 * pmap_mapdev support pre initialization (i.e. console) 233 */ 234#define PMAP_PREINIT_MAPPING_COUNT 8 235static struct pmap_preinit_mapping { 236 vm_paddr_t pa; 237 vm_offset_t va; 238 vm_size_t sz; 239 int mode; 240} pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 241static int pmap_initialized; 242 243static struct rwlock_padalign pvh_global_lock; 244 245/* 246 * Data for the pv entry allocation mechanism 247 */ 248static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 249static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 250static struct md_page *pv_table; 251static int shpgperproc = PMAP_SHPGPERPROC; 252 253struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 254int pv_maxchunks; /* How many chunks we have KVA for */ 255vm_offset_t pv_vafree; /* freelist stored in the PTE */ 256 257/* 258 * All those kernel PT submaps that BSD is so fond of 259 */ 260pt_entry_t *CMAP3; 261static pd_entry_t *KPTD; 262caddr_t ptvmmap = 0; 263caddr_t CADDR3; 264struct msgbuf *msgbufp = NULL; 265 266/* 267 * Crashdump maps. 268 */ 269static caddr_t crashdumpmap; 270 271static pt_entry_t *PMAP1 = NULL, *PMAP2; 272static pt_entry_t *PADDR1 = NULL, *PADDR2; 273#ifdef SMP 274static int PMAP1cpu; 275static int PMAP1changedcpu; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 277 &PMAP1changedcpu, 0, 278 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 279#endif 280static int PMAP1changed; 281SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 282 &PMAP1changed, 0, 283 "Number of times pmap_pte_quick changed PMAP1"); 284static int PMAP1unchanged; 285SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 286 &PMAP1unchanged, 0, 287 "Number of times pmap_pte_quick didn't change PMAP1"); 288static struct mtx PMAP2mutex; 289 290static void free_pv_chunk(struct pv_chunk *pc); 291static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 292static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 293static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 294static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 295static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 296static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 297static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 298 vm_offset_t va); 299static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 300 301static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 302static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 303 vm_prot_t prot); 304static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 305 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 306static void pmap_flush_page(vm_page_t m); 307static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 308static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 309static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 310static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 311static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 312static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 313static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 314static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 315static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 316static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 317 vm_prot_t prot); 318static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 319static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 320 struct spglist *free); 321static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 322 struct spglist *free); 323static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 324static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 325 struct spglist *free); 326static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 327 vm_offset_t va); 328static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 329static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 330 vm_page_t m); 331static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 332 pd_entry_t newpde); 333static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 334 335static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 336 337static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags); 338static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free); 339static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 340static void pmap_pte_release(pt_entry_t *pte); 341static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *); 342#if defined(PAE) || defined(PAE_TABLES) 343static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 344 int wait); 345#endif 346static void pmap_set_pg(void); 347 348static __inline void pagezero(void *page); 349 350CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 351CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 352 353/* 354 * If you get an error here, then you set KVA_PAGES wrong! See the 355 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 356 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 357 */ 358CTASSERT(KERNBASE % (1 << 24) == 0); 359 360/* 361 * Bootstrap the system enough to run with virtual memory. 362 * 363 * On the i386 this is called after mapping has already been enabled 364 * and just syncs the pmap module with what has already been done. 365 * [We can't call it easily with mapping off since the kernel is not 366 * mapped with PA == VA, hence we would have to relocate every address 367 * from the linked base (virtual) address "KERNBASE" to the actual 368 * (physical) address starting relative to 0] 369 */ 370void 371pmap_bootstrap(vm_paddr_t firstaddr) 372{ 373 vm_offset_t va; 374 pt_entry_t *pte, *unused; 375 struct pcpu *pc; 376 int i; 377 378 /* 379 * Add a physical memory segment (vm_phys_seg) corresponding to the 380 * preallocated kernel page table pages so that vm_page structures 381 * representing these pages will be created. The vm_page structures 382 * are required for promotion of the corresponding kernel virtual 383 * addresses to superpage mappings. 384 */ 385 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt)); 386 387 /* 388 * Initialize the first available kernel virtual address. However, 389 * using "firstaddr" may waste a few pages of the kernel virtual 390 * address space, because locore may not have mapped every physical 391 * page that it allocated. Preferably, locore would provide a first 392 * unused virtual address in addition to "firstaddr". 393 */ 394 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 395 396 virtual_end = VM_MAX_KERNEL_ADDRESS; 397 398 /* 399 * Initialize the kernel pmap (which is statically allocated). 400 */ 401 PMAP_LOCK_INIT(kernel_pmap); 402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 403#if defined(PAE) || defined(PAE_TABLES) 404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 405#endif 406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 407 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 408 409 /* 410 * Initialize the global pv list lock. 411 */ 412 rw_init(&pvh_global_lock, "pmap pv global"); 413 414 LIST_INIT(&allpmaps); 415 416 /* 417 * Request a spin mutex so that changes to allpmaps cannot be 418 * preempted by smp_rendezvous_cpus(). Otherwise, 419 * pmap_update_pde_kernel() could access allpmaps while it is 420 * being changed. 421 */ 422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 423 mtx_lock_spin(&allpmaps_lock); 424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 425 mtx_unlock_spin(&allpmaps_lock); 426 427 /* 428 * Reserve some special page table entries/VA space for temporary 429 * mapping of pages. 430 */ 431#define SYSMAP(c, p, v, n) \ 432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 433 434 va = virtual_avail; 435 pte = vtopte(va); 436 437 438 /* 439 * Initialize temporary map objects on the current CPU for use 440 * during early boot. 441 * CMAP1/CMAP2 are used for zeroing and copying pages. 442 * CMAP3 is used for the idle process page zeroing. 443 */ 444 pc = get_pcpu(); 445 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 446 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1) 447 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1) 448 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1) 449 450 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 451 452 /* 453 * Crashdump maps. 454 */ 455 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 456 457 /* 458 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 459 */ 460 SYSMAP(caddr_t, unused, ptvmmap, 1) 461 462 /* 463 * msgbufp is used to map the system message buffer. 464 */ 465 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 466 467 /* 468 * KPTmap is used by pmap_kextract(). 469 * 470 * KPTmap is first initialized by locore. However, that initial 471 * KPTmap can only support NKPT page table pages. Here, a larger 472 * KPTmap is created that can support KVA_PAGES page table pages. 473 */ 474 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 475 476 for (i = 0; i < NKPT; i++) 477 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 478 479 /* 480 * Adjust the start of the KPTD and KPTmap so that the implementation 481 * of pmap_kextract() and pmap_growkernel() can be made simpler. 482 */ 483 KPTD -= KPTDI; 484 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 485 486 /* 487 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 488 * respectively. 489 */ 490 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 491 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 492 493 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 494 495 virtual_avail = va; 496 497 /* 498 * Leave in place an identity mapping (virt == phys) for the low 1 MB 499 * physical memory region that is used by the ACPI wakeup code. This 500 * mapping must not have PG_G set. 501 */ 502#ifdef XBOX 503 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 504 * an early stadium, we cannot yet neatly map video memory ... :-( 505 * Better fixes are very welcome! */ 506 if (!arch_i386_is_xbox) 507#endif 508 for (i = 1; i < NKPT; i++) 509 PTD[i] = 0; 510 511 /* 512 * Initialize the PAT MSR if present. 513 * pmap_init_pat() clears and sets CR4_PGE, which, as a 514 * side-effect, invalidates stale PG_G TLB entries that might 515 * have been created in our pre-boot environment. We assume 516 * that PAT support implies PGE and in reverse, PGE presence 517 * comes with PAT. Both features were added for Pentium Pro. 518 */ 519 pmap_init_pat(); 520 521 /* Turn on PG_G on kernel page(s) */ 522 pmap_set_pg(); 523} 524 525static void 526pmap_init_reserved_pages(void) 527{ 528 struct pcpu *pc; 529 vm_offset_t pages; 530 int i; 531 532 CPU_FOREACH(i) { 533 pc = pcpu_find(i); 534 /* 535 * Skip if the mapping has already been initialized, 536 * i.e. this is the BSP. 537 */ 538 if (pc->pc_cmap_addr1 != 0) 539 continue; 540 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 541 pages = kva_alloc(PAGE_SIZE * 3); 542 if (pages == 0) 543 panic("%s: unable to allocate KVA", __func__); 544 pc->pc_cmap_pte1 = vtopte(pages); 545 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE); 546 pc->pc_cmap_addr1 = (caddr_t)pages; 547 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE); 548 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2); 549 } 550} 551 552SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL); 553 554/* 555 * Setup the PAT MSR. 556 */ 557void 558pmap_init_pat(void) 559{ 560 int pat_table[PAT_INDEX_SIZE]; 561 uint64_t pat_msr; 562 u_long cr0, cr4; 563 int i; 564 565 /* Set default PAT index table. */ 566 for (i = 0; i < PAT_INDEX_SIZE; i++) 567 pat_table[i] = -1; 568 pat_table[PAT_WRITE_BACK] = 0; 569 pat_table[PAT_WRITE_THROUGH] = 1; 570 pat_table[PAT_UNCACHEABLE] = 3; 571 pat_table[PAT_WRITE_COMBINING] = 3; 572 pat_table[PAT_WRITE_PROTECTED] = 3; 573 pat_table[PAT_UNCACHED] = 3; 574 575 /* 576 * Bail if this CPU doesn't implement PAT. 577 * We assume that PAT support implies PGE. 578 */ 579 if ((cpu_feature & CPUID_PAT) == 0) { 580 for (i = 0; i < PAT_INDEX_SIZE; i++) 581 pat_index[i] = pat_table[i]; 582 pat_works = 0; 583 return; 584 } 585 586 /* 587 * Due to some Intel errata, we can only safely use the lower 4 588 * PAT entries. 589 * 590 * Intel Pentium III Processor Specification Update 591 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 592 * or Mode C Paging) 593 * 594 * Intel Pentium IV Processor Specification Update 595 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 596 */ 597 if (cpu_vendor_id == CPU_VENDOR_INTEL && 598 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) 599 pat_works = 0; 600 601 /* Initialize default PAT entries. */ 602 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 603 PAT_VALUE(1, PAT_WRITE_THROUGH) | 604 PAT_VALUE(2, PAT_UNCACHED) | 605 PAT_VALUE(3, PAT_UNCACHEABLE) | 606 PAT_VALUE(4, PAT_WRITE_BACK) | 607 PAT_VALUE(5, PAT_WRITE_THROUGH) | 608 PAT_VALUE(6, PAT_UNCACHED) | 609 PAT_VALUE(7, PAT_UNCACHEABLE); 610 611 if (pat_works) { 612 /* 613 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 614 * Program 5 and 6 as WP and WC. 615 * Leave 4 and 7 as WB and UC. 616 */ 617 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 618 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 619 PAT_VALUE(6, PAT_WRITE_COMBINING); 620 pat_table[PAT_UNCACHED] = 2; 621 pat_table[PAT_WRITE_PROTECTED] = 5; 622 pat_table[PAT_WRITE_COMBINING] = 6; 623 } else { 624 /* 625 * Just replace PAT Index 2 with WC instead of UC-. 626 */ 627 pat_msr &= ~PAT_MASK(2); 628 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 629 pat_table[PAT_WRITE_COMBINING] = 2; 630 } 631 632 /* Disable PGE. */ 633 cr4 = rcr4(); 634 load_cr4(cr4 & ~CR4_PGE); 635 636 /* Disable caches (CD = 1, NW = 0). */ 637 cr0 = rcr0(); 638 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 639 640 /* Flushes caches and TLBs. */ 641 wbinvd(); 642 invltlb(); 643 644 /* Update PAT and index table. */ 645 wrmsr(MSR_PAT, pat_msr); 646 for (i = 0; i < PAT_INDEX_SIZE; i++) 647 pat_index[i] = pat_table[i]; 648 649 /* Flush caches and TLBs again. */ 650 wbinvd(); 651 invltlb(); 652 653 /* Restore caches and PGE. */ 654 load_cr0(cr0); 655 load_cr4(cr4); 656} 657 658/* 659 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 660 */ 661static void 662pmap_set_pg(void) 663{ 664 pt_entry_t *pte; 665 vm_offset_t va, endva; 666 667 if (pgeflag == 0) 668 return; 669 670 endva = KERNBASE + KERNend; 671 672 if (pseflag) { 673 va = KERNBASE + KERNLOAD; 674 while (va < endva) { 675 pdir_pde(PTD, va) |= pgeflag; 676 invltlb(); /* Flush non-PG_G entries. */ 677 va += NBPDR; 678 } 679 } else { 680 va = (vm_offset_t)btext; 681 while (va < endva) { 682 pte = vtopte(va); 683 if (*pte) 684 *pte |= pgeflag; 685 invltlb(); /* Flush non-PG_G entries. */ 686 va += PAGE_SIZE; 687 } 688 } 689} 690 691/* 692 * Initialize a vm_page's machine-dependent fields. 693 */ 694void 695pmap_page_init(vm_page_t m) 696{ 697 698 TAILQ_INIT(&m->md.pv_list); 699 m->md.pat_mode = PAT_WRITE_BACK; 700} 701 702#if defined(PAE) || defined(PAE_TABLES) 703static void * 704pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait) 705{ 706 707 /* Inform UMA that this allocator uses kernel_map/object. */ 708 *flags = UMA_SLAB_KERNEL; 709 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL, 710 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 711} 712#endif 713 714/* 715 * Abuse the pte nodes for unmapped kva to thread a kva freelist through. 716 * Requirements: 717 * - Must deal with pages in order to ensure that none of the PG_* bits 718 * are ever set, PG_V in particular. 719 * - Assumes we can write to ptes without pte_store() atomic ops, even 720 * on PAE systems. This should be ok. 721 * - Assumes nothing will ever test these addresses for 0 to indicate 722 * no mapping instead of correctly checking PG_V. 723 * - Assumes a vm_offset_t will fit in a pte (true for i386). 724 * Because PG_V is never set, there can be no mappings to invalidate. 725 */ 726static vm_offset_t 727pmap_ptelist_alloc(vm_offset_t *head) 728{ 729 pt_entry_t *pte; 730 vm_offset_t va; 731 732 va = *head; 733 if (va == 0) 734 panic("pmap_ptelist_alloc: exhausted ptelist KVA"); 735 pte = vtopte(va); 736 *head = *pte; 737 if (*head & PG_V) 738 panic("pmap_ptelist_alloc: va with PG_V set!"); 739 *pte = 0; 740 return (va); 741} 742 743static void 744pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 745{ 746 pt_entry_t *pte; 747 748 if (va & PG_V) 749 panic("pmap_ptelist_free: freeing va with PG_V set!"); 750 pte = vtopte(va); 751 *pte = *head; /* virtual! PG_V is 0 though */ 752 *head = va; 753} 754 755static void 756pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 757{ 758 int i; 759 vm_offset_t va; 760 761 *head = 0; 762 for (i = npages - 1; i >= 0; i--) { 763 va = (vm_offset_t)base + i * PAGE_SIZE; 764 pmap_ptelist_free(head, va); 765 } 766} 767 768 769/* 770 * Initialize the pmap module. 771 * Called by vm_init, to initialize any structures that the pmap 772 * system needs to map virtual memory. 773 */ 774void 775pmap_init(void) 776{ 777 struct pmap_preinit_mapping *ppim; 778 vm_page_t mpte; 779 vm_size_t s; 780 int i, pv_npg; 781 782 /* 783 * Initialize the vm page array entries for the kernel pmap's 784 * page table pages. 785 */ 786 for (i = 0; i < NKPT; i++) { 787 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 788 KASSERT(mpte >= vm_page_array && 789 mpte < &vm_page_array[vm_page_array_size], 790 ("pmap_init: page table page is out of range")); 791 mpte->pindex = i + KPTDI; 792 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 793 } 794 795 /* 796 * Initialize the address space (zone) for the pv entries. Set a 797 * high water mark so that the system can recover from excessive 798 * numbers of pv entries. 799 */ 800 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 801 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 802 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 803 pv_entry_max = roundup(pv_entry_max, _NPCPV); 804 pv_entry_high_water = 9 * (pv_entry_max / 10); 805 806 /* 807 * If the kernel is running on a virtual machine, then it must assume 808 * that MCA is enabled by the hypervisor. Moreover, the kernel must 809 * be prepared for the hypervisor changing the vendor and family that 810 * are reported by CPUID. Consequently, the workaround for AMD Family 811 * 10h Erratum 383 is enabled if the processor's feature set does not 812 * include at least one feature that is only supported by older Intel 813 * or newer AMD processors. 814 */ 815 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 && 816 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 817 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 818 AMDID2_FMA4)) == 0) 819 workaround_erratum383 = 1; 820 821 /* 822 * Are large page mappings supported and enabled? 823 */ 824 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 825 if (pseflag == 0) 826 pg_ps_enabled = 0; 827 else if (pg_ps_enabled) { 828 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 829 ("pmap_init: can't assign to pagesizes[1]")); 830 pagesizes[1] = NBPDR; 831 } 832 833 /* 834 * Calculate the size of the pv head table for superpages. 835 * Handle the possibility that "vm_phys_segs[...].end" is zero. 836 */ 837 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end - 838 PAGE_SIZE) / NBPDR + 1; 839 840 /* 841 * Allocate memory for the pv head table for superpages. 842 */ 843 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 844 s = round_page(s); 845 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 846 M_WAITOK | M_ZERO); 847 for (i = 0; i < pv_npg; i++) 848 TAILQ_INIT(&pv_table[i].pv_list); 849 850 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 851 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 852 if (pv_chunkbase == NULL) 853 panic("pmap_init: not enough kvm for pv chunks"); 854 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 855#if defined(PAE) || defined(PAE_TABLES) 856 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 857 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 858 UMA_ZONE_VM | UMA_ZONE_NOFREE); 859 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 860#endif 861 862 pmap_initialized = 1; 863 if (!bootverbose) 864 return; 865 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 866 ppim = pmap_preinit_mapping + i; 867 if (ppim->va == 0) 868 continue; 869 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i, 870 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode); 871 } 872} 873 874 875SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 876 "Max number of PV entries"); 877SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 878 "Page share factor per proc"); 879 880static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 881 "2/4MB page mapping counters"); 882 883static u_long pmap_pde_demotions; 884SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 885 &pmap_pde_demotions, 0, "2/4MB page demotions"); 886 887static u_long pmap_pde_mappings; 888SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 889 &pmap_pde_mappings, 0, "2/4MB page mappings"); 890 891static u_long pmap_pde_p_failures; 892SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 893 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 894 895static u_long pmap_pde_promotions; 896SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 897 &pmap_pde_promotions, 0, "2/4MB page promotions"); 898 899/*************************************************** 900 * Low level helper routines..... 901 ***************************************************/ 902 903/* 904 * Determine the appropriate bits to set in a PTE or PDE for a specified 905 * caching mode. 906 */ 907int 908pmap_cache_bits(int mode, boolean_t is_pde) 909{ 910 int cache_bits, pat_flag, pat_idx; 911 912 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0) 913 panic("Unknown caching mode %d\n", mode); 914 915 /* The PAT bit is different for PTE's and PDE's. */ 916 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 917 918 /* Map the caching mode to a PAT index. */ 919 pat_idx = pat_index[mode]; 920 921 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 922 cache_bits = 0; 923 if (pat_idx & 0x4) 924 cache_bits |= pat_flag; 925 if (pat_idx & 0x2) 926 cache_bits |= PG_NC_PCD; 927 if (pat_idx & 0x1) 928 cache_bits |= PG_NC_PWT; 929 return (cache_bits); 930} 931 932/* 933 * The caller is responsible for maintaining TLB consistency. 934 */ 935static void 936pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 937{ 938 pd_entry_t *pde; 939 pmap_t pmap; 940 boolean_t PTD_updated; 941 942 PTD_updated = FALSE; 943 mtx_lock_spin(&allpmaps_lock); 944 LIST_FOREACH(pmap, &allpmaps, pm_list) { 945 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 946 PG_FRAME)) 947 PTD_updated = TRUE; 948 pde = pmap_pde(pmap, va); 949 pde_store(pde, newpde); 950 } 951 mtx_unlock_spin(&allpmaps_lock); 952 KASSERT(PTD_updated, 953 ("pmap_kenter_pde: current page table is not in allpmaps")); 954} 955 956/* 957 * After changing the page size for the specified virtual address in the page 958 * table, flush the corresponding entries from the processor's TLB. Only the 959 * calling processor's TLB is affected. 960 * 961 * The calling thread must be pinned to a processor. 962 */ 963static void 964pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 965{ 966 u_long cr4; 967 968 if ((newpde & PG_PS) == 0) 969 /* Demotion: flush a specific 2MB page mapping. */ 970 invlpg(va); 971 else if ((newpde & PG_G) == 0) 972 /* 973 * Promotion: flush every 4KB page mapping from the TLB 974 * because there are too many to flush individually. 975 */ 976 invltlb(); 977 else { 978 /* 979 * Promotion: flush every 4KB page mapping from the TLB, 980 * including any global (PG_G) mappings. 981 */ 982 cr4 = rcr4(); 983 load_cr4(cr4 & ~CR4_PGE); 984 /* 985 * Although preemption at this point could be detrimental to 986 * performance, it would not lead to an error. PG_G is simply 987 * ignored if CR4.PGE is clear. Moreover, in case this block 988 * is re-entered, the load_cr4() either above or below will 989 * modify CR4.PGE flushing the TLB. 990 */ 991 load_cr4(cr4 | CR4_PGE); 992 } 993} 994 995void 996invltlb_glob(void) 997{ 998 uint64_t cr4; 999 1000 if (pgeflag == 0) { 1001 invltlb(); 1002 } else { 1003 cr4 = rcr4(); 1004 load_cr4(cr4 & ~CR4_PGE); 1005 load_cr4(cr4 | CR4_PGE); 1006 } 1007} 1008 1009 1010#ifdef SMP 1011/* 1012 * For SMP, these functions have to use the IPI mechanism for coherence. 1013 * 1014 * N.B.: Before calling any of the following TLB invalidation functions, 1015 * the calling processor must ensure that all stores updating a non- 1016 * kernel page table are globally performed. Otherwise, another 1017 * processor could cache an old, pre-update entry without being 1018 * invalidated. This can happen one of two ways: (1) The pmap becomes 1019 * active on another processor after its pm_active field is checked by 1020 * one of the following functions but before a store updating the page 1021 * table is globally performed. (2) The pmap becomes active on another 1022 * processor before its pm_active field is checked but due to 1023 * speculative loads one of the following functions stills reads the 1024 * pmap as inactive on the other processor. 1025 * 1026 * The kernel page table is exempt because its pm_active field is 1027 * immutable. The kernel page table is always active on every 1028 * processor. 1029 */ 1030void 1031pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1032{ 1033 cpuset_t *mask, other_cpus; 1034 u_int cpuid; 1035 1036 sched_pin(); 1037 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1038 invlpg(va); 1039 mask = &all_cpus; 1040 } else { 1041 cpuid = PCPU_GET(cpuid); 1042 other_cpus = all_cpus; 1043 CPU_CLR(cpuid, &other_cpus); 1044 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1045 invlpg(va); 1046 CPU_AND(&other_cpus, &pmap->pm_active); 1047 mask = &other_cpus; 1048 } 1049 smp_masked_invlpg(*mask, va); 1050 sched_unpin(); 1051} 1052 1053/* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */ 1054#define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE) 1055 1056void 1057pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1058{ 1059 cpuset_t *mask, other_cpus; 1060 vm_offset_t addr; 1061 u_int cpuid; 1062 1063 if (eva - sva >= PMAP_INVLPG_THRESHOLD) { 1064 pmap_invalidate_all(pmap); 1065 return; 1066 } 1067 1068 sched_pin(); 1069 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1070 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1071 invlpg(addr); 1072 mask = &all_cpus; 1073 } else { 1074 cpuid = PCPU_GET(cpuid); 1075 other_cpus = all_cpus; 1076 CPU_CLR(cpuid, &other_cpus); 1077 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1078 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1079 invlpg(addr); 1080 CPU_AND(&other_cpus, &pmap->pm_active); 1081 mask = &other_cpus; 1082 } 1083 smp_masked_invlpg_range(*mask, sva, eva); 1084 sched_unpin(); 1085} 1086 1087void 1088pmap_invalidate_all(pmap_t pmap) 1089{ 1090 cpuset_t *mask, other_cpus; 1091 u_int cpuid; 1092 1093 sched_pin(); 1094 if (pmap == kernel_pmap) { 1095 invltlb_glob(); 1096 mask = &all_cpus; 1097 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) { 1098 invltlb(); 1099 mask = &all_cpus; 1100 } else { 1101 cpuid = PCPU_GET(cpuid); 1102 other_cpus = all_cpus; 1103 CPU_CLR(cpuid, &other_cpus); 1104 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1105 invltlb(); 1106 CPU_AND(&other_cpus, &pmap->pm_active); 1107 mask = &other_cpus; 1108 } 1109 smp_masked_invltlb(*mask, pmap); 1110 sched_unpin(); 1111} 1112 1113void 1114pmap_invalidate_cache(void) 1115{ 1116 1117 sched_pin(); 1118 wbinvd(); 1119 smp_cache_flush(); 1120 sched_unpin(); 1121} 1122 1123struct pde_action { 1124 cpuset_t invalidate; /* processors that invalidate their TLB */ 1125 vm_offset_t va; 1126 pd_entry_t *pde; 1127 pd_entry_t newpde; 1128 u_int store; /* processor that updates the PDE */ 1129}; 1130 1131static void 1132pmap_update_pde_kernel(void *arg) 1133{ 1134 struct pde_action *act = arg; 1135 pd_entry_t *pde; 1136 pmap_t pmap; 1137 1138 if (act->store == PCPU_GET(cpuid)) { 1139 1140 /* 1141 * Elsewhere, this operation requires allpmaps_lock for 1142 * synchronization. Here, it does not because it is being 1143 * performed in the context of an all_cpus rendezvous. 1144 */ 1145 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1146 pde = pmap_pde(pmap, act->va); 1147 pde_store(pde, act->newpde); 1148 } 1149 } 1150} 1151 1152static void 1153pmap_update_pde_user(void *arg) 1154{ 1155 struct pde_action *act = arg; 1156 1157 if (act->store == PCPU_GET(cpuid)) 1158 pde_store(act->pde, act->newpde); 1159} 1160 1161static void 1162pmap_update_pde_teardown(void *arg) 1163{ 1164 struct pde_action *act = arg; 1165 1166 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1167 pmap_update_pde_invalidate(act->va, act->newpde); 1168} 1169 1170/* 1171 * Change the page size for the specified virtual address in a way that 1172 * prevents any possibility of the TLB ever having two entries that map the 1173 * same virtual address using different page sizes. This is the recommended 1174 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1175 * machine check exception for a TLB state that is improperly diagnosed as a 1176 * hardware error. 1177 */ 1178static void 1179pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1180{ 1181 struct pde_action act; 1182 cpuset_t active, other_cpus; 1183 u_int cpuid; 1184 1185 sched_pin(); 1186 cpuid = PCPU_GET(cpuid); 1187 other_cpus = all_cpus; 1188 CPU_CLR(cpuid, &other_cpus); 1189 if (pmap == kernel_pmap) 1190 active = all_cpus; 1191 else 1192 active = pmap->pm_active; 1193 if (CPU_OVERLAP(&active, &other_cpus)) { 1194 act.store = cpuid; 1195 act.invalidate = active; 1196 act.va = va; 1197 act.pde = pde; 1198 act.newpde = newpde; 1199 CPU_SET(cpuid, &active); 1200 smp_rendezvous_cpus(active, 1201 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1202 pmap_update_pde_kernel : pmap_update_pde_user, 1203 pmap_update_pde_teardown, &act); 1204 } else { 1205 if (pmap == kernel_pmap) 1206 pmap_kenter_pde(va, newpde); 1207 else 1208 pde_store(pde, newpde); 1209 if (CPU_ISSET(cpuid, &active)) 1210 pmap_update_pde_invalidate(va, newpde); 1211 } 1212 sched_unpin(); 1213} 1214#else /* !SMP */ 1215/* 1216 * Normal, non-SMP, 486+ invalidation functions. 1217 * We inline these within pmap.c for speed. 1218 */ 1219PMAP_INLINE void 1220pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1221{ 1222 1223 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1224 invlpg(va); 1225} 1226 1227PMAP_INLINE void 1228pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1229{ 1230 vm_offset_t addr; 1231 1232 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1233 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1234 invlpg(addr); 1235} 1236 1237PMAP_INLINE void 1238pmap_invalidate_all(pmap_t pmap) 1239{ 1240 1241 if (pmap == kernel_pmap) 1242 invltlb_glob(); 1243 else if (!CPU_EMPTY(&pmap->pm_active)) 1244 invltlb(); 1245} 1246 1247PMAP_INLINE void 1248pmap_invalidate_cache(void) 1249{ 1250 1251 wbinvd(); 1252} 1253 1254static void 1255pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1256{ 1257 1258 if (pmap == kernel_pmap) 1259 pmap_kenter_pde(va, newpde); 1260 else 1261 pde_store(pde, newpde); 1262 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1263 pmap_update_pde_invalidate(va, newpde); 1264} 1265#endif /* !SMP */ 1266 1267#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 1268 1269void 1270pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force) 1271{ 1272 1273 if (force) { 1274 sva &= ~(vm_offset_t)cpu_clflush_line_size; 1275 } else { 1276 KASSERT((sva & PAGE_MASK) == 0, 1277 ("pmap_invalidate_cache_range: sva not page-aligned")); 1278 KASSERT((eva & PAGE_MASK) == 0, 1279 ("pmap_invalidate_cache_range: eva not page-aligned")); 1280 } 1281 1282 if ((cpu_feature & CPUID_SS) != 0 && !force) 1283 ; /* If "Self Snoop" is supported and allowed, do nothing. */ 1284 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 && 1285 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1286#ifdef DEV_APIC 1287 /* 1288 * XXX: Some CPUs fault, hang, or trash the local APIC 1289 * registers if we use CLFLUSH on the local APIC 1290 * range. The local APIC is always uncached, so we 1291 * don't need to flush for that range anyway. 1292 */ 1293 if (pmap_kextract(sva) == lapic_paddr) 1294 return; 1295#endif 1296 /* 1297 * Otherwise, do per-cache line flush. Use the sfence 1298 * instruction to insure that previous stores are 1299 * included in the write-back. The processor 1300 * propagates flush to other processors in the cache 1301 * coherence domain. 1302 */ 1303 sfence(); 1304 for (; sva < eva; sva += cpu_clflush_line_size) 1305 clflushopt(sva); 1306 sfence(); 1307 } else if ((cpu_feature & CPUID_CLFSH) != 0 && 1308 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1309#ifdef DEV_APIC 1310 if (pmap_kextract(sva) == lapic_paddr) 1311 return; 1312#endif 1313 /* 1314 * Writes are ordered by CLFLUSH on Intel CPUs. 1315 */ 1316 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1317 mfence(); 1318 for (; sva < eva; sva += cpu_clflush_line_size) 1319 clflush(sva); 1320 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1321 mfence(); 1322 } else { 1323 1324 /* 1325 * No targeted cache flush methods are supported by CPU, 1326 * or the supplied range is bigger than 2MB. 1327 * Globally invalidate cache. 1328 */ 1329 pmap_invalidate_cache(); 1330 } 1331} 1332 1333void 1334pmap_invalidate_cache_pages(vm_page_t *pages, int count) 1335{ 1336 int i; 1337 1338 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 1339 (cpu_feature & CPUID_CLFSH) == 0) { 1340 pmap_invalidate_cache(); 1341 } else { 1342 for (i = 0; i < count; i++) 1343 pmap_flush_page(pages[i]); 1344 } 1345} 1346 1347/* 1348 * Are we current address space or kernel? 1349 */ 1350static __inline int 1351pmap_is_current(pmap_t pmap) 1352{ 1353 1354 return (pmap == kernel_pmap || pmap == 1355 vmspace_pmap(curthread->td_proc->p_vmspace)); 1356} 1357 1358/* 1359 * If the given pmap is not the current or kernel pmap, the returned pte must 1360 * be released by passing it to pmap_pte_release(). 1361 */ 1362pt_entry_t * 1363pmap_pte(pmap_t pmap, vm_offset_t va) 1364{ 1365 pd_entry_t newpf; 1366 pd_entry_t *pde; 1367 1368 pde = pmap_pde(pmap, va); 1369 if (*pde & PG_PS) 1370 return (pde); 1371 if (*pde != 0) { 1372 /* are we current address space or kernel? */ 1373 if (pmap_is_current(pmap)) 1374 return (vtopte(va)); 1375 mtx_lock(&PMAP2mutex); 1376 newpf = *pde & PG_FRAME; 1377 if ((*PMAP2 & PG_FRAME) != newpf) { 1378 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1379 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1380 } 1381 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1382 } 1383 return (NULL); 1384} 1385 1386/* 1387 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1388 * being NULL. 1389 */ 1390static __inline void 1391pmap_pte_release(pt_entry_t *pte) 1392{ 1393 1394 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1395 mtx_unlock(&PMAP2mutex); 1396} 1397 1398/* 1399 * NB: The sequence of updating a page table followed by accesses to the 1400 * corresponding pages is subject to the situation described in the "AMD64 1401 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23, 1402 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG 1403 * right after modifying the PTE bits is crucial. 1404 */ 1405static __inline void 1406invlcaddr(void *caddr) 1407{ 1408 1409 invlpg((u_int)caddr); 1410} 1411 1412/* 1413 * Super fast pmap_pte routine best used when scanning 1414 * the pv lists. This eliminates many coarse-grained 1415 * invltlb calls. Note that many of the pv list 1416 * scans are across different pmaps. It is very wasteful 1417 * to do an entire invltlb for checking a single mapping. 1418 * 1419 * If the given pmap is not the current pmap, pvh_global_lock 1420 * must be held and curthread pinned to a CPU. 1421 */ 1422static pt_entry_t * 1423pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1424{ 1425 pd_entry_t newpf; 1426 pd_entry_t *pde; 1427 1428 pde = pmap_pde(pmap, va); 1429 if (*pde & PG_PS) 1430 return (pde); 1431 if (*pde != 0) { 1432 /* are we current address space or kernel? */ 1433 if (pmap_is_current(pmap)) 1434 return (vtopte(va)); 1435 rw_assert(&pvh_global_lock, RA_WLOCKED); 1436 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1437 newpf = *pde & PG_FRAME; 1438 if ((*PMAP1 & PG_FRAME) != newpf) { 1439 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1440#ifdef SMP 1441 PMAP1cpu = PCPU_GET(cpuid); 1442#endif 1443 invlcaddr(PADDR1); 1444 PMAP1changed++; 1445 } else 1446#ifdef SMP 1447 if (PMAP1cpu != PCPU_GET(cpuid)) { 1448 PMAP1cpu = PCPU_GET(cpuid); 1449 invlcaddr(PADDR1); 1450 PMAP1changedcpu++; 1451 } else 1452#endif 1453 PMAP1unchanged++; 1454 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1455 } 1456 return (0); 1457} 1458 1459/* 1460 * Routine: pmap_extract 1461 * Function: 1462 * Extract the physical page address associated 1463 * with the given map/virtual_address pair. 1464 */ 1465vm_paddr_t 1466pmap_extract(pmap_t pmap, vm_offset_t va) 1467{ 1468 vm_paddr_t rtval; 1469 pt_entry_t *pte; 1470 pd_entry_t pde; 1471 1472 rtval = 0; 1473 PMAP_LOCK(pmap); 1474 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1475 if (pde != 0) { 1476 if ((pde & PG_PS) != 0) 1477 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1478 else { 1479 pte = pmap_pte(pmap, va); 1480 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1481 pmap_pte_release(pte); 1482 } 1483 } 1484 PMAP_UNLOCK(pmap); 1485 return (rtval); 1486} 1487 1488/* 1489 * Routine: pmap_extract_and_hold 1490 * Function: 1491 * Atomically extract and hold the physical page 1492 * with the given pmap and virtual address pair 1493 * if that mapping permits the given protection. 1494 */ 1495vm_page_t 1496pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1497{ 1498 pd_entry_t pde; 1499 pt_entry_t pte, *ptep; 1500 vm_page_t m; 1501 vm_paddr_t pa; 1502 1503 pa = 0; 1504 m = NULL; 1505 PMAP_LOCK(pmap); 1506retry: 1507 pde = *pmap_pde(pmap, va); 1508 if (pde != 0) { 1509 if (pde & PG_PS) { 1510 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1511 if (vm_page_pa_tryrelock(pmap, (pde & 1512 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1513 goto retry; 1514 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1515 (va & PDRMASK)); 1516 vm_page_hold(m); 1517 } 1518 } else { 1519 ptep = pmap_pte(pmap, va); 1520 pte = *ptep; 1521 pmap_pte_release(ptep); 1522 if (pte != 0 && 1523 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1524 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1525 &pa)) 1526 goto retry; 1527 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1528 vm_page_hold(m); 1529 } 1530 } 1531 } 1532 PA_UNLOCK_COND(pa); 1533 PMAP_UNLOCK(pmap); 1534 return (m); 1535} 1536 1537/*************************************************** 1538 * Low level mapping routines..... 1539 ***************************************************/ 1540 1541/* 1542 * Add a wired page to the kva. 1543 * Note: not SMP coherent. 1544 * 1545 * This function may be used before pmap_bootstrap() is called. 1546 */ 1547PMAP_INLINE void 1548pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1549{ 1550 pt_entry_t *pte; 1551 1552 pte = vtopte(va); 1553 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1554} 1555 1556static __inline void 1557pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1558{ 1559 pt_entry_t *pte; 1560 1561 pte = vtopte(va); 1562 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1563} 1564 1565/* 1566 * Remove a page from the kernel pagetables. 1567 * Note: not SMP coherent. 1568 * 1569 * This function may be used before pmap_bootstrap() is called. 1570 */ 1571PMAP_INLINE void 1572pmap_kremove(vm_offset_t va) 1573{ 1574 pt_entry_t *pte; 1575 1576 pte = vtopte(va); 1577 pte_clear(pte); 1578} 1579 1580/* 1581 * Used to map a range of physical addresses into kernel 1582 * virtual address space. 1583 * 1584 * The value passed in '*virt' is a suggested virtual address for 1585 * the mapping. Architectures which can support a direct-mapped 1586 * physical to virtual region can return the appropriate address 1587 * within that region, leaving '*virt' unchanged. Other 1588 * architectures should map the pages starting at '*virt' and 1589 * update '*virt' with the first usable address after the mapped 1590 * region. 1591 */ 1592vm_offset_t 1593pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1594{ 1595 vm_offset_t va, sva; 1596 vm_paddr_t superpage_offset; 1597 pd_entry_t newpde; 1598 1599 va = *virt; 1600 /* 1601 * Does the physical address range's size and alignment permit at 1602 * least one superpage mapping to be created? 1603 */ 1604 superpage_offset = start & PDRMASK; 1605 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) { 1606 /* 1607 * Increase the starting virtual address so that its alignment 1608 * does not preclude the use of superpage mappings. 1609 */ 1610 if ((va & PDRMASK) < superpage_offset) 1611 va = (va & ~PDRMASK) + superpage_offset; 1612 else if ((va & PDRMASK) > superpage_offset) 1613 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset; 1614 } 1615 sva = va; 1616 while (start < end) { 1617 if ((start & PDRMASK) == 0 && end - start >= NBPDR && 1618 pseflag) { 1619 KASSERT((va & PDRMASK) == 0, 1620 ("pmap_map: misaligned va %#x", va)); 1621 newpde = start | PG_PS | pgeflag | PG_RW | PG_V; 1622 pmap_kenter_pde(va, newpde); 1623 va += NBPDR; 1624 start += NBPDR; 1625 } else { 1626 pmap_kenter(va, start); 1627 va += PAGE_SIZE; 1628 start += PAGE_SIZE; 1629 } 1630 } 1631 pmap_invalidate_range(kernel_pmap, sva, va); 1632 *virt = va; 1633 return (sva); 1634} 1635 1636 1637/* 1638 * Add a list of wired pages to the kva 1639 * this routine is only used for temporary 1640 * kernel mappings that do not need to have 1641 * page modification or references recorded. 1642 * Note that old mappings are simply written 1643 * over. The page *must* be wired. 1644 * Note: SMP coherent. Uses a ranged shootdown IPI. 1645 */ 1646void 1647pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1648{ 1649 pt_entry_t *endpte, oldpte, pa, *pte; 1650 vm_page_t m; 1651 1652 oldpte = 0; 1653 pte = vtopte(sva); 1654 endpte = pte + count; 1655 while (pte < endpte) { 1656 m = *ma++; 1657 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 1658 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1659 oldpte |= *pte; 1660 pte_store(pte, pa | pgeflag | PG_RW | PG_V); 1661 } 1662 pte++; 1663 } 1664 if (__predict_false((oldpte & PG_V) != 0)) 1665 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1666 PAGE_SIZE); 1667} 1668 1669/* 1670 * This routine tears out page mappings from the 1671 * kernel -- it is meant only for temporary mappings. 1672 * Note: SMP coherent. Uses a ranged shootdown IPI. 1673 */ 1674void 1675pmap_qremove(vm_offset_t sva, int count) 1676{ 1677 vm_offset_t va; 1678 1679 va = sva; 1680 while (count-- > 0) { 1681 pmap_kremove(va); 1682 va += PAGE_SIZE; 1683 } 1684 pmap_invalidate_range(kernel_pmap, sva, va); 1685} 1686 1687/*************************************************** 1688 * Page table page management routines..... 1689 ***************************************************/ 1690static __inline void 1691pmap_free_zero_pages(struct spglist *free) 1692{ 1693 vm_page_t m; 1694 1695 while ((m = SLIST_FIRST(free)) != NULL) { 1696 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1697 /* Preserve the page's PG_ZERO setting. */ 1698 vm_page_free_toq(m); 1699 } 1700} 1701 1702/* 1703 * Schedule the specified unused page table page to be freed. Specifically, 1704 * add the page to the specified list of pages that will be released to the 1705 * physical memory manager after the TLB has been updated. 1706 */ 1707static __inline void 1708pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1709 boolean_t set_PG_ZERO) 1710{ 1711 1712 if (set_PG_ZERO) 1713 m->flags |= PG_ZERO; 1714 else 1715 m->flags &= ~PG_ZERO; 1716 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1717} 1718 1719/* 1720 * Inserts the specified page table page into the specified pmap's collection 1721 * of idle page table pages. Each of a pmap's page table pages is responsible 1722 * for mapping a distinct range of virtual addresses. The pmap's collection is 1723 * ordered by this virtual address range. 1724 */ 1725static __inline int 1726pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1727{ 1728 1729 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1730 return (vm_radix_insert(&pmap->pm_root, mpte)); 1731} 1732 1733/* 1734 * Looks for a page table page mapping the specified virtual address in the 1735 * specified pmap's collection of idle page table pages. Returns NULL if there 1736 * is no page table page corresponding to the specified virtual address. 1737 */ 1738static __inline vm_page_t 1739pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1740{ 1741 1742 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1743 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT)); 1744} 1745 1746/* 1747 * Removes the specified page table page from the specified pmap's collection 1748 * of idle page table pages. The specified page table page must be a member of 1749 * the pmap's collection. 1750 */ 1751static __inline void 1752pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1753{ 1754 1755 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1756 vm_radix_remove(&pmap->pm_root, mpte->pindex); 1757} 1758 1759/* 1760 * Decrements a page table page's wire count, which is used to record the 1761 * number of valid page table entries within the page. If the wire count 1762 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1763 * page table page was unmapped and FALSE otherwise. 1764 */ 1765static inline boolean_t 1766pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1767{ 1768 1769 --m->wire_count; 1770 if (m->wire_count == 0) { 1771 _pmap_unwire_ptp(pmap, m, free); 1772 return (TRUE); 1773 } else 1774 return (FALSE); 1775} 1776 1777static void 1778_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1779{ 1780 vm_offset_t pteva; 1781 1782 /* 1783 * unmap the page table page 1784 */ 1785 pmap->pm_pdir[m->pindex] = 0; 1786 --pmap->pm_stats.resident_count; 1787 1788 /* 1789 * This is a release store so that the ordinary store unmapping 1790 * the page table page is globally performed before TLB shoot- 1791 * down is begun. 1792 */ 1793 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1); 1794 1795 /* 1796 * Do an invltlb to make the invalidated mapping 1797 * take effect immediately. 1798 */ 1799 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1800 pmap_invalidate_page(pmap, pteva); 1801 1802 /* 1803 * Put page on a list so that it is released after 1804 * *ALL* TLB shootdown is done 1805 */ 1806 pmap_add_delayed_free_list(m, free, TRUE); 1807} 1808 1809/* 1810 * After removing a page table entry, this routine is used to 1811 * conditionally free the page, and manage the hold/wire counts. 1812 */ 1813static int 1814pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free) 1815{ 1816 pd_entry_t ptepde; 1817 vm_page_t mpte; 1818 1819 if (va >= VM_MAXUSER_ADDRESS) 1820 return (0); 1821 ptepde = *pmap_pde(pmap, va); 1822 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1823 return (pmap_unwire_ptp(pmap, mpte, free)); 1824} 1825 1826/* 1827 * Initialize the pmap for the swapper process. 1828 */ 1829void 1830pmap_pinit0(pmap_t pmap) 1831{ 1832 1833 PMAP_LOCK_INIT(pmap); 1834 /* 1835 * Since the page table directory is shared with the kernel pmap, 1836 * which is already included in the list "allpmaps", this pmap does 1837 * not need to be inserted into that list. 1838 */ 1839 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1840#if defined(PAE) || defined(PAE_TABLES) 1841 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1842#endif 1843 pmap->pm_root.rt_root = 0; 1844 CPU_ZERO(&pmap->pm_active); 1845 PCPU_SET(curpmap, pmap); 1846 TAILQ_INIT(&pmap->pm_pvchunk); 1847 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1848} 1849 1850/* 1851 * Initialize a preallocated and zeroed pmap structure, 1852 * such as one in a vmspace structure. 1853 */ 1854int 1855pmap_pinit(pmap_t pmap) 1856{ 1857 vm_page_t m, ptdpg[NPGPTD]; 1858 vm_paddr_t pa; 1859 int i; 1860 1861 /* 1862 * No need to allocate page table space yet but we do need a valid 1863 * page directory table. 1864 */ 1865 if (pmap->pm_pdir == NULL) { 1866 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1867 if (pmap->pm_pdir == NULL) 1868 return (0); 1869#if defined(PAE) || defined(PAE_TABLES) 1870 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1871 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1872 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1873 ("pmap_pinit: pdpt misaligned")); 1874 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1875 ("pmap_pinit: pdpt above 4g")); 1876#endif 1877 pmap->pm_root.rt_root = 0; 1878 } 1879 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1880 ("pmap_pinit: pmap has reserved page table page(s)")); 1881 1882 /* 1883 * allocate the page directory page(s) 1884 */ 1885 for (i = 0; i < NPGPTD;) { 1886 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1887 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1888 if (m == NULL) 1889 VM_WAIT; 1890 else { 1891 ptdpg[i++] = m; 1892 } 1893 } 1894 1895 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1896 1897 for (i = 0; i < NPGPTD; i++) 1898 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1899 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1900 1901 mtx_lock_spin(&allpmaps_lock); 1902 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1903 /* Copy the kernel page table directory entries. */ 1904 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1905 mtx_unlock_spin(&allpmaps_lock); 1906 1907 /* install self-referential address mapping entry(s) */ 1908 for (i = 0; i < NPGPTD; i++) { 1909 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1910 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1911#if defined(PAE) || defined(PAE_TABLES) 1912 pmap->pm_pdpt[i] = pa | PG_V; 1913#endif 1914 } 1915 1916 CPU_ZERO(&pmap->pm_active); 1917 TAILQ_INIT(&pmap->pm_pvchunk); 1918 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1919 1920 return (1); 1921} 1922 1923/* 1924 * this routine is called if the page table page is not 1925 * mapped correctly. 1926 */ 1927static vm_page_t 1928_pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags) 1929{ 1930 vm_paddr_t ptepa; 1931 vm_page_t m; 1932 1933 /* 1934 * Allocate a page table page. 1935 */ 1936 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1937 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1938 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1939 PMAP_UNLOCK(pmap); 1940 rw_wunlock(&pvh_global_lock); 1941 VM_WAIT; 1942 rw_wlock(&pvh_global_lock); 1943 PMAP_LOCK(pmap); 1944 } 1945 1946 /* 1947 * Indicate the need to retry. While waiting, the page table 1948 * page may have been allocated. 1949 */ 1950 return (NULL); 1951 } 1952 if ((m->flags & PG_ZERO) == 0) 1953 pmap_zero_page(m); 1954 1955 /* 1956 * Map the pagetable page into the process address space, if 1957 * it isn't already there. 1958 */ 1959 1960 pmap->pm_stats.resident_count++; 1961 1962 ptepa = VM_PAGE_TO_PHYS(m); 1963 pmap->pm_pdir[ptepindex] = 1964 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1965 1966 return (m); 1967} 1968 1969static vm_page_t 1970pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1971{ 1972 u_int ptepindex; 1973 pd_entry_t ptepa; 1974 vm_page_t m; 1975 1976 /* 1977 * Calculate pagetable page index 1978 */ 1979 ptepindex = va >> PDRSHIFT; 1980retry: 1981 /* 1982 * Get the page directory entry 1983 */ 1984 ptepa = pmap->pm_pdir[ptepindex]; 1985 1986 /* 1987 * This supports switching from a 4MB page to a 1988 * normal 4K page. 1989 */ 1990 if (ptepa & PG_PS) { 1991 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1992 ptepa = pmap->pm_pdir[ptepindex]; 1993 } 1994 1995 /* 1996 * If the page table page is mapped, we just increment the 1997 * hold count, and activate it. 1998 */ 1999 if (ptepa) { 2000 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 2001 m->wire_count++; 2002 } else { 2003 /* 2004 * Here if the pte page isn't mapped, or if it has 2005 * been deallocated. 2006 */ 2007 m = _pmap_allocpte(pmap, ptepindex, flags); 2008 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 2009 goto retry; 2010 } 2011 return (m); 2012} 2013 2014 2015/*************************************************** 2016* Pmap allocation/deallocation routines. 2017 ***************************************************/ 2018 2019/* 2020 * Release any resources held by the given physical map. 2021 * Called when a pmap initialized by pmap_pinit is being released. 2022 * Should only be called if the map contains no valid mappings. 2023 */ 2024void 2025pmap_release(pmap_t pmap) 2026{ 2027 vm_page_t m, ptdpg[NPGPTD]; 2028 int i; 2029 2030 KASSERT(pmap->pm_stats.resident_count == 0, 2031 ("pmap_release: pmap resident count %ld != 0", 2032 pmap->pm_stats.resident_count)); 2033 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2034 ("pmap_release: pmap has reserved page table page(s)")); 2035 KASSERT(CPU_EMPTY(&pmap->pm_active), 2036 ("releasing active pmap %p", pmap)); 2037 2038 mtx_lock_spin(&allpmaps_lock); 2039 LIST_REMOVE(pmap, pm_list); 2040 mtx_unlock_spin(&allpmaps_lock); 2041 2042 for (i = 0; i < NPGPTD; i++) 2043 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 2044 PG_FRAME); 2045 2046 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 2047 sizeof(*pmap->pm_pdir)); 2048 2049 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2050 2051 for (i = 0; i < NPGPTD; i++) { 2052 m = ptdpg[i]; 2053#if defined(PAE) || defined(PAE_TABLES) 2054 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2055 ("pmap_release: got wrong ptd page")); 2056#endif 2057 m->wire_count--; 2058 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 2059 vm_page_free_zero(m); 2060 } 2061} 2062 2063static int 2064kvm_size(SYSCTL_HANDLER_ARGS) 2065{ 2066 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2067 2068 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2069} 2070SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2071 0, 0, kvm_size, "IU", "Size of KVM"); 2072 2073static int 2074kvm_free(SYSCTL_HANDLER_ARGS) 2075{ 2076 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2077 2078 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2079} 2080SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2081 0, 0, kvm_free, "IU", "Amount of KVM free"); 2082 2083/* 2084 * grow the number of kernel page table entries, if needed 2085 */ 2086void 2087pmap_growkernel(vm_offset_t addr) 2088{ 2089 vm_paddr_t ptppaddr; 2090 vm_page_t nkpg; 2091 pd_entry_t newpdir; 2092 2093 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2094 addr = roundup2(addr, NBPDR); 2095 if (addr - 1 >= kernel_map->max_offset) 2096 addr = kernel_map->max_offset; 2097 while (kernel_vm_end < addr) { 2098 if (pdir_pde(PTD, kernel_vm_end)) { 2099 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2100 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2101 kernel_vm_end = kernel_map->max_offset; 2102 break; 2103 } 2104 continue; 2105 } 2106 2107 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2108 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2109 VM_ALLOC_ZERO); 2110 if (nkpg == NULL) 2111 panic("pmap_growkernel: no memory to grow kernel"); 2112 2113 nkpt++; 2114 2115 if ((nkpg->flags & PG_ZERO) == 0) 2116 pmap_zero_page(nkpg); 2117 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2118 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2119 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2120 2121 pmap_kenter_pde(kernel_vm_end, newpdir); 2122 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2123 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2124 kernel_vm_end = kernel_map->max_offset; 2125 break; 2126 } 2127 } 2128} 2129 2130 2131/*************************************************** 2132 * page management routines. 2133 ***************************************************/ 2134 2135CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2136CTASSERT(_NPCM == 11); 2137CTASSERT(_NPCPV == 336); 2138 2139static __inline struct pv_chunk * 2140pv_to_chunk(pv_entry_t pv) 2141{ 2142 2143 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2144} 2145 2146#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2147 2148#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2149#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2150 2151static const uint32_t pc_freemask[_NPCM] = { 2152 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2153 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2154 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2155 PC_FREE0_9, PC_FREE10 2156}; 2157 2158SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2159 "Current number of pv entries"); 2160 2161#ifdef PV_STATS 2162static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2163 2164SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2165 "Current number of pv entry chunks"); 2166SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2167 "Current number of pv entry chunks allocated"); 2168SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2169 "Current number of pv entry chunks frees"); 2170SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2171 "Number of times tried to get a chunk page but failed."); 2172 2173static long pv_entry_frees, pv_entry_allocs; 2174static int pv_entry_spare; 2175 2176SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2177 "Current number of pv entry frees"); 2178SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2179 "Current number of pv entry allocs"); 2180SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2181 "Current number of spare pv entries"); 2182#endif 2183 2184/* 2185 * We are in a serious low memory condition. Resort to 2186 * drastic measures to free some pages so we can allocate 2187 * another pv entry chunk. 2188 */ 2189static vm_page_t 2190pmap_pv_reclaim(pmap_t locked_pmap) 2191{ 2192 struct pch newtail; 2193 struct pv_chunk *pc; 2194 struct md_page *pvh; 2195 pd_entry_t *pde; 2196 pmap_t pmap; 2197 pt_entry_t *pte, tpte; 2198 pv_entry_t pv; 2199 vm_offset_t va; 2200 vm_page_t m, m_pc; 2201 struct spglist free; 2202 uint32_t inuse; 2203 int bit, field, freed; 2204 2205 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2206 pmap = NULL; 2207 m_pc = NULL; 2208 SLIST_INIT(&free); 2209 TAILQ_INIT(&newtail); 2210 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 2211 SLIST_EMPTY(&free))) { 2212 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2213 if (pmap != pc->pc_pmap) { 2214 if (pmap != NULL) { 2215 pmap_invalidate_all(pmap); 2216 if (pmap != locked_pmap) 2217 PMAP_UNLOCK(pmap); 2218 } 2219 pmap = pc->pc_pmap; 2220 /* Avoid deadlock and lock recursion. */ 2221 if (pmap > locked_pmap) 2222 PMAP_LOCK(pmap); 2223 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2224 pmap = NULL; 2225 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2226 continue; 2227 } 2228 } 2229 2230 /* 2231 * Destroy every non-wired, 4 KB page mapping in the chunk. 2232 */ 2233 freed = 0; 2234 for (field = 0; field < _NPCM; field++) { 2235 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2236 inuse != 0; inuse &= ~(1UL << bit)) { 2237 bit = bsfl(inuse); 2238 pv = &pc->pc_pventry[field * 32 + bit]; 2239 va = pv->pv_va; 2240 pde = pmap_pde(pmap, va); 2241 if ((*pde & PG_PS) != 0) 2242 continue; 2243 pte = pmap_pte(pmap, va); 2244 tpte = *pte; 2245 if ((tpte & PG_W) == 0) 2246 tpte = pte_load_clear(pte); 2247 pmap_pte_release(pte); 2248 if ((tpte & PG_W) != 0) 2249 continue; 2250 KASSERT(tpte != 0, 2251 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2252 pmap, va)); 2253 if ((tpte & PG_G) != 0) 2254 pmap_invalidate_page(pmap, va); 2255 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2256 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2257 vm_page_dirty(m); 2258 if ((tpte & PG_A) != 0) 2259 vm_page_aflag_set(m, PGA_REFERENCED); 2260 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2261 if (TAILQ_EMPTY(&m->md.pv_list) && 2262 (m->flags & PG_FICTITIOUS) == 0) { 2263 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2264 if (TAILQ_EMPTY(&pvh->pv_list)) { 2265 vm_page_aflag_clear(m, 2266 PGA_WRITEABLE); 2267 } 2268 } 2269 pc->pc_map[field] |= 1UL << bit; 2270 pmap_unuse_pt(pmap, va, &free); 2271 freed++; 2272 } 2273 } 2274 if (freed == 0) { 2275 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2276 continue; 2277 } 2278 /* Every freed mapping is for a 4 KB page. */ 2279 pmap->pm_stats.resident_count -= freed; 2280 PV_STAT(pv_entry_frees += freed); 2281 PV_STAT(pv_entry_spare += freed); 2282 pv_entry_count -= freed; 2283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2284 for (field = 0; field < _NPCM; field++) 2285 if (pc->pc_map[field] != pc_freemask[field]) { 2286 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2287 pc_list); 2288 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2289 2290 /* 2291 * One freed pv entry in locked_pmap is 2292 * sufficient. 2293 */ 2294 if (pmap == locked_pmap) 2295 goto out; 2296 break; 2297 } 2298 if (field == _NPCM) { 2299 PV_STAT(pv_entry_spare -= _NPCPV); 2300 PV_STAT(pc_chunk_count--); 2301 PV_STAT(pc_chunk_frees++); 2302 /* Entire chunk is free; return it. */ 2303 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2304 pmap_qremove((vm_offset_t)pc, 1); 2305 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2306 break; 2307 } 2308 } 2309out: 2310 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2311 if (pmap != NULL) { 2312 pmap_invalidate_all(pmap); 2313 if (pmap != locked_pmap) 2314 PMAP_UNLOCK(pmap); 2315 } 2316 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) { 2317 m_pc = SLIST_FIRST(&free); 2318 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2319 /* Recycle a freed page table page. */ 2320 m_pc->wire_count = 1; 2321 atomic_add_int(&vm_cnt.v_wire_count, 1); 2322 } 2323 pmap_free_zero_pages(&free); 2324 return (m_pc); 2325} 2326 2327/* 2328 * free the pv_entry back to the free list 2329 */ 2330static void 2331free_pv_entry(pmap_t pmap, pv_entry_t pv) 2332{ 2333 struct pv_chunk *pc; 2334 int idx, field, bit; 2335 2336 rw_assert(&pvh_global_lock, RA_WLOCKED); 2337 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2338 PV_STAT(pv_entry_frees++); 2339 PV_STAT(pv_entry_spare++); 2340 pv_entry_count--; 2341 pc = pv_to_chunk(pv); 2342 idx = pv - &pc->pc_pventry[0]; 2343 field = idx / 32; 2344 bit = idx % 32; 2345 pc->pc_map[field] |= 1ul << bit; 2346 for (idx = 0; idx < _NPCM; idx++) 2347 if (pc->pc_map[idx] != pc_freemask[idx]) { 2348 /* 2349 * 98% of the time, pc is already at the head of the 2350 * list. If it isn't already, move it to the head. 2351 */ 2352 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2353 pc)) { 2354 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2355 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2356 pc_list); 2357 } 2358 return; 2359 } 2360 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2361 free_pv_chunk(pc); 2362} 2363 2364static void 2365free_pv_chunk(struct pv_chunk *pc) 2366{ 2367 vm_page_t m; 2368 2369 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2370 PV_STAT(pv_entry_spare -= _NPCPV); 2371 PV_STAT(pc_chunk_count--); 2372 PV_STAT(pc_chunk_frees++); 2373 /* entire chunk is free, return it */ 2374 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2375 pmap_qremove((vm_offset_t)pc, 1); 2376 vm_page_unwire(m, PQ_NONE); 2377 vm_page_free(m); 2378 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2379} 2380 2381/* 2382 * get a new pv_entry, allocating a block from the system 2383 * when needed. 2384 */ 2385static pv_entry_t 2386get_pv_entry(pmap_t pmap, boolean_t try) 2387{ 2388 static const struct timeval printinterval = { 60, 0 }; 2389 static struct timeval lastprint; 2390 int bit, field; 2391 pv_entry_t pv; 2392 struct pv_chunk *pc; 2393 vm_page_t m; 2394 2395 rw_assert(&pvh_global_lock, RA_WLOCKED); 2396 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2397 PV_STAT(pv_entry_allocs++); 2398 pv_entry_count++; 2399 if (pv_entry_count > pv_entry_high_water) 2400 if (ratecheck(&lastprint, &printinterval)) 2401 printf("Approaching the limit on PV entries, consider " 2402 "increasing either the vm.pmap.shpgperproc or the " 2403 "vm.pmap.pv_entry_max tunable.\n"); 2404retry: 2405 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2406 if (pc != NULL) { 2407 for (field = 0; field < _NPCM; field++) { 2408 if (pc->pc_map[field]) { 2409 bit = bsfl(pc->pc_map[field]); 2410 break; 2411 } 2412 } 2413 if (field < _NPCM) { 2414 pv = &pc->pc_pventry[field * 32 + bit]; 2415 pc->pc_map[field] &= ~(1ul << bit); 2416 /* If this was the last item, move it to tail */ 2417 for (field = 0; field < _NPCM; field++) 2418 if (pc->pc_map[field] != 0) { 2419 PV_STAT(pv_entry_spare--); 2420 return (pv); /* not full, return */ 2421 } 2422 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2423 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2424 PV_STAT(pv_entry_spare--); 2425 return (pv); 2426 } 2427 } 2428 /* 2429 * Access to the ptelist "pv_vafree" is synchronized by the pvh 2430 * global lock. If "pv_vafree" is currently non-empty, it will 2431 * remain non-empty until pmap_ptelist_alloc() completes. 2432 */ 2433 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2434 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2435 if (try) { 2436 pv_entry_count--; 2437 PV_STAT(pc_chunk_tryfail++); 2438 return (NULL); 2439 } 2440 m = pmap_pv_reclaim(pmap); 2441 if (m == NULL) 2442 goto retry; 2443 } 2444 PV_STAT(pc_chunk_count++); 2445 PV_STAT(pc_chunk_allocs++); 2446 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2447 pmap_qenter((vm_offset_t)pc, &m, 1); 2448 pc->pc_pmap = pmap; 2449 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2450 for (field = 1; field < _NPCM; field++) 2451 pc->pc_map[field] = pc_freemask[field]; 2452 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2453 pv = &pc->pc_pventry[0]; 2454 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2455 PV_STAT(pv_entry_spare += _NPCPV - 1); 2456 return (pv); 2457} 2458 2459static __inline pv_entry_t 2460pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2461{ 2462 pv_entry_t pv; 2463 2464 rw_assert(&pvh_global_lock, RA_WLOCKED); 2465 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2466 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2467 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2468 break; 2469 } 2470 } 2471 return (pv); 2472} 2473 2474static void 2475pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2476{ 2477 struct md_page *pvh; 2478 pv_entry_t pv; 2479 vm_offset_t va_last; 2480 vm_page_t m; 2481 2482 rw_assert(&pvh_global_lock, RA_WLOCKED); 2483 KASSERT((pa & PDRMASK) == 0, 2484 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2485 2486 /* 2487 * Transfer the 4mpage's pv entry for this mapping to the first 2488 * page's pv list. 2489 */ 2490 pvh = pa_to_pvh(pa); 2491 va = trunc_4mpage(va); 2492 pv = pmap_pvh_remove(pvh, pmap, va); 2493 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2494 m = PHYS_TO_VM_PAGE(pa); 2495 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2496 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2497 va_last = va + NBPDR - PAGE_SIZE; 2498 do { 2499 m++; 2500 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2501 ("pmap_pv_demote_pde: page %p is not managed", m)); 2502 va += PAGE_SIZE; 2503 pmap_insert_entry(pmap, va, m); 2504 } while (va < va_last); 2505} 2506 2507static void 2508pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2509{ 2510 struct md_page *pvh; 2511 pv_entry_t pv; 2512 vm_offset_t va_last; 2513 vm_page_t m; 2514 2515 rw_assert(&pvh_global_lock, RA_WLOCKED); 2516 KASSERT((pa & PDRMASK) == 0, 2517 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2518 2519 /* 2520 * Transfer the first page's pv entry for this mapping to the 2521 * 4mpage's pv list. Aside from avoiding the cost of a call 2522 * to get_pv_entry(), a transfer avoids the possibility that 2523 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2524 * removes one of the mappings that is being promoted. 2525 */ 2526 m = PHYS_TO_VM_PAGE(pa); 2527 va = trunc_4mpage(va); 2528 pv = pmap_pvh_remove(&m->md, pmap, va); 2529 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2530 pvh = pa_to_pvh(pa); 2531 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2532 /* Free the remaining NPTEPG - 1 pv entries. */ 2533 va_last = va + NBPDR - PAGE_SIZE; 2534 do { 2535 m++; 2536 va += PAGE_SIZE; 2537 pmap_pvh_free(&m->md, pmap, va); 2538 } while (va < va_last); 2539} 2540 2541static void 2542pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2543{ 2544 pv_entry_t pv; 2545 2546 pv = pmap_pvh_remove(pvh, pmap, va); 2547 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2548 free_pv_entry(pmap, pv); 2549} 2550 2551static void 2552pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2553{ 2554 struct md_page *pvh; 2555 2556 rw_assert(&pvh_global_lock, RA_WLOCKED); 2557 pmap_pvh_free(&m->md, pmap, va); 2558 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) { 2559 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2560 if (TAILQ_EMPTY(&pvh->pv_list)) 2561 vm_page_aflag_clear(m, PGA_WRITEABLE); 2562 } 2563} 2564 2565/* 2566 * Create a pv entry for page at pa for 2567 * (pmap, va). 2568 */ 2569static void 2570pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2571{ 2572 pv_entry_t pv; 2573 2574 rw_assert(&pvh_global_lock, RA_WLOCKED); 2575 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2576 pv = get_pv_entry(pmap, FALSE); 2577 pv->pv_va = va; 2578 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2579} 2580 2581/* 2582 * Conditionally create a pv entry. 2583 */ 2584static boolean_t 2585pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2586{ 2587 pv_entry_t pv; 2588 2589 rw_assert(&pvh_global_lock, RA_WLOCKED); 2590 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2591 if (pv_entry_count < pv_entry_high_water && 2592 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2593 pv->pv_va = va; 2594 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2595 return (TRUE); 2596 } else 2597 return (FALSE); 2598} 2599 2600/* 2601 * Create the pv entries for each of the pages within a superpage. 2602 */ 2603static boolean_t 2604pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2605{ 2606 struct md_page *pvh; 2607 pv_entry_t pv; 2608 2609 rw_assert(&pvh_global_lock, RA_WLOCKED); 2610 if (pv_entry_count < pv_entry_high_water && 2611 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2612 pv->pv_va = va; 2613 pvh = pa_to_pvh(pa); 2614 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2615 return (TRUE); 2616 } else 2617 return (FALSE); 2618} 2619 2620/* 2621 * Fills a page table page with mappings to consecutive physical pages. 2622 */ 2623static void 2624pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2625{ 2626 pt_entry_t *pte; 2627 2628 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2629 *pte = newpte; 2630 newpte += PAGE_SIZE; 2631 } 2632} 2633 2634/* 2635 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2636 * 2- or 4MB page mapping is invalidated. 2637 */ 2638static boolean_t 2639pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2640{ 2641 pd_entry_t newpde, oldpde; 2642 pt_entry_t *firstpte, newpte; 2643 vm_paddr_t mptepa; 2644 vm_page_t mpte; 2645 struct spglist free; 2646 vm_offset_t sva; 2647 2648 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2649 oldpde = *pde; 2650 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2651 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2652 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) != 2653 NULL) 2654 pmap_remove_pt_page(pmap, mpte); 2655 else { 2656 KASSERT((oldpde & PG_W) == 0, 2657 ("pmap_demote_pde: page table page for a wired mapping" 2658 " is missing")); 2659 2660 /* 2661 * Invalidate the 2- or 4MB page mapping and return 2662 * "failure" if the mapping was never accessed or the 2663 * allocation of the new page table page fails. 2664 */ 2665 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2666 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2667 VM_ALLOC_WIRED)) == NULL) { 2668 SLIST_INIT(&free); 2669 sva = trunc_4mpage(va); 2670 pmap_remove_pde(pmap, pde, sva, &free); 2671 pmap_invalidate_range(pmap, sva, sva + NBPDR - 1); 2672 pmap_free_zero_pages(&free); 2673 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2674 " in pmap %p", va, pmap); 2675 return (FALSE); 2676 } 2677 if (va < VM_MAXUSER_ADDRESS) 2678 pmap->pm_stats.resident_count++; 2679 } 2680 mptepa = VM_PAGE_TO_PHYS(mpte); 2681 2682 /* 2683 * If the page mapping is in the kernel's address space, then the 2684 * KPTmap can provide access to the page table page. Otherwise, 2685 * temporarily map the page table page (mpte) into the kernel's 2686 * address space at either PADDR1 or PADDR2. 2687 */ 2688 if (va >= KERNBASE) 2689 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2690 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) { 2691 if ((*PMAP1 & PG_FRAME) != mptepa) { 2692 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2693#ifdef SMP 2694 PMAP1cpu = PCPU_GET(cpuid); 2695#endif 2696 invlcaddr(PADDR1); 2697 PMAP1changed++; 2698 } else 2699#ifdef SMP 2700 if (PMAP1cpu != PCPU_GET(cpuid)) { 2701 PMAP1cpu = PCPU_GET(cpuid); 2702 invlcaddr(PADDR1); 2703 PMAP1changedcpu++; 2704 } else 2705#endif 2706 PMAP1unchanged++; 2707 firstpte = PADDR1; 2708 } else { 2709 mtx_lock(&PMAP2mutex); 2710 if ((*PMAP2 & PG_FRAME) != mptepa) { 2711 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2712 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2713 } 2714 firstpte = PADDR2; 2715 } 2716 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2717 KASSERT((oldpde & PG_A) != 0, 2718 ("pmap_demote_pde: oldpde is missing PG_A")); 2719 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2720 ("pmap_demote_pde: oldpde is missing PG_M")); 2721 newpte = oldpde & ~PG_PS; 2722 if ((newpte & PG_PDE_PAT) != 0) 2723 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2724 2725 /* 2726 * If the page table page is new, initialize it. 2727 */ 2728 if (mpte->wire_count == 1) { 2729 mpte->wire_count = NPTEPG; 2730 pmap_fill_ptp(firstpte, newpte); 2731 } 2732 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2733 ("pmap_demote_pde: firstpte and newpte map different physical" 2734 " addresses")); 2735 2736 /* 2737 * If the mapping has changed attributes, update the page table 2738 * entries. 2739 */ 2740 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2741 pmap_fill_ptp(firstpte, newpte); 2742 2743 /* 2744 * Demote the mapping. This pmap is locked. The old PDE has 2745 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2746 * set. Thus, there is no danger of a race with another 2747 * processor changing the setting of PG_A and/or PG_M between 2748 * the read above and the store below. 2749 */ 2750 if (workaround_erratum383) 2751 pmap_update_pde(pmap, va, pde, newpde); 2752 else if (pmap == kernel_pmap) 2753 pmap_kenter_pde(va, newpde); 2754 else 2755 pde_store(pde, newpde); 2756 if (firstpte == PADDR2) 2757 mtx_unlock(&PMAP2mutex); 2758 2759 /* 2760 * Invalidate the recursive mapping of the page table page. 2761 */ 2762 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2763 2764 /* 2765 * Demote the pv entry. This depends on the earlier demotion 2766 * of the mapping. Specifically, the (re)creation of a per- 2767 * page pv entry might trigger the execution of pmap_collect(), 2768 * which might reclaim a newly (re)created per-page pv entry 2769 * and destroy the associated mapping. In order to destroy 2770 * the mapping, the PDE must have already changed from mapping 2771 * the 2mpage to referencing the page table page. 2772 */ 2773 if ((oldpde & PG_MANAGED) != 0) 2774 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2775 2776 pmap_pde_demotions++; 2777 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2778 " in pmap %p", va, pmap); 2779 return (TRUE); 2780} 2781 2782/* 2783 * Removes a 2- or 4MB page mapping from the kernel pmap. 2784 */ 2785static void 2786pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2787{ 2788 pd_entry_t newpde; 2789 vm_paddr_t mptepa; 2790 vm_page_t mpte; 2791 2792 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2793 mpte = pmap_lookup_pt_page(pmap, va); 2794 if (mpte == NULL) 2795 panic("pmap_remove_kernel_pde: Missing pt page."); 2796 2797 pmap_remove_pt_page(pmap, mpte); 2798 mptepa = VM_PAGE_TO_PHYS(mpte); 2799 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V; 2800 2801 /* 2802 * Initialize the page table page. 2803 */ 2804 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]); 2805 2806 /* 2807 * Remove the mapping. 2808 */ 2809 if (workaround_erratum383) 2810 pmap_update_pde(pmap, va, pde, newpde); 2811 else 2812 pmap_kenter_pde(va, newpde); 2813 2814 /* 2815 * Invalidate the recursive mapping of the page table page. 2816 */ 2817 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2818} 2819 2820/* 2821 * pmap_remove_pde: do the things to unmap a superpage in a process 2822 */ 2823static void 2824pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2825 struct spglist *free) 2826{ 2827 struct md_page *pvh; 2828 pd_entry_t oldpde; 2829 vm_offset_t eva, va; 2830 vm_page_t m, mpte; 2831 2832 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2833 KASSERT((sva & PDRMASK) == 0, 2834 ("pmap_remove_pde: sva is not 4mpage aligned")); 2835 oldpde = pte_load_clear(pdq); 2836 if (oldpde & PG_W) 2837 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2838 2839 /* 2840 * Machines that don't support invlpg, also don't support 2841 * PG_G. 2842 * 2843 * When workaround_erratum383 is false, a promotion to a 2M/4M 2844 * page mapping does not invalidate the 512/1024 4K page mappings 2845 * from the TLB. Consequently, at this point, the TLB may 2846 * hold both 4K and 2M/4M page mappings. Therefore, the entire 2847 * range of addresses must be invalidated here. In contrast, 2848 * when workaround_erratum383 is true, a promotion does 2849 * invalidate the 512/1024 4K page mappings, and so a single INVLPG 2850 * suffices to invalidate the 2M/4M page mapping. 2851 */ 2852 if ((oldpde & PG_G) != 0) { 2853 if (workaround_erratum383) 2854 pmap_invalidate_page(kernel_pmap, sva); 2855 else 2856 pmap_invalidate_range(kernel_pmap, sva, 2857 sva + NBPDR - 1); 2858 } 2859 2860 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2861 if (oldpde & PG_MANAGED) { 2862 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2863 pmap_pvh_free(pvh, pmap, sva); 2864 eva = sva + NBPDR; 2865 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2866 va < eva; va += PAGE_SIZE, m++) { 2867 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2868 vm_page_dirty(m); 2869 if (oldpde & PG_A) 2870 vm_page_aflag_set(m, PGA_REFERENCED); 2871 if (TAILQ_EMPTY(&m->md.pv_list) && 2872 TAILQ_EMPTY(&pvh->pv_list)) 2873 vm_page_aflag_clear(m, PGA_WRITEABLE); 2874 } 2875 } 2876 if (pmap == kernel_pmap) { 2877 pmap_remove_kernel_pde(pmap, pdq, sva); 2878 } else { 2879 mpte = pmap_lookup_pt_page(pmap, sva); 2880 if (mpte != NULL) { 2881 pmap_remove_pt_page(pmap, mpte); 2882 pmap->pm_stats.resident_count--; 2883 KASSERT(mpte->wire_count == NPTEPG, 2884 ("pmap_remove_pde: pte page wire count error")); 2885 mpte->wire_count = 0; 2886 pmap_add_delayed_free_list(mpte, free, FALSE); 2887 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 2888 } 2889 } 2890} 2891 2892/* 2893 * pmap_remove_pte: do the things to unmap a page in a process 2894 */ 2895static int 2896pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 2897 struct spglist *free) 2898{ 2899 pt_entry_t oldpte; 2900 vm_page_t m; 2901 2902 rw_assert(&pvh_global_lock, RA_WLOCKED); 2903 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2904 oldpte = pte_load_clear(ptq); 2905 KASSERT(oldpte != 0, 2906 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2907 if (oldpte & PG_W) 2908 pmap->pm_stats.wired_count -= 1; 2909 /* 2910 * Machines that don't support invlpg, also don't support 2911 * PG_G. 2912 */ 2913 if (oldpte & PG_G) 2914 pmap_invalidate_page(kernel_pmap, va); 2915 pmap->pm_stats.resident_count -= 1; 2916 if (oldpte & PG_MANAGED) { 2917 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2918 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2919 vm_page_dirty(m); 2920 if (oldpte & PG_A) 2921 vm_page_aflag_set(m, PGA_REFERENCED); 2922 pmap_remove_entry(pmap, m, va); 2923 } 2924 return (pmap_unuse_pt(pmap, va, free)); 2925} 2926 2927/* 2928 * Remove a single page from a process address space 2929 */ 2930static void 2931pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free) 2932{ 2933 pt_entry_t *pte; 2934 2935 rw_assert(&pvh_global_lock, RA_WLOCKED); 2936 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2937 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2938 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2939 return; 2940 pmap_remove_pte(pmap, pte, va, free); 2941 pmap_invalidate_page(pmap, va); 2942} 2943 2944/* 2945 * Remove the given range of addresses from the specified map. 2946 * 2947 * It is assumed that the start and end are properly 2948 * rounded to the page size. 2949 */ 2950void 2951pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2952{ 2953 vm_offset_t pdnxt; 2954 pd_entry_t ptpaddr; 2955 pt_entry_t *pte; 2956 struct spglist free; 2957 int anyvalid; 2958 2959 /* 2960 * Perform an unsynchronized read. This is, however, safe. 2961 */ 2962 if (pmap->pm_stats.resident_count == 0) 2963 return; 2964 2965 anyvalid = 0; 2966 SLIST_INIT(&free); 2967 2968 rw_wlock(&pvh_global_lock); 2969 sched_pin(); 2970 PMAP_LOCK(pmap); 2971 2972 /* 2973 * special handling of removing one page. a very 2974 * common operation and easy to short circuit some 2975 * code. 2976 */ 2977 if ((sva + PAGE_SIZE == eva) && 2978 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2979 pmap_remove_page(pmap, sva, &free); 2980 goto out; 2981 } 2982 2983 for (; sva < eva; sva = pdnxt) { 2984 u_int pdirindex; 2985 2986 /* 2987 * Calculate index for next page table. 2988 */ 2989 pdnxt = (sva + NBPDR) & ~PDRMASK; 2990 if (pdnxt < sva) 2991 pdnxt = eva; 2992 if (pmap->pm_stats.resident_count == 0) 2993 break; 2994 2995 pdirindex = sva >> PDRSHIFT; 2996 ptpaddr = pmap->pm_pdir[pdirindex]; 2997 2998 /* 2999 * Weed out invalid mappings. Note: we assume that the page 3000 * directory table is always allocated, and in kernel virtual. 3001 */ 3002 if (ptpaddr == 0) 3003 continue; 3004 3005 /* 3006 * Check for large page. 3007 */ 3008 if ((ptpaddr & PG_PS) != 0) { 3009 /* 3010 * Are we removing the entire large page? If not, 3011 * demote the mapping and fall through. 3012 */ 3013 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3014 /* 3015 * The TLB entry for a PG_G mapping is 3016 * invalidated by pmap_remove_pde(). 3017 */ 3018 if ((ptpaddr & PG_G) == 0) 3019 anyvalid = 1; 3020 pmap_remove_pde(pmap, 3021 &pmap->pm_pdir[pdirindex], sva, &free); 3022 continue; 3023 } else if (!pmap_demote_pde(pmap, 3024 &pmap->pm_pdir[pdirindex], sva)) { 3025 /* The large page mapping was destroyed. */ 3026 continue; 3027 } 3028 } 3029 3030 /* 3031 * Limit our scan to either the end of the va represented 3032 * by the current page table page, or to the end of the 3033 * range being removed. 3034 */ 3035 if (pdnxt > eva) 3036 pdnxt = eva; 3037 3038 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3039 sva += PAGE_SIZE) { 3040 if (*pte == 0) 3041 continue; 3042 3043 /* 3044 * The TLB entry for a PG_G mapping is invalidated 3045 * by pmap_remove_pte(). 3046 */ 3047 if ((*pte & PG_G) == 0) 3048 anyvalid = 1; 3049 if (pmap_remove_pte(pmap, pte, sva, &free)) 3050 break; 3051 } 3052 } 3053out: 3054 sched_unpin(); 3055 if (anyvalid) 3056 pmap_invalidate_all(pmap); 3057 rw_wunlock(&pvh_global_lock); 3058 PMAP_UNLOCK(pmap); 3059 pmap_free_zero_pages(&free); 3060} 3061 3062/* 3063 * Routine: pmap_remove_all 3064 * Function: 3065 * Removes this physical page from 3066 * all physical maps in which it resides. 3067 * Reflects back modify bits to the pager. 3068 * 3069 * Notes: 3070 * Original versions of this routine were very 3071 * inefficient because they iteratively called 3072 * pmap_remove (slow...) 3073 */ 3074 3075void 3076pmap_remove_all(vm_page_t m) 3077{ 3078 struct md_page *pvh; 3079 pv_entry_t pv; 3080 pmap_t pmap; 3081 pt_entry_t *pte, tpte; 3082 pd_entry_t *pde; 3083 vm_offset_t va; 3084 struct spglist free; 3085 3086 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3087 ("pmap_remove_all: page %p is not managed", m)); 3088 SLIST_INIT(&free); 3089 rw_wlock(&pvh_global_lock); 3090 sched_pin(); 3091 if ((m->flags & PG_FICTITIOUS) != 0) 3092 goto small_mappings; 3093 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3094 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3095 va = pv->pv_va; 3096 pmap = PV_PMAP(pv); 3097 PMAP_LOCK(pmap); 3098 pde = pmap_pde(pmap, va); 3099 (void)pmap_demote_pde(pmap, pde, va); 3100 PMAP_UNLOCK(pmap); 3101 } 3102small_mappings: 3103 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3104 pmap = PV_PMAP(pv); 3105 PMAP_LOCK(pmap); 3106 pmap->pm_stats.resident_count--; 3107 pde = pmap_pde(pmap, pv->pv_va); 3108 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3109 " a 4mpage in page %p's pv list", m)); 3110 pte = pmap_pte_quick(pmap, pv->pv_va); 3111 tpte = pte_load_clear(pte); 3112 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 3113 pmap, pv->pv_va)); 3114 if (tpte & PG_W) 3115 pmap->pm_stats.wired_count--; 3116 if (tpte & PG_A) 3117 vm_page_aflag_set(m, PGA_REFERENCED); 3118 3119 /* 3120 * Update the vm_page_t clean and reference bits. 3121 */ 3122 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3123 vm_page_dirty(m); 3124 pmap_unuse_pt(pmap, pv->pv_va, &free); 3125 pmap_invalidate_page(pmap, pv->pv_va); 3126 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3127 free_pv_entry(pmap, pv); 3128 PMAP_UNLOCK(pmap); 3129 } 3130 vm_page_aflag_clear(m, PGA_WRITEABLE); 3131 sched_unpin(); 3132 rw_wunlock(&pvh_global_lock); 3133 pmap_free_zero_pages(&free); 3134} 3135 3136/* 3137 * pmap_protect_pde: do the things to protect a 4mpage in a process 3138 */ 3139static boolean_t 3140pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3141{ 3142 pd_entry_t newpde, oldpde; 3143 vm_offset_t eva, va; 3144 vm_page_t m; 3145 boolean_t anychanged; 3146 3147 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3148 KASSERT((sva & PDRMASK) == 0, 3149 ("pmap_protect_pde: sva is not 4mpage aligned")); 3150 anychanged = FALSE; 3151retry: 3152 oldpde = newpde = *pde; 3153 if (oldpde & PG_MANAGED) { 3154 eva = sva + NBPDR; 3155 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3156 va < eva; va += PAGE_SIZE, m++) 3157 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3158 vm_page_dirty(m); 3159 } 3160 if ((prot & VM_PROT_WRITE) == 0) 3161 newpde &= ~(PG_RW | PG_M); 3162#if defined(PAE) || defined(PAE_TABLES) 3163 if ((prot & VM_PROT_EXECUTE) == 0) 3164 newpde |= pg_nx; 3165#endif 3166 if (newpde != oldpde) { 3167 if (!pde_cmpset(pde, oldpde, newpde)) 3168 goto retry; 3169 if (oldpde & PG_G) { 3170 /* See pmap_remove_pde() for explanation. */ 3171 if (workaround_erratum383) 3172 pmap_invalidate_page(kernel_pmap, sva); 3173 else 3174 pmap_invalidate_range(kernel_pmap, sva, 3175 sva + NBPDR - 1); 3176 } else 3177 anychanged = TRUE; 3178 } 3179 return (anychanged); 3180} 3181 3182/* 3183 * Set the physical protection on the 3184 * specified range of this map as requested. 3185 */ 3186void 3187pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3188{ 3189 vm_offset_t pdnxt; 3190 pd_entry_t ptpaddr; 3191 pt_entry_t *pte; 3192 boolean_t anychanged, pv_lists_locked; 3193 3194 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 3195 if (prot == VM_PROT_NONE) { 3196 pmap_remove(pmap, sva, eva); 3197 return; 3198 } 3199 3200#if defined(PAE) || defined(PAE_TABLES) 3201 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3202 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3203 return; 3204#else 3205 if (prot & VM_PROT_WRITE) 3206 return; 3207#endif 3208 3209 if (pmap_is_current(pmap)) 3210 pv_lists_locked = FALSE; 3211 else { 3212 pv_lists_locked = TRUE; 3213resume: 3214 rw_wlock(&pvh_global_lock); 3215 sched_pin(); 3216 } 3217 anychanged = FALSE; 3218 3219 PMAP_LOCK(pmap); 3220 for (; sva < eva; sva = pdnxt) { 3221 pt_entry_t obits, pbits; 3222 u_int pdirindex; 3223 3224 pdnxt = (sva + NBPDR) & ~PDRMASK; 3225 if (pdnxt < sva) 3226 pdnxt = eva; 3227 3228 pdirindex = sva >> PDRSHIFT; 3229 ptpaddr = pmap->pm_pdir[pdirindex]; 3230 3231 /* 3232 * Weed out invalid mappings. Note: we assume that the page 3233 * directory table is always allocated, and in kernel virtual. 3234 */ 3235 if (ptpaddr == 0) 3236 continue; 3237 3238 /* 3239 * Check for large page. 3240 */ 3241 if ((ptpaddr & PG_PS) != 0) { 3242 /* 3243 * Are we protecting the entire large page? If not, 3244 * demote the mapping and fall through. 3245 */ 3246 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3247 /* 3248 * The TLB entry for a PG_G mapping is 3249 * invalidated by pmap_protect_pde(). 3250 */ 3251 if (pmap_protect_pde(pmap, 3252 &pmap->pm_pdir[pdirindex], sva, prot)) 3253 anychanged = TRUE; 3254 continue; 3255 } else { 3256 if (!pv_lists_locked) { 3257 pv_lists_locked = TRUE; 3258 if (!rw_try_wlock(&pvh_global_lock)) { 3259 if (anychanged) 3260 pmap_invalidate_all( 3261 pmap); 3262 PMAP_UNLOCK(pmap); 3263 goto resume; 3264 } 3265 sched_pin(); 3266 } 3267 if (!pmap_demote_pde(pmap, 3268 &pmap->pm_pdir[pdirindex], sva)) { 3269 /* 3270 * The large page mapping was 3271 * destroyed. 3272 */ 3273 continue; 3274 } 3275 } 3276 } 3277 3278 if (pdnxt > eva) 3279 pdnxt = eva; 3280 3281 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3282 sva += PAGE_SIZE) { 3283 vm_page_t m; 3284 3285retry: 3286 /* 3287 * Regardless of whether a pte is 32 or 64 bits in 3288 * size, PG_RW, PG_A, and PG_M are among the least 3289 * significant 32 bits. 3290 */ 3291 obits = pbits = *pte; 3292 if ((pbits & PG_V) == 0) 3293 continue; 3294 3295 if ((prot & VM_PROT_WRITE) == 0) { 3296 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3297 (PG_MANAGED | PG_M | PG_RW)) { 3298 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3299 vm_page_dirty(m); 3300 } 3301 pbits &= ~(PG_RW | PG_M); 3302 } 3303#if defined(PAE) || defined(PAE_TABLES) 3304 if ((prot & VM_PROT_EXECUTE) == 0) 3305 pbits |= pg_nx; 3306#endif 3307 3308 if (pbits != obits) { 3309#if defined(PAE) || defined(PAE_TABLES) 3310 if (!atomic_cmpset_64(pte, obits, pbits)) 3311 goto retry; 3312#else 3313 if (!atomic_cmpset_int((u_int *)pte, obits, 3314 pbits)) 3315 goto retry; 3316#endif 3317 if (obits & PG_G) 3318 pmap_invalidate_page(pmap, sva); 3319 else 3320 anychanged = TRUE; 3321 } 3322 } 3323 } 3324 if (anychanged) 3325 pmap_invalidate_all(pmap); 3326 if (pv_lists_locked) { 3327 sched_unpin(); 3328 rw_wunlock(&pvh_global_lock); 3329 } 3330 PMAP_UNLOCK(pmap); 3331} 3332 3333/* 3334 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3335 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3336 * For promotion to occur, two conditions must be met: (1) the 4KB page 3337 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3338 * mappings must have identical characteristics. 3339 * 3340 * Managed (PG_MANAGED) mappings within the kernel address space are not 3341 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3342 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3343 * pmap. 3344 */ 3345static void 3346pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3347{ 3348 pd_entry_t newpde; 3349 pt_entry_t *firstpte, oldpte, pa, *pte; 3350 vm_offset_t oldpteva; 3351 vm_page_t mpte; 3352 3353 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3354 3355 /* 3356 * Examine the first PTE in the specified PTP. Abort if this PTE is 3357 * either invalid, unused, or does not map the first 4KB physical page 3358 * within a 2- or 4MB page. 3359 */ 3360 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3361setpde: 3362 newpde = *firstpte; 3363 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3364 pmap_pde_p_failures++; 3365 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3366 " in pmap %p", va, pmap); 3367 return; 3368 } 3369 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3370 pmap_pde_p_failures++; 3371 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3372 " in pmap %p", va, pmap); 3373 return; 3374 } 3375 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3376 /* 3377 * When PG_M is already clear, PG_RW can be cleared without 3378 * a TLB invalidation. 3379 */ 3380 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3381 ~PG_RW)) 3382 goto setpde; 3383 newpde &= ~PG_RW; 3384 } 3385 3386 /* 3387 * Examine each of the other PTEs in the specified PTP. Abort if this 3388 * PTE maps an unexpected 4KB physical page or does not have identical 3389 * characteristics to the first PTE. 3390 */ 3391 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3392 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3393setpte: 3394 oldpte = *pte; 3395 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3396 pmap_pde_p_failures++; 3397 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3398 " in pmap %p", va, pmap); 3399 return; 3400 } 3401 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3402 /* 3403 * When PG_M is already clear, PG_RW can be cleared 3404 * without a TLB invalidation. 3405 */ 3406 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3407 oldpte & ~PG_RW)) 3408 goto setpte; 3409 oldpte &= ~PG_RW; 3410 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3411 (va & ~PDRMASK); 3412 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3413 " in pmap %p", oldpteva, pmap); 3414 } 3415 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3416 pmap_pde_p_failures++; 3417 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3418 " in pmap %p", va, pmap); 3419 return; 3420 } 3421 pa -= PAGE_SIZE; 3422 } 3423 3424 /* 3425 * Save the page table page in its current state until the PDE 3426 * mapping the superpage is demoted by pmap_demote_pde() or 3427 * destroyed by pmap_remove_pde(). 3428 */ 3429 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3430 KASSERT(mpte >= vm_page_array && 3431 mpte < &vm_page_array[vm_page_array_size], 3432 ("pmap_promote_pde: page table page is out of range")); 3433 KASSERT(mpte->pindex == va >> PDRSHIFT, 3434 ("pmap_promote_pde: page table page's pindex is wrong")); 3435 if (pmap_insert_pt_page(pmap, mpte)) { 3436 pmap_pde_p_failures++; 3437 CTR2(KTR_PMAP, 3438 "pmap_promote_pde: failure for va %#x in pmap %p", va, 3439 pmap); 3440 return; 3441 } 3442 3443 /* 3444 * Promote the pv entries. 3445 */ 3446 if ((newpde & PG_MANAGED) != 0) 3447 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3448 3449 /* 3450 * Propagate the PAT index to its proper position. 3451 */ 3452 if ((newpde & PG_PTE_PAT) != 0) 3453 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3454 3455 /* 3456 * Map the superpage. 3457 */ 3458 if (workaround_erratum383) 3459 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3460 else if (pmap == kernel_pmap) 3461 pmap_kenter_pde(va, PG_PS | newpde); 3462 else 3463 pde_store(pde, PG_PS | newpde); 3464 3465 pmap_pde_promotions++; 3466 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3467 " in pmap %p", va, pmap); 3468} 3469 3470/* 3471 * Insert the given physical page (p) at 3472 * the specified virtual address (v) in the 3473 * target physical map with the protection requested. 3474 * 3475 * If specified, the page will be wired down, meaning 3476 * that the related pte can not be reclaimed. 3477 * 3478 * NB: This is the only routine which MAY NOT lazy-evaluate 3479 * or lose information. That is, this routine must actually 3480 * insert this page into the given map NOW. 3481 */ 3482int 3483pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3484 u_int flags, int8_t psind) 3485{ 3486 pd_entry_t *pde; 3487 pt_entry_t *pte; 3488 pt_entry_t newpte, origpte; 3489 pv_entry_t pv; 3490 vm_paddr_t opa, pa; 3491 vm_page_t mpte, om; 3492 boolean_t invlva, wired; 3493 3494 va = trunc_page(va); 3495 mpte = NULL; 3496 wired = (flags & PMAP_ENTER_WIRED) != 0; 3497 3498 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3499 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3500 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3501 va)); 3502 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3503 VM_OBJECT_ASSERT_LOCKED(m->object); 3504 3505 rw_wlock(&pvh_global_lock); 3506 PMAP_LOCK(pmap); 3507 sched_pin(); 3508 3509 pde = pmap_pde(pmap, va); 3510 if (va < VM_MAXUSER_ADDRESS) { 3511 /* 3512 * va is for UVA. 3513 * In the case that a page table page is not resident, 3514 * we are creating it here. pmap_allocpte() handles 3515 * demotion. 3516 */ 3517 mpte = pmap_allocpte(pmap, va, flags); 3518 if (mpte == NULL) { 3519 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 3520 ("pmap_allocpte failed with sleep allowed")); 3521 sched_unpin(); 3522 rw_wunlock(&pvh_global_lock); 3523 PMAP_UNLOCK(pmap); 3524 return (KERN_RESOURCE_SHORTAGE); 3525 } 3526 } else { 3527 /* 3528 * va is for KVA, so pmap_demote_pde() will never fail 3529 * to install a page table page. PG_V is also 3530 * asserted by pmap_demote_pde(). 3531 */ 3532 KASSERT(pde != NULL && (*pde & PG_V) != 0, 3533 ("KVA %#x invalid pde pdir %#jx", va, 3534 (uintmax_t)pmap->pm_pdir[PTDPTDI])); 3535 if ((*pde & PG_PS) != 0) 3536 pmap_demote_pde(pmap, pde, va); 3537 } 3538 pte = pmap_pte_quick(pmap, va); 3539 3540 /* 3541 * Page Directory table entry is not valid, which should not 3542 * happen. We should have either allocated the page table 3543 * page or demoted the existing mapping above. 3544 */ 3545 if (pte == NULL) { 3546 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3547 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3548 } 3549 3550 pa = VM_PAGE_TO_PHYS(m); 3551 om = NULL; 3552 origpte = *pte; 3553 opa = origpte & PG_FRAME; 3554 3555 /* 3556 * Mapping has not changed, must be protection or wiring change. 3557 */ 3558 if (origpte && (opa == pa)) { 3559 /* 3560 * Wiring change, just update stats. We don't worry about 3561 * wiring PT pages as they remain resident as long as there 3562 * are valid mappings in them. Hence, if a user page is wired, 3563 * the PT page will be also. 3564 */ 3565 if (wired && ((origpte & PG_W) == 0)) 3566 pmap->pm_stats.wired_count++; 3567 else if (!wired && (origpte & PG_W)) 3568 pmap->pm_stats.wired_count--; 3569 3570 /* 3571 * Remove extra pte reference 3572 */ 3573 if (mpte) 3574 mpte->wire_count--; 3575 3576 if (origpte & PG_MANAGED) { 3577 om = m; 3578 pa |= PG_MANAGED; 3579 } 3580 goto validate; 3581 } 3582 3583 pv = NULL; 3584 3585 /* 3586 * Mapping has changed, invalidate old range and fall through to 3587 * handle validating new mapping. 3588 */ 3589 if (opa) { 3590 if (origpte & PG_W) 3591 pmap->pm_stats.wired_count--; 3592 if (origpte & PG_MANAGED) { 3593 om = PHYS_TO_VM_PAGE(opa); 3594 pv = pmap_pvh_remove(&om->md, pmap, va); 3595 } 3596 if (mpte != NULL) { 3597 mpte->wire_count--; 3598 KASSERT(mpte->wire_count > 0, 3599 ("pmap_enter: missing reference to page table page," 3600 " va: 0x%x", va)); 3601 } 3602 } else 3603 pmap->pm_stats.resident_count++; 3604 3605 /* 3606 * Enter on the PV list if part of our managed memory. 3607 */ 3608 if ((m->oflags & VPO_UNMANAGED) == 0) { 3609 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3610 ("pmap_enter: managed mapping within the clean submap")); 3611 if (pv == NULL) 3612 pv = get_pv_entry(pmap, FALSE); 3613 pv->pv_va = va; 3614 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3615 pa |= PG_MANAGED; 3616 } else if (pv != NULL) 3617 free_pv_entry(pmap, pv); 3618 3619 /* 3620 * Increment counters 3621 */ 3622 if (wired) 3623 pmap->pm_stats.wired_count++; 3624 3625validate: 3626 /* 3627 * Now validate mapping with desired protection/wiring. 3628 */ 3629 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3630 if ((prot & VM_PROT_WRITE) != 0) { 3631 newpte |= PG_RW; 3632 if ((newpte & PG_MANAGED) != 0) 3633 vm_page_aflag_set(m, PGA_WRITEABLE); 3634 } 3635#if defined(PAE) || defined(PAE_TABLES) 3636 if ((prot & VM_PROT_EXECUTE) == 0) 3637 newpte |= pg_nx; 3638#endif 3639 if (wired) 3640 newpte |= PG_W; 3641 if (va < VM_MAXUSER_ADDRESS) 3642 newpte |= PG_U; 3643 if (pmap == kernel_pmap) 3644 newpte |= pgeflag; 3645 3646 /* 3647 * if the mapping or permission bits are different, we need 3648 * to update the pte. 3649 */ 3650 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3651 newpte |= PG_A; 3652 if ((flags & VM_PROT_WRITE) != 0) 3653 newpte |= PG_M; 3654 if (origpte & PG_V) { 3655 invlva = FALSE; 3656 origpte = pte_load_store(pte, newpte); 3657 if (origpte & PG_A) { 3658 if (origpte & PG_MANAGED) 3659 vm_page_aflag_set(om, PGA_REFERENCED); 3660 if (opa != VM_PAGE_TO_PHYS(m)) 3661 invlva = TRUE; 3662#if defined(PAE) || defined(PAE_TABLES) 3663 if ((origpte & PG_NX) == 0 && 3664 (newpte & PG_NX) != 0) 3665 invlva = TRUE; 3666#endif 3667 } 3668 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3669 if ((origpte & PG_MANAGED) != 0) 3670 vm_page_dirty(om); 3671 if ((prot & VM_PROT_WRITE) == 0) 3672 invlva = TRUE; 3673 } 3674 if ((origpte & PG_MANAGED) != 0 && 3675 TAILQ_EMPTY(&om->md.pv_list) && 3676 ((om->flags & PG_FICTITIOUS) != 0 || 3677 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3678 vm_page_aflag_clear(om, PGA_WRITEABLE); 3679 if (invlva) 3680 pmap_invalidate_page(pmap, va); 3681 } else 3682 pte_store(pte, newpte); 3683 } 3684 3685 /* 3686 * If both the page table page and the reservation are fully 3687 * populated, then attempt promotion. 3688 */ 3689 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3690 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3691 vm_reserv_level_iffullpop(m) == 0) 3692 pmap_promote_pde(pmap, pde, va); 3693 3694 sched_unpin(); 3695 rw_wunlock(&pvh_global_lock); 3696 PMAP_UNLOCK(pmap); 3697 return (KERN_SUCCESS); 3698} 3699 3700/* 3701 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3702 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3703 * blocking, (2) a mapping already exists at the specified virtual address, or 3704 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3705 */ 3706static boolean_t 3707pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3708{ 3709 pd_entry_t *pde, newpde; 3710 3711 rw_assert(&pvh_global_lock, RA_WLOCKED); 3712 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3713 pde = pmap_pde(pmap, va); 3714 if (*pde != 0) { 3715 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3716 " in pmap %p", va, pmap); 3717 return (FALSE); 3718 } 3719 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3720 PG_PS | PG_V; 3721 if ((m->oflags & VPO_UNMANAGED) == 0) { 3722 newpde |= PG_MANAGED; 3723 3724 /* 3725 * Abort this mapping if its PV entry could not be created. 3726 */ 3727 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3728 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3729 " in pmap %p", va, pmap); 3730 return (FALSE); 3731 } 3732 } 3733#if defined(PAE) || defined(PAE_TABLES) 3734 if ((prot & VM_PROT_EXECUTE) == 0) 3735 newpde |= pg_nx; 3736#endif 3737 if (va < VM_MAXUSER_ADDRESS) 3738 newpde |= PG_U; 3739 3740 /* 3741 * Increment counters. 3742 */ 3743 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3744 3745 /* 3746 * Map the superpage. 3747 */ 3748 pde_store(pde, newpde); 3749 3750 pmap_pde_mappings++; 3751 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3752 " in pmap %p", va, pmap); 3753 return (TRUE); 3754} 3755 3756/* 3757 * Maps a sequence of resident pages belonging to the same object. 3758 * The sequence begins with the given page m_start. This page is 3759 * mapped at the given virtual address start. Each subsequent page is 3760 * mapped at a virtual address that is offset from start by the same 3761 * amount as the page is offset from m_start within the object. The 3762 * last page in the sequence is the page with the largest offset from 3763 * m_start that can be mapped at a virtual address less than the given 3764 * virtual address end. Not every virtual page between start and end 3765 * is mapped; only those for which a resident page exists with the 3766 * corresponding offset from m_start are mapped. 3767 */ 3768void 3769pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3770 vm_page_t m_start, vm_prot_t prot) 3771{ 3772 vm_offset_t va; 3773 vm_page_t m, mpte; 3774 vm_pindex_t diff, psize; 3775 3776 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3777 3778 psize = atop(end - start); 3779 mpte = NULL; 3780 m = m_start; 3781 rw_wlock(&pvh_global_lock); 3782 PMAP_LOCK(pmap); 3783 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3784 va = start + ptoa(diff); 3785 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3786 m->psind == 1 && pg_ps_enabled && 3787 pmap_enter_pde(pmap, va, m, prot)) 3788 m = &m[NBPDR / PAGE_SIZE - 1]; 3789 else 3790 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3791 mpte); 3792 m = TAILQ_NEXT(m, listq); 3793 } 3794 rw_wunlock(&pvh_global_lock); 3795 PMAP_UNLOCK(pmap); 3796} 3797 3798/* 3799 * this code makes some *MAJOR* assumptions: 3800 * 1. Current pmap & pmap exists. 3801 * 2. Not wired. 3802 * 3. Read access. 3803 * 4. No page table pages. 3804 * but is *MUCH* faster than pmap_enter... 3805 */ 3806 3807void 3808pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3809{ 3810 3811 rw_wlock(&pvh_global_lock); 3812 PMAP_LOCK(pmap); 3813 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3814 rw_wunlock(&pvh_global_lock); 3815 PMAP_UNLOCK(pmap); 3816} 3817 3818static vm_page_t 3819pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3820 vm_prot_t prot, vm_page_t mpte) 3821{ 3822 pt_entry_t *pte; 3823 vm_paddr_t pa; 3824 struct spglist free; 3825 3826 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3827 (m->oflags & VPO_UNMANAGED) != 0, 3828 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3829 rw_assert(&pvh_global_lock, RA_WLOCKED); 3830 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3831 3832 /* 3833 * In the case that a page table page is not 3834 * resident, we are creating it here. 3835 */ 3836 if (va < VM_MAXUSER_ADDRESS) { 3837 u_int ptepindex; 3838 pd_entry_t ptepa; 3839 3840 /* 3841 * Calculate pagetable page index 3842 */ 3843 ptepindex = va >> PDRSHIFT; 3844 if (mpte && (mpte->pindex == ptepindex)) { 3845 mpte->wire_count++; 3846 } else { 3847 /* 3848 * Get the page directory entry 3849 */ 3850 ptepa = pmap->pm_pdir[ptepindex]; 3851 3852 /* 3853 * If the page table page is mapped, we just increment 3854 * the hold count, and activate it. 3855 */ 3856 if (ptepa) { 3857 if (ptepa & PG_PS) 3858 return (NULL); 3859 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3860 mpte->wire_count++; 3861 } else { 3862 mpte = _pmap_allocpte(pmap, ptepindex, 3863 PMAP_ENTER_NOSLEEP); 3864 if (mpte == NULL) 3865 return (mpte); 3866 } 3867 } 3868 } else { 3869 mpte = NULL; 3870 } 3871 3872 /* 3873 * This call to vtopte makes the assumption that we are 3874 * entering the page into the current pmap. In order to support 3875 * quick entry into any pmap, one would likely use pmap_pte_quick. 3876 * But that isn't as quick as vtopte. 3877 */ 3878 pte = vtopte(va); 3879 if (*pte) { 3880 if (mpte != NULL) { 3881 mpte->wire_count--; 3882 mpte = NULL; 3883 } 3884 return (mpte); 3885 } 3886 3887 /* 3888 * Enter on the PV list if part of our managed memory. 3889 */ 3890 if ((m->oflags & VPO_UNMANAGED) == 0 && 3891 !pmap_try_insert_pv_entry(pmap, va, m)) { 3892 if (mpte != NULL) { 3893 SLIST_INIT(&free); 3894 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3895 pmap_invalidate_page(pmap, va); 3896 pmap_free_zero_pages(&free); 3897 } 3898 3899 mpte = NULL; 3900 } 3901 return (mpte); 3902 } 3903 3904 /* 3905 * Increment counters 3906 */ 3907 pmap->pm_stats.resident_count++; 3908 3909 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3910#if defined(PAE) || defined(PAE_TABLES) 3911 if ((prot & VM_PROT_EXECUTE) == 0) 3912 pa |= pg_nx; 3913#endif 3914 3915 /* 3916 * Now validate mapping with RO protection 3917 */ 3918 if ((m->oflags & VPO_UNMANAGED) != 0) 3919 pte_store(pte, pa | PG_V | PG_U); 3920 else 3921 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3922 return (mpte); 3923} 3924 3925/* 3926 * Make a temporary mapping for a physical address. This is only intended 3927 * to be used for panic dumps. 3928 */ 3929void * 3930pmap_kenter_temporary(vm_paddr_t pa, int i) 3931{ 3932 vm_offset_t va; 3933 3934 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3935 pmap_kenter(va, pa); 3936 invlpg(va); 3937 return ((void *)crashdumpmap); 3938} 3939 3940/* 3941 * This code maps large physical mmap regions into the 3942 * processor address space. Note that some shortcuts 3943 * are taken, but the code works. 3944 */ 3945void 3946pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3947 vm_pindex_t pindex, vm_size_t size) 3948{ 3949 pd_entry_t *pde; 3950 vm_paddr_t pa, ptepa; 3951 vm_page_t p; 3952 int pat_mode; 3953 3954 VM_OBJECT_ASSERT_WLOCKED(object); 3955 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3956 ("pmap_object_init_pt: non-device object")); 3957 if (pseflag && 3958 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3959 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3960 return; 3961 p = vm_page_lookup(object, pindex); 3962 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3963 ("pmap_object_init_pt: invalid page %p", p)); 3964 pat_mode = p->md.pat_mode; 3965 3966 /* 3967 * Abort the mapping if the first page is not physically 3968 * aligned to a 2/4MB page boundary. 3969 */ 3970 ptepa = VM_PAGE_TO_PHYS(p); 3971 if (ptepa & (NBPDR - 1)) 3972 return; 3973 3974 /* 3975 * Skip the first page. Abort the mapping if the rest of 3976 * the pages are not physically contiguous or have differing 3977 * memory attributes. 3978 */ 3979 p = TAILQ_NEXT(p, listq); 3980 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3981 pa += PAGE_SIZE) { 3982 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3983 ("pmap_object_init_pt: invalid page %p", p)); 3984 if (pa != VM_PAGE_TO_PHYS(p) || 3985 pat_mode != p->md.pat_mode) 3986 return; 3987 p = TAILQ_NEXT(p, listq); 3988 } 3989 3990 /* 3991 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3992 * "size" is a multiple of 2/4M, adding the PAT setting to 3993 * "pa" will not affect the termination of this loop. 3994 */ 3995 PMAP_LOCK(pmap); 3996 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3997 size; pa += NBPDR) { 3998 pde = pmap_pde(pmap, addr); 3999 if (*pde == 0) { 4000 pde_store(pde, pa | PG_PS | PG_M | PG_A | 4001 PG_U | PG_RW | PG_V); 4002 pmap->pm_stats.resident_count += NBPDR / 4003 PAGE_SIZE; 4004 pmap_pde_mappings++; 4005 } 4006 /* Else continue on if the PDE is already valid. */ 4007 addr += NBPDR; 4008 } 4009 PMAP_UNLOCK(pmap); 4010 } 4011} 4012 4013/* 4014 * Clear the wired attribute from the mappings for the specified range of 4015 * addresses in the given pmap. Every valid mapping within that range 4016 * must have the wired attribute set. In contrast, invalid mappings 4017 * cannot have the wired attribute set, so they are ignored. 4018 * 4019 * The wired attribute of the page table entry is not a hardware feature, 4020 * so there is no need to invalidate any TLB entries. 4021 */ 4022void 4023pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 4024{ 4025 vm_offset_t pdnxt; 4026 pd_entry_t *pde; 4027 pt_entry_t *pte; 4028 boolean_t pv_lists_locked; 4029 4030 if (pmap_is_current(pmap)) 4031 pv_lists_locked = FALSE; 4032 else { 4033 pv_lists_locked = TRUE; 4034resume: 4035 rw_wlock(&pvh_global_lock); 4036 sched_pin(); 4037 } 4038 PMAP_LOCK(pmap); 4039 for (; sva < eva; sva = pdnxt) { 4040 pdnxt = (sva + NBPDR) & ~PDRMASK; 4041 if (pdnxt < sva) 4042 pdnxt = eva; 4043 pde = pmap_pde(pmap, sva); 4044 if ((*pde & PG_V) == 0) 4045 continue; 4046 if ((*pde & PG_PS) != 0) { 4047 if ((*pde & PG_W) == 0) 4048 panic("pmap_unwire: pde %#jx is missing PG_W", 4049 (uintmax_t)*pde); 4050 4051 /* 4052 * Are we unwiring the entire large page? If not, 4053 * demote the mapping and fall through. 4054 */ 4055 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 4056 /* 4057 * Regardless of whether a pde (or pte) is 32 4058 * or 64 bits in size, PG_W is among the least 4059 * significant 32 bits. 4060 */ 4061 atomic_clear_int((u_int *)pde, PG_W); 4062 pmap->pm_stats.wired_count -= NBPDR / 4063 PAGE_SIZE; 4064 continue; 4065 } else { 4066 if (!pv_lists_locked) { 4067 pv_lists_locked = TRUE; 4068 if (!rw_try_wlock(&pvh_global_lock)) { 4069 PMAP_UNLOCK(pmap); 4070 /* Repeat sva. */ 4071 goto resume; 4072 } 4073 sched_pin(); 4074 } 4075 if (!pmap_demote_pde(pmap, pde, sva)) 4076 panic("pmap_unwire: demotion failed"); 4077 } 4078 } 4079 if (pdnxt > eva) 4080 pdnxt = eva; 4081 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 4082 sva += PAGE_SIZE) { 4083 if ((*pte & PG_V) == 0) 4084 continue; 4085 if ((*pte & PG_W) == 0) 4086 panic("pmap_unwire: pte %#jx is missing PG_W", 4087 (uintmax_t)*pte); 4088 4089 /* 4090 * PG_W must be cleared atomically. Although the pmap 4091 * lock synchronizes access to PG_W, another processor 4092 * could be setting PG_M and/or PG_A concurrently. 4093 * 4094 * PG_W is among the least significant 32 bits. 4095 */ 4096 atomic_clear_int((u_int *)pte, PG_W); 4097 pmap->pm_stats.wired_count--; 4098 } 4099 } 4100 if (pv_lists_locked) { 4101 sched_unpin(); 4102 rw_wunlock(&pvh_global_lock); 4103 } 4104 PMAP_UNLOCK(pmap); 4105} 4106 4107 4108/* 4109 * Copy the range specified by src_addr/len 4110 * from the source map to the range dst_addr/len 4111 * in the destination map. 4112 * 4113 * This routine is only advisory and need not do anything. 4114 */ 4115 4116void 4117pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4118 vm_offset_t src_addr) 4119{ 4120 struct spglist free; 4121 vm_offset_t addr; 4122 vm_offset_t end_addr = src_addr + len; 4123 vm_offset_t pdnxt; 4124 4125 if (dst_addr != src_addr) 4126 return; 4127 4128 if (!pmap_is_current(src_pmap)) 4129 return; 4130 4131 rw_wlock(&pvh_global_lock); 4132 if (dst_pmap < src_pmap) { 4133 PMAP_LOCK(dst_pmap); 4134 PMAP_LOCK(src_pmap); 4135 } else { 4136 PMAP_LOCK(src_pmap); 4137 PMAP_LOCK(dst_pmap); 4138 } 4139 sched_pin(); 4140 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 4141 pt_entry_t *src_pte, *dst_pte; 4142 vm_page_t dstmpte, srcmpte; 4143 pd_entry_t srcptepaddr; 4144 u_int ptepindex; 4145 4146 KASSERT(addr < UPT_MIN_ADDRESS, 4147 ("pmap_copy: invalid to pmap_copy page tables")); 4148 4149 pdnxt = (addr + NBPDR) & ~PDRMASK; 4150 if (pdnxt < addr) 4151 pdnxt = end_addr; 4152 ptepindex = addr >> PDRSHIFT; 4153 4154 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 4155 if (srcptepaddr == 0) 4156 continue; 4157 4158 if (srcptepaddr & PG_PS) { 4159 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4160 continue; 4161 if (dst_pmap->pm_pdir[ptepindex] == 0 && 4162 ((srcptepaddr & PG_MANAGED) == 0 || 4163 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 4164 PG_PS_FRAME))) { 4165 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 4166 ~PG_W; 4167 dst_pmap->pm_stats.resident_count += 4168 NBPDR / PAGE_SIZE; 4169 pmap_pde_mappings++; 4170 } 4171 continue; 4172 } 4173 4174 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 4175 KASSERT(srcmpte->wire_count > 0, 4176 ("pmap_copy: source page table page is unused")); 4177 4178 if (pdnxt > end_addr) 4179 pdnxt = end_addr; 4180 4181 src_pte = vtopte(addr); 4182 while (addr < pdnxt) { 4183 pt_entry_t ptetemp; 4184 ptetemp = *src_pte; 4185 /* 4186 * we only virtual copy managed pages 4187 */ 4188 if ((ptetemp & PG_MANAGED) != 0) { 4189 dstmpte = pmap_allocpte(dst_pmap, addr, 4190 PMAP_ENTER_NOSLEEP); 4191 if (dstmpte == NULL) 4192 goto out; 4193 dst_pte = pmap_pte_quick(dst_pmap, addr); 4194 if (*dst_pte == 0 && 4195 pmap_try_insert_pv_entry(dst_pmap, addr, 4196 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 4197 /* 4198 * Clear the wired, modified, and 4199 * accessed (referenced) bits 4200 * during the copy. 4201 */ 4202 *dst_pte = ptetemp & ~(PG_W | PG_M | 4203 PG_A); 4204 dst_pmap->pm_stats.resident_count++; 4205 } else { 4206 SLIST_INIT(&free); 4207 if (pmap_unwire_ptp(dst_pmap, dstmpte, 4208 &free)) { 4209 pmap_invalidate_page(dst_pmap, 4210 addr); 4211 pmap_free_zero_pages(&free); 4212 } 4213 goto out; 4214 } 4215 if (dstmpte->wire_count >= srcmpte->wire_count) 4216 break; 4217 } 4218 addr += PAGE_SIZE; 4219 src_pte++; 4220 } 4221 } 4222out: 4223 sched_unpin(); 4224 rw_wunlock(&pvh_global_lock); 4225 PMAP_UNLOCK(src_pmap); 4226 PMAP_UNLOCK(dst_pmap); 4227} 4228 4229static __inline void 4230pagezero(void *page) 4231{ 4232#if defined(I686_CPU) 4233 if (cpu_class == CPUCLASS_686) { 4234#if defined(CPU_ENABLE_SSE) 4235 if (cpu_feature & CPUID_SSE2) 4236 sse2_pagezero(page); 4237 else 4238#endif 4239 i686_pagezero(page); 4240 } else 4241#endif 4242 bzero(page, PAGE_SIZE); 4243} 4244 4245/* 4246 * pmap_zero_page zeros the specified hardware page by mapping 4247 * the page into KVM and using bzero to clear its contents. 4248 */ 4249void 4250pmap_zero_page(vm_page_t m) 4251{ 4252 pt_entry_t *cmap_pte2; 4253 struct pcpu *pc; 4254 4255 sched_pin(); 4256 pc = get_pcpu(); 4257 cmap_pte2 = pc->pc_cmap_pte2; 4258 mtx_lock(&pc->pc_cmap_lock); 4259 if (*cmap_pte2) 4260 panic("pmap_zero_page: CMAP2 busy"); 4261 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4262 pmap_cache_bits(m->md.pat_mode, 0); 4263 invlcaddr(pc->pc_cmap_addr2); 4264 pagezero(pc->pc_cmap_addr2); 4265 *cmap_pte2 = 0; 4266 4267 /* 4268 * Unpin the thread before releasing the lock. Otherwise the thread 4269 * could be rescheduled while still bound to the current CPU, only 4270 * to unpin itself immediately upon resuming execution. 4271 */ 4272 sched_unpin(); 4273 mtx_unlock(&pc->pc_cmap_lock); 4274} 4275 4276/* 4277 * pmap_zero_page_area zeros the specified hardware page by mapping 4278 * the page into KVM and using bzero to clear its contents. 4279 * 4280 * off and size may not cover an area beyond a single hardware page. 4281 */ 4282void 4283pmap_zero_page_area(vm_page_t m, int off, int size) 4284{ 4285 pt_entry_t *cmap_pte2; 4286 struct pcpu *pc; 4287 4288 sched_pin(); 4289 pc = get_pcpu(); 4290 cmap_pte2 = pc->pc_cmap_pte2; 4291 mtx_lock(&pc->pc_cmap_lock); 4292 if (*cmap_pte2) 4293 panic("pmap_zero_page_area: CMAP2 busy"); 4294 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4295 pmap_cache_bits(m->md.pat_mode, 0); 4296 invlcaddr(pc->pc_cmap_addr2); 4297 if (off == 0 && size == PAGE_SIZE) 4298 pagezero(pc->pc_cmap_addr2); 4299 else 4300 bzero(pc->pc_cmap_addr2 + off, size); 4301 *cmap_pte2 = 0; 4302 sched_unpin(); 4303 mtx_unlock(&pc->pc_cmap_lock); 4304} 4305 4306/* 4307 * pmap_zero_page_idle zeros the specified hardware page by mapping 4308 * the page into KVM and using bzero to clear its contents. This 4309 * is intended to be called from the vm_pagezero process only and 4310 * outside of Giant. 4311 */ 4312void 4313pmap_zero_page_idle(vm_page_t m) 4314{ 4315 4316 if (*CMAP3) 4317 panic("pmap_zero_page_idle: CMAP3 busy"); 4318 sched_pin(); 4319 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4320 pmap_cache_bits(m->md.pat_mode, 0); 4321 invlcaddr(CADDR3); 4322 pagezero(CADDR3); 4323 *CMAP3 = 0; 4324 sched_unpin(); 4325} 4326 4327/* 4328 * pmap_copy_page copies the specified (machine independent) 4329 * page by mapping the page into virtual memory and using 4330 * bcopy to copy the page, one machine dependent page at a 4331 * time. 4332 */ 4333void 4334pmap_copy_page(vm_page_t src, vm_page_t dst) 4335{ 4336 pt_entry_t *cmap_pte1, *cmap_pte2; 4337 struct pcpu *pc; 4338 4339 sched_pin(); 4340 pc = get_pcpu(); 4341 cmap_pte1 = pc->pc_cmap_pte1; 4342 cmap_pte2 = pc->pc_cmap_pte2; 4343 mtx_lock(&pc->pc_cmap_lock); 4344 if (*cmap_pte1) 4345 panic("pmap_copy_page: CMAP1 busy"); 4346 if (*cmap_pte2) 4347 panic("pmap_copy_page: CMAP2 busy"); 4348 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4349 pmap_cache_bits(src->md.pat_mode, 0); 4350 invlcaddr(pc->pc_cmap_addr1); 4351 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4352 pmap_cache_bits(dst->md.pat_mode, 0); 4353 invlcaddr(pc->pc_cmap_addr2); 4354 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE); 4355 *cmap_pte1 = 0; 4356 *cmap_pte2 = 0; 4357 sched_unpin(); 4358 mtx_unlock(&pc->pc_cmap_lock); 4359} 4360 4361int unmapped_buf_allowed = 1; 4362 4363void 4364pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4365 vm_offset_t b_offset, int xfersize) 4366{ 4367 vm_page_t a_pg, b_pg; 4368 char *a_cp, *b_cp; 4369 vm_offset_t a_pg_offset, b_pg_offset; 4370 pt_entry_t *cmap_pte1, *cmap_pte2; 4371 struct pcpu *pc; 4372 int cnt; 4373 4374 sched_pin(); 4375 pc = get_pcpu(); 4376 cmap_pte1 = pc->pc_cmap_pte1; 4377 cmap_pte2 = pc->pc_cmap_pte2; 4378 mtx_lock(&pc->pc_cmap_lock); 4379 if (*cmap_pte1 != 0) 4380 panic("pmap_copy_pages: CMAP1 busy"); 4381 if (*cmap_pte2 != 0) 4382 panic("pmap_copy_pages: CMAP2 busy"); 4383 while (xfersize > 0) { 4384 a_pg = ma[a_offset >> PAGE_SHIFT]; 4385 a_pg_offset = a_offset & PAGE_MASK; 4386 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4387 b_pg = mb[b_offset >> PAGE_SHIFT]; 4388 b_pg_offset = b_offset & PAGE_MASK; 4389 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4390 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A | 4391 pmap_cache_bits(a_pg->md.pat_mode, 0); 4392 invlcaddr(pc->pc_cmap_addr1); 4393 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A | 4394 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0); 4395 invlcaddr(pc->pc_cmap_addr2); 4396 a_cp = pc->pc_cmap_addr1 + a_pg_offset; 4397 b_cp = pc->pc_cmap_addr2 + b_pg_offset; 4398 bcopy(a_cp, b_cp, cnt); 4399 a_offset += cnt; 4400 b_offset += cnt; 4401 xfersize -= cnt; 4402 } 4403 *cmap_pte1 = 0; 4404 *cmap_pte2 = 0; 4405 sched_unpin(); 4406 mtx_unlock(&pc->pc_cmap_lock); 4407} 4408 4409/* 4410 * Returns true if the pmap's pv is one of the first 4411 * 16 pvs linked to from this page. This count may 4412 * be changed upwards or downwards in the future; it 4413 * is only necessary that true be returned for a small 4414 * subset of pmaps for proper page aging. 4415 */ 4416boolean_t 4417pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4418{ 4419 struct md_page *pvh; 4420 pv_entry_t pv; 4421 int loops = 0; 4422 boolean_t rv; 4423 4424 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4425 ("pmap_page_exists_quick: page %p is not managed", m)); 4426 rv = FALSE; 4427 rw_wlock(&pvh_global_lock); 4428 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4429 if (PV_PMAP(pv) == pmap) { 4430 rv = TRUE; 4431 break; 4432 } 4433 loops++; 4434 if (loops >= 16) 4435 break; 4436 } 4437 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4438 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4439 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4440 if (PV_PMAP(pv) == pmap) { 4441 rv = TRUE; 4442 break; 4443 } 4444 loops++; 4445 if (loops >= 16) 4446 break; 4447 } 4448 } 4449 rw_wunlock(&pvh_global_lock); 4450 return (rv); 4451} 4452 4453/* 4454 * pmap_page_wired_mappings: 4455 * 4456 * Return the number of managed mappings to the given physical page 4457 * that are wired. 4458 */ 4459int 4460pmap_page_wired_mappings(vm_page_t m) 4461{ 4462 int count; 4463 4464 count = 0; 4465 if ((m->oflags & VPO_UNMANAGED) != 0) 4466 return (count); 4467 rw_wlock(&pvh_global_lock); 4468 count = pmap_pvh_wired_mappings(&m->md, count); 4469 if ((m->flags & PG_FICTITIOUS) == 0) { 4470 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4471 count); 4472 } 4473 rw_wunlock(&pvh_global_lock); 4474 return (count); 4475} 4476 4477/* 4478 * pmap_pvh_wired_mappings: 4479 * 4480 * Return the updated number "count" of managed mappings that are wired. 4481 */ 4482static int 4483pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4484{ 4485 pmap_t pmap; 4486 pt_entry_t *pte; 4487 pv_entry_t pv; 4488 4489 rw_assert(&pvh_global_lock, RA_WLOCKED); 4490 sched_pin(); 4491 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4492 pmap = PV_PMAP(pv); 4493 PMAP_LOCK(pmap); 4494 pte = pmap_pte_quick(pmap, pv->pv_va); 4495 if ((*pte & PG_W) != 0) 4496 count++; 4497 PMAP_UNLOCK(pmap); 4498 } 4499 sched_unpin(); 4500 return (count); 4501} 4502 4503/* 4504 * Returns TRUE if the given page is mapped individually or as part of 4505 * a 4mpage. Otherwise, returns FALSE. 4506 */ 4507boolean_t 4508pmap_page_is_mapped(vm_page_t m) 4509{ 4510 boolean_t rv; 4511 4512 if ((m->oflags & VPO_UNMANAGED) != 0) 4513 return (FALSE); 4514 rw_wlock(&pvh_global_lock); 4515 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4516 ((m->flags & PG_FICTITIOUS) == 0 && 4517 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 4518 rw_wunlock(&pvh_global_lock); 4519 return (rv); 4520} 4521 4522/* 4523 * Remove all pages from specified address space 4524 * this aids process exit speeds. Also, this code 4525 * is special cased for current process only, but 4526 * can have the more generic (and slightly slower) 4527 * mode enabled. This is much faster than pmap_remove 4528 * in the case of running down an entire address space. 4529 */ 4530void 4531pmap_remove_pages(pmap_t pmap) 4532{ 4533 pt_entry_t *pte, tpte; 4534 vm_page_t m, mpte, mt; 4535 pv_entry_t pv; 4536 struct md_page *pvh; 4537 struct pv_chunk *pc, *npc; 4538 struct spglist free; 4539 int field, idx; 4540 int32_t bit; 4541 uint32_t inuse, bitmask; 4542 int allfree; 4543 4544 if (pmap != PCPU_GET(curpmap)) { 4545 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4546 return; 4547 } 4548 SLIST_INIT(&free); 4549 rw_wlock(&pvh_global_lock); 4550 PMAP_LOCK(pmap); 4551 sched_pin(); 4552 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4553 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 4554 pc->pc_pmap)); 4555 allfree = 1; 4556 for (field = 0; field < _NPCM; field++) { 4557 inuse = ~pc->pc_map[field] & pc_freemask[field]; 4558 while (inuse != 0) { 4559 bit = bsfl(inuse); 4560 bitmask = 1UL << bit; 4561 idx = field * 32 + bit; 4562 pv = &pc->pc_pventry[idx]; 4563 inuse &= ~bitmask; 4564 4565 pte = pmap_pde(pmap, pv->pv_va); 4566 tpte = *pte; 4567 if ((tpte & PG_PS) == 0) { 4568 pte = vtopte(pv->pv_va); 4569 tpte = *pte & ~PG_PTE_PAT; 4570 } 4571 4572 if (tpte == 0) { 4573 printf( 4574 "TPTE at %p IS ZERO @ VA %08x\n", 4575 pte, pv->pv_va); 4576 panic("bad pte"); 4577 } 4578 4579/* 4580 * We cannot remove wired pages from a process' mapping at this time 4581 */ 4582 if (tpte & PG_W) { 4583 allfree = 0; 4584 continue; 4585 } 4586 4587 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4588 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4589 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4590 m, (uintmax_t)m->phys_addr, 4591 (uintmax_t)tpte)); 4592 4593 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 4594 m < &vm_page_array[vm_page_array_size], 4595 ("pmap_remove_pages: bad tpte %#jx", 4596 (uintmax_t)tpte)); 4597 4598 pte_clear(pte); 4599 4600 /* 4601 * Update the vm_page_t clean/reference bits. 4602 */ 4603 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4604 if ((tpte & PG_PS) != 0) { 4605 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4606 vm_page_dirty(mt); 4607 } else 4608 vm_page_dirty(m); 4609 } 4610 4611 /* Mark free */ 4612 PV_STAT(pv_entry_frees++); 4613 PV_STAT(pv_entry_spare++); 4614 pv_entry_count--; 4615 pc->pc_map[field] |= bitmask; 4616 if ((tpte & PG_PS) != 0) { 4617 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4618 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4619 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4620 if (TAILQ_EMPTY(&pvh->pv_list)) { 4621 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4622 if (TAILQ_EMPTY(&mt->md.pv_list)) 4623 vm_page_aflag_clear(mt, PGA_WRITEABLE); 4624 } 4625 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4626 if (mpte != NULL) { 4627 pmap_remove_pt_page(pmap, mpte); 4628 pmap->pm_stats.resident_count--; 4629 KASSERT(mpte->wire_count == NPTEPG, 4630 ("pmap_remove_pages: pte page wire count error")); 4631 mpte->wire_count = 0; 4632 pmap_add_delayed_free_list(mpte, &free, FALSE); 4633 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 4634 } 4635 } else { 4636 pmap->pm_stats.resident_count--; 4637 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4638 if (TAILQ_EMPTY(&m->md.pv_list) && 4639 (m->flags & PG_FICTITIOUS) == 0) { 4640 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4641 if (TAILQ_EMPTY(&pvh->pv_list)) 4642 vm_page_aflag_clear(m, PGA_WRITEABLE); 4643 } 4644 pmap_unuse_pt(pmap, pv->pv_va, &free); 4645 } 4646 } 4647 } 4648 if (allfree) { 4649 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4650 free_pv_chunk(pc); 4651 } 4652 } 4653 sched_unpin(); 4654 pmap_invalidate_all(pmap); 4655 rw_wunlock(&pvh_global_lock); 4656 PMAP_UNLOCK(pmap); 4657 pmap_free_zero_pages(&free); 4658} 4659 4660/* 4661 * pmap_is_modified: 4662 * 4663 * Return whether or not the specified physical page was modified 4664 * in any physical maps. 4665 */ 4666boolean_t 4667pmap_is_modified(vm_page_t m) 4668{ 4669 boolean_t rv; 4670 4671 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4672 ("pmap_is_modified: page %p is not managed", m)); 4673 4674 /* 4675 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4676 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4677 * is clear, no PTEs can have PG_M set. 4678 */ 4679 VM_OBJECT_ASSERT_WLOCKED(m->object); 4680 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4681 return (FALSE); 4682 rw_wlock(&pvh_global_lock); 4683 rv = pmap_is_modified_pvh(&m->md) || 4684 ((m->flags & PG_FICTITIOUS) == 0 && 4685 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4686 rw_wunlock(&pvh_global_lock); 4687 return (rv); 4688} 4689 4690/* 4691 * Returns TRUE if any of the given mappings were used to modify 4692 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4693 * mappings are supported. 4694 */ 4695static boolean_t 4696pmap_is_modified_pvh(struct md_page *pvh) 4697{ 4698 pv_entry_t pv; 4699 pt_entry_t *pte; 4700 pmap_t pmap; 4701 boolean_t rv; 4702 4703 rw_assert(&pvh_global_lock, RA_WLOCKED); 4704 rv = FALSE; 4705 sched_pin(); 4706 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4707 pmap = PV_PMAP(pv); 4708 PMAP_LOCK(pmap); 4709 pte = pmap_pte_quick(pmap, pv->pv_va); 4710 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4711 PMAP_UNLOCK(pmap); 4712 if (rv) 4713 break; 4714 } 4715 sched_unpin(); 4716 return (rv); 4717} 4718 4719/* 4720 * pmap_is_prefaultable: 4721 * 4722 * Return whether or not the specified virtual address is elgible 4723 * for prefault. 4724 */ 4725boolean_t 4726pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4727{ 4728 pd_entry_t *pde; 4729 pt_entry_t *pte; 4730 boolean_t rv; 4731 4732 rv = FALSE; 4733 PMAP_LOCK(pmap); 4734 pde = pmap_pde(pmap, addr); 4735 if (*pde != 0 && (*pde & PG_PS) == 0) { 4736 pte = vtopte(addr); 4737 rv = *pte == 0; 4738 } 4739 PMAP_UNLOCK(pmap); 4740 return (rv); 4741} 4742 4743/* 4744 * pmap_is_referenced: 4745 * 4746 * Return whether or not the specified physical page was referenced 4747 * in any physical maps. 4748 */ 4749boolean_t 4750pmap_is_referenced(vm_page_t m) 4751{ 4752 boolean_t rv; 4753 4754 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4755 ("pmap_is_referenced: page %p is not managed", m)); 4756 rw_wlock(&pvh_global_lock); 4757 rv = pmap_is_referenced_pvh(&m->md) || 4758 ((m->flags & PG_FICTITIOUS) == 0 && 4759 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4760 rw_wunlock(&pvh_global_lock); 4761 return (rv); 4762} 4763 4764/* 4765 * Returns TRUE if any of the given mappings were referenced and FALSE 4766 * otherwise. Both page and 4mpage mappings are supported. 4767 */ 4768static boolean_t 4769pmap_is_referenced_pvh(struct md_page *pvh) 4770{ 4771 pv_entry_t pv; 4772 pt_entry_t *pte; 4773 pmap_t pmap; 4774 boolean_t rv; 4775 4776 rw_assert(&pvh_global_lock, RA_WLOCKED); 4777 rv = FALSE; 4778 sched_pin(); 4779 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4780 pmap = PV_PMAP(pv); 4781 PMAP_LOCK(pmap); 4782 pte = pmap_pte_quick(pmap, pv->pv_va); 4783 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4784 PMAP_UNLOCK(pmap); 4785 if (rv) 4786 break; 4787 } 4788 sched_unpin(); 4789 return (rv); 4790} 4791 4792/* 4793 * Clear the write and modified bits in each of the given page's mappings. 4794 */ 4795void 4796pmap_remove_write(vm_page_t m) 4797{ 4798 struct md_page *pvh; 4799 pv_entry_t next_pv, pv; 4800 pmap_t pmap; 4801 pd_entry_t *pde; 4802 pt_entry_t oldpte, *pte; 4803 vm_offset_t va; 4804 4805 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4806 ("pmap_remove_write: page %p is not managed", m)); 4807 4808 /* 4809 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4810 * set by another thread while the object is locked. Thus, 4811 * if PGA_WRITEABLE is clear, no page table entries need updating. 4812 */ 4813 VM_OBJECT_ASSERT_WLOCKED(m->object); 4814 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4815 return; 4816 rw_wlock(&pvh_global_lock); 4817 sched_pin(); 4818 if ((m->flags & PG_FICTITIOUS) != 0) 4819 goto small_mappings; 4820 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4821 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4822 va = pv->pv_va; 4823 pmap = PV_PMAP(pv); 4824 PMAP_LOCK(pmap); 4825 pde = pmap_pde(pmap, va); 4826 if ((*pde & PG_RW) != 0) 4827 (void)pmap_demote_pde(pmap, pde, va); 4828 PMAP_UNLOCK(pmap); 4829 } 4830small_mappings: 4831 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4832 pmap = PV_PMAP(pv); 4833 PMAP_LOCK(pmap); 4834 pde = pmap_pde(pmap, pv->pv_va); 4835 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4836 " a 4mpage in page %p's pv list", m)); 4837 pte = pmap_pte_quick(pmap, pv->pv_va); 4838retry: 4839 oldpte = *pte; 4840 if ((oldpte & PG_RW) != 0) { 4841 /* 4842 * Regardless of whether a pte is 32 or 64 bits 4843 * in size, PG_RW and PG_M are among the least 4844 * significant 32 bits. 4845 */ 4846 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4847 oldpte & ~(PG_RW | PG_M))) 4848 goto retry; 4849 if ((oldpte & PG_M) != 0) 4850 vm_page_dirty(m); 4851 pmap_invalidate_page(pmap, pv->pv_va); 4852 } 4853 PMAP_UNLOCK(pmap); 4854 } 4855 vm_page_aflag_clear(m, PGA_WRITEABLE); 4856 sched_unpin(); 4857 rw_wunlock(&pvh_global_lock); 4858} 4859 4860#define PMAP_TS_REFERENCED_MAX 5 4861 4862/* 4863 * pmap_ts_referenced: 4864 * 4865 * Return a count of reference bits for a page, clearing those bits. 4866 * It is not necessary for every reference bit to be cleared, but it 4867 * is necessary that 0 only be returned when there are truly no 4868 * reference bits set. 4869 * 4870 * XXX: The exact number of bits to check and clear is a matter that 4871 * should be tested and standardized at some point in the future for 4872 * optimal aging of shared pages. 4873 * 4874 * As an optimization, update the page's dirty field if a modified bit is 4875 * found while counting reference bits. This opportunistic update can be 4876 * performed at low cost and can eliminate the need for some future calls 4877 * to pmap_is_modified(). However, since this function stops after 4878 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 4879 * dirty pages. Those dirty pages will only be detected by a future call 4880 * to pmap_is_modified(). 4881 */ 4882int 4883pmap_ts_referenced(vm_page_t m) 4884{ 4885 struct md_page *pvh; 4886 pv_entry_t pv, pvf; 4887 pmap_t pmap; 4888 pd_entry_t *pde; 4889 pt_entry_t *pte; 4890 vm_paddr_t pa; 4891 int rtval = 0; 4892 4893 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4894 ("pmap_ts_referenced: page %p is not managed", m)); 4895 pa = VM_PAGE_TO_PHYS(m); 4896 pvh = pa_to_pvh(pa); 4897 rw_wlock(&pvh_global_lock); 4898 sched_pin(); 4899 if ((m->flags & PG_FICTITIOUS) != 0 || 4900 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 4901 goto small_mappings; 4902 pv = pvf; 4903 do { 4904 pmap = PV_PMAP(pv); 4905 PMAP_LOCK(pmap); 4906 pde = pmap_pde(pmap, pv->pv_va); 4907 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4908 /* 4909 * Although "*pde" is mapping a 2/4MB page, because 4910 * this function is called at a 4KB page granularity, 4911 * we only update the 4KB page under test. 4912 */ 4913 vm_page_dirty(m); 4914 } 4915 if ((*pde & PG_A) != 0) { 4916 /* 4917 * Since this reference bit is shared by either 1024 4918 * or 512 4KB pages, it should not be cleared every 4919 * time it is tested. Apply a simple "hash" function 4920 * on the physical page number, the virtual superpage 4921 * number, and the pmap address to select one 4KB page 4922 * out of the 1024 or 512 on which testing the 4923 * reference bit will result in clearing that bit. 4924 * This function is designed to avoid the selection of 4925 * the same 4KB page for every 2- or 4MB page mapping. 4926 * 4927 * On demotion, a mapping that hasn't been referenced 4928 * is simply destroyed. To avoid the possibility of a 4929 * subsequent page fault on a demoted wired mapping, 4930 * always leave its reference bit set. Moreover, 4931 * since the superpage is wired, the current state of 4932 * its reference bit won't affect page replacement. 4933 */ 4934 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 4935 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 4936 (*pde & PG_W) == 0) { 4937 atomic_clear_int((u_int *)pde, PG_A); 4938 pmap_invalidate_page(pmap, pv->pv_va); 4939 } 4940 rtval++; 4941 } 4942 PMAP_UNLOCK(pmap); 4943 /* Rotate the PV list if it has more than one entry. */ 4944 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4945 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4946 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4947 } 4948 if (rtval >= PMAP_TS_REFERENCED_MAX) 4949 goto out; 4950 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4951small_mappings: 4952 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4953 goto out; 4954 pv = pvf; 4955 do { 4956 pmap = PV_PMAP(pv); 4957 PMAP_LOCK(pmap); 4958 pde = pmap_pde(pmap, pv->pv_va); 4959 KASSERT((*pde & PG_PS) == 0, 4960 ("pmap_ts_referenced: found a 4mpage in page %p's pv list", 4961 m)); 4962 pte = pmap_pte_quick(pmap, pv->pv_va); 4963 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4964 vm_page_dirty(m); 4965 if ((*pte & PG_A) != 0) { 4966 atomic_clear_int((u_int *)pte, PG_A); 4967 pmap_invalidate_page(pmap, pv->pv_va); 4968 rtval++; 4969 } 4970 PMAP_UNLOCK(pmap); 4971 /* Rotate the PV list if it has more than one entry. */ 4972 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4973 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4974 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4975 } 4976 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval < 4977 PMAP_TS_REFERENCED_MAX); 4978out: 4979 sched_unpin(); 4980 rw_wunlock(&pvh_global_lock); 4981 return (rtval); 4982} 4983 4984/* 4985 * Apply the given advice to the specified range of addresses within the 4986 * given pmap. Depending on the advice, clear the referenced and/or 4987 * modified flags in each mapping and set the mapped page's dirty field. 4988 */ 4989void 4990pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4991{ 4992 pd_entry_t oldpde, *pde; 4993 pt_entry_t *pte; 4994 vm_offset_t va, pdnxt; 4995 vm_page_t m; 4996 boolean_t anychanged, pv_lists_locked; 4997 4998 if (advice != MADV_DONTNEED && advice != MADV_FREE) 4999 return; 5000 if (pmap_is_current(pmap)) 5001 pv_lists_locked = FALSE; 5002 else { 5003 pv_lists_locked = TRUE; 5004resume: 5005 rw_wlock(&pvh_global_lock); 5006 sched_pin(); 5007 } 5008 anychanged = FALSE; 5009 PMAP_LOCK(pmap); 5010 for (; sva < eva; sva = pdnxt) { 5011 pdnxt = (sva + NBPDR) & ~PDRMASK; 5012 if (pdnxt < sva) 5013 pdnxt = eva; 5014 pde = pmap_pde(pmap, sva); 5015 oldpde = *pde; 5016 if ((oldpde & PG_V) == 0) 5017 continue; 5018 else if ((oldpde & PG_PS) != 0) { 5019 if ((oldpde & PG_MANAGED) == 0) 5020 continue; 5021 if (!pv_lists_locked) { 5022 pv_lists_locked = TRUE; 5023 if (!rw_try_wlock(&pvh_global_lock)) { 5024 if (anychanged) 5025 pmap_invalidate_all(pmap); 5026 PMAP_UNLOCK(pmap); 5027 goto resume; 5028 } 5029 sched_pin(); 5030 } 5031 if (!pmap_demote_pde(pmap, pde, sva)) { 5032 /* 5033 * The large page mapping was destroyed. 5034 */ 5035 continue; 5036 } 5037 5038 /* 5039 * Unless the page mappings are wired, remove the 5040 * mapping to a single page so that a subsequent 5041 * access may repromote. Since the underlying page 5042 * table page is fully populated, this removal never 5043 * frees a page table page. 5044 */ 5045 if ((oldpde & PG_W) == 0) { 5046 pte = pmap_pte_quick(pmap, sva); 5047 KASSERT((*pte & PG_V) != 0, 5048 ("pmap_advise: invalid PTE")); 5049 pmap_remove_pte(pmap, pte, sva, NULL); 5050 anychanged = TRUE; 5051 } 5052 } 5053 if (pdnxt > eva) 5054 pdnxt = eva; 5055 va = pdnxt; 5056 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 5057 sva += PAGE_SIZE) { 5058 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V)) 5059 goto maybe_invlrng; 5060 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5061 if (advice == MADV_DONTNEED) { 5062 /* 5063 * Future calls to pmap_is_modified() 5064 * can be avoided by making the page 5065 * dirty now. 5066 */ 5067 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 5068 vm_page_dirty(m); 5069 } 5070 atomic_clear_int((u_int *)pte, PG_M | PG_A); 5071 } else if ((*pte & PG_A) != 0) 5072 atomic_clear_int((u_int *)pte, PG_A); 5073 else 5074 goto maybe_invlrng; 5075 if ((*pte & PG_G) != 0) { 5076 if (va == pdnxt) 5077 va = sva; 5078 } else 5079 anychanged = TRUE; 5080 continue; 5081maybe_invlrng: 5082 if (va != pdnxt) { 5083 pmap_invalidate_range(pmap, va, sva); 5084 va = pdnxt; 5085 } 5086 } 5087 if (va != pdnxt) 5088 pmap_invalidate_range(pmap, va, sva); 5089 } 5090 if (anychanged) 5091 pmap_invalidate_all(pmap); 5092 if (pv_lists_locked) { 5093 sched_unpin(); 5094 rw_wunlock(&pvh_global_lock); 5095 } 5096 PMAP_UNLOCK(pmap); 5097} 5098 5099/* 5100 * Clear the modify bits on the specified physical page. 5101 */ 5102void 5103pmap_clear_modify(vm_page_t m) 5104{ 5105 struct md_page *pvh; 5106 pv_entry_t next_pv, pv; 5107 pmap_t pmap; 5108 pd_entry_t oldpde, *pde; 5109 pt_entry_t oldpte, *pte; 5110 vm_offset_t va; 5111 5112 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5113 ("pmap_clear_modify: page %p is not managed", m)); 5114 VM_OBJECT_ASSERT_WLOCKED(m->object); 5115 KASSERT(!vm_page_xbusied(m), 5116 ("pmap_clear_modify: page %p is exclusive busied", m)); 5117 5118 /* 5119 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 5120 * If the object containing the page is locked and the page is not 5121 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 5122 */ 5123 if ((m->aflags & PGA_WRITEABLE) == 0) 5124 return; 5125 rw_wlock(&pvh_global_lock); 5126 sched_pin(); 5127 if ((m->flags & PG_FICTITIOUS) != 0) 5128 goto small_mappings; 5129 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5130 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5131 va = pv->pv_va; 5132 pmap = PV_PMAP(pv); 5133 PMAP_LOCK(pmap); 5134 pde = pmap_pde(pmap, va); 5135 oldpde = *pde; 5136 if ((oldpde & PG_RW) != 0) { 5137 if (pmap_demote_pde(pmap, pde, va)) { 5138 if ((oldpde & PG_W) == 0) { 5139 /* 5140 * Write protect the mapping to a 5141 * single page so that a subsequent 5142 * write access may repromote. 5143 */ 5144 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5145 PG_PS_FRAME); 5146 pte = pmap_pte_quick(pmap, va); 5147 oldpte = *pte; 5148 if ((oldpte & PG_V) != 0) { 5149 /* 5150 * Regardless of whether a pte is 32 or 64 bits 5151 * in size, PG_RW and PG_M are among the least 5152 * significant 32 bits. 5153 */ 5154 while (!atomic_cmpset_int((u_int *)pte, 5155 oldpte, 5156 oldpte & ~(PG_M | PG_RW))) 5157 oldpte = *pte; 5158 vm_page_dirty(m); 5159 pmap_invalidate_page(pmap, va); 5160 } 5161 } 5162 } 5163 } 5164 PMAP_UNLOCK(pmap); 5165 } 5166small_mappings: 5167 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5168 pmap = PV_PMAP(pv); 5169 PMAP_LOCK(pmap); 5170 pde = pmap_pde(pmap, pv->pv_va); 5171 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 5172 " a 4mpage in page %p's pv list", m)); 5173 pte = pmap_pte_quick(pmap, pv->pv_va); 5174 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5175 /* 5176 * Regardless of whether a pte is 32 or 64 bits 5177 * in size, PG_M is among the least significant 5178 * 32 bits. 5179 */ 5180 atomic_clear_int((u_int *)pte, PG_M); 5181 pmap_invalidate_page(pmap, pv->pv_va); 5182 } 5183 PMAP_UNLOCK(pmap); 5184 } 5185 sched_unpin(); 5186 rw_wunlock(&pvh_global_lock); 5187} 5188 5189/* 5190 * Miscellaneous support routines follow 5191 */ 5192 5193/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 5194static __inline void 5195pmap_pte_attr(pt_entry_t *pte, int cache_bits) 5196{ 5197 u_int opte, npte; 5198 5199 /* 5200 * The cache mode bits are all in the low 32-bits of the 5201 * PTE, so we can just spin on updating the low 32-bits. 5202 */ 5203 do { 5204 opte = *(u_int *)pte; 5205 npte = opte & ~PG_PTE_CACHE; 5206 npte |= cache_bits; 5207 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 5208} 5209 5210/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 5211static __inline void 5212pmap_pde_attr(pd_entry_t *pde, int cache_bits) 5213{ 5214 u_int opde, npde; 5215 5216 /* 5217 * The cache mode bits are all in the low 32-bits of the 5218 * PDE, so we can just spin on updating the low 32-bits. 5219 */ 5220 do { 5221 opde = *(u_int *)pde; 5222 npde = opde & ~PG_PDE_CACHE; 5223 npde |= cache_bits; 5224 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 5225} 5226 5227/* 5228 * Map a set of physical memory pages into the kernel virtual 5229 * address space. Return a pointer to where it is mapped. This 5230 * routine is intended to be used for mapping device memory, 5231 * NOT real memory. 5232 */ 5233void * 5234pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 5235{ 5236 struct pmap_preinit_mapping *ppim; 5237 vm_offset_t va, offset; 5238 vm_size_t tmpsize; 5239 int i; 5240 5241 offset = pa & PAGE_MASK; 5242 size = round_page(offset + size); 5243 pa = pa & PG_FRAME; 5244 5245 if (pa < KERNLOAD && pa + size <= KERNLOAD) 5246 va = KERNBASE + pa; 5247 else if (!pmap_initialized) { 5248 va = 0; 5249 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5250 ppim = pmap_preinit_mapping + i; 5251 if (ppim->va == 0) { 5252 ppim->pa = pa; 5253 ppim->sz = size; 5254 ppim->mode = mode; 5255 ppim->va = virtual_avail; 5256 virtual_avail += size; 5257 va = ppim->va; 5258 break; 5259 } 5260 } 5261 if (va == 0) 5262 panic("%s: too many preinit mappings", __func__); 5263 } else { 5264 /* 5265 * If we have a preinit mapping, re-use it. 5266 */ 5267 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5268 ppim = pmap_preinit_mapping + i; 5269 if (ppim->pa == pa && ppim->sz == size && 5270 ppim->mode == mode) 5271 return ((void *)(ppim->va + offset)); 5272 } 5273 va = kva_alloc(size); 5274 if (va == 0) 5275 panic("%s: Couldn't allocate KVA", __func__); 5276 } 5277 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 5278 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 5279 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 5280 pmap_invalidate_cache_range(va, va + size, FALSE); 5281 return ((void *)(va + offset)); 5282} 5283 5284void * 5285pmap_mapdev(vm_paddr_t pa, vm_size_t size) 5286{ 5287 5288 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 5289} 5290 5291void * 5292pmap_mapbios(vm_paddr_t pa, vm_size_t size) 5293{ 5294 5295 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 5296} 5297 5298void 5299pmap_unmapdev(vm_offset_t va, vm_size_t size) 5300{ 5301 struct pmap_preinit_mapping *ppim; 5302 vm_offset_t offset; 5303 int i; 5304 5305 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 5306 return; 5307 offset = va & PAGE_MASK; 5308 size = round_page(offset + size); 5309 va = trunc_page(va); 5310 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5311 ppim = pmap_preinit_mapping + i; 5312 if (ppim->va == va && ppim->sz == size) { 5313 if (pmap_initialized) 5314 return; 5315 ppim->pa = 0; 5316 ppim->va = 0; 5317 ppim->sz = 0; 5318 ppim->mode = 0; 5319 if (va + size == virtual_avail) 5320 virtual_avail = va; 5321 return; 5322 } 5323 } 5324 if (pmap_initialized) 5325 kva_free(va, size); 5326} 5327 5328/* 5329 * Sets the memory attribute for the specified page. 5330 */ 5331void 5332pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5333{ 5334 5335 m->md.pat_mode = ma; 5336 if ((m->flags & PG_FICTITIOUS) != 0) 5337 return; 5338 5339 /* 5340 * If "m" is a normal page, flush it from the cache. 5341 * See pmap_invalidate_cache_range(). 5342 * 5343 * First, try to find an existing mapping of the page by sf 5344 * buffer. sf_buf_invalidate_cache() modifies mapping and 5345 * flushes the cache. 5346 */ 5347 if (sf_buf_invalidate_cache(m)) 5348 return; 5349 5350 /* 5351 * If page is not mapped by sf buffer, but CPU does not 5352 * support self snoop, map the page transient and do 5353 * invalidation. In the worst case, whole cache is flushed by 5354 * pmap_invalidate_cache_range(). 5355 */ 5356 if ((cpu_feature & CPUID_SS) == 0) 5357 pmap_flush_page(m); 5358} 5359 5360static void 5361pmap_flush_page(vm_page_t m) 5362{ 5363 pt_entry_t *cmap_pte2; 5364 struct pcpu *pc; 5365 vm_offset_t sva, eva; 5366 bool useclflushopt; 5367 5368 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0; 5369 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) { 5370 sched_pin(); 5371 pc = get_pcpu(); 5372 cmap_pte2 = pc->pc_cmap_pte2; 5373 mtx_lock(&pc->pc_cmap_lock); 5374 if (*cmap_pte2) 5375 panic("pmap_flush_page: CMAP2 busy"); 5376 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 5377 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 5378 invlcaddr(pc->pc_cmap_addr2); 5379 sva = (vm_offset_t)pc->pc_cmap_addr2; 5380 eva = sva + PAGE_SIZE; 5381 5382 /* 5383 * Use mfence or sfence despite the ordering implied by 5384 * mtx_{un,}lock() because clflush on non-Intel CPUs 5385 * and clflushopt are not guaranteed to be ordered by 5386 * any other instruction. 5387 */ 5388 if (useclflushopt) 5389 sfence(); 5390 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5391 mfence(); 5392 for (; sva < eva; sva += cpu_clflush_line_size) { 5393 if (useclflushopt) 5394 clflushopt(sva); 5395 else 5396 clflush(sva); 5397 } 5398 if (useclflushopt) 5399 sfence(); 5400 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5401 mfence(); 5402 *cmap_pte2 = 0; 5403 sched_unpin(); 5404 mtx_unlock(&pc->pc_cmap_lock); 5405 } else 5406 pmap_invalidate_cache(); 5407} 5408 5409/* 5410 * Changes the specified virtual address range's memory type to that given by 5411 * the parameter "mode". The specified virtual address range must be 5412 * completely contained within either the kernel map. 5413 * 5414 * Returns zero if the change completed successfully, and either EINVAL or 5415 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 5416 * of the virtual address range was not mapped, and ENOMEM is returned if 5417 * there was insufficient memory available to complete the change. 5418 */ 5419int 5420pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 5421{ 5422 vm_offset_t base, offset, tmpva; 5423 pd_entry_t *pde; 5424 pt_entry_t *pte; 5425 int cache_bits_pte, cache_bits_pde; 5426 boolean_t changed; 5427 5428 base = trunc_page(va); 5429 offset = va & PAGE_MASK; 5430 size = round_page(offset + size); 5431 5432 /* 5433 * Only supported on kernel virtual addresses above the recursive map. 5434 */ 5435 if (base < VM_MIN_KERNEL_ADDRESS) 5436 return (EINVAL); 5437 5438 cache_bits_pde = pmap_cache_bits(mode, 1); 5439 cache_bits_pte = pmap_cache_bits(mode, 0); 5440 changed = FALSE; 5441 5442 /* 5443 * Pages that aren't mapped aren't supported. Also break down 5444 * 2/4MB pages into 4KB pages if required. 5445 */ 5446 PMAP_LOCK(kernel_pmap); 5447 for (tmpva = base; tmpva < base + size; ) { 5448 pde = pmap_pde(kernel_pmap, tmpva); 5449 if (*pde == 0) { 5450 PMAP_UNLOCK(kernel_pmap); 5451 return (EINVAL); 5452 } 5453 if (*pde & PG_PS) { 5454 /* 5455 * If the current 2/4MB page already has 5456 * the required memory type, then we need not 5457 * demote this page. Just increment tmpva to 5458 * the next 2/4MB page frame. 5459 */ 5460 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 5461 tmpva = trunc_4mpage(tmpva) + NBPDR; 5462 continue; 5463 } 5464 5465 /* 5466 * If the current offset aligns with a 2/4MB 5467 * page frame and there is at least 2/4MB left 5468 * within the range, then we need not break 5469 * down this page into 4KB pages. 5470 */ 5471 if ((tmpva & PDRMASK) == 0 && 5472 tmpva + PDRMASK < base + size) { 5473 tmpva += NBPDR; 5474 continue; 5475 } 5476 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 5477 PMAP_UNLOCK(kernel_pmap); 5478 return (ENOMEM); 5479 } 5480 } 5481 pte = vtopte(tmpva); 5482 if (*pte == 0) { 5483 PMAP_UNLOCK(kernel_pmap); 5484 return (EINVAL); 5485 } 5486 tmpva += PAGE_SIZE; 5487 } 5488 PMAP_UNLOCK(kernel_pmap); 5489 5490 /* 5491 * Ok, all the pages exist, so run through them updating their 5492 * cache mode if required. 5493 */ 5494 for (tmpva = base; tmpva < base + size; ) { 5495 pde = pmap_pde(kernel_pmap, tmpva); 5496 if (*pde & PG_PS) { 5497 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 5498 pmap_pde_attr(pde, cache_bits_pde); 5499 changed = TRUE; 5500 } 5501 tmpva = trunc_4mpage(tmpva) + NBPDR; 5502 } else { 5503 pte = vtopte(tmpva); 5504 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 5505 pmap_pte_attr(pte, cache_bits_pte); 5506 changed = TRUE; 5507 } 5508 tmpva += PAGE_SIZE; 5509 } 5510 } 5511 5512 /* 5513 * Flush CPU caches to make sure any data isn't cached that 5514 * shouldn't be, etc. 5515 */ 5516 if (changed) { 5517 pmap_invalidate_range(kernel_pmap, base, tmpva); 5518 pmap_invalidate_cache_range(base, tmpva, FALSE); 5519 } 5520 return (0); 5521} 5522 5523/* 5524 * perform the pmap work for mincore 5525 */ 5526int 5527pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5528{ 5529 pd_entry_t *pdep; 5530 pt_entry_t *ptep, pte; 5531 vm_paddr_t pa; 5532 int val; 5533 5534 PMAP_LOCK(pmap); 5535retry: 5536 pdep = pmap_pde(pmap, addr); 5537 if (*pdep != 0) { 5538 if (*pdep & PG_PS) { 5539 pte = *pdep; 5540 /* Compute the physical address of the 4KB page. */ 5541 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5542 PG_FRAME; 5543 val = MINCORE_SUPER; 5544 } else { 5545 ptep = pmap_pte(pmap, addr); 5546 pte = *ptep; 5547 pmap_pte_release(ptep); 5548 pa = pte & PG_FRAME; 5549 val = 0; 5550 } 5551 } else { 5552 pte = 0; 5553 pa = 0; 5554 val = 0; 5555 } 5556 if ((pte & PG_V) != 0) { 5557 val |= MINCORE_INCORE; 5558 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5559 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5560 if ((pte & PG_A) != 0) 5561 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5562 } 5563 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5564 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5565 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5566 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5567 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5568 goto retry; 5569 } else 5570 PA_UNLOCK_COND(*locked_pa); 5571 PMAP_UNLOCK(pmap); 5572 return (val); 5573} 5574 5575void 5576pmap_activate(struct thread *td) 5577{ 5578 pmap_t pmap, oldpmap; 5579 u_int cpuid; 5580 u_int32_t cr3; 5581 5582 critical_enter(); 5583 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5584 oldpmap = PCPU_GET(curpmap); 5585 cpuid = PCPU_GET(cpuid); 5586#if defined(SMP) 5587 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 5588 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5589#else 5590 CPU_CLR(cpuid, &oldpmap->pm_active); 5591 CPU_SET(cpuid, &pmap->pm_active); 5592#endif 5593#if defined(PAE) || defined(PAE_TABLES) 5594 cr3 = vtophys(pmap->pm_pdpt); 5595#else 5596 cr3 = vtophys(pmap->pm_pdir); 5597#endif 5598 /* 5599 * pmap_activate is for the current thread on the current cpu 5600 */ 5601 td->td_pcb->pcb_cr3 = cr3; 5602 load_cr3(cr3); 5603 PCPU_SET(curpmap, pmap); 5604 critical_exit(); 5605} 5606 5607void 5608pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5609{ 5610} 5611 5612/* 5613 * Increase the starting virtual address of the given mapping if a 5614 * different alignment might result in more superpage mappings. 5615 */ 5616void 5617pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5618 vm_offset_t *addr, vm_size_t size) 5619{ 5620 vm_offset_t superpage_offset; 5621 5622 if (size < NBPDR) 5623 return; 5624 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5625 offset += ptoa(object->pg_color); 5626 superpage_offset = offset & PDRMASK; 5627 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5628 (*addr & PDRMASK) == superpage_offset) 5629 return; 5630 if ((*addr & PDRMASK) < superpage_offset) 5631 *addr = (*addr & ~PDRMASK) + superpage_offset; 5632 else 5633 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5634} 5635 5636vm_offset_t 5637pmap_quick_enter_page(vm_page_t m) 5638{ 5639 vm_offset_t qaddr; 5640 pt_entry_t *pte; 5641 5642 critical_enter(); 5643 qaddr = PCPU_GET(qmap_addr); 5644 pte = vtopte(qaddr); 5645 5646 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy")); 5647 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 5648 pmap_cache_bits(pmap_page_get_memattr(m), 0); 5649 invlpg(qaddr); 5650 5651 return (qaddr); 5652} 5653 5654void 5655pmap_quick_remove_page(vm_offset_t addr) 5656{ 5657 vm_offset_t qaddr; 5658 pt_entry_t *pte; 5659 5660 qaddr = PCPU_GET(qmap_addr); 5661 pte = vtopte(qaddr); 5662 5663 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use")); 5664 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address")); 5665 5666 *pte = 0; 5667 critical_exit(); 5668} 5669 5670#if defined(PMAP_DEBUG) 5671pmap_pid_dump(int pid) 5672{ 5673 pmap_t pmap; 5674 struct proc *p; 5675 int npte = 0; 5676 int index; 5677 5678 sx_slock(&allproc_lock); 5679 FOREACH_PROC_IN_SYSTEM(p) { 5680 if (p->p_pid != pid) 5681 continue; 5682 5683 if (p->p_vmspace) { 5684 int i,j; 5685 index = 0; 5686 pmap = vmspace_pmap(p->p_vmspace); 5687 for (i = 0; i < NPDEPTD; i++) { 5688 pd_entry_t *pde; 5689 pt_entry_t *pte; 5690 vm_offset_t base = i << PDRSHIFT; 5691 5692 pde = &pmap->pm_pdir[i]; 5693 if (pde && pmap_pde_v(pde)) { 5694 for (j = 0; j < NPTEPG; j++) { 5695 vm_offset_t va = base + (j << PAGE_SHIFT); 5696 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5697 if (index) { 5698 index = 0; 5699 printf("\n"); 5700 } 5701 sx_sunlock(&allproc_lock); 5702 return (npte); 5703 } 5704 pte = pmap_pte(pmap, va); 5705 if (pte && pmap_pte_v(pte)) { 5706 pt_entry_t pa; 5707 vm_page_t m; 5708 pa = *pte; 5709 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5710 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5711 va, pa, m->hold_count, m->wire_count, m->flags); 5712 npte++; 5713 index++; 5714 if (index >= 2) { 5715 index = 0; 5716 printf("\n"); 5717 } else { 5718 printf(" "); 5719 } 5720 } 5721 } 5722 } 5723 } 5724 } 5725 } 5726 sx_sunlock(&allproc_lock); 5727 return (npte); 5728} 5729#endif 5730