mp_machdep.c revision 278325
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/i386/i386/mp_machdep.c 278325 2015-02-06 18:19:59Z jhb $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_pmap.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#include <sys/cpuset.h> 54#ifdef GPROF 55#include <sys/gmon.h> 56#endif 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/memrange.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/sched.h> 66#include <sys/smp.h> 67#include <sys/sysctl.h> 68 69#include <vm/vm.h> 70#include <vm/vm_param.h> 71#include <vm/pmap.h> 72#include <vm/vm_kern.h> 73#include <vm/vm_extern.h> 74 75#include <x86/apicreg.h> 76#include <machine/clock.h> 77#include <machine/cputypes.h> 78#include <x86/mca.h> 79#include <machine/md_var.h> 80#include <machine/pcb.h> 81#include <machine/psl.h> 82#include <machine/smp.h> 83#include <machine/specialreg.h> 84#include <machine/cpu.h> 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#define CMOS_REG (0x70) 91#define CMOS_DATA (0x71) 92#define BIOS_RESET (0x0f) 93#define BIOS_WARM (0x0a) 94 95/* 96 * this code MUST be enabled here and in mpboot.s. 97 * it follows the very early stages of AP boot by placing values in CMOS ram. 98 * it NORMALLY will never be needed and thus the primitive method for enabling. 99 * 100#define CHECK_POINTS 101 */ 102 103#if defined(CHECK_POINTS) && !defined(PC98) 104#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 105#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 106 107#define CHECK_INIT(D); \ 108 CHECK_WRITE(0x34, (D)); \ 109 CHECK_WRITE(0x35, (D)); \ 110 CHECK_WRITE(0x36, (D)); \ 111 CHECK_WRITE(0x37, (D)); \ 112 CHECK_WRITE(0x38, (D)); \ 113 CHECK_WRITE(0x39, (D)); 114 115#define CHECK_PRINT(S); \ 116 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 117 (S), \ 118 CHECK_READ(0x34), \ 119 CHECK_READ(0x35), \ 120 CHECK_READ(0x36), \ 121 CHECK_READ(0x37), \ 122 CHECK_READ(0x38), \ 123 CHECK_READ(0x39)); 124 125#else /* CHECK_POINTS */ 126 127#define CHECK_INIT(D) 128#define CHECK_PRINT(S) 129#define CHECK_WRITE(A, D) 130 131#endif /* CHECK_POINTS */ 132 133/* lock region used by kernel profiling */ 134int mcount_lock; 135 136int mp_naps; /* # of Applications processors */ 137int boot_cpu_id = -1; /* designated BSP */ 138 139extern struct pcpu __pcpu[]; 140 141/* AP uses this during bootstrap. Do not staticize. */ 142char *bootSTK; 143static int bootAP; 144 145/* Free these after use */ 146void *bootstacks[MAXCPU]; 147static void *dpcpu; 148 149struct pcb stoppcbs[MAXCPU]; 150struct susppcb **susppcbs; 151 152/* Variables needed for SMP tlb shootdown. */ 153vm_offset_t smp_tlb_addr1; 154vm_offset_t smp_tlb_addr2; 155volatile int smp_tlb_wait; 156 157#ifdef COUNT_IPIS 158/* Interrupt counts. */ 159static u_long *ipi_preempt_counts[MAXCPU]; 160static u_long *ipi_ast_counts[MAXCPU]; 161u_long *ipi_invltlb_counts[MAXCPU]; 162u_long *ipi_invlrng_counts[MAXCPU]; 163u_long *ipi_invlpg_counts[MAXCPU]; 164u_long *ipi_invlcache_counts[MAXCPU]; 165u_long *ipi_rendezvous_counts[MAXCPU]; 166u_long *ipi_lazypmap_counts[MAXCPU]; 167static u_long *ipi_hardclock_counts[MAXCPU]; 168#endif 169 170/* Default cpu_ops implementation. */ 171struct cpu_ops cpu_ops; 172 173/* 174 * Local data and functions. 175 */ 176 177static volatile cpuset_t ipi_nmi_pending; 178 179/* used to hold the AP's until we are ready to release them */ 180static struct mtx ap_boot_mtx; 181 182/* Set to 1 once we're ready to let the APs out of the pen. */ 183static volatile int aps_ready = 0; 184 185/* 186 * Store data from cpu_add() until later in the boot when we actually setup 187 * the APs. 188 */ 189struct cpu_info { 190 int cpu_present:1; 191 int cpu_bsp:1; 192 int cpu_disabled:1; 193 int cpu_hyperthread:1; 194} static cpu_info[MAX_APIC_ID + 1]; 195int cpu_apic_ids[MAXCPU]; 196int apic_cpuids[MAX_APIC_ID + 1]; 197 198/* Holds pending bitmap based IPIs per CPU */ 199volatile u_int cpu_ipi_pending[MAXCPU]; 200 201static u_int boot_address; 202static int cpu_logical; /* logical cpus per core */ 203static int cpu_cores; /* cores per package */ 204 205static void assign_cpu_ids(void); 206static void install_ap_tramp(void); 207static void set_interrupt_apic_ids(void); 208static int start_all_aps(void); 209static int start_ap(int apic_id); 210static void release_aps(void *dummy); 211 212static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 213static int hyperthreading_allowed = 1; 214 215static void 216mem_range_AP_init(void) 217{ 218 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 219 mem_range_softc.mr_op->initAP(&mem_range_softc); 220} 221 222static void 223topo_probe_amd(void) 224{ 225 int core_id_bits; 226 int id; 227 228 /* AMD processors do not support HTT. */ 229 cpu_logical = 1; 230 231 if ((amd_feature2 & AMDID2_CMP) == 0) { 232 cpu_cores = 1; 233 return; 234 } 235 236 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 237 AMDID_COREID_SIZE_SHIFT; 238 if (core_id_bits == 0) { 239 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 240 return; 241 } 242 243 /* Fam 10h and newer should get here. */ 244 for (id = 0; id <= MAX_APIC_ID; id++) { 245 /* Check logical CPU availability. */ 246 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 247 continue; 248 /* Check if logical CPU has the same package ID. */ 249 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 250 continue; 251 cpu_cores++; 252 } 253} 254 255/* 256 * Round up to the next power of two, if necessary, and then 257 * take log2. 258 * Returns -1 if argument is zero. 259 */ 260static __inline int 261mask_width(u_int x) 262{ 263 264 return (fls(x << (1 - powerof2(x))) - 1); 265} 266 267static void 268topo_probe_0x4(void) 269{ 270 u_int p[4]; 271 int pkg_id_bits; 272 int core_id_bits; 273 int max_cores; 274 int max_logical; 275 int id; 276 277 /* Both zero and one here mean one logical processor per package. */ 278 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 279 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 280 if (max_logical <= 1) 281 return; 282 283 /* 284 * Because of uniformity assumption we examine only 285 * those logical processors that belong to the same 286 * package as BSP. Further, we count number of 287 * logical processors that belong to the same core 288 * as BSP thus deducing number of threads per core. 289 */ 290 if (cpu_high >= 0x4) { 291 cpuid_count(0x04, 0, p); 292 max_cores = ((p[0] >> 26) & 0x3f) + 1; 293 } else 294 max_cores = 1; 295 core_id_bits = mask_width(max_logical/max_cores); 296 if (core_id_bits < 0) 297 return; 298 pkg_id_bits = core_id_bits + mask_width(max_cores); 299 300 for (id = 0; id <= MAX_APIC_ID; id++) { 301 /* Check logical CPU availability. */ 302 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 303 continue; 304 /* Check if logical CPU has the same package ID. */ 305 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 306 continue; 307 cpu_cores++; 308 /* Check if logical CPU has the same package and core IDs. */ 309 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 310 cpu_logical++; 311 } 312 313 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 314 ("topo_probe_0x4 couldn't find BSP")); 315 316 cpu_cores /= cpu_logical; 317 hyperthreading_cpus = cpu_logical; 318} 319 320static void 321topo_probe_0xb(void) 322{ 323 u_int p[4]; 324 int bits; 325 int cnt; 326 int i; 327 int logical; 328 int type; 329 int x; 330 331 /* We only support three levels for now. */ 332 for (i = 0; i < 3; i++) { 333 cpuid_count(0x0b, i, p); 334 335 /* Fall back if CPU leaf 11 doesn't really exist. */ 336 if (i == 0 && p[1] == 0) { 337 topo_probe_0x4(); 338 return; 339 } 340 341 bits = p[0] & 0x1f; 342 logical = p[1] &= 0xffff; 343 type = (p[2] >> 8) & 0xff; 344 if (type == 0 || logical == 0) 345 break; 346 /* 347 * Because of uniformity assumption we examine only 348 * those logical processors that belong to the same 349 * package as BSP. 350 */ 351 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 352 if (!cpu_info[x].cpu_present || 353 cpu_info[x].cpu_disabled) 354 continue; 355 if (x >> bits == boot_cpu_id >> bits) 356 cnt++; 357 } 358 if (type == CPUID_TYPE_SMT) 359 cpu_logical = cnt; 360 else if (type == CPUID_TYPE_CORE) 361 cpu_cores = cnt; 362 } 363 if (cpu_logical == 0) 364 cpu_logical = 1; 365 cpu_cores /= cpu_logical; 366} 367 368/* 369 * Both topology discovery code and code that consumes topology 370 * information assume top-down uniformity of the topology. 371 * That is, all physical packages must be identical and each 372 * core in a package must have the same number of threads. 373 * Topology information is queried only on BSP, on which this 374 * code runs and for which it can query CPUID information. 375 * Then topology is extrapolated on all packages using the 376 * uniformity assumption. 377 */ 378static void 379topo_probe(void) 380{ 381 static int cpu_topo_probed = 0; 382 383 if (cpu_topo_probed) 384 return; 385 386 CPU_ZERO(&logical_cpus_mask); 387 if (mp_ncpus <= 1) 388 cpu_cores = cpu_logical = 1; 389 else if (cpu_vendor_id == CPU_VENDOR_AMD) 390 topo_probe_amd(); 391 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 392 /* 393 * See Intel(R) 64 Architecture Processor 394 * Topology Enumeration article for details. 395 * 396 * Note that 0x1 <= cpu_high < 4 case should be 397 * compatible with topo_probe_0x4() logic when 398 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 399 * or it should trigger the fallback otherwise. 400 */ 401 if (cpu_high >= 0xb) 402 topo_probe_0xb(); 403 else if (cpu_high >= 0x1) 404 topo_probe_0x4(); 405 } 406 407 /* 408 * Fallback: assume each logical CPU is in separate 409 * physical package. That is, no multi-core, no SMT. 410 */ 411 if (cpu_cores == 0 || cpu_logical == 0) 412 cpu_cores = cpu_logical = 1; 413 cpu_topo_probed = 1; 414} 415 416struct cpu_group * 417cpu_topo(void) 418{ 419 int cg_flags; 420 421 /* 422 * Determine whether any threading flags are 423 * necessry. 424 */ 425 topo_probe(); 426 if (cpu_logical > 1 && hyperthreading_cpus) 427 cg_flags = CG_FLAG_HTT; 428 else if (cpu_logical > 1) 429 cg_flags = CG_FLAG_SMT; 430 else 431 cg_flags = 0; 432 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 433 printf("WARNING: Non-uniform processors.\n"); 434 printf("WARNING: Using suboptimal topology.\n"); 435 return (smp_topo_none()); 436 } 437 /* 438 * No multi-core or hyper-threaded. 439 */ 440 if (cpu_logical * cpu_cores == 1) 441 return (smp_topo_none()); 442 /* 443 * Only HTT no multi-core. 444 */ 445 if (cpu_logical > 1 && cpu_cores == 1) 446 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 447 /* 448 * Only multi-core no HTT. 449 */ 450 if (cpu_cores > 1 && cpu_logical == 1) 451 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 452 /* 453 * Both HTT and multi-core. 454 */ 455 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 456 CG_SHARE_L1, cpu_logical, cg_flags)); 457} 458 459 460/* 461 * Calculate usable address in base memory for AP trampoline code. 462 */ 463u_int 464mp_bootaddress(u_int basemem) 465{ 466 467 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 468 if ((basemem - boot_address) < bootMP_size) 469 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 470 471 return boot_address; 472} 473 474void 475cpu_add(u_int apic_id, char boot_cpu) 476{ 477 478 if (apic_id > MAX_APIC_ID) { 479 panic("SMP: APIC ID %d too high", apic_id); 480 return; 481 } 482 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 483 apic_id)); 484 cpu_info[apic_id].cpu_present = 1; 485 if (boot_cpu) { 486 KASSERT(boot_cpu_id == -1, 487 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 488 boot_cpu_id)); 489 boot_cpu_id = apic_id; 490 cpu_info[apic_id].cpu_bsp = 1; 491 } 492 if (mp_ncpus < MAXCPU) { 493 mp_ncpus++; 494 mp_maxid = mp_ncpus - 1; 495 } 496 if (bootverbose) 497 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 498 "AP"); 499} 500 501void 502cpu_mp_setmaxid(void) 503{ 504 505 /* 506 * mp_maxid should be already set by calls to cpu_add(). 507 * Just sanity check its value here. 508 */ 509 if (mp_ncpus == 0) 510 KASSERT(mp_maxid == 0, 511 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 512 else if (mp_ncpus == 1) 513 mp_maxid = 0; 514 else 515 KASSERT(mp_maxid >= mp_ncpus - 1, 516 ("%s: counters out of sync: max %d, count %d", __func__, 517 mp_maxid, mp_ncpus)); 518} 519 520int 521cpu_mp_probe(void) 522{ 523 524 /* 525 * Always record BSP in CPU map so that the mbuf init code works 526 * correctly. 527 */ 528 CPU_SETOF(0, &all_cpus); 529 if (mp_ncpus == 0) { 530 /* 531 * No CPUs were found, so this must be a UP system. Setup 532 * the variables to represent a system with a single CPU 533 * with an id of 0. 534 */ 535 mp_ncpus = 1; 536 return (0); 537 } 538 539 /* At least one CPU was found. */ 540 if (mp_ncpus == 1) { 541 /* 542 * One CPU was found, so this must be a UP system with 543 * an I/O APIC. 544 */ 545 mp_maxid = 0; 546 return (0); 547 } 548 549 /* At least two CPUs were found. */ 550 return (1); 551} 552 553/* 554 * Initialize the IPI handlers and start up the AP's. 555 */ 556void 557cpu_mp_start(void) 558{ 559 int i; 560 561 /* Initialize the logical ID to APIC ID table. */ 562 for (i = 0; i < MAXCPU; i++) { 563 cpu_apic_ids[i] = -1; 564 cpu_ipi_pending[i] = 0; 565 } 566 567 /* Install an inter-CPU IPI for TLB invalidation */ 568 setidt(IPI_INVLTLB, IDTVEC(invltlb), 569 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 570 setidt(IPI_INVLPG, IDTVEC(invlpg), 571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 572 setidt(IPI_INVLRNG, IDTVEC(invlrng), 573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 574 575 /* Install an inter-CPU IPI for cache invalidation. */ 576 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 577 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 578 579 /* Install an inter-CPU IPI for lazy pmap release */ 580 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 581 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 582 583 /* Install an inter-CPU IPI for all-CPU rendezvous */ 584 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 585 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 586 587 /* Install generic inter-CPU IPI handler */ 588 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 589 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 590 591 /* Install an inter-CPU IPI for CPU stop/restart */ 592 setidt(IPI_STOP, IDTVEC(cpustop), 593 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 594 595 /* Install an inter-CPU IPI for CPU suspend/resume */ 596 setidt(IPI_SUSPEND, IDTVEC(cpususpend), 597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 598 599 /* Set boot_cpu_id if needed. */ 600 if (boot_cpu_id == -1) { 601 boot_cpu_id = PCPU_GET(apic_id); 602 cpu_info[boot_cpu_id].cpu_bsp = 1; 603 } else 604 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 605 ("BSP's APIC ID doesn't match boot_cpu_id")); 606 607 /* Probe logical/physical core configuration. */ 608 topo_probe(); 609 610 assign_cpu_ids(); 611 612 /* Start each Application Processor */ 613 start_all_aps(); 614 615 set_interrupt_apic_ids(); 616} 617 618 619/* 620 * Print various information about the SMP system hardware and setup. 621 */ 622void 623cpu_mp_announce(void) 624{ 625 const char *hyperthread; 626 int i; 627 628 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 629 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 630 if (hyperthreading_cpus > 1) 631 printf(" x %d HTT threads", cpu_logical); 632 else if (cpu_logical > 1) 633 printf(" x %d SMT threads", cpu_logical); 634 printf("\n"); 635 636 /* List active CPUs first. */ 637 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 638 for (i = 1; i < mp_ncpus; i++) { 639 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 640 hyperthread = "/HT"; 641 else 642 hyperthread = ""; 643 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 644 cpu_apic_ids[i]); 645 } 646 647 /* List disabled CPUs last. */ 648 for (i = 0; i <= MAX_APIC_ID; i++) { 649 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 650 continue; 651 if (cpu_info[i].cpu_hyperthread) 652 hyperthread = "/HT"; 653 else 654 hyperthread = ""; 655 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 656 i); 657 } 658} 659 660/* 661 * AP CPU's call this to initialize themselves. 662 */ 663void 664init_secondary(void) 665{ 666 struct pcpu *pc; 667 vm_offset_t addr; 668 int gsel_tss; 669 int x, myid; 670 u_int cpuid, cr0; 671 672 /* bootAP is set in start_ap() to our ID. */ 673 myid = bootAP; 674 675 /* Get per-cpu data */ 676 pc = &__pcpu[myid]; 677 678 /* prime data page for it to use */ 679 pcpu_init(pc, myid, sizeof(struct pcpu)); 680 dpcpu_init(dpcpu, myid); 681 pc->pc_apic_id = cpu_apic_ids[myid]; 682 pc->pc_prvspace = pc; 683 pc->pc_curthread = 0; 684 685 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 686 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 687 688 for (x = 0; x < NGDT; x++) { 689 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 690 } 691 692 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 693 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 694 lgdt(&r_gdt); /* does magic intra-segment return */ 695 696 lidt(&r_idt); 697 698 lldt(_default_ldt); 699 PCPU_SET(currentldt, _default_ldt); 700 701 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 702 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 703 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 704 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 705 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 706 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 707 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 708 ltr(gsel_tss); 709 710 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 711 712 /* 713 * Set to a known state: 714 * Set by mpboot.s: CR0_PG, CR0_PE 715 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 716 */ 717 cr0 = rcr0(); 718 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 719 load_cr0(cr0); 720 CHECK_WRITE(0x38, 5); 721 722 /* Disable local APIC just to be sure. */ 723 lapic_disable(); 724 725 /* signal our startup to the BSP. */ 726 mp_naps++; 727 CHECK_WRITE(0x39, 6); 728 729 /* Spin until the BSP releases the AP's. */ 730 while (!aps_ready) 731 ia32_pause(); 732 733 /* BSP may have changed PTD while we were waiting */ 734 invltlb(); 735 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 736 invlpg(addr); 737 738#if defined(I586_CPU) && !defined(NO_F00F_HACK) 739 lidt(&r_idt); 740#endif 741 742 /* Initialize the PAT MSR if present. */ 743 pmap_init_pat(); 744 745 /* set up CPU registers and state */ 746 cpu_setregs(); 747 748 /* set up SSE/NX */ 749 initializecpu(); 750 751 /* set up FPU state on the AP */ 752 npxinit(false); 753 754 if (cpu_ops.cpu_init) 755 cpu_ops.cpu_init(); 756 757 /* A quick check from sanity claus */ 758 cpuid = PCPU_GET(cpuid); 759 if (PCPU_GET(apic_id) != lapic_id()) { 760 printf("SMP: cpuid = %d\n", cpuid); 761 printf("SMP: actual apic_id = %d\n", lapic_id()); 762 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 763 panic("cpuid mismatch! boom!!"); 764 } 765 766 /* Initialize curthread. */ 767 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 768 PCPU_SET(curthread, PCPU_GET(idlethread)); 769 770 mca_init(); 771 772 mtx_lock_spin(&ap_boot_mtx); 773 774 /* Init local apic for irq's */ 775 lapic_setup(1); 776 777 /* Set memory range attributes for this CPU to match the BSP */ 778 mem_range_AP_init(); 779 780 smp_cpus++; 781 782 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 783 printf("SMP: AP CPU #%d Launched!\n", cpuid); 784 785 /* Determine if we are a logical CPU. */ 786 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 787 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 788 CPU_SET(cpuid, &logical_cpus_mask); 789 790 if (bootverbose) 791 lapic_dump("AP"); 792 793 if (smp_cpus == mp_ncpus) { 794 /* enable IPI's, tlb shootdown, freezes etc */ 795 atomic_store_rel_int(&smp_started, 1); 796 } 797 798 mtx_unlock_spin(&ap_boot_mtx); 799 800 /* Wait until all the AP's are up. */ 801 while (smp_started == 0) 802 ia32_pause(); 803 804 /* Start per-CPU event timers. */ 805 cpu_initclocks_ap(); 806 807 /* Enter the scheduler. */ 808 sched_throw(NULL); 809 810 panic("scheduler returned us to %s", __func__); 811 /* NOTREACHED */ 812} 813 814/******************************************************************* 815 * local functions and data 816 */ 817 818/* 819 * We tell the I/O APIC code about all the CPUs we want to receive 820 * interrupts. If we don't want certain CPUs to receive IRQs we 821 * can simply not tell the I/O APIC code about them in this function. 822 * We also do not tell it about the BSP since it tells itself about 823 * the BSP internally to work with UP kernels and on UP machines. 824 */ 825static void 826set_interrupt_apic_ids(void) 827{ 828 u_int i, apic_id; 829 830 for (i = 0; i < MAXCPU; i++) { 831 apic_id = cpu_apic_ids[i]; 832 if (apic_id == -1) 833 continue; 834 if (cpu_info[apic_id].cpu_bsp) 835 continue; 836 if (cpu_info[apic_id].cpu_disabled) 837 continue; 838 839 /* Don't let hyperthreads service interrupts. */ 840 if (hyperthreading_cpus > 1 && 841 apic_id % hyperthreading_cpus != 0) 842 continue; 843 844 intr_add_cpu(i); 845 } 846} 847 848/* 849 * Assign logical CPU IDs to local APICs. 850 */ 851static void 852assign_cpu_ids(void) 853{ 854 u_int i; 855 856 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 857 &hyperthreading_allowed); 858 859 /* Check for explicitly disabled CPUs. */ 860 for (i = 0; i <= MAX_APIC_ID; i++) { 861 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 862 continue; 863 864 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 865 cpu_info[i].cpu_hyperthread = 1; 866 867 /* 868 * Don't use HT CPU if it has been disabled by a 869 * tunable. 870 */ 871 if (hyperthreading_allowed == 0) { 872 cpu_info[i].cpu_disabled = 1; 873 continue; 874 } 875 } 876 877 /* Don't use this CPU if it has been disabled by a tunable. */ 878 if (resource_disabled("lapic", i)) { 879 cpu_info[i].cpu_disabled = 1; 880 continue; 881 } 882 } 883 884 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 885 hyperthreading_cpus = 0; 886 cpu_logical = 1; 887 } 888 889 /* 890 * Assign CPU IDs to local APIC IDs and disable any CPUs 891 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 892 * 893 * To minimize confusion for userland, we attempt to number 894 * CPUs such that all threads and cores in a package are 895 * grouped together. For now we assume that the BSP is always 896 * the first thread in a package and just start adding APs 897 * starting with the BSP's APIC ID. 898 */ 899 mp_ncpus = 1; 900 cpu_apic_ids[0] = boot_cpu_id; 901 apic_cpuids[boot_cpu_id] = 0; 902 for (i = boot_cpu_id + 1; i != boot_cpu_id; 903 i == MAX_APIC_ID ? i = 0 : i++) { 904 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 905 cpu_info[i].cpu_disabled) 906 continue; 907 908 if (mp_ncpus < MAXCPU) { 909 cpu_apic_ids[mp_ncpus] = i; 910 apic_cpuids[i] = mp_ncpus; 911 mp_ncpus++; 912 } else 913 cpu_info[i].cpu_disabled = 1; 914 } 915 KASSERT(mp_maxid >= mp_ncpus - 1, 916 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 917 mp_ncpus)); 918} 919 920/* 921 * start each AP in our list 922 */ 923/* Lowest 1MB is already mapped: don't touch*/ 924#define TMPMAP_START 1 925static int 926start_all_aps(void) 927{ 928#ifndef PC98 929 u_char mpbiosreason; 930#endif 931 u_int32_t mpbioswarmvec; 932 int apic_id, cpu, i; 933 934 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 935 936 /* install the AP 1st level boot code */ 937 install_ap_tramp(); 938 939 /* save the current value of the warm-start vector */ 940 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 941#ifndef PC98 942 outb(CMOS_REG, BIOS_RESET); 943 mpbiosreason = inb(CMOS_DATA); 944#endif 945 946 /* set up temporary P==V mapping for AP boot */ 947 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 948 for (i = TMPMAP_START; i < NKPT; i++) 949 PTD[i] = PTD[KPTDI + i]; 950 invltlb(); 951 952 /* start each AP */ 953 for (cpu = 1; cpu < mp_ncpus; cpu++) { 954 apic_id = cpu_apic_ids[cpu]; 955 956 /* allocate and set up a boot stack data page */ 957 bootstacks[cpu] = 958 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE, 959 M_WAITOK | M_ZERO); 960 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 961 M_WAITOK | M_ZERO); 962 /* setup a vector to our boot code */ 963 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 964 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 965#ifndef PC98 966 outb(CMOS_REG, BIOS_RESET); 967 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 968#endif 969 970 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 971 bootAP = cpu; 972 973 /* attempt to start the Application Processor */ 974 CHECK_INIT(99); /* setup checkpoints */ 975 if (!start_ap(apic_id)) { 976 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 977 CHECK_PRINT("trace"); /* show checkpoints */ 978 /* better panic as the AP may be running loose */ 979 printf("panic y/n? [y] "); 980 if (cngetc() != 'n') 981 panic("bye-bye"); 982 } 983 CHECK_PRINT("trace"); /* show checkpoints */ 984 985 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 986 } 987 988 /* restore the warmstart vector */ 989 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 990 991#ifndef PC98 992 outb(CMOS_REG, BIOS_RESET); 993 outb(CMOS_DATA, mpbiosreason); 994#endif 995 996 /* Undo V==P hack from above */ 997 for (i = TMPMAP_START; i < NKPT; i++) 998 PTD[i] = 0; 999 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 1000 1001 /* number of APs actually started */ 1002 return mp_naps; 1003} 1004 1005/* 1006 * load the 1st level AP boot code into base memory. 1007 */ 1008 1009/* targets for relocation */ 1010extern void bigJump(void); 1011extern void bootCodeSeg(void); 1012extern void bootDataSeg(void); 1013extern void MPentry(void); 1014extern u_int MP_GDT; 1015extern u_int mp_gdtbase; 1016 1017static void 1018install_ap_tramp(void) 1019{ 1020 int x; 1021 int size = *(int *) ((u_long) & bootMP_size); 1022 vm_offset_t va = boot_address + KERNBASE; 1023 u_char *src = (u_char *) ((u_long) bootMP); 1024 u_char *dst = (u_char *) va; 1025 u_int boot_base = (u_int) bootMP; 1026 u_int8_t *dst8; 1027 u_int16_t *dst16; 1028 u_int32_t *dst32; 1029 1030 KASSERT (size <= PAGE_SIZE, 1031 ("'size' do not fit into PAGE_SIZE, as expected.")); 1032 pmap_kenter(va, boot_address); 1033 pmap_invalidate_page (kernel_pmap, va); 1034 for (x = 0; x < size; ++x) 1035 *dst++ = *src++; 1036 1037 /* 1038 * modify addresses in code we just moved to basemem. unfortunately we 1039 * need fairly detailed info about mpboot.s for this to work. changes 1040 * to mpboot.s might require changes here. 1041 */ 1042 1043 /* boot code is located in KERNEL space */ 1044 dst = (u_char *) va; 1045 1046 /* modify the lgdt arg */ 1047 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1048 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 1049 1050 /* modify the ljmp target for MPentry() */ 1051 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1052 *dst32 = ((u_int) MPentry - KERNBASE); 1053 1054 /* modify the target for boot code segment */ 1055 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1056 dst8 = (u_int8_t *) (dst16 + 1); 1057 *dst16 = (u_int) boot_address & 0xffff; 1058 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1059 1060 /* modify the target for boot data segment */ 1061 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1062 dst8 = (u_int8_t *) (dst16 + 1); 1063 *dst16 = (u_int) boot_address & 0xffff; 1064 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1065} 1066 1067/* 1068 * This function starts the AP (application processor) identified 1069 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1070 * to accomplish this. This is necessary because of the nuances 1071 * of the different hardware we might encounter. It isn't pretty, 1072 * but it seems to work. 1073 */ 1074static int 1075start_ap(int apic_id) 1076{ 1077 int vector, ms; 1078 int cpus; 1079 1080 /* calculate the vector */ 1081 vector = (boot_address >> 12) & 0xff; 1082 1083 /* used as a watchpoint to signal AP startup */ 1084 cpus = mp_naps; 1085 1086 ipi_startup(apic_id, vector); 1087 1088 /* Wait up to 5 seconds for it to start. */ 1089 for (ms = 0; ms < 5000; ms++) { 1090 if (mp_naps > cpus) 1091 return 1; /* return SUCCESS */ 1092 DELAY(1000); 1093 } 1094 return 0; /* return FAILURE */ 1095} 1096 1097#ifdef COUNT_XINVLTLB_HITS 1098u_int xhits_gbl[MAXCPU]; 1099u_int xhits_pg[MAXCPU]; 1100u_int xhits_rng[MAXCPU]; 1101static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1102SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1103 sizeof(xhits_gbl), "IU", ""); 1104SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1105 sizeof(xhits_pg), "IU", ""); 1106SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1107 sizeof(xhits_rng), "IU", ""); 1108 1109u_int ipi_global; 1110u_int ipi_page; 1111u_int ipi_range; 1112u_int ipi_range_size; 1113SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1114SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1115SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1116SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1117 0, ""); 1118 1119u_int ipi_masked_global; 1120u_int ipi_masked_page; 1121u_int ipi_masked_range; 1122u_int ipi_masked_range_size; 1123SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1124 &ipi_masked_global, 0, ""); 1125SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1126 &ipi_masked_page, 0, ""); 1127SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1128 &ipi_masked_range, 0, ""); 1129SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1130 &ipi_masked_range_size, 0, ""); 1131#endif /* COUNT_XINVLTLB_HITS */ 1132 1133/* 1134 * Init and startup IPI. 1135 */ 1136void 1137ipi_startup(int apic_id, int vector) 1138{ 1139 1140 /* 1141 * This attempts to follow the algorithm described in the 1142 * Intel Multiprocessor Specification v1.4 in section B.4. 1143 * For each IPI, we allow the local APIC ~20us to deliver the 1144 * IPI. If that times out, we panic. 1145 */ 1146 1147 /* 1148 * first we do an INIT IPI: this INIT IPI might be run, resetting 1149 * and running the target CPU. OR this INIT IPI might be latched (P5 1150 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1151 * ignored. 1152 */ 1153 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1154 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1155 lapic_ipi_wait(20); 1156 1157 /* Explicitly deassert the INIT IPI. */ 1158 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1159 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 1160 apic_id); 1161 1162 DELAY(10000); /* wait ~10mS */ 1163 1164 /* 1165 * next we do a STARTUP IPI: the previous INIT IPI might still be 1166 * latched, (P5 bug) this 1st STARTUP would then terminate 1167 * immediately, and the previously started INIT IPI would continue. OR 1168 * the previous INIT IPI has already run. and this STARTUP IPI will 1169 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1170 * will run. 1171 */ 1172 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1173 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1174 vector, apic_id); 1175 if (!lapic_ipi_wait(20)) 1176 panic("Failed to deliver first STARTUP IPI to APIC %d", 1177 apic_id); 1178 DELAY(200); /* wait ~200uS */ 1179 1180 /* 1181 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1182 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1183 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1184 * recognized after hardware RESET or INIT IPI. 1185 */ 1186 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1187 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1188 vector, apic_id); 1189 if (!lapic_ipi_wait(20)) 1190 panic("Failed to deliver second STARTUP IPI to APIC %d", 1191 apic_id); 1192 1193 DELAY(200); /* wait ~200uS */ 1194} 1195 1196/* 1197 * Send an IPI to specified CPU handling the bitmap logic. 1198 */ 1199static void 1200ipi_send_cpu(int cpu, u_int ipi) 1201{ 1202 u_int bitmap, old_pending, new_pending; 1203 1204 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1205 1206 if (IPI_IS_BITMAPED(ipi)) { 1207 bitmap = 1 << ipi; 1208 ipi = IPI_BITMAP_VECTOR; 1209 do { 1210 old_pending = cpu_ipi_pending[cpu]; 1211 new_pending = old_pending | bitmap; 1212 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1213 old_pending, new_pending)); 1214 if (old_pending) 1215 return; 1216 } 1217 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1218} 1219 1220/* 1221 * Flush the TLB on all other CPU's 1222 */ 1223static void 1224smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1225{ 1226 u_int ncpu; 1227 1228 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1229 if (ncpu < 1) 1230 return; /* no other cpus */ 1231 if (!(read_eflags() & PSL_I)) 1232 panic("%s: interrupts disabled", __func__); 1233 mtx_lock_spin(&smp_ipi_mtx); 1234 smp_tlb_addr1 = addr1; 1235 smp_tlb_addr2 = addr2; 1236 atomic_store_rel_int(&smp_tlb_wait, 0); 1237 ipi_all_but_self(vector); 1238 while (smp_tlb_wait < ncpu) 1239 ia32_pause(); 1240 mtx_unlock_spin(&smp_ipi_mtx); 1241} 1242 1243static void 1244smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1245{ 1246 int cpu, ncpu, othercpus; 1247 1248 othercpus = mp_ncpus - 1; 1249 if (CPU_ISFULLSET(&mask)) { 1250 if (othercpus < 1) 1251 return; 1252 } else { 1253 CPU_CLR(PCPU_GET(cpuid), &mask); 1254 if (CPU_EMPTY(&mask)) 1255 return; 1256 } 1257 if (!(read_eflags() & PSL_I)) 1258 panic("%s: interrupts disabled", __func__); 1259 mtx_lock_spin(&smp_ipi_mtx); 1260 smp_tlb_addr1 = addr1; 1261 smp_tlb_addr2 = addr2; 1262 atomic_store_rel_int(&smp_tlb_wait, 0); 1263 if (CPU_ISFULLSET(&mask)) { 1264 ncpu = othercpus; 1265 ipi_all_but_self(vector); 1266 } else { 1267 ncpu = 0; 1268 while ((cpu = CPU_FFS(&mask)) != 0) { 1269 cpu--; 1270 CPU_CLR(cpu, &mask); 1271 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, 1272 vector); 1273 ipi_send_cpu(cpu, vector); 1274 ncpu++; 1275 } 1276 } 1277 while (smp_tlb_wait < ncpu) 1278 ia32_pause(); 1279 mtx_unlock_spin(&smp_ipi_mtx); 1280} 1281 1282void 1283smp_cache_flush(void) 1284{ 1285 1286 if (smp_started) 1287 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1288} 1289 1290void 1291smp_invltlb(void) 1292{ 1293 1294 if (smp_started) { 1295 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1296#ifdef COUNT_XINVLTLB_HITS 1297 ipi_global++; 1298#endif 1299 } 1300} 1301 1302void 1303smp_invlpg(vm_offset_t addr) 1304{ 1305 1306 if (smp_started) { 1307 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1308#ifdef COUNT_XINVLTLB_HITS 1309 ipi_page++; 1310#endif 1311 } 1312} 1313 1314void 1315smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1316{ 1317 1318 if (smp_started) { 1319 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1320#ifdef COUNT_XINVLTLB_HITS 1321 ipi_range++; 1322 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1323#endif 1324 } 1325} 1326 1327void 1328smp_masked_invltlb(cpuset_t mask) 1329{ 1330 1331 if (smp_started) { 1332 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1333#ifdef COUNT_XINVLTLB_HITS 1334 ipi_masked_global++; 1335#endif 1336 } 1337} 1338 1339void 1340smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) 1341{ 1342 1343 if (smp_started) { 1344 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1345#ifdef COUNT_XINVLTLB_HITS 1346 ipi_masked_page++; 1347#endif 1348 } 1349} 1350 1351void 1352smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) 1353{ 1354 1355 if (smp_started) { 1356 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1357#ifdef COUNT_XINVLTLB_HITS 1358 ipi_masked_range++; 1359 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1360#endif 1361 } 1362} 1363 1364void 1365ipi_bitmap_handler(struct trapframe frame) 1366{ 1367 struct trapframe *oldframe; 1368 struct thread *td; 1369 int cpu = PCPU_GET(cpuid); 1370 u_int ipi_bitmap; 1371 1372 critical_enter(); 1373 td = curthread; 1374 td->td_intr_nesting_level++; 1375 oldframe = td->td_intr_frame; 1376 td->td_intr_frame = &frame; 1377 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1378 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1379#ifdef COUNT_IPIS 1380 (*ipi_preempt_counts[cpu])++; 1381#endif 1382 sched_preempt(td); 1383 } 1384 if (ipi_bitmap & (1 << IPI_AST)) { 1385#ifdef COUNT_IPIS 1386 (*ipi_ast_counts[cpu])++; 1387#endif 1388 /* Nothing to do for AST */ 1389 } 1390 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1391#ifdef COUNT_IPIS 1392 (*ipi_hardclock_counts[cpu])++; 1393#endif 1394 hardclockintr(); 1395 } 1396 td->td_intr_frame = oldframe; 1397 td->td_intr_nesting_level--; 1398 critical_exit(); 1399} 1400 1401/* 1402 * send an IPI to a set of cpus. 1403 */ 1404void 1405ipi_selected(cpuset_t cpus, u_int ipi) 1406{ 1407 int cpu; 1408 1409 /* 1410 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1411 * of help in order to understand what is the source. 1412 * Set the mask of receiving CPUs for this purpose. 1413 */ 1414 if (ipi == IPI_STOP_HARD) 1415 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1416 1417 while ((cpu = CPU_FFS(&cpus)) != 0) { 1418 cpu--; 1419 CPU_CLR(cpu, &cpus); 1420 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1421 ipi_send_cpu(cpu, ipi); 1422 } 1423} 1424 1425/* 1426 * send an IPI to a specific CPU. 1427 */ 1428void 1429ipi_cpu(int cpu, u_int ipi) 1430{ 1431 1432 /* 1433 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1434 * of help in order to understand what is the source. 1435 * Set the mask of receiving CPUs for this purpose. 1436 */ 1437 if (ipi == IPI_STOP_HARD) 1438 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1439 1440 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1441 ipi_send_cpu(cpu, ipi); 1442} 1443 1444/* 1445 * send an IPI to all CPUs EXCEPT myself 1446 */ 1447void 1448ipi_all_but_self(u_int ipi) 1449{ 1450 cpuset_t other_cpus; 1451 1452 other_cpus = all_cpus; 1453 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1454 if (IPI_IS_BITMAPED(ipi)) { 1455 ipi_selected(other_cpus, ipi); 1456 return; 1457 } 1458 1459 /* 1460 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1461 * of help in order to understand what is the source. 1462 * Set the mask of receiving CPUs for this purpose. 1463 */ 1464 if (ipi == IPI_STOP_HARD) 1465 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1466 1467 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1468 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1469} 1470 1471int 1472ipi_nmi_handler() 1473{ 1474 u_int cpuid; 1475 1476 /* 1477 * As long as there is not a simple way to know about a NMI's 1478 * source, if the bitmask for the current CPU is present in 1479 * the global pending bitword an IPI_STOP_HARD has been issued 1480 * and should be handled. 1481 */ 1482 cpuid = PCPU_GET(cpuid); 1483 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1484 return (1); 1485 1486 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1487 cpustop_handler(); 1488 return (0); 1489} 1490 1491/* 1492 * Handle an IPI_STOP by saving our current context and spinning until we 1493 * are resumed. 1494 */ 1495void 1496cpustop_handler(void) 1497{ 1498 u_int cpu; 1499 1500 cpu = PCPU_GET(cpuid); 1501 1502 savectx(&stoppcbs[cpu]); 1503 1504 /* Indicate that we are stopped */ 1505 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1506 1507 /* Wait for restart */ 1508 while (!CPU_ISSET(cpu, &started_cpus)) 1509 ia32_pause(); 1510 1511 CPU_CLR_ATOMIC(cpu, &started_cpus); 1512 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1513 1514 if (cpu == 0 && cpustop_restartfunc != NULL) { 1515 cpustop_restartfunc(); 1516 cpustop_restartfunc = NULL; 1517 } 1518} 1519 1520/* 1521 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1522 * are resumed. 1523 */ 1524void 1525cpususpend_handler(void) 1526{ 1527 u_int cpu; 1528 1529 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED); 1530 1531 cpu = PCPU_GET(cpuid); 1532 if (savectx(&susppcbs[cpu]->sp_pcb)) { 1533 npxsuspend(susppcbs[cpu]->sp_fpususpend); 1534 wbinvd(); 1535 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1536 } else { 1537 npxresume(susppcbs[cpu]->sp_fpususpend); 1538 pmap_init_pat(); 1539 initializecpu(); 1540 PCPU_SET(switchtime, 0); 1541 PCPU_SET(switchticks, ticks); 1542 1543 /* Indicate that we are resumed */ 1544 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1545 } 1546 1547 /* Wait for resume */ 1548 while (!CPU_ISSET(cpu, &started_cpus)) 1549 ia32_pause(); 1550 1551 if (cpu_ops.cpu_resume) 1552 cpu_ops.cpu_resume(); 1553 1554 /* Resume MCA and local APIC */ 1555 mca_resume(); 1556 lapic_setup(0); 1557 1558 /* Indicate that we are resumed */ 1559 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1560 CPU_CLR_ATOMIC(cpu, &started_cpus); 1561} 1562 1563/* 1564 * Handlers for TLB related IPIs 1565 */ 1566void 1567invltlb_handler(void) 1568{ 1569 uint64_t cr3; 1570#ifdef COUNT_XINVLTLB_HITS 1571 xhits_gbl[PCPU_GET(cpuid)]++; 1572#endif /* COUNT_XINVLTLB_HITS */ 1573#ifdef COUNT_IPIS 1574 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1575#endif /* COUNT_IPIS */ 1576 1577 cr3 = rcr3(); 1578 load_cr3(cr3); 1579 atomic_add_int(&smp_tlb_wait, 1); 1580} 1581 1582void 1583invlpg_handler(void) 1584{ 1585#ifdef COUNT_XINVLTLB_HITS 1586 xhits_pg[PCPU_GET(cpuid)]++; 1587#endif /* COUNT_XINVLTLB_HITS */ 1588#ifdef COUNT_IPIS 1589 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1590#endif /* COUNT_IPIS */ 1591 1592 invlpg(smp_tlb_addr1); 1593 1594 atomic_add_int(&smp_tlb_wait, 1); 1595} 1596 1597void 1598invlrng_handler(void) 1599{ 1600 vm_offset_t addr; 1601#ifdef COUNT_XINVLTLB_HITS 1602 xhits_rng[PCPU_GET(cpuid)]++; 1603#endif /* COUNT_XINVLTLB_HITS */ 1604#ifdef COUNT_IPIS 1605 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++; 1606#endif /* COUNT_IPIS */ 1607 1608 addr = smp_tlb_addr1; 1609 do { 1610 invlpg(addr); 1611 addr += PAGE_SIZE; 1612 } while (addr < smp_tlb_addr2); 1613 1614 atomic_add_int(&smp_tlb_wait, 1); 1615} 1616 1617void 1618invlcache_handler(void) 1619{ 1620#ifdef COUNT_IPIS 1621 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++; 1622#endif /* COUNT_IPIS */ 1623 1624 wbinvd(); 1625 atomic_add_int(&smp_tlb_wait, 1); 1626} 1627 1628/* 1629 * This is called once the rest of the system is up and running and we're 1630 * ready to let the AP's out of the pen. 1631 */ 1632static void 1633release_aps(void *dummy __unused) 1634{ 1635 1636 if (mp_ncpus == 1) 1637 return; 1638 atomic_store_rel_int(&aps_ready, 1); 1639 while (smp_started == 0) 1640 ia32_pause(); 1641} 1642SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1643 1644#ifdef COUNT_IPIS 1645/* 1646 * Setup interrupt counters for IPI handlers. 1647 */ 1648static void 1649mp_ipi_intrcnt(void *dummy) 1650{ 1651 char buf[64]; 1652 int i; 1653 1654 CPU_FOREACH(i) { 1655 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1656 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1657 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1658 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1659 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1660 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1661 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1662 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1663 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1664 intrcnt_add(buf, &ipi_preempt_counts[i]); 1665 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1666 intrcnt_add(buf, &ipi_ast_counts[i]); 1667 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1668 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1669 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i); 1670 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1671 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1672 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1673 } 1674} 1675SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1676#endif 1677