mp_machdep.c revision 27697
1178525Sjb/* 2178525Sjb * Copyright (c) 1996, by Steve Passe 3178525Sjb * All rights reserved. 4178525Sjb * 5178525Sjb * Redistribution and use in source and binary forms, with or without 6178525Sjb * modification, are permitted provided that the following conditions 7178525Sjb * are met: 8178525Sjb * 1. Redistributions of source code must retain the above copyright 9178525Sjb * notice, this list of conditions and the following disclaimer. 10178525Sjb * 2. The name of the developer may NOT be used to endorse or promote products 11178525Sjb * derived from this software without specific prior written permission. 12178525Sjb * 13178525Sjb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14178525Sjb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15178525Sjb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16178525Sjb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17178525Sjb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18178525Sjb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19178525Sjb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20178525Sjb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21178525Sjb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22178525Sjb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23178525Sjb * SUCH DAMAGE. 24178525Sjb * 25178525Sjb * $Id: mp_machdep.c,v 1.36 1997/07/23 20:47:19 fsmp Exp $ 26178525Sjb */ 27178525Sjb 28178525Sjb#include "opt_smp.h" 29178525Sjb 30178525Sjb#include <sys/param.h> /* for KERNBASE */ 31178525Sjb#include <sys/systm.h> 32178525Sjb 33178525Sjb#include <vm/vm.h> /* for KERNBASE */ 34178525Sjb#include <vm/vm_param.h> /* for KERNBASE */ 35178525Sjb#include <vm/pmap.h> /* for KERNBASE */ 36178525Sjb#include <vm/vm_kern.h> 37178525Sjb#include <vm/vm_extern.h> 38178525Sjb 39178525Sjb#include <machine/smp.h> 40178525Sjb#include <machine/apic.h> 41178525Sjb#include <machine/mpapic.h> 42178525Sjb#include <machine/segments.h> 43178525Sjb#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 44178525Sjb#include <machine/tss.h> 45178525Sjb#include <machine/specialreg.h> 46178525Sjb 47178525Sjb#include <i386/i386/cons.h> /* cngetc() */ 48178525Sjb 49178525Sjb#if defined(APIC_IO) 50178525Sjb#include <machine/md_var.h> /* setidt() */ 51178525Sjb#include <i386/isa/icu.h> /* IPIs */ 52178525Sjb#include <i386/isa/intr_machdep.h> /* IPIs */ 53178525Sjb#endif /* APIC_IO */ 54178525Sjb 55178525Sjb#define WARMBOOT_TARGET 0 56178525Sjb#define WARMBOOT_OFF (KERNBASE + 0x0467) 57178525Sjb#define WARMBOOT_SEG (KERNBASE + 0x0469) 58178525Sjb 59178525Sjb#define BIOS_BASE (0xf0000) 60178525Sjb#define BIOS_SIZE (0x10000) 61178525Sjb#define BIOS_COUNT (BIOS_SIZE/4) 62178525Sjb 63178525Sjb#define CMOS_REG (0x70) 64178525Sjb#define CMOS_DATA (0x71) 65178525Sjb#define BIOS_RESET (0x0f) 66178525Sjb#define BIOS_WARM (0x0a) 67178525Sjb 68178525Sjb#define PROCENTRY_FLAG_EN 0x01 69178525Sjb#define PROCENTRY_FLAG_BP 0x02 70178525Sjb#define IOAPICENTRY_FLAG_EN 0x01 71178525Sjb 72178525Sjb 73178525Sjb/* MP Floating Pointer Structure */ 74178525Sjbtypedef struct MPFPS { 75178525Sjb char signature[4]; 76178525Sjb void *pap; 77178525Sjb u_char length; 78178525Sjb u_char spec_rev; 79178525Sjb u_char checksum; 80178525Sjb u_char mpfb1; 81178525Sjb u_char mpfb2; 82178525Sjb u_char mpfb3; 83178525Sjb u_char mpfb4; 84178525Sjb u_char mpfb5; 85178525Sjb} *mpfps_t; 86178525Sjb 87178525Sjb/* MP Configuration Table Header */ 88178525Sjbtypedef struct MPCTH { 89178525Sjb char signature[4]; 90178525Sjb u_short base_table_length; 91178525Sjb u_char spec_rev; 92178525Sjb u_char checksum; 93178525Sjb u_char oem_id[8]; 94178525Sjb u_char product_id[12]; 95178525Sjb void *oem_table_pointer; 96178525Sjb u_short oem_table_size; 97178525Sjb u_short entry_count; 98178525Sjb void *apic_address; 99178525Sjb u_short extended_table_length; 100178525Sjb u_char extended_table_checksum; 101178525Sjb u_char reserved; 102178525Sjb} *mpcth_t; 103178525Sjb 104178525Sjb 105178525Sjbtypedef struct PROCENTRY { 106178525Sjb u_char type; 107178525Sjb u_char apic_id; 108178525Sjb u_char apic_version; 109178525Sjb u_char cpu_flags; 110178525Sjb u_long cpu_signature; 111178525Sjb u_long feature_flags; 112178525Sjb u_long reserved1; 113178525Sjb u_long reserved2; 114178525Sjb} *proc_entry_ptr; 115178525Sjb 116178525Sjbtypedef struct BUSENTRY { 117178525Sjb u_char type; 118178525Sjb u_char bus_id; 119178525Sjb char bus_type[6]; 120178525Sjb} *bus_entry_ptr; 121178525Sjb 122178525Sjbtypedef struct IOAPICENTRY { 123178525Sjb u_char type; 124178525Sjb u_char apic_id; 125178525Sjb u_char apic_version; 126178525Sjb u_char apic_flags; 127178525Sjb void *apic_address; 128178525Sjb} *io_apic_entry_ptr; 129178525Sjb 130178525Sjbtypedef struct INTENTRY { 131178525Sjb u_char type; 132178525Sjb u_char int_type; 133178525Sjb u_short int_flags; 134178525Sjb u_char src_bus_id; 135178525Sjb u_char src_bus_irq; 136178525Sjb u_char dst_apic_id; 137178525Sjb u_char dst_apic_int; 138178525Sjb} *int_entry_ptr; 139178525Sjb 140178525Sjb/* descriptions of MP basetable entries */ 141178525Sjbtypedef struct BASETABLE_ENTRY { 142178525Sjb u_char type; 143178525Sjb u_char length; 144178525Sjb char name[16]; 145178525Sjb} basetable_entry; 146178525Sjb 147178525Sjb/* 148178525Sjb * this code MUST be enabled here and in mpboot.s. 149178525Sjb * it follows the very early stages of AP boot by placing values in CMOS ram. 150178525Sjb * it NORMALLY will never be needed and thus the primitive method for enabling. 151178525Sjb * 152178525Sjb#define CHECK_POINTS 153 */ 154 155#if defined(CHECK_POINTS) 156#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 157#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 158 159#define CHECK_INIT(D); \ 160 CHECK_WRITE(0x34, (D)); \ 161 CHECK_WRITE(0x35, (D)); \ 162 CHECK_WRITE(0x36, (D)); \ 163 CHECK_WRITE(0x37, (D)); \ 164 CHECK_WRITE(0x38, (D)); \ 165 CHECK_WRITE(0x39, (D)); 166 167#define CHECK_PRINT(S); \ 168 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 169 (S), \ 170 CHECK_READ(0x34), \ 171 CHECK_READ(0x35), \ 172 CHECK_READ(0x36), \ 173 CHECK_READ(0x37), \ 174 CHECK_READ(0x38), \ 175 CHECK_READ(0x39)); 176 177#else /* CHECK_POINTS */ 178 179#define CHECK_INIT(D) 180#define CHECK_PRINT(S) 181 182#endif /* CHECK_POINTS */ 183 184/* 185 * Values to send to the POST hardware. 186 */ 187#define MP_BOOTADDRESS_POST 0x10 188#define MP_PROBE_POST 0x11 189#define MP_START_POST 0x12 190#define MP_ANNOUNCE_POST 0x13 191#define MPTABLE_PASS1_POST 0x14 192#define MPTABLE_PASS2_POST 0x15 193#define MP_ENABLE_POST 0x16 194#define START_ALL_APS_POST 0x17 195#define INSTALL_AP_TRAMP_POST 0x18 196#define START_AP_POST 0x19 197 198/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 199int current_postcode; 200 201/** XXX FIXME: what system files declare these??? */ 202extern struct region_descriptor r_gdt, r_idt; 203 204int mp_ncpus; /* # of CPUs, including BSP */ 205int mp_naps; /* # of Applications processors */ 206int mp_nbusses; /* # of busses */ 207int mp_napics; /* # of IO APICs */ 208int boot_cpu_id; /* designated BSP */ 209vm_offset_t cpu_apic_address; 210vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 211 212u_int32_t cpu_apic_versions[NCPU]; 213u_int32_t io_apic_versions[NAPIC]; 214 215/* 216 * APIC ID logical/physical mapping structures. 217 * We oversize these to simplify boot-time config. 218 */ 219int cpu_num_to_apic_id[NAPICID]; 220int io_num_to_apic_id[NAPICID]; 221int apic_id_to_logical[NAPICID]; 222 223/* Bitmap of all available CPUs */ 224u_int all_cpus; 225 226/* Boot of AP uses this PTD */ 227u_int *bootPTD; 228 229/* Hotwire a 0->4MB V==P mapping */ 230extern pt_entry_t KPTphys; 231 232/* Virtual address of per-cpu common_tss */ 233extern struct i386tss common_tss; 234 235/* 236 * Local data and functions. 237 */ 238 239static int mp_capable; 240static u_int boot_address; 241static u_int base_memory; 242 243static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 244static mpfps_t mpfps; 245static int search_for_sig(u_int32_t target, int count); 246static void mp_enable(u_int boot_addr); 247 248static int mptable_pass1(void); 249static int mptable_pass2(void); 250static void default_mp_table(int type); 251static void init_locks(void); 252static int start_all_aps(u_int boot_addr); 253static void install_ap_tramp(u_int boot_addr); 254static int start_ap(int logicalCpu, u_int boot_addr); 255 256 257/* 258 * Calculate usable address in base memory for AP trampoline code. 259 */ 260u_int 261mp_bootaddress(u_int basemem) 262{ 263 POSTCODE(MP_BOOTADDRESS_POST); 264 265 base_memory = basemem * 1024; /* convert to bytes */ 266 267 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 268 if ((base_memory - boot_address) < bootMP_size) 269 boot_address -= 4096; /* not enough, lower by 4k */ 270 271 return boot_address; 272} 273 274 275/* 276 * Look for an Intel MP spec table (ie, SMP capable hardware). 277 */ 278int 279mp_probe(void) 280{ 281 int x; 282 u_long segment; 283 u_int32_t target; 284 285 POSTCODE(MP_PROBE_POST); 286 287 /* see if EBDA exists */ 288 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 289 /* search first 1K of EBDA */ 290 target = (u_int32_t) (segment << 4); 291 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 292 goto found; 293 } else { 294 /* last 1K of base memory, effective 'top of base' passed in */ 295 target = (u_int32_t) (base_memory - 0x400); 296 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 297 goto found; 298 } 299 300 /* search the BIOS */ 301 target = (u_int32_t) BIOS_BASE; 302 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 303 goto found; 304 305 /* nothing found */ 306 mpfps = (mpfps_t)0; 307 mp_capable = 0; 308 return 0; 309 310found: 311 /* calculate needed resources */ 312 mpfps = (mpfps_t)x; 313 if (mptable_pass1()) 314 panic("you must reconfigure your kernel"); 315 316 /* flag fact that we are running multiple processors */ 317 mp_capable = 1; 318 return 1; 319} 320 321 322/* 323 * Startup the SMP processors. 324 */ 325void 326mp_start(void) 327{ 328 POSTCODE(MP_START_POST); 329 330 /* look for MP capable motherboard */ 331 if (mp_capable) 332 mp_enable(boot_address); 333 else 334 panic("MP hardware not found!"); 335} 336 337 338/* 339 * Print various information about the SMP system hardware and setup. 340 */ 341void 342mp_announce(void) 343{ 344 int x; 345 346 POSTCODE(MP_ANNOUNCE_POST); 347 348 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 349 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 350 printf(", version: 0x%08x", cpu_apic_versions[0]); 351 printf(", at 0x%08x\n", cpu_apic_address); 352 for (x = 1; x <= mp_naps; ++x) { 353 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 354 printf(", version: 0x%08x", cpu_apic_versions[x]); 355 printf(", at 0x%08x\n", cpu_apic_address); 356 } 357 358#if defined(APIC_IO) 359 for (x = 0; x < mp_napics; ++x) { 360 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 361 printf(", version: 0x%08x", io_apic_versions[x]); 362 printf(", at 0x%08x\n", io_apic_address[x]); 363 } 364#else 365 printf(" Warning: APIC I/O disabled\n"); 366#endif /* APIC_IO */ 367} 368 369/* 370 * AP cpu's call this to sync up protected mode. 371 */ 372void 373init_secondary(void) 374{ 375 int gsel_tss, slot; 376 377 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 378 r_gdt.rd_base = (int) gdt; 379 lgdt(&r_gdt); /* does magic intra-segment return */ 380 lidt(&r_idt); 381 lldt(_default_ldt); 382 383 slot = NGDT + cpuid; 384 gsel_tss = GSEL(slot, SEL_KPL); 385 gdt[slot].sd.sd_type = SDT_SYS386TSS; 386 common_tss.tss_esp0 = 0; /* not used until after switch */ 387 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 388 common_tss.tss_ioopt = (sizeof common_tss) << 16; 389 ltr(gsel_tss); 390 391 load_cr0(0x8005003b); /* XXX! */ 392 393 PTD[0] = 0; 394 pmap_set_opt((unsigned *)PTD); 395 396 invltlb(); 397} 398 399 400#if defined(APIC_IO) 401/* 402 * Final configuration of the BSP's local APIC: 403 * - disable 'pic mode'. 404 * - disable 'virtual wire mode'. 405 * - enable NMI. 406 */ 407void 408bsp_apic_configure(void) 409{ 410 u_char byte; 411 u_int32_t temp; 412 413 /* leave 'pic mode' if necessary */ 414 if (picmode) { 415 outb(0x22, 0x70); /* select IMCR */ 416 byte = inb(0x23); /* current contents */ 417 byte |= 0x01; /* mask external INTR */ 418 outb(0x23, byte); /* disconnect 8259s/NMI */ 419 } 420 421 /* mask lint0 (the 8259 'virtual wire' connection) */ 422 temp = lapic.lvt_lint0; 423 temp |= APIC_LVT_M; /* set the mask */ 424 lapic.lvt_lint0 = temp; 425 426 /* setup lint1 to handle NMI */ 427 temp = lapic.lvt_lint1; 428 temp &= ~APIC_LVT_M; /* clear the mask */ 429 lapic.lvt_lint1 = temp; 430 431 if (bootverbose) 432 apic_dump("bsp_apic_configure()"); 433} 434#endif /* APIC_IO */ 435 436 437/******************************************************************* 438 * local functions and data 439 */ 440 441/* 442 * start the SMP system 443 */ 444static void 445mp_enable(u_int boot_addr) 446{ 447 int x; 448#if defined(APIC_IO) 449 int apic; 450 u_int ux; 451#endif /* APIC_IO */ 452 453 POSTCODE(MP_ENABLE_POST); 454 455 /* turn on 4MB of V == P addressing so we can get to MP table */ 456 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 457 invltlb(); 458 459 /* examine the MP table for needed info, uses physical addresses */ 460 x = mptable_pass2(); 461 462 *(int *)PTD = 0; 463 invltlb(); 464 465 /* can't process default configs till the CPU APIC is pmapped */ 466 if (x) 467 default_mp_table(x); 468 469#if defined(APIC_IO) 470 471 /* fill the LOGICAL io_apic_versions table */ 472 for (apic = 0; apic < mp_napics; ++apic) { 473 ux = io_apic_read(apic, IOAPIC_VER); 474 io_apic_versions[apic] = ux; 475 } 476 477 /* program each IO APIC in the system */ 478 for (apic = 0; apic < mp_napics; ++apic) 479 if (io_apic_setup(apic) < 0) 480 panic("IO APIC setup failure"); 481 482 /* install a 'Spurious INTerrupt' vector */ 483 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 484 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 485 486 /* install an inter-CPU IPI for TLB invalidation */ 487 setidt(XINVLTLB_OFFSET, Xinvltlb, 488 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 489 490 /* install an inter-CPU IPI for CPU stop/restart */ 491 setidt(XCPUSTOP_OFFSET, Xcpustop, 492 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 493 494#if defined(TEST_TEST1) 495 /* install a "fake hardware INTerrupt" vector */ 496 setidt(XTEST1_OFFSET, Xtest1, 497 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 498#endif /** TEST_TEST1 */ 499 500#endif /* APIC_IO */ 501 502 /* initialize all SMP locks */ 503 init_locks(); 504 505 /* start each Application Processor */ 506 start_all_aps(boot_addr); 507 508 /* 509 * The init process might be started on a different CPU now, 510 * and the boot CPU might not call prepare_usermode to get 511 * cr0 correctly configured. Thus we initialize cr0 here. 512 */ 513 load_cr0(rcr0() | CR0_WP | CR0_AM); 514} 515 516 517/* 518 * look for the MP spec signature 519 */ 520 521/* string defined by the Intel MP Spec as identifying the MP table */ 522#define MP_SIG 0x5f504d5f /* _MP_ */ 523#define NEXT(X) ((X) += 4) 524static int 525search_for_sig(u_int32_t target, int count) 526{ 527 int x; 528 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 529 530 for (x = 0; x < count; NEXT(x)) 531 if (addr[x] == MP_SIG) 532 /* make array index a byte index */ 533 return (target + (x * sizeof(u_int32_t))); 534 535 return -1; 536} 537 538 539static basetable_entry basetable_entry_types[] = 540{ 541 {0, 20, "Processor"}, 542 {1, 8, "Bus"}, 543 {2, 8, "I/O APIC"}, 544 {3, 8, "I/O INT"}, 545 {4, 8, "Local INT"} 546}; 547 548typedef struct BUSDATA { 549 u_char bus_id; 550 enum busTypes bus_type; 551} bus_datum; 552 553typedef struct INTDATA { 554 u_char int_type; 555 u_short int_flags; 556 u_char src_bus_id; 557 u_char src_bus_irq; 558 u_char dst_apic_id; 559 u_char dst_apic_int; 560} io_int, local_int; 561 562typedef struct BUSTYPENAME { 563 u_char type; 564 char name[7]; 565} bus_type_name; 566 567static bus_type_name bus_type_table[] = 568{ 569 {CBUS, "CBUS"}, 570 {CBUSII, "CBUSII"}, 571 {EISA, "EISA"}, 572 {UNKNOWN_BUSTYPE, "---"}, 573 {UNKNOWN_BUSTYPE, "---"}, 574 {ISA, "ISA"}, 575 {UNKNOWN_BUSTYPE, "---"}, 576 {UNKNOWN_BUSTYPE, "---"}, 577 {UNKNOWN_BUSTYPE, "---"}, 578 {UNKNOWN_BUSTYPE, "---"}, 579 {UNKNOWN_BUSTYPE, "---"}, 580 {UNKNOWN_BUSTYPE, "---"}, 581 {PCI, "PCI"}, 582 {UNKNOWN_BUSTYPE, "---"}, 583 {UNKNOWN_BUSTYPE, "---"}, 584 {UNKNOWN_BUSTYPE, "---"}, 585 {UNKNOWN_BUSTYPE, "---"}, 586 {XPRESS, "XPRESS"}, 587 {UNKNOWN_BUSTYPE, "---"} 588}; 589/* from MP spec v1.4, table 5-1 */ 590static int default_data[7][5] = 591{ 592/* nbus, id0, type0, id1, type1 */ 593 {1, 0, ISA, 255, 255}, 594 {1, 0, EISA, 255, 255}, 595 {1, 0, EISA, 255, 255}, 596 {0, 255, 255, 255, 255},/* MCA not supported */ 597 {2, 0, ISA, 1, PCI}, 598 {2, 0, EISA, 1, PCI}, 599 {0, 255, 255, 255, 255} /* MCA not supported */ 600}; 601 602 603/* the bus data */ 604bus_datum bus_data[NBUS]; 605 606/* the IO INT data, one entry per possible APIC INTerrupt */ 607io_int io_apic_ints[NINTR]; 608 609static int nintrs; 610 611static void fix_mp_table __P((void)); 612static int processor_entry __P((proc_entry_ptr entry, int cpu)); 613static int bus_entry __P((bus_entry_ptr entry, int bus)); 614static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 615static int int_entry __P((int_entry_ptr entry, int intr)); 616static int lookup_bus_type __P((char *name)); 617 618 619/* 620 * 1st pass on motherboard's Intel MP specification table. 621 * 622 * initializes: 623 * mp_ncpus = 1 624 * 625 * determines: 626 * cpu_apic_address (common to all CPUs) 627 * io_apic_address[N] 628 * mp_naps 629 * mp_nbusses 630 * mp_napics 631 * nintrs 632 */ 633static int 634mptable_pass1(void) 635{ 636 int x; 637 mpcth_t cth; 638 int totalSize; 639 void* position; 640 int count; 641 int type; 642 int mustpanic; 643 644 POSTCODE(MPTABLE_PASS1_POST); 645 646 mustpanic = 0; 647 648 /* clear various tables */ 649 for (x = 0; x < NAPICID; ++x) { 650 io_apic_address[x] = ~0; /* IO APIC address table */ 651 } 652 653 /* init everything to empty */ 654 mp_naps = 0; 655 mp_nbusses = 0; 656 mp_napics = 0; 657 nintrs = 0; 658 659 /* check for use of 'default' configuration */ 660 if (mpfps->mpfb1 != 0) { 661 /* use default addresses */ 662 cpu_apic_address = DEFAULT_APIC_BASE; 663 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 664 665 /* fill in with defaults */ 666 mp_naps = 2; /* includes BSP */ 667 mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; 668#if defined(APIC_IO) 669 mp_napics = 1; 670 nintrs = 16; 671#endif /* APIC_IO */ 672 } 673 else { 674 if ((cth = mpfps->pap) == 0) 675 panic("MP Configuration Table Header MISSING!"); 676 677 cpu_apic_address = (vm_offset_t) cth->apic_address; 678 679 /* walk the table, recording info of interest */ 680 totalSize = cth->base_table_length - sizeof(struct MPCTH); 681 position = (u_char *) cth + sizeof(struct MPCTH); 682 count = cth->entry_count; 683 684 while (count--) { 685 switch (type = *(u_char *) position) { 686 case 0: /* processor_entry */ 687 if (((proc_entry_ptr)position)->cpu_flags 688 & PROCENTRY_FLAG_EN) 689 ++mp_naps; 690 break; 691 case 1: /* bus_entry */ 692 ++mp_nbusses; 693 break; 694 case 2: /* io_apic_entry */ 695 if (((io_apic_entry_ptr)position)->apic_flags 696 & IOAPICENTRY_FLAG_EN) 697 io_apic_address[mp_napics++] = 698 (vm_offset_t)((io_apic_entry_ptr) 699 position)->apic_address; 700 break; 701 case 3: /* int_entry */ 702 ++nintrs; 703 break; 704 case 4: /* int_entry */ 705 break; 706 default: 707 panic("mpfps Base Table HOSED!"); 708 /* NOTREACHED */ 709 } 710 711 totalSize -= basetable_entry_types[type].length; 712 (u_char*)position += basetable_entry_types[type].length; 713 } 714 } 715 716 /* qualify the numbers */ 717 if (mp_naps > NCPU) 718 printf("Warning: only using %d of %d available CPUs!\n", 719 NCPU, mp_naps); 720#if 0 721 /** XXX we consider this legal now (but should we?) */ 722 mustpanic = 1; 723#endif 724 if (mp_nbusses > NBUS) { 725 printf("found %d busses, increase NBUS\n", mp_nbusses); 726 mustpanic = 1; 727 } 728 if (mp_napics > NAPIC) { 729 printf("found %d apics, increase NAPIC\n", mp_napics); 730 mustpanic = 1; 731 } 732 if (nintrs > NINTR) { 733 printf("found %d intrs, increase NINTR\n", nintrs); 734 mustpanic = 1; 735 } 736 737 /* 738 * Count the BSP. 739 * This is also used as a counter while starting the APs. 740 */ 741 mp_ncpus = 1; 742 743 --mp_naps; /* subtract the BSP */ 744 745 return mustpanic; 746} 747 748 749/* 750 * 2nd pass on motherboard's Intel MP specification table. 751 * 752 * sets: 753 * boot_cpu_id 754 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 755 * CPU_TO_ID(N), logical CPU to APIC ID table 756 * IO_TO_ID(N), logical IO to APIC ID table 757 * bus_data[N] 758 * io_apic_ints[N] 759 */ 760static int 761mptable_pass2(void) 762{ 763 int x; 764 mpcth_t cth; 765 int totalSize; 766 void* position; 767 int count; 768 int type; 769 int apic, bus, cpu, intr; 770 771 POSTCODE(MPTABLE_PASS2_POST); 772 773 /* clear various tables */ 774 for (x = 0; x < NAPICID; ++x) { 775 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 776 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 777 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 778 } 779 780 /* clear bus data table */ 781 for (x = 0; x < NBUS; ++x) 782 bus_data[x].bus_id = 0xff; 783 784 /* clear IO APIC INT table */ 785 for (x = 0; x < NINTR; ++x) 786 io_apic_ints[x].int_type = 0xff; 787 788 /* setup the cpu/apic mapping arrays */ 789 boot_cpu_id = -1; 790 791 /* record whether PIC or virtual-wire mode */ 792 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 793 794 /* check for use of 'default' configuration */ 795#if defined(TEST_DEFAULT_CONFIG) 796 return TEST_DEFAULT_CONFIG; 797#else 798 if (mpfps->mpfb1 != 0) 799 return mpfps->mpfb1; /* return default configuration type */ 800#endif /* TEST_DEFAULT_CONFIG */ 801 802 if ((cth = mpfps->pap) == 0) 803 panic("MP Configuration Table Header MISSING!"); 804 805 /* walk the table, recording info of interest */ 806 totalSize = cth->base_table_length - sizeof(struct MPCTH); 807 position = (u_char *) cth + sizeof(struct MPCTH); 808 count = cth->entry_count; 809 apic = bus = intr = 0; 810 cpu = 1; /* pre-count the BSP */ 811 812 while (count--) { 813 switch (type = *(u_char *) position) { 814 case 0: 815 if (processor_entry(position, cpu)) 816 ++cpu; 817 break; 818 case 1: 819 if (bus_entry(position, bus)) 820 ++bus; 821 break; 822 case 2: 823 if (io_apic_entry(position, apic)) 824 ++apic; 825 break; 826 case 3: 827 if (int_entry(position, intr)) 828 ++intr; 829 break; 830 case 4: 831 /* int_entry(position); */ 832 break; 833 default: 834 panic("mpfps Base Table HOSED!"); 835 /* NOTREACHED */ 836 } 837 838 totalSize -= basetable_entry_types[type].length; 839 (u_char *) position += basetable_entry_types[type].length; 840 } 841 842 if (boot_cpu_id == -1) 843 panic("NO BSP found!"); 844 845 /* post scan cleanup */ 846 fix_mp_table(); 847 848 /* report fact that its NOT a default configuration */ 849 return 0; 850} 851 852 853/* 854 * parse an Intel MP specification table 855 */ 856static void 857fix_mp_table(void) 858{ 859 int x; 860 int id; 861 int bus_0; 862 int bus_pci; 863 int num_pci_bus; 864 865 /* 866 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 867 * did it wrong. The MP spec says that when more than 1 PCI bus 868 * exists the BIOS must begin with bus entries for the PCI bus and use 869 * actual PCI bus numbering. This implies that when only 1 PCI bus 870 * exists the BIOS can choose to ignore this ordering, and indeed many 871 * MP motherboards do ignore it. This causes a problem when the PCI 872 * sub-system makes requests of the MP sub-system based on PCI bus 873 * numbers. So here we look for the situation and renumber the 874 * busses and associated INTs in an effort to "make it right". 875 */ 876 877 /* find bus 0, PCI bus, count the number of PCI busses */ 878 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 879 if (bus_data[x].bus_id == 0) { 880 bus_0 = x; 881 } 882 if (bus_data[x].bus_type == PCI) { 883 ++num_pci_bus; 884 bus_pci = x; 885 } 886 } 887 /* 888 * bus_0 == slot of bus with ID of 0 889 * bus_pci == slot of last PCI bus encountered 890 */ 891 892 /* check the 1 PCI bus case for sanity */ 893 if (num_pci_bus == 1) { 894 895 /* if it is number 0 all is well */ 896 if (bus_data[bus_pci].bus_id == 0) 897 return; 898 899 /* mis-numbered, swap with whichever bus uses slot 0 */ 900 901 /* swap the bus entry types */ 902 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 903 bus_data[bus_0].bus_type = PCI; 904 905 /* swap each relavant INTerrupt entry */ 906 id = bus_data[bus_pci].bus_id; 907 for (x = 0; x < nintrs; ++x) { 908 if (io_apic_ints[x].src_bus_id == id) { 909 io_apic_ints[x].src_bus_id = 0; 910 } 911 else if (io_apic_ints[x].src_bus_id == 0) { 912 io_apic_ints[x].src_bus_id = id; 913 } 914 } 915 } 916 /* sanity check if more than 1 PCI bus */ 917 else if (num_pci_bus > 1) { 918 for (x = 0; x < mp_nbusses; ++x) { 919 if (bus_data[x].bus_type != PCI) 920 continue; 921 if (bus_data[x].bus_id >= num_pci_bus) 922 panic("bad PCI bus numbering"); 923 } 924 } 925} 926 927 928static int 929processor_entry(proc_entry_ptr entry, int cpu) 930{ 931 /* check for usability */ 932 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 933 return 0; 934 935 /* check for BSP flag */ 936 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 937 boot_cpu_id = entry->apic_id; 938 CPU_TO_ID(0) = entry->apic_id; 939 ID_TO_CPU(entry->apic_id) = 0; 940 return 0; /* its already been counted */ 941 } 942 943 /* add another AP to list, if less than max number of CPUs */ 944 else { 945 CPU_TO_ID(cpu) = entry->apic_id; 946 ID_TO_CPU(entry->apic_id) = cpu; 947 return 1; 948 } 949} 950 951 952static int 953bus_entry(bus_entry_ptr entry, int bus) 954{ 955 int x; 956 char c, name[8]; 957 958 /* encode the name into an index */ 959 for (x = 0; x < 6; ++x) { 960 if ((c = entry->bus_type[x]) == ' ') 961 break; 962 name[x] = c; 963 } 964 name[x] = '\0'; 965 966 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 967 panic("unknown bus type: '%s'", name); 968 969 bus_data[bus].bus_id = entry->bus_id; 970 bus_data[bus].bus_type = x; 971 972 return 1; 973} 974 975 976static int 977io_apic_entry(io_apic_entry_ptr entry, int apic) 978{ 979 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 980 return 0; 981 982 IO_TO_ID(apic) = entry->apic_id; 983 ID_TO_IO(entry->apic_id) = apic; 984 985 return 1; 986} 987 988 989static int 990lookup_bus_type(char *name) 991{ 992 int x; 993 994 for (x = 0; x < MAX_BUSTYPE; ++x) 995 if (strcmp(bus_type_table[x].name, name) == 0) 996 return bus_type_table[x].type; 997 998 return UNKNOWN_BUSTYPE; 999} 1000 1001 1002static int 1003int_entry(int_entry_ptr entry, int intr) 1004{ 1005 io_apic_ints[intr].int_type = entry->int_type; 1006 io_apic_ints[intr].int_flags = entry->int_flags; 1007 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1008 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1009 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1010 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1011 1012 return 1; 1013} 1014 1015 1016static int 1017apic_int_is_bus_type(int intr, int bus_type) 1018{ 1019 int bus; 1020 1021 for (bus = 0; bus < mp_nbusses; ++bus) 1022 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1023 && ((int) bus_data[bus].bus_type == bus_type)) 1024 return 1; 1025 1026 return 0; 1027} 1028 1029 1030/* 1031 * Given a traditional ISA INT mask, return an APIC mask. 1032 */ 1033u_int 1034isa_apic_mask(u_int isa_mask) 1035{ 1036 int isa_irq; 1037 int apic_pin; 1038 1039#if defined(SKIP_IRQ15_REDIRECT) 1040 if (isa_mask == (1 << 15)) { 1041 printf("skipping ISA IRQ15 redirect\n"); 1042 return isa_mask; 1043 } 1044#endif /* SKIP_IRQ15_REDIRECT */ 1045 1046 isa_irq = ffs(isa_mask); /* find its bit position */ 1047 if (isa_irq == 0) /* doesn't exist */ 1048 return 0; 1049 --isa_irq; /* make it zero based */ 1050 1051 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1052 if (apic_pin == -1) 1053 return 0; 1054 1055 return (1 << apic_pin); /* convert pin# to a mask */ 1056} 1057 1058 1059/* 1060 * Determine which APIC pin an ISA/EISA INT is attached to. 1061 */ 1062#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1063#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1064 1065#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1066int 1067isa_apic_pin(int isa_irq) 1068{ 1069 int intr; 1070 1071 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1072 if (INTTYPE(intr) == 0) { /* standard INT */ 1073 if (SRCBUSIRQ(intr) == isa_irq) { 1074 if (apic_int_is_bus_type(intr, ISA) || 1075 apic_int_is_bus_type(intr, EISA)) 1076 return INTPIN(intr); /* found */ 1077 } 1078 } 1079 } 1080 return -1; /* NOT found */ 1081} 1082#undef SRCBUSIRQ 1083 1084 1085/* 1086 * Determine which APIC pin a PCI INT is attached to. 1087 */ 1088#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1089#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1090#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1091int 1092pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1093{ 1094 int intr; 1095 1096 --pciInt; /* zero based */ 1097 1098 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1099 if ((INTTYPE(intr) == 0) /* standard INT */ 1100 && (SRCBUSID(intr) == pciBus) 1101 && (SRCBUSDEVICE(intr) == pciDevice) 1102 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1103 if (apic_int_is_bus_type(intr, PCI)) 1104 return INTPIN(intr); /* exact match */ 1105 1106 return -1; /* NOT found */ 1107} 1108#undef SRCBUSLINE 1109#undef SRCBUSDEVICE 1110#undef SRCBUSID 1111 1112#undef INTPIN 1113#undef INTTYPE 1114 1115 1116/* 1117 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1118 * 1119 * XXX FIXME: 1120 * Exactly what this means is unclear at this point. It is a solution 1121 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1122 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1123 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1124 * option. 1125 */ 1126int 1127undirect_isa_irq(int rirq) 1128{ 1129#if defined(READY) 1130 printf("Freeing redirected ISA irq %d.\n", rirq); 1131 /** FIXME: tickle the MB redirector chip */ 1132 return ???; 1133#else 1134 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1135 return 0; 1136#endif /* READY */ 1137} 1138 1139 1140/* 1141 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1142 */ 1143int 1144undirect_pci_irq(int rirq) 1145{ 1146#if defined(READY) 1147 if (bootverbose) 1148 printf("Freeing redirected PCI irq %d.\n", rirq); 1149 1150 /** FIXME: tickle the MB redirector chip */ 1151 return ???; 1152#else 1153 if (bootverbose) 1154 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1155 rirq); 1156 return 0; 1157#endif /* READY */ 1158} 1159 1160 1161/* 1162 * given a bus ID, return: 1163 * the bus type if found 1164 * -1 if NOT found 1165 */ 1166int 1167apic_bus_type(int id) 1168{ 1169 int x; 1170 1171 for (x = 0; x < mp_nbusses; ++x) 1172 if (bus_data[x].bus_id == id) 1173 return bus_data[x].bus_type; 1174 1175 return -1; 1176} 1177 1178 1179/* 1180 * given a LOGICAL APIC# and pin#, return: 1181 * the associated src bus ID if found 1182 * -1 if NOT found 1183 */ 1184int 1185apic_src_bus_id(int apic, int pin) 1186{ 1187 int x; 1188 1189 /* search each of the possible INTerrupt sources */ 1190 for (x = 0; x < nintrs; ++x) 1191 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1192 (pin == io_apic_ints[x].dst_apic_int)) 1193 return (io_apic_ints[x].src_bus_id); 1194 1195 return -1; /* NOT found */ 1196} 1197 1198 1199/* 1200 * given a LOGICAL APIC# and pin#, return: 1201 * the associated src bus IRQ if found 1202 * -1 if NOT found 1203 */ 1204int 1205apic_src_bus_irq(int apic, int pin) 1206{ 1207 int x; 1208 1209 for (x = 0; x < nintrs; x++) 1210 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1211 (pin == io_apic_ints[x].dst_apic_int)) 1212 return (io_apic_ints[x].src_bus_irq); 1213 1214 return -1; /* NOT found */ 1215} 1216 1217 1218/* 1219 * given a LOGICAL APIC# and pin#, return: 1220 * the associated INTerrupt type if found 1221 * -1 if NOT found 1222 */ 1223int 1224apic_int_type(int apic, int pin) 1225{ 1226 int x; 1227 1228 /* search each of the possible INTerrupt sources */ 1229 for (x = 0; x < nintrs; ++x) 1230 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1231 (pin == io_apic_ints[x].dst_apic_int)) 1232 return (io_apic_ints[x].int_type); 1233 1234 return -1; /* NOT found */ 1235} 1236 1237 1238/* 1239 * given a LOGICAL APIC# and pin#, return: 1240 * the associated trigger mode if found 1241 * -1 if NOT found 1242 */ 1243int 1244apic_trigger(int apic, int pin) 1245{ 1246 int x; 1247 1248 /* search each of the possible INTerrupt sources */ 1249 for (x = 0; x < nintrs; ++x) 1250 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1251 (pin == io_apic_ints[x].dst_apic_int)) 1252 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1253 1254 return -1; /* NOT found */ 1255} 1256 1257 1258/* 1259 * given a LOGICAL APIC# and pin#, return: 1260 * the associated 'active' level if found 1261 * -1 if NOT found 1262 */ 1263int 1264apic_polarity(int apic, int pin) 1265{ 1266 int x; 1267 1268 /* search each of the possible INTerrupt sources */ 1269 for (x = 0; x < nintrs; ++x) 1270 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1271 (pin == io_apic_ints[x].dst_apic_int)) 1272 return (io_apic_ints[x].int_flags & 0x03); 1273 1274 return -1; /* NOT found */ 1275} 1276 1277 1278/* 1279 * set data according to MP defaults 1280 * FIXME: probably not complete yet... 1281 */ 1282static void 1283default_mp_table(int type) 1284{ 1285 int ap_cpu_id; 1286#if defined(APIC_IO) 1287 u_int32_t ux; 1288 int io_apic_id; 1289 int pin; 1290#endif /* APIC_IO */ 1291 1292#if 0 1293 printf(" MP default config type: %d\n", type); 1294 switch (type) { 1295 case 1: 1296 printf(" bus: ISA, APIC: 82489DX\n"); 1297 break; 1298 case 2: 1299 printf(" bus: EISA, APIC: 82489DX\n"); 1300 break; 1301 case 3: 1302 printf(" bus: EISA, APIC: 82489DX\n"); 1303 break; 1304 case 4: 1305 printf(" bus: MCA, APIC: 82489DX\n"); 1306 break; 1307 case 5: 1308 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1309 break; 1310 case 6: 1311 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1312 break; 1313 case 7: 1314 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1315 break; 1316 default: 1317 printf(" future type\n"); 1318 break; 1319 /* NOTREACHED */ 1320 } 1321#endif /* 0 */ 1322 1323 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1324 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1325 1326 /* BSP */ 1327 CPU_TO_ID(0) = boot_cpu_id; 1328 ID_TO_CPU(boot_cpu_id) = 0; 1329 1330 /* one and only AP */ 1331 CPU_TO_ID(1) = ap_cpu_id; 1332 ID_TO_CPU(ap_cpu_id) = 1; 1333 1334#if defined(APIC_IO) 1335 /* one and only IO APIC */ 1336 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1337 1338 /* 1339 * sanity check, refer to MP spec section 3.6.6, last paragraph 1340 * necessary as some hardware isn't properly setting up the IO APIC 1341 */ 1342#if defined(REALLY_ANAL_IOAPICID_VALUE) 1343 if (io_apic_id != 2) { 1344#else 1345 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1346#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1347 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1348 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1349 ux |= 0x02000000; /* set it to '2' */ 1350 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1351 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1352 if ((ux & APIC_ID_MASK) != 0x02000000) 1353 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1354 io_apic_id = 2; 1355 } 1356 IO_TO_ID(0) = io_apic_id; 1357 ID_TO_IO(io_apic_id) = 0; 1358#endif /* APIC_IO */ 1359 1360 /* fill out bus entries */ 1361 switch (type) { 1362 case 1: 1363 case 2: 1364 case 3: 1365 case 5: 1366 case 6: 1367 bus_data[0].bus_id = default_data[type - 1][1]; 1368 bus_data[0].bus_type = default_data[type - 1][2]; 1369 bus_data[1].bus_id = default_data[type - 1][3]; 1370 bus_data[1].bus_type = default_data[type - 1][4]; 1371 break; 1372 1373 /* case 4: case 7: MCA NOT supported */ 1374 default: /* illegal/reserved */ 1375 panic("BAD default MP config: %d", type); 1376 /* NOTREACHED */ 1377 } 1378 1379#if defined(APIC_IO) 1380 /* general cases from MP v1.4, table 5-2 */ 1381 for (pin = 0; pin < 16; ++pin) { 1382 io_apic_ints[pin].int_type = 0; 1383 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1384 io_apic_ints[pin].src_bus_id = 0; 1385 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1386 io_apic_ints[pin].dst_apic_id = io_apic_id; 1387 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1388 } 1389 1390 /* special cases from MP v1.4, table 5-2 */ 1391 if (type == 2) { 1392 io_apic_ints[2].int_type = 0xff; /* N/C */ 1393 io_apic_ints[13].int_type = 0xff; /* N/C */ 1394#if !defined(APIC_MIXED_MODE) 1395 /** FIXME: ??? */ 1396 panic("sorry, can't support type 2 default yet"); 1397#endif /* APIC_MIXED_MODE */ 1398 } 1399 else 1400 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1401 1402 if (type == 7) 1403 io_apic_ints[0].int_type = 0xff; /* N/C */ 1404 else 1405 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1406#endif /* APIC_IO */ 1407} 1408 1409 1410/* 1411 * initialize all the SMP locks 1412 */ 1413static void 1414init_locks(void) 1415{ 1416 /* 1417 * Get the initial mp_lock with a count of 1 for the BSP. 1418 * This uses a LOGICAL cpu ID, ie BSP == 0. 1419 */ 1420 mp_lock = 0x00000001; 1421 1422 /* locks the IO APIC and apic_imen accesses */ 1423 s_lock_init(&imen_lock); 1424} 1425 1426 1427/* 1428 * start each AP in our list 1429 */ 1430static int 1431start_all_aps(u_int boot_addr) 1432{ 1433 int x, i; 1434 u_char mpbiosreason; 1435 u_long mpbioswarmvec; 1436 pd_entry_t newptd; 1437 pt_entry_t newpt; 1438 int *newpp; 1439 1440 POSTCODE(START_ALL_APS_POST); 1441 1442 /* initialize BSP's local APIC */ 1443 apic_initialize(); 1444 1445 /* install the AP 1st level boot code */ 1446 install_ap_tramp(boot_addr); 1447 1448 1449 /* save the current value of the warm-start vector */ 1450 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1451 outb(CMOS_REG, BIOS_RESET); 1452 mpbiosreason = inb(CMOS_DATA); 1453 1454 /* record BSP in CPU map */ 1455 all_cpus = 1; 1456 1457 /* start each AP */ 1458 for (x = 1; x <= mp_naps; ++x) { 1459 1460 /* HACK HACK HACK !!! */ 1461 1462 /* alloc new page table directory */ 1463 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1464 1465 /* clone currently active one (ie: IdlePTD) */ 1466 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1467 1468 /* set up 0 -> 4MB P==V mapping for AP boot */ 1469 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1470 1471 /* store PTD for this AP */ 1472 bootPTD = (pd_entry_t)vtophys(newptd); 1473 1474 /* alloc new page table page */ 1475 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1476 1477 /* set the new PTD's private page to point there */ 1478 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1479 1480 /* install self referential entry */ 1481 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1482 1483 /* get a new private data page */ 1484 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1485 1486 /* wire it into the private page table page */ 1487 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1488 1489 /* wire the ptp into itself for access */ 1490 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1491 1492 /* and the local apic */ 1493 newpt[2] = SMP_prvpt[2]; 1494 1495 /* and the IO apic mapping[s] */ 1496 for (i = 16; i < 32; i++) 1497 newpt[i] = SMP_prvpt[i]; 1498 1499 /* prime data page for it to use */ 1500 newpp[0] = x; /* cpuid */ 1501 newpp[1] = 0; /* curproc */ 1502 newpp[2] = 0; /* curpcb */ 1503 newpp[3] = 0; /* npxproc */ 1504 newpp[4] = 0; /* runtime.tv_sec */ 1505 newpp[5] = 0; /* runtime.tv_usec */ 1506 newpp[6] = x << 24; /* cpu_lockid */ 1507 1508 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1509 1510 /* END REVOLTING HACKERY */ 1511 1512 /* setup a vector to our boot code */ 1513 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1514 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1515 outb(CMOS_REG, BIOS_RESET); 1516 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1517 1518 /* attempt to start the Application Processor */ 1519 CHECK_INIT(99); /* setup checkpoints */ 1520 if (!start_ap(x, boot_addr)) { 1521 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1522 CHECK_PRINT("trace"); /* show checkpoints */ 1523 /* better panic as the AP may be running loose */ 1524 printf("panic y/n? [y] "); 1525 if (cngetc() != 'n') 1526 panic("bye-bye"); 1527 } 1528 CHECK_PRINT("trace"); /* show checkpoints */ 1529 1530 /* record its version info */ 1531 cpu_apic_versions[x] = cpu_apic_versions[0]; 1532 1533 all_cpus |= (1 << x); /* record AP in CPU map */ 1534 } 1535 1536 /* build our map of 'other' CPUs */ 1537 other_cpus = all_cpus & ~(1 << cpuid); 1538 1539 /* fill in our (BSP) APIC version */ 1540 cpu_apic_versions[0] = lapic.version; 1541 1542 /* restore the warmstart vector */ 1543 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1544 outb(CMOS_REG, BIOS_RESET); 1545 outb(CMOS_DATA, mpbiosreason); 1546 1547 pmap_set_opt_bsp(); 1548 1549 /* number of APs actually started */ 1550 return mp_ncpus - 1; 1551} 1552 1553 1554/* 1555 * load the 1st level AP boot code into base memory. 1556 */ 1557 1558/* targets for relocation */ 1559extern void bigJump(void); 1560extern void bootCodeSeg(void); 1561extern void bootDataSeg(void); 1562extern void MPentry(void); 1563extern u_int MP_GDT; 1564extern u_int mp_gdtbase; 1565 1566static void 1567install_ap_tramp(u_int boot_addr) 1568{ 1569 int x; 1570 int size = *(int *) ((u_long) & bootMP_size); 1571 u_char *src = (u_char *) ((u_long) bootMP); 1572 u_char *dst = (u_char *) boot_addr + KERNBASE; 1573 u_int boot_base = (u_int) bootMP; 1574 u_int8_t *dst8; 1575 u_int16_t *dst16; 1576 u_int32_t *dst32; 1577 1578 POSTCODE(INSTALL_AP_TRAMP_POST); 1579 1580 for (x = 0; x < size; ++x) 1581 *dst++ = *src++; 1582 1583 /* 1584 * modify addresses in code we just moved to basemem. unfortunately we 1585 * need fairly detailed info about mpboot.s for this to work. changes 1586 * to mpboot.s might require changes here. 1587 */ 1588 1589 /* boot code is located in KERNEL space */ 1590 dst = (u_char *) boot_addr + KERNBASE; 1591 1592 /* modify the lgdt arg */ 1593 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1594 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1595 1596 /* modify the ljmp target for MPentry() */ 1597 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1598 *dst32 = ((u_int) MPentry - KERNBASE); 1599 1600 /* modify the target for boot code segment */ 1601 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1602 dst8 = (u_int8_t *) (dst16 + 1); 1603 *dst16 = (u_int) boot_addr & 0xffff; 1604 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1605 1606 /* modify the target for boot data segment */ 1607 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1608 dst8 = (u_int8_t *) (dst16 + 1); 1609 *dst16 = (u_int) boot_addr & 0xffff; 1610 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1611} 1612 1613 1614/* 1615 * this function starts the AP (application processor) identified 1616 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1617 * to accomplish this. This is necessary because of the nuances 1618 * of the different hardware we might encounter. It ain't pretty, 1619 * but it seems to work. 1620 */ 1621static int 1622start_ap(int logical_cpu, u_int boot_addr) 1623{ 1624 int physical_cpu; 1625 int vector; 1626 int cpus; 1627 u_long icr_lo, icr_hi; 1628 1629 POSTCODE(START_AP_POST); 1630 1631 /* get the PHYSICAL APIC ID# */ 1632 physical_cpu = CPU_TO_ID(logical_cpu); 1633 1634 /* calculate the vector */ 1635 vector = (boot_addr >> 12) & 0xff; 1636 1637 /* used as a watchpoint to signal AP startup */ 1638 cpus = mp_ncpus; 1639 1640 /* 1641 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1642 * and running the target CPU. OR this INIT IPI might be latched (P5 1643 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1644 * ignored. 1645 */ 1646 1647 /* setup the address for the target AP */ 1648 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1649 icr_hi |= (physical_cpu << 24); 1650 lapic.icr_hi = icr_hi; 1651 1652 /* do an INIT IPI: assert RESET */ 1653 icr_lo = lapic.icr_lo & 0xfff00000; 1654 lapic.icr_lo = icr_lo | 0x0000c500; 1655 1656 /* wait for pending status end */ 1657 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1658 /* spin */ ; 1659 1660 /* do an INIT IPI: deassert RESET */ 1661 lapic.icr_lo = icr_lo | 0x00008500; 1662 1663 /* wait for pending status end */ 1664 u_sleep(10000); /* wait ~10mS */ 1665 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1666 /* spin */ ; 1667 1668 /* 1669 * next we do a STARTUP IPI: the previous INIT IPI might still be 1670 * latched, (P5 bug) this 1st STARTUP would then terminate 1671 * immediately, and the previously started INIT IPI would continue. OR 1672 * the previous INIT IPI has already run. and this STARTUP IPI will 1673 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1674 * will run. 1675 */ 1676 1677 /* do a STARTUP IPI */ 1678 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1679 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1680 /* spin */ ; 1681 u_sleep(200); /* wait ~200uS */ 1682 1683 /* 1684 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1685 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1686 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1687 * recognized after hardware RESET or INIT IPI. 1688 */ 1689 1690 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1691 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1692 /* spin */ ; 1693 u_sleep(200); /* wait ~200uS */ 1694 1695 /* wait for it to start */ 1696 set_apic_timer(5000000);/* == 5 seconds */ 1697 while (read_apic_timer()) 1698 if (mp_ncpus > cpus) 1699 return 1; /* return SUCCESS */ 1700 1701 return 0; /* return FAILURE */ 1702} 1703 1704 1705/* 1706 * Flush the TLB on all other CPU's 1707 * 1708 * XXX: Needs to handshake and wait for completion before proceding. 1709 */ 1710void 1711smp_invltlb(void) 1712{ 1713#if defined(APIC_IO) 1714 if (smp_active && invltlb_ok) 1715 all_but_self_ipi(XINVLTLB_OFFSET); 1716#endif /* APIC_IO */ 1717} 1718 1719void 1720invlpg(u_int addr) 1721{ 1722 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1723 1724 /* send a message to the other CPUs */ 1725 smp_invltlb(); 1726} 1727 1728void 1729invltlb(void) 1730{ 1731 u_long temp; 1732 1733 /* 1734 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1735 * inlined. 1736 */ 1737 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1738 1739 /* send a message to the other CPUs */ 1740 smp_invltlb(); 1741} 1742 1743 1744/* 1745 * When called the executing CPU will send an IPI to all other CPUs 1746 * requesting that they halt execution. 1747 * 1748 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1749 * 1750 * - Signals all CPUs in map to stop. 1751 * - Waits for each to stop. 1752 * 1753 * Returns: 1754 * -1: error 1755 * 0: NA 1756 * 1: ok 1757 * 1758 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1759 * from executing at same time. 1760 */ 1761int 1762stop_cpus( u_int map ) 1763{ 1764 if (!smp_active) 1765 return 0; 1766 1767 /* send IPI to all CPUs in map */ 1768 stopped_cpus = 0; 1769 1770 /* send the Xcpustop IPI to all CPUs in map */ 1771 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1772 1773 while (stopped_cpus != map) 1774 /* spin */ ; 1775 1776 return 1; 1777} 1778 1779 1780/* 1781 * Called by a CPU to restart stopped CPUs. 1782 * 1783 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1784 * 1785 * - Signals all CPUs in map to restart. 1786 * - Waits for each to restart. 1787 * 1788 * Returns: 1789 * -1: error 1790 * 0: NA 1791 * 1: ok 1792 */ 1793int 1794restart_cpus( u_int map ) 1795{ 1796 if (!smp_active) 1797 return 0; 1798 1799 started_cpus = map; /* signal other cpus to restart */ 1800 1801 while (started_cpus) /* wait for each to clear its bit */ 1802 /* spin */ ; 1803 1804 return 1; 1805} 1806