1295011Sandrew/* 2295011Sandrew * Copyright 2014 Linaro Ltd. 3295011Sandrew * Copyright (C) 2014 ZTE Corporation. 4295011Sandrew * 5295011Sandrew * This program is free software; you can redistribute it and/or modify 6295011Sandrew * it under the terms of the GNU General Public License version 2 as 7295011Sandrew * published by the Free Software Foundation. 8295011Sandrew */ 9295011Sandrew 10295011Sandrew#ifndef __DT_BINDINGS_CLOCK_ZX296702_H 11295011Sandrew#define __DT_BINDINGS_CLOCK_ZX296702_H 12295011Sandrew 13295011Sandrew#define ZX296702_OSC 0 14295011Sandrew#define ZX296702_PLL_A9 1 15295011Sandrew#define ZX296702_PLL_A9_350M 2 16295011Sandrew#define ZX296702_PLL_MAC_1000M 3 17295011Sandrew#define ZX296702_PLL_MAC_333M 4 18295011Sandrew#define ZX296702_PLL_MM0_1188M 5 19295011Sandrew#define ZX296702_PLL_MM0_396M 6 20295011Sandrew#define ZX296702_PLL_MM0_198M 7 21295011Sandrew#define ZX296702_PLL_MM1_108M 8 22295011Sandrew#define ZX296702_PLL_MM1_72M 9 23295011Sandrew#define ZX296702_PLL_MM1_54M 10 24295011Sandrew#define ZX296702_PLL_LSP_104M 11 25295011Sandrew#define ZX296702_PLL_LSP_26M 12 26295011Sandrew#define ZX296702_PLL_AUDIO_294M912 13 27295011Sandrew#define ZX296702_PLL_DDR_266M 14 28295011Sandrew#define ZX296702_CLK_148M5 15 29295011Sandrew#define ZX296702_MATRIX_ACLK 16 30295011Sandrew#define ZX296702_MAIN_HCLK 17 31295011Sandrew#define ZX296702_MAIN_PCLK 18 32295011Sandrew#define ZX296702_CLK_500 19 33295011Sandrew#define ZX296702_CLK_250 20 34295011Sandrew#define ZX296702_CLK_125 21 35295011Sandrew#define ZX296702_CLK_74M25 22 36295011Sandrew#define ZX296702_A9_WCLK 23 37295011Sandrew#define ZX296702_A9_AS1_ACLK_MUX 24 38295011Sandrew#define ZX296702_A9_TRACE_CLKIN_MUX 25 39295011Sandrew#define ZX296702_A9_AS1_ACLK_DIV 26 40295011Sandrew#define ZX296702_CLK_2 27 41295011Sandrew#define ZX296702_CLK_27 28 42295011Sandrew#define ZX296702_DECPPU_ACLK_MUX 29 43295011Sandrew#define ZX296702_PPU_ACLK_MUX 30 44295011Sandrew#define ZX296702_MALI400_ACLK_MUX 31 45295011Sandrew#define ZX296702_VOU_ACLK_MUX 32 46295011Sandrew#define ZX296702_VOU_MAIN_WCLK_MUX 33 47295011Sandrew#define ZX296702_VOU_AUX_WCLK_MUX 34 48295011Sandrew#define ZX296702_VOU_SCALER_WCLK_MUX 35 49295011Sandrew#define ZX296702_R2D_ACLK_MUX 36 50295011Sandrew#define ZX296702_R2D_WCLK_MUX 37 51295011Sandrew#define ZX296702_CLK_50 38 52295011Sandrew#define ZX296702_CLK_25 39 53295011Sandrew#define ZX296702_CLK_12 40 54295011Sandrew#define ZX296702_CLK_16M384 41 55295011Sandrew#define ZX296702_CLK_32K768 42 56295011Sandrew#define ZX296702_SEC_WCLK_DIV 43 57295011Sandrew#define ZX296702_DDR_WCLK_MUX 44 58295011Sandrew#define ZX296702_NAND_WCLK_MUX 45 59295011Sandrew#define ZX296702_LSP_26_WCLK_MUX 46 60295011Sandrew#define ZX296702_A9_AS0_ACLK 47 61295011Sandrew#define ZX296702_A9_AS1_ACLK 48 62295011Sandrew#define ZX296702_A9_TRACE_CLKIN 49 63295011Sandrew#define ZX296702_DECPPU_AXI_M_ACLK 50 64295011Sandrew#define ZX296702_DECPPU_AHB_S_HCLK 51 65295011Sandrew#define ZX296702_PPU_AXI_M_ACLK 52 66295011Sandrew#define ZX296702_PPU_AHB_S_HCLK 53 67295011Sandrew#define ZX296702_VOU_AXI_M_ACLK 54 68295011Sandrew#define ZX296702_VOU_APB_PCLK 55 69295011Sandrew#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 70295011Sandrew#define ZX296702_VOU_AUX_CHANNEL_WCLK 57 71295011Sandrew#define ZX296702_VOU_HDMI_OSCLK_CEC 58 72295011Sandrew#define ZX296702_VOU_SCALER_WCLK 59 73295011Sandrew#define ZX296702_MALI400_AXI_M_ACLK 60 74295011Sandrew#define ZX296702_MALI400_APB_PCLK 61 75295011Sandrew#define ZX296702_R2D_WCLK 62 76295011Sandrew#define ZX296702_R2D_AXI_M_ACLK 63 77295011Sandrew#define ZX296702_R2D_AHB_HCLK 64 78295011Sandrew#define ZX296702_DDR3_AXI_S0_ACLK 65 79295011Sandrew#define ZX296702_DDR3_APB_PCLK 66 80295011Sandrew#define ZX296702_DDR3_WCLK 67 81295011Sandrew#define ZX296702_USB20_0_AHB_HCLK 68 82295011Sandrew#define ZX296702_USB20_0_EXTREFCLK 69 83295011Sandrew#define ZX296702_USB20_1_AHB_HCLK 70 84295011Sandrew#define ZX296702_USB20_1_EXTREFCLK 71 85295011Sandrew#define ZX296702_USB20_2_AHB_HCLK 72 86295011Sandrew#define ZX296702_USB20_2_EXTREFCLK 73 87295011Sandrew#define ZX296702_GMAC_AXI_M_ACLK 74 88295011Sandrew#define ZX296702_GMAC_APB_PCLK 75 89295011Sandrew#define ZX296702_GMAC_125_CLKIN 76 90295011Sandrew#define ZX296702_GMAC_RMII_CLKIN 77 91295011Sandrew#define ZX296702_GMAC_25M_CLK 78 92295011Sandrew#define ZX296702_NANDFLASH_AHB_HCLK 79 93295011Sandrew#define ZX296702_NANDFLASH_WCLK 80 94295011Sandrew#define ZX296702_LSP0_APB_PCLK 81 95295011Sandrew#define ZX296702_LSP0_AHB_HCLK 82 96295011Sandrew#define ZX296702_LSP0_26M_WCLK 83 97295011Sandrew#define ZX296702_LSP0_104M_WCLK 84 98295011Sandrew#define ZX296702_LSP0_16M384_WCLK 85 99295011Sandrew#define ZX296702_LSP1_APB_PCLK 86 100295011Sandrew#define ZX296702_LSP1_26M_WCLK 87 101295011Sandrew#define ZX296702_LSP1_104M_WCLK 88 102295011Sandrew#define ZX296702_LSP1_32K_CLK 89 103295011Sandrew#define ZX296702_AON_HCLK 90 104295011Sandrew#define ZX296702_SYS_CTRL_PCLK 91 105295011Sandrew#define ZX296702_DMA_PCLK 92 106295011Sandrew#define ZX296702_DMA_ACLK 93 107295011Sandrew#define ZX296702_SEC_HCLK 94 108295011Sandrew#define ZX296702_AES_WCLK 95 109295011Sandrew#define ZX296702_DES_WCLK 96 110295011Sandrew#define ZX296702_IRAM_ACLK 97 111295011Sandrew#define ZX296702_IROM_ACLK 98 112295011Sandrew#define ZX296702_BOOT_CTRL_HCLK 99 113295011Sandrew#define ZX296702_EFUSE_CLK_30 100 114295011Sandrew#define ZX296702_VOU_MAIN_CHANNEL_DIV 101 115295011Sandrew#define ZX296702_VOU_AUX_CHANNEL_DIV 102 116295011Sandrew#define ZX296702_VOU_TV_ENC_HD_DIV 103 117295011Sandrew#define ZX296702_VOU_TV_ENC_SD_DIV 104 118295011Sandrew#define ZX296702_VL0_MUX 105 119295011Sandrew#define ZX296702_VL1_MUX 106 120295011Sandrew#define ZX296702_VL2_MUX 107 121295011Sandrew#define ZX296702_GL0_MUX 108 122295011Sandrew#define ZX296702_GL1_MUX 109 123295011Sandrew#define ZX296702_GL2_MUX 110 124295011Sandrew#define ZX296702_WB_MUX 111 125295011Sandrew#define ZX296702_HDMI_MUX 112 126295011Sandrew#define ZX296702_VOU_TV_ENC_HD_MUX 113 127295011Sandrew#define ZX296702_VOU_TV_ENC_SD_MUX 114 128295011Sandrew#define ZX296702_VL0_CLK 115 129295011Sandrew#define ZX296702_VL1_CLK 116 130295011Sandrew#define ZX296702_VL2_CLK 117 131295011Sandrew#define ZX296702_GL0_CLK 118 132295011Sandrew#define ZX296702_GL1_CLK 119 133295011Sandrew#define ZX296702_GL2_CLK 120 134295011Sandrew#define ZX296702_WB_CLK 121 135295011Sandrew#define ZX296702_CL_CLK 122 136295011Sandrew#define ZX296702_MAIN_MIX_CLK 123 137295011Sandrew#define ZX296702_AUX_MIX_CLK 124 138295011Sandrew#define ZX296702_HDMI_CLK 125 139295011Sandrew#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 140295011Sandrew#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 141295011Sandrew#define ZX296702_A9_PERIPHCLK 128 142295011Sandrew#define ZX296702_TOPCLK_END 129 143295011Sandrew 144295011Sandrew#define ZX296702_SDMMC1_WCLK_MUX 0 145295011Sandrew#define ZX296702_SDMMC1_WCLK_DIV 1 146295011Sandrew#define ZX296702_SDMMC1_WCLK 2 147295011Sandrew#define ZX296702_SDMMC1_PCLK 3 148295011Sandrew#define ZX296702_SPDIF0_WCLK_MUX 4 149295011Sandrew#define ZX296702_SPDIF0_WCLK 5 150295011Sandrew#define ZX296702_SPDIF0_PCLK 6 151295011Sandrew#define ZX296702_SPDIF0_DIV 7 152295011Sandrew#define ZX296702_I2S0_WCLK_MUX 8 153295011Sandrew#define ZX296702_I2S0_WCLK 9 154295011Sandrew#define ZX296702_I2S0_PCLK 10 155295011Sandrew#define ZX296702_I2S0_DIV 11 156295011Sandrew#define ZX296702_I2S1_WCLK_MUX 12 157295011Sandrew#define ZX296702_I2S1_WCLK 13 158295011Sandrew#define ZX296702_I2S1_PCLK 14 159295011Sandrew#define ZX296702_I2S1_DIV 15 160295011Sandrew#define ZX296702_I2S2_WCLK_MUX 16 161295011Sandrew#define ZX296702_I2S2_WCLK 17 162295011Sandrew#define ZX296702_I2S2_PCLK 18 163295011Sandrew#define ZX296702_I2S2_DIV 19 164295011Sandrew#define ZX296702_GPIO_CLK 20 165295011Sandrew#define ZX296702_LSP0CLK_END 21 166295011Sandrew 167295011Sandrew#define ZX296702_UART0_WCLK_MUX 0 168295011Sandrew#define ZX296702_UART0_WCLK 1 169295011Sandrew#define ZX296702_UART0_PCLK 2 170295011Sandrew#define ZX296702_UART1_WCLK_MUX 3 171295011Sandrew#define ZX296702_UART1_WCLK 4 172295011Sandrew#define ZX296702_UART1_PCLK 5 173295011Sandrew#define ZX296702_SDMMC0_WCLK_MUX 6 174295011Sandrew#define ZX296702_SDMMC0_WCLK_DIV 7 175295011Sandrew#define ZX296702_SDMMC0_WCLK 8 176295011Sandrew#define ZX296702_SDMMC0_PCLK 9 177295011Sandrew#define ZX296702_SPDIF1_WCLK_MUX 10 178295011Sandrew#define ZX296702_SPDIF1_WCLK 11 179295011Sandrew#define ZX296702_SPDIF1_PCLK 12 180295011Sandrew#define ZX296702_SPDIF1_DIV 13 181295011Sandrew#define ZX296702_LSP1CLK_END 14 182295011Sandrew 183295011Sandrew#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ 184