1262569Simp/* 2262569Simp * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3262569Simp * 4262569Simp * This software is licensed under the terms of the GNU General Public 5262569Simp * License version 2, as published by the Free Software Foundation, and 6262569Simp * may be copied, distributed, and modified under those terms. 7262569Simp * 8262569Simp * This program is distributed in the hope that it will be useful, 9262569Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 10262569Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11262569Simp * GNU General Public License for more details. 12262569Simp */ 13262569Simp 14262569Simp#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H 15262569Simp#define _DT_BINDINGS_CLK_MSM_GCC_8974_H 16262569Simp 17262569Simp#define GPLL0 0 18262569Simp#define GPLL0_VOTE 1 19262569Simp#define CONFIG_NOC_CLK_SRC 2 20262569Simp#define GPLL2 3 21262569Simp#define GPLL2_VOTE 4 22262569Simp#define GPLL3 5 23262569Simp#define GPLL3_VOTE 6 24262569Simp#define PERIPH_NOC_CLK_SRC 7 25262569Simp#define BLSP_UART_SIM_CLK_SRC 8 26262569Simp#define QDSS_TSCTR_CLK_SRC 9 27262569Simp#define BIMC_DDR_CLK_SRC 10 28262569Simp#define SYSTEM_NOC_CLK_SRC 11 29262569Simp#define GPLL1 12 30262569Simp#define GPLL1_VOTE 13 31262569Simp#define RPM_CLK_SRC 14 32262569Simp#define GCC_BIMC_CLK 15 33262569Simp#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 34262569Simp#define KPSS_AHB_CLK_SRC 17 35262569Simp#define QDSS_AT_CLK_SRC 18 36262569Simp#define USB30_MASTER_CLK_SRC 19 37262569Simp#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 38262569Simp#define QDSS_STM_CLK_SRC 21 39262569Simp#define ACC_CLK_SRC 22 40262569Simp#define SEC_CTRL_CLK_SRC 23 41262569Simp#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 42262569Simp#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 43262569Simp#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 44262569Simp#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 45262569Simp#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 46262569Simp#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 47262569Simp#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 48262569Simp#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 49262569Simp#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 50262569Simp#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 51262569Simp#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 52262569Simp#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 53262569Simp#define BLSP1_UART1_APPS_CLK_SRC 36 54262569Simp#define BLSP1_UART2_APPS_CLK_SRC 37 55262569Simp#define BLSP1_UART3_APPS_CLK_SRC 38 56262569Simp#define BLSP1_UART4_APPS_CLK_SRC 39 57262569Simp#define BLSP1_UART5_APPS_CLK_SRC 40 58262569Simp#define BLSP1_UART6_APPS_CLK_SRC 41 59262569Simp#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 60262569Simp#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 61262569Simp#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 62262569Simp#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 63262569Simp#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 64262569Simp#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 65262569Simp#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 66262569Simp#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 67262569Simp#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 68262569Simp#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 69262569Simp#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 70262569Simp#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 71262569Simp#define BLSP2_UART1_APPS_CLK_SRC 54 72262569Simp#define BLSP2_UART2_APPS_CLK_SRC 55 73262569Simp#define BLSP2_UART3_APPS_CLK_SRC 56 74262569Simp#define BLSP2_UART4_APPS_CLK_SRC 57 75262569Simp#define BLSP2_UART5_APPS_CLK_SRC 58 76262569Simp#define BLSP2_UART6_APPS_CLK_SRC 59 77262569Simp#define CE1_CLK_SRC 60 78262569Simp#define CE2_CLK_SRC 61 79262569Simp#define GP1_CLK_SRC 62 80262569Simp#define GP2_CLK_SRC 63 81262569Simp#define GP3_CLK_SRC 64 82262569Simp#define PDM2_CLK_SRC 65 83262569Simp#define QDSS_TRACECLKIN_CLK_SRC 66 84262569Simp#define RBCPR_CLK_SRC 67 85262569Simp#define SDCC1_APPS_CLK_SRC 68 86262569Simp#define SDCC2_APPS_CLK_SRC 69 87262569Simp#define SDCC3_APPS_CLK_SRC 70 88262569Simp#define SDCC4_APPS_CLK_SRC 71 89262569Simp#define SPMI_AHB_CLK_SRC 72 90262569Simp#define SPMI_SER_CLK_SRC 73 91262569Simp#define TSIF_REF_CLK_SRC 74 92262569Simp#define USB30_MOCK_UTMI_CLK_SRC 75 93262569Simp#define USB_HS_SYSTEM_CLK_SRC 76 94262569Simp#define USB_HSIC_CLK_SRC 77 95262569Simp#define USB_HSIC_IO_CAL_CLK_SRC 78 96262569Simp#define USB_HSIC_SYSTEM_CLK_SRC 79 97262569Simp#define GCC_BAM_DMA_AHB_CLK 80 98262569Simp#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 99262569Simp#define GCC_BIMC_CFG_AHB_CLK 82 100262569Simp#define GCC_BIMC_KPSS_AXI_CLK 83 101262569Simp#define GCC_BIMC_SLEEP_CLK 84 102262569Simp#define GCC_BIMC_SYSNOC_AXI_CLK 85 103262569Simp#define GCC_BIMC_XO_CLK 86 104262569Simp#define GCC_BLSP1_AHB_CLK 87 105262569Simp#define GCC_BLSP1_SLEEP_CLK 88 106262569Simp#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 107262569Simp#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 108262569Simp#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 109262569Simp#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 110262569Simp#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 111262569Simp#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 112262569Simp#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 113262569Simp#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 114262569Simp#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 115262569Simp#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 116262569Simp#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 117262569Simp#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 118262569Simp#define GCC_BLSP1_UART1_APPS_CLK 101 119262569Simp#define GCC_BLSP1_UART1_SIM_CLK 102 120262569Simp#define GCC_BLSP1_UART2_APPS_CLK 103 121262569Simp#define GCC_BLSP1_UART2_SIM_CLK 104 122262569Simp#define GCC_BLSP1_UART3_APPS_CLK 105 123262569Simp#define GCC_BLSP1_UART3_SIM_CLK 106 124262569Simp#define GCC_BLSP1_UART4_APPS_CLK 107 125262569Simp#define GCC_BLSP1_UART4_SIM_CLK 108 126262569Simp#define GCC_BLSP1_UART5_APPS_CLK 109 127262569Simp#define GCC_BLSP1_UART5_SIM_CLK 110 128262569Simp#define GCC_BLSP1_UART6_APPS_CLK 111 129262569Simp#define GCC_BLSP1_UART6_SIM_CLK 112 130262569Simp#define GCC_BLSP2_AHB_CLK 113 131262569Simp#define GCC_BLSP2_SLEEP_CLK 114 132262569Simp#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 133262569Simp#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 134262569Simp#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 135262569Simp#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 136262569Simp#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 137262569Simp#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 138262569Simp#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 139262569Simp#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 140262569Simp#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 141262569Simp#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 142262569Simp#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 143262569Simp#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 144262569Simp#define GCC_BLSP2_UART1_APPS_CLK 127 145262569Simp#define GCC_BLSP2_UART1_SIM_CLK 128 146262569Simp#define GCC_BLSP2_UART2_APPS_CLK 129 147262569Simp#define GCC_BLSP2_UART2_SIM_CLK 130 148262569Simp#define GCC_BLSP2_UART3_APPS_CLK 131 149262569Simp#define GCC_BLSP2_UART3_SIM_CLK 132 150262569Simp#define GCC_BLSP2_UART4_APPS_CLK 133 151262569Simp#define GCC_BLSP2_UART4_SIM_CLK 134 152262569Simp#define GCC_BLSP2_UART5_APPS_CLK 135 153262569Simp#define GCC_BLSP2_UART5_SIM_CLK 136 154262569Simp#define GCC_BLSP2_UART6_APPS_CLK 137 155262569Simp#define GCC_BLSP2_UART6_SIM_CLK 138 156262569Simp#define GCC_BOOT_ROM_AHB_CLK 139 157262569Simp#define GCC_CE1_AHB_CLK 140 158262569Simp#define GCC_CE1_AXI_CLK 141 159262569Simp#define GCC_CE1_CLK 142 160262569Simp#define GCC_CE2_AHB_CLK 143 161262569Simp#define GCC_CE2_AXI_CLK 144 162262569Simp#define GCC_CE2_CLK 145 163262569Simp#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 164262569Simp#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 165262569Simp#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 166262569Simp#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 167262569Simp#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 168262569Simp#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 169262569Simp#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 170262569Simp#define GCC_CFG_NOC_AHB_CLK 153 171262569Simp#define GCC_CFG_NOC_DDR_CFG_CLK 154 172262569Simp#define GCC_CFG_NOC_RPM_AHB_CLK 155 173262569Simp#define GCC_BIMC_DDR_CPLL0_CLK 156 174262569Simp#define GCC_BIMC_DDR_CPLL1_CLK 157 175262569Simp#define GCC_DDR_DIM_CFG_CLK 158 176262569Simp#define GCC_DDR_DIM_SLEEP_CLK 159 177262569Simp#define GCC_DEHR_CLK 160 178262569Simp#define GCC_AHB_CLK 161 179262569Simp#define GCC_IM_SLEEP_CLK 162 180262569Simp#define GCC_XO_CLK 163 181262569Simp#define GCC_XO_DIV4_CLK 164 182262569Simp#define GCC_GP1_CLK 165 183262569Simp#define GCC_GP2_CLK 166 184262569Simp#define GCC_GP3_CLK 167 185262569Simp#define GCC_IMEM_AXI_CLK 168 186262569Simp#define GCC_IMEM_CFG_AHB_CLK 169 187262569Simp#define GCC_KPSS_AHB_CLK 170 188262569Simp#define GCC_KPSS_AXI_CLK 171 189262569Simp#define GCC_LPASS_Q6_AXI_CLK 172 190262569Simp#define GCC_MMSS_NOC_AT_CLK 173 191262569Simp#define GCC_MMSS_NOC_CFG_AHB_CLK 174 192262569Simp#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 193262569Simp#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 194262569Simp#define GCC_MPM_AHB_CLK 177 195262569Simp#define GCC_MSG_RAM_AHB_CLK 178 196262569Simp#define GCC_MSS_CFG_AHB_CLK 179 197262569Simp#define GCC_MSS_Q6_BIMC_AXI_CLK 180 198262569Simp#define GCC_NOC_CONF_XPU_AHB_CLK 181 199262569Simp#define GCC_PDM2_CLK 182 200262569Simp#define GCC_PDM_AHB_CLK 183 201262569Simp#define GCC_PDM_XO4_CLK 184 202262569Simp#define GCC_PERIPH_NOC_AHB_CLK 185 203262569Simp#define GCC_PERIPH_NOC_AT_CLK 186 204262569Simp#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 205262569Simp#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 206262569Simp#define GCC_PERIPH_XPU_AHB_CLK 189 207262569Simp#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 208262569Simp#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 209262569Simp#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 210262569Simp#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 211262569Simp#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 212262569Simp#define GCC_PRNG_AHB_CLK 195 213262569Simp#define GCC_QDSS_AT_CLK 196 214262569Simp#define GCC_QDSS_CFG_AHB_CLK 197 215262569Simp#define GCC_QDSS_DAP_AHB_CLK 198 216262569Simp#define GCC_QDSS_DAP_CLK 199 217262569Simp#define GCC_QDSS_ETR_USB_CLK 200 218262569Simp#define GCC_QDSS_STM_CLK 201 219262569Simp#define GCC_QDSS_TRACECLKIN_CLK 202 220262569Simp#define GCC_QDSS_TSCTR_DIV16_CLK 203 221262569Simp#define GCC_QDSS_TSCTR_DIV2_CLK 204 222262569Simp#define GCC_QDSS_TSCTR_DIV3_CLK 205 223262569Simp#define GCC_QDSS_TSCTR_DIV4_CLK 206 224262569Simp#define GCC_QDSS_TSCTR_DIV8_CLK 207 225262569Simp#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 226262569Simp#define GCC_RBCPR_AHB_CLK 209 227262569Simp#define GCC_RBCPR_CLK 210 228262569Simp#define GCC_RPM_BUS_AHB_CLK 211 229262569Simp#define GCC_RPM_PROC_HCLK 212 230262569Simp#define GCC_RPM_SLEEP_CLK 213 231262569Simp#define GCC_RPM_TIMER_CLK 214 232262569Simp#define GCC_SDCC1_AHB_CLK 215 233262569Simp#define GCC_SDCC1_APPS_CLK 216 234262569Simp#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 235262569Simp#define GCC_SDCC2_AHB_CLK 218 236262569Simp#define GCC_SDCC2_APPS_CLK 219 237262569Simp#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 238262569Simp#define GCC_SDCC3_AHB_CLK 221 239262569Simp#define GCC_SDCC3_APPS_CLK 222 240262569Simp#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 241262569Simp#define GCC_SDCC4_AHB_CLK 224 242262569Simp#define GCC_SDCC4_APPS_CLK 225 243262569Simp#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 244262569Simp#define GCC_SEC_CTRL_ACC_CLK 227 245262569Simp#define GCC_SEC_CTRL_AHB_CLK 228 246262569Simp#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 247262569Simp#define GCC_SEC_CTRL_CLK 230 248262569Simp#define GCC_SEC_CTRL_SENSE_CLK 231 249262569Simp#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 250262569Simp#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 251262569Simp#define GCC_SPDM_BIMC_CY_CLK 234 252262569Simp#define GCC_SPDM_CFG_AHB_CLK 235 253262569Simp#define GCC_SPDM_DEBUG_CY_CLK 236 254262569Simp#define GCC_SPDM_FF_CLK 237 255262569Simp#define GCC_SPDM_MSTR_AHB_CLK 238 256262569Simp#define GCC_SPDM_PNOC_CY_CLK 239 257262569Simp#define GCC_SPDM_RPM_CY_CLK 240 258262569Simp#define GCC_SPDM_SNOC_CY_CLK 241 259262569Simp#define GCC_SPMI_AHB_CLK 242 260262569Simp#define GCC_SPMI_CNOC_AHB_CLK 243 261262569Simp#define GCC_SPMI_SER_CLK 244 262262569Simp#define GCC_SNOC_CNOC_AHB_CLK 245 263262569Simp#define GCC_SNOC_PNOC_AHB_CLK 246 264262569Simp#define GCC_SYS_NOC_AT_CLK 247 265262569Simp#define GCC_SYS_NOC_AXI_CLK 248 266262569Simp#define GCC_SYS_NOC_KPSS_AHB_CLK 249 267262569Simp#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 268262569Simp#define GCC_SYS_NOC_USB3_AXI_CLK 251 269262569Simp#define GCC_TCSR_AHB_CLK 252 270262569Simp#define GCC_TLMM_AHB_CLK 253 271262569Simp#define GCC_TLMM_CLK 254 272262569Simp#define GCC_TSIF_AHB_CLK 255 273262569Simp#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 274262569Simp#define GCC_TSIF_REF_CLK 257 275262569Simp#define GCC_USB2A_PHY_SLEEP_CLK 258 276262569Simp#define GCC_USB2B_PHY_SLEEP_CLK 259 277262569Simp#define GCC_USB30_MASTER_CLK 260 278262569Simp#define GCC_USB30_MOCK_UTMI_CLK 261 279262569Simp#define GCC_USB30_SLEEP_CLK 262 280262569Simp#define GCC_USB_HS_AHB_CLK 263 281262569Simp#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 282262569Simp#define GCC_USB_HS_SYSTEM_CLK 265 283262569Simp#define GCC_USB_HSIC_AHB_CLK 266 284262569Simp#define GCC_USB_HSIC_CLK 267 285262569Simp#define GCC_USB_HSIC_IO_CAL_CLK 268 286262569Simp#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 287262569Simp#define GCC_USB_HSIC_SYSTEM_CLK 270 288262569Simp#define GCC_WCSS_GPLL1_CLK_SRC 271 289262569Simp#define GCC_MMSS_GPLL0_CLK_SRC 272 290262569Simp#define GCC_LPASS_GPLL0_CLK_SRC 273 291262569Simp#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 292262569Simp#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 293262569Simp#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 294262569Simp#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 295262569Simp#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 296262569Simp#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 297262569Simp#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 298262569Simp#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 299262569Simp#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 300262569Simp#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 301262569Simp#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 302262569Simp#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 303262569Simp#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 304262569Simp#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 305262569Simp#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 306262569Simp#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 307262569Simp#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 308262569Simp#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 309262569Simp#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 310262569Simp#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 311262569Simp#define GCC_TLMM_CLK_SLEEP_ENA 294 312262569Simp#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 313262569Simp#define GCC_CE1_CLK_SLEEP_ENA 296 314262569Simp#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 315262569Simp#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 316262569Simp#define GCC_CE2_CLK_SLEEP_ENA 299 317262569Simp#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 318262569Simp#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 319270864Simp#define GPLL4 302 320270864Simp#define GPLL4_VOTE 303 321270864Simp#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 322270864Simp#define GCC_SDCC1_CDCCAL_FF_CLK 305 323262569Simp 324295011Sandrew/* gdscs */ 325295011Sandrew#define USB_HS_HSIC_GDSC 0 326295011Sandrew 327262569Simp#endif 328