1279377Simp#ifndef __DTS_MARVELL_MMP2_CLOCK_H 2279377Simp#define __DTS_MARVELL_MMP2_CLOCK_H 3279377Simp 4279377Simp/* fixed clocks and plls */ 5279377Simp#define MMP2_CLK_CLK32 1 6279377Simp#define MMP2_CLK_VCTCXO 2 7279377Simp#define MMP2_CLK_PLL1 3 8279377Simp#define MMP2_CLK_PLL1_2 8 9279377Simp#define MMP2_CLK_PLL1_4 9 10279377Simp#define MMP2_CLK_PLL1_8 10 11279377Simp#define MMP2_CLK_PLL1_16 11 12279377Simp#define MMP2_CLK_PLL1_3 12 13279377Simp#define MMP2_CLK_PLL1_6 13 14279377Simp#define MMP2_CLK_PLL1_12 14 15279377Simp#define MMP2_CLK_PLL1_20 15 16279377Simp#define MMP2_CLK_PLL2 16 17279377Simp#define MMP2_CLK_PLL2_2 17 18279377Simp#define MMP2_CLK_PLL2_4 18 19279377Simp#define MMP2_CLK_PLL2_8 19 20279377Simp#define MMP2_CLK_PLL2_16 20 21279377Simp#define MMP2_CLK_PLL2_3 21 22279377Simp#define MMP2_CLK_PLL2_6 22 23279377Simp#define MMP2_CLK_PLL2_12 23 24279377Simp#define MMP2_CLK_VCTCXO_2 24 25279377Simp#define MMP2_CLK_VCTCXO_4 25 26279377Simp#define MMP2_CLK_UART_PLL 26 27279377Simp#define MMP2_CLK_USB_PLL 27 28279377Simp 29279377Simp/* apb periphrals */ 30279377Simp#define MMP2_CLK_TWSI0 60 31279377Simp#define MMP2_CLK_TWSI1 61 32279377Simp#define MMP2_CLK_TWSI2 62 33279377Simp#define MMP2_CLK_TWSI3 63 34279377Simp#define MMP2_CLK_TWSI4 64 35279377Simp#define MMP2_CLK_TWSI5 65 36279377Simp#define MMP2_CLK_GPIO 66 37279377Simp#define MMP2_CLK_KPC 67 38279377Simp#define MMP2_CLK_RTC 68 39279377Simp#define MMP2_CLK_PWM0 69 40279377Simp#define MMP2_CLK_PWM1 70 41279377Simp#define MMP2_CLK_PWM2 71 42279377Simp#define MMP2_CLK_PWM3 72 43279377Simp#define MMP2_CLK_UART0 73 44279377Simp#define MMP2_CLK_UART1 74 45279377Simp#define MMP2_CLK_UART2 75 46279377Simp#define MMP2_CLK_UART3 76 47279377Simp#define MMP2_CLK_SSP0 77 48279377Simp#define MMP2_CLK_SSP1 78 49279377Simp#define MMP2_CLK_SSP2 79 50279377Simp#define MMP2_CLK_SSP3 80 51295011Sandrew#define MMP2_CLK_TIMER 81 52279377Simp 53279377Simp/* axi periphrals */ 54279377Simp#define MMP2_CLK_SDH0 101 55279377Simp#define MMP2_CLK_SDH1 102 56279377Simp#define MMP2_CLK_SDH2 103 57279377Simp#define MMP2_CLK_SDH3 104 58279377Simp#define MMP2_CLK_USB 105 59279377Simp#define MMP2_CLK_DISP0 106 60279377Simp#define MMP2_CLK_DISP0_MUX 107 61279377Simp#define MMP2_CLK_DISP0_SPHY 108 62279377Simp#define MMP2_CLK_DISP1 109 63279377Simp#define MMP2_CLK_DISP1_MUX 110 64279377Simp#define MMP2_CLK_CCIC_ARBITER 111 65279377Simp#define MMP2_CLK_CCIC0 112 66279377Simp#define MMP2_CLK_CCIC0_MIX 113 67279377Simp#define MMP2_CLK_CCIC0_PHY 114 68279377Simp#define MMP2_CLK_CCIC0_SPHY 115 69279377Simp#define MMP2_CLK_CCIC1 116 70279377Simp#define MMP2_CLK_CCIC1_MIX 117 71279377Simp#define MMP2_CLK_CCIC1_PHY 118 72279377Simp#define MMP2_CLK_CCIC1_SPHY 119 73279377Simp 74279377Simp#define MMP2_NR_CLKS 200 75279377Simp#endif 76