exynos3250.h revision 270866
1270866Simp/* 2270866Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3270866Simp * Author: Tomasz Figa <t.figa@samsung.com> 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify 6270866Simp * it under the terms of the GNU General Public License version 2 as 7270866Simp * published by the Free Software Foundation. 8270866Simp * 9270866Simp * Device Tree binding constants for Samsung Exynos3250 clock controllers. 10270866Simp */ 11270866Simp 12270866Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 13270866Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 14270866Simp 15270866Simp/* 16270866Simp * Let each exported clock get a unique index, which is used on DT-enabled 17270866Simp * platforms to lookup the clock from a clock specifier. These indices are 18270866Simp * therefore considered an ABI and so must not be changed. This implies 19270866Simp * that new clocks should be added either in free spaces between clock groups 20270866Simp * or at the end. 21270866Simp */ 22270866Simp 23270866Simp 24270866Simp/* 25270866Simp * Main CMU 26270866Simp */ 27270866Simp 28270866Simp#define CLK_OSCSEL 1 29270866Simp#define CLK_FIN_PLL 2 30270866Simp#define CLK_FOUT_APLL 3 31270866Simp#define CLK_FOUT_VPLL 4 32270866Simp#define CLK_FOUT_UPLL 5 33270866Simp#define CLK_FOUT_MPLL 6 34270866Simp 35270866Simp/* Muxes */ 36270866Simp#define CLK_MOUT_MPLL_USER_L 16 37270866Simp#define CLK_MOUT_GDL 17 38270866Simp#define CLK_MOUT_MPLL_USER_R 18 39270866Simp#define CLK_MOUT_GDR 19 40270866Simp#define CLK_MOUT_EBI 20 41270866Simp#define CLK_MOUT_ACLK_200 21 42270866Simp#define CLK_MOUT_ACLK_160 22 43270866Simp#define CLK_MOUT_ACLK_100 23 44270866Simp#define CLK_MOUT_ACLK_266_1 24 45270866Simp#define CLK_MOUT_ACLK_266_0 25 46270866Simp#define CLK_MOUT_ACLK_266 26 47270866Simp#define CLK_MOUT_VPLL 27 48270866Simp#define CLK_MOUT_EPLL_USER 28 49270866Simp#define CLK_MOUT_EBI_1 29 50270866Simp#define CLK_MOUT_UPLL 30 51270866Simp#define CLK_MOUT_ACLK_400_MCUISP_SUB 31 52270866Simp#define CLK_MOUT_MPLL 32 53270866Simp#define CLK_MOUT_ACLK_400_MCUISP 33 54270866Simp#define CLK_MOUT_VPLLSRC 34 55270866Simp#define CLK_MOUT_CAM1 35 56270866Simp#define CLK_MOUT_CAM_BLK 36 57270866Simp#define CLK_MOUT_MFC 37 58270866Simp#define CLK_MOUT_MFC_1 38 59270866Simp#define CLK_MOUT_MFC_0 39 60270866Simp#define CLK_MOUT_G3D 40 61270866Simp#define CLK_MOUT_G3D_1 41 62270866Simp#define CLK_MOUT_G3D_0 42 63270866Simp#define CLK_MOUT_MIPI0 43 64270866Simp#define CLK_MOUT_FIMD0 44 65270866Simp#define CLK_MOUT_UART_ISP 45 66270866Simp#define CLK_MOUT_SPI1_ISP 46 67270866Simp#define CLK_MOUT_SPI0_ISP 47 68270866Simp#define CLK_MOUT_TSADC 48 69270866Simp#define CLK_MOUT_MMC1 49 70270866Simp#define CLK_MOUT_MMC0 50 71270866Simp#define CLK_MOUT_UART1 51 72270866Simp#define CLK_MOUT_UART0 52 73270866Simp#define CLK_MOUT_SPI1 53 74270866Simp#define CLK_MOUT_SPI0 54 75270866Simp#define CLK_MOUT_AUDIO 55 76270866Simp#define CLK_MOUT_MPLL_USER_C 56 77270866Simp#define CLK_MOUT_HPM 57 78270866Simp#define CLK_MOUT_CORE 58 79270866Simp#define CLK_MOUT_APLL 59 80270866Simp#define CLK_MOUT_ACLK_266_SUB 60 81270866Simp 82270866Simp/* Dividers */ 83270866Simp#define CLK_DIV_GPL 64 84270866Simp#define CLK_DIV_GDL 65 85270866Simp#define CLK_DIV_GPR 66 86270866Simp#define CLK_DIV_GDR 67 87270866Simp#define CLK_DIV_MPLL_PRE 68 88270866Simp#define CLK_DIV_ACLK_400_MCUISP 69 89270866Simp#define CLK_DIV_EBI 70 90270866Simp#define CLK_DIV_ACLK_200 71 91270866Simp#define CLK_DIV_ACLK_160 72 92270866Simp#define CLK_DIV_ACLK_100 73 93270866Simp#define CLK_DIV_ACLK_266 74 94270866Simp#define CLK_DIV_CAM1 75 95270866Simp#define CLK_DIV_CAM_BLK 76 96270866Simp#define CLK_DIV_MFC 77 97270866Simp#define CLK_DIV_G3D 78 98270866Simp#define CLK_DIV_MIPI0_PRE 79 99270866Simp#define CLK_DIV_MIPI0 80 100270866Simp#define CLK_DIV_FIMD0 81 101270866Simp#define CLK_DIV_UART_ISP 82 102270866Simp#define CLK_DIV_SPI1_ISP_PRE 83 103270866Simp#define CLK_DIV_SPI1_ISP 84 104270866Simp#define CLK_DIV_SPI0_ISP_PRE 85 105270866Simp#define CLK_DIV_SPI0_ISP 86 106270866Simp#define CLK_DIV_TSADC_PRE 87 107270866Simp#define CLK_DIV_TSADC 88 108270866Simp#define CLK_DIV_MMC1_PRE 89 109270866Simp#define CLK_DIV_MMC1 90 110270866Simp#define CLK_DIV_MMC0_PRE 91 111270866Simp#define CLK_DIV_MMC0 92 112270866Simp#define CLK_DIV_UART1 93 113270866Simp#define CLK_DIV_UART0 94 114270866Simp#define CLK_DIV_SPI1_PRE 95 115270866Simp#define CLK_DIV_SPI1 96 116270866Simp#define CLK_DIV_SPI0_PRE 97 117270866Simp#define CLK_DIV_SPI0 98 118270866Simp#define CLK_DIV_PCM 99 119270866Simp#define CLK_DIV_AUDIO 100 120270866Simp#define CLK_DIV_I2S 101 121270866Simp#define CLK_DIV_CORE2 102 122270866Simp#define CLK_DIV_APLL 103 123270866Simp#define CLK_DIV_PCLK_DBG 104 124270866Simp#define CLK_DIV_ATB 105 125270866Simp#define CLK_DIV_COREM 106 126270866Simp#define CLK_DIV_CORE 107 127270866Simp#define CLK_DIV_HPM 108 128270866Simp#define CLK_DIV_COPY 109 129270866Simp 130270866Simp/* Gates */ 131270866Simp#define CLK_ASYNC_G3D 128 132270866Simp#define CLK_ASYNC_MFCL 129 133270866Simp#define CLK_PPMULEFT 130 134270866Simp#define CLK_GPIO_LEFT 131 135270866Simp#define CLK_ASYNC_ISPMX 132 136270866Simp#define CLK_ASYNC_FSYSD 133 137270866Simp#define CLK_ASYNC_LCD0X 134 138270866Simp#define CLK_ASYNC_CAMX 135 139270866Simp#define CLK_PPMURIGHT 136 140270866Simp#define CLK_GPIO_RIGHT 137 141270866Simp#define CLK_MONOCNT 138 142270866Simp#define CLK_TZPC6 139 143270866Simp#define CLK_PROVISIONKEY1 140 144270866Simp#define CLK_PROVISIONKEY0 141 145270866Simp#define CLK_CMU_ISPPART 142 146270866Simp#define CLK_TMU_APBIF 143 147270866Simp#define CLK_KEYIF 144 148270866Simp#define CLK_RTC 145 149270866Simp#define CLK_WDT 146 150270866Simp#define CLK_MCT 147 151270866Simp#define CLK_SECKEY 148 152270866Simp#define CLK_TZPC5 149 153270866Simp#define CLK_TZPC4 150 154270866Simp#define CLK_TZPC3 151 155270866Simp#define CLK_TZPC2 152 156270866Simp#define CLK_TZPC1 153 157270866Simp#define CLK_TZPC0 154 158270866Simp#define CLK_CMU_COREPART 155 159270866Simp#define CLK_CMU_TOPPART 156 160270866Simp#define CLK_PMU_APBIF 157 161270866Simp#define CLK_SYSREG 158 162270866Simp#define CLK_CHIP_ID 159 163270866Simp#define CLK_QEJPEG 160 164270866Simp#define CLK_PIXELASYNCM1 161 165270866Simp#define CLK_PIXELASYNCM0 162 166270866Simp#define CLK_PPMUCAMIF 163 167270866Simp#define CLK_QEM2MSCALER 164 168270866Simp#define CLK_QEGSCALER1 165 169270866Simp#define CLK_QEGSCALER0 166 170270866Simp#define CLK_SMMUJPEG 167 171270866Simp#define CLK_SMMUM2M2SCALER 168 172270866Simp#define CLK_SMMUGSCALER1 169 173270866Simp#define CLK_SMMUGSCALER0 170 174270866Simp#define CLK_JPEG 171 175270866Simp#define CLK_M2MSCALER 172 176270866Simp#define CLK_GSCALER1 173 177270866Simp#define CLK_GSCALER0 174 178270866Simp#define CLK_QEMFC 175 179270866Simp#define CLK_PPMUMFC_L 176 180270866Simp#define CLK_SMMUMFC_L 177 181270866Simp#define CLK_MFC 178 182270866Simp#define CLK_SMMUG3D 179 183270866Simp#define CLK_QEG3D 180 184270866Simp#define CLK_PPMUG3D 181 185270866Simp#define CLK_G3D 182 186270866Simp#define CLK_QE_CH1_LCD 183 187270866Simp#define CLK_QE_CH0_LCD 184 188270866Simp#define CLK_PPMULCD0 185 189270866Simp#define CLK_SMMUFIMD0 186 190270866Simp#define CLK_DSIM0 187 191270866Simp#define CLK_FIMD0 188 192270866Simp#define CLK_CAM1 189 193270866Simp#define CLK_UART_ISP_TOP 190 194270866Simp#define CLK_SPI1_ISP_TOP 191 195270866Simp#define CLK_SPI0_ISP_TOP 192 196270866Simp#define CLK_TSADC 193 197270866Simp#define CLK_PPMUFILE 194 198270866Simp#define CLK_USBOTG 195 199270866Simp#define CLK_USBHOST 196 200270866Simp#define CLK_SROMC 197 201270866Simp#define CLK_SDMMC1 198 202270866Simp#define CLK_SDMMC0 199 203270866Simp#define CLK_PDMA1 200 204270866Simp#define CLK_PDMA0 201 205270866Simp#define CLK_PWM 202 206270866Simp#define CLK_PCM 203 207270866Simp#define CLK_I2S 204 208270866Simp#define CLK_SPI1 205 209270866Simp#define CLK_SPI0 206 210270866Simp#define CLK_I2C7 207 211270866Simp#define CLK_I2C6 208 212270866Simp#define CLK_I2C5 209 213270866Simp#define CLK_I2C4 210 214270866Simp#define CLK_I2C3 211 215270866Simp#define CLK_I2C2 212 216270866Simp#define CLK_I2C1 213 217270866Simp#define CLK_I2C0 214 218270866Simp#define CLK_UART1 215 219270866Simp#define CLK_UART0 216 220270866Simp#define CLK_BLOCK_LCD 217 221270866Simp#define CLK_BLOCK_G3D 218 222270866Simp#define CLK_BLOCK_MFC 219 223270866Simp#define CLK_BLOCK_CAM 220 224270866Simp#define CLK_SMIES 221 225270866Simp 226270866Simp/* Special clocks */ 227270866Simp#define CLK_SCLK_JPEG 224 228270866Simp#define CLK_SCLK_M2MSCALER 225 229270866Simp#define CLK_SCLK_GSCALER1 226 230270866Simp#define CLK_SCLK_GSCALER0 227 231270866Simp#define CLK_SCLK_MFC 228 232270866Simp#define CLK_SCLK_G3D 229 233270866Simp#define CLK_SCLK_MIPIDPHY2L 230 234270866Simp#define CLK_SCLK_MIPI0 231 235270866Simp#define CLK_SCLK_FIMD0 232 236270866Simp#define CLK_SCLK_CAM1 233 237270866Simp#define CLK_SCLK_UART_ISP 234 238270866Simp#define CLK_SCLK_SPI1_ISP 235 239270866Simp#define CLK_SCLK_SPI0_ISP 236 240270866Simp#define CLK_SCLK_UPLL 237 241270866Simp#define CLK_SCLK_TSADC 238 242270866Simp#define CLK_SCLK_EBI 239 243270866Simp#define CLK_SCLK_MMC1 240 244270866Simp#define CLK_SCLK_MMC0 241 245270866Simp#define CLK_SCLK_I2S 242 246270866Simp#define CLK_SCLK_PCM 243 247270866Simp#define CLK_SCLK_SPI1 244 248270866Simp#define CLK_SCLK_SPI0 245 249270866Simp#define CLK_SCLK_UART1 246 250270866Simp#define CLK_SCLK_UART0 247 251270866Simp 252270866Simp/* 253270866Simp * Total number of clocks of main CMU. 254270866Simp * NOTE: Must be equal to last clock ID increased by one. 255270866Simp */ 256270866Simp#define CLK_NR_CLKS 248 257270866Simp 258270866Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 259