1270866Simp/* 2270866Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3270866Simp * Author: Tomasz Figa <t.figa@samsung.com> 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify 6270866Simp * it under the terms of the GNU General Public License version 2 as 7270866Simp * published by the Free Software Foundation. 8270866Simp * 9270866Simp * Device Tree binding constants for Samsung Exynos3250 clock controllers. 10270866Simp */ 11270866Simp 12270866Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 13270866Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 14270866Simp 15270866Simp/* 16270866Simp * Let each exported clock get a unique index, which is used on DT-enabled 17270866Simp * platforms to lookup the clock from a clock specifier. These indices are 18270866Simp * therefore considered an ABI and so must not be changed. This implies 19270866Simp * that new clocks should be added either in free spaces between clock groups 20270866Simp * or at the end. 21270866Simp */ 22270866Simp 23270866Simp 24270866Simp/* 25270866Simp * Main CMU 26270866Simp */ 27270866Simp 28270866Simp#define CLK_OSCSEL 1 29270866Simp#define CLK_FIN_PLL 2 30270866Simp#define CLK_FOUT_APLL 3 31270866Simp#define CLK_FOUT_VPLL 4 32270866Simp#define CLK_FOUT_UPLL 5 33270866Simp#define CLK_FOUT_MPLL 6 34295436Sandrew#define CLK_ARM_CLK 7 35270866Simp 36270866Simp/* Muxes */ 37270866Simp#define CLK_MOUT_MPLL_USER_L 16 38270866Simp#define CLK_MOUT_GDL 17 39270866Simp#define CLK_MOUT_MPLL_USER_R 18 40270866Simp#define CLK_MOUT_GDR 19 41270866Simp#define CLK_MOUT_EBI 20 42270866Simp#define CLK_MOUT_ACLK_200 21 43270866Simp#define CLK_MOUT_ACLK_160 22 44270866Simp#define CLK_MOUT_ACLK_100 23 45270866Simp#define CLK_MOUT_ACLK_266_1 24 46270866Simp#define CLK_MOUT_ACLK_266_0 25 47270866Simp#define CLK_MOUT_ACLK_266 26 48270866Simp#define CLK_MOUT_VPLL 27 49270866Simp#define CLK_MOUT_EPLL_USER 28 50270866Simp#define CLK_MOUT_EBI_1 29 51270866Simp#define CLK_MOUT_UPLL 30 52270866Simp#define CLK_MOUT_ACLK_400_MCUISP_SUB 31 53270866Simp#define CLK_MOUT_MPLL 32 54270866Simp#define CLK_MOUT_ACLK_400_MCUISP 33 55270866Simp#define CLK_MOUT_VPLLSRC 34 56270866Simp#define CLK_MOUT_CAM1 35 57270866Simp#define CLK_MOUT_CAM_BLK 36 58270866Simp#define CLK_MOUT_MFC 37 59270866Simp#define CLK_MOUT_MFC_1 38 60270866Simp#define CLK_MOUT_MFC_0 39 61270866Simp#define CLK_MOUT_G3D 40 62270866Simp#define CLK_MOUT_G3D_1 41 63270866Simp#define CLK_MOUT_G3D_0 42 64270866Simp#define CLK_MOUT_MIPI0 43 65270866Simp#define CLK_MOUT_FIMD0 44 66270866Simp#define CLK_MOUT_UART_ISP 45 67270866Simp#define CLK_MOUT_SPI1_ISP 46 68270866Simp#define CLK_MOUT_SPI0_ISP 47 69270866Simp#define CLK_MOUT_TSADC 48 70270866Simp#define CLK_MOUT_MMC1 49 71270866Simp#define CLK_MOUT_MMC0 50 72270866Simp#define CLK_MOUT_UART1 51 73270866Simp#define CLK_MOUT_UART0 52 74270866Simp#define CLK_MOUT_SPI1 53 75270866Simp#define CLK_MOUT_SPI0 54 76270866Simp#define CLK_MOUT_AUDIO 55 77270866Simp#define CLK_MOUT_MPLL_USER_C 56 78270866Simp#define CLK_MOUT_HPM 57 79270866Simp#define CLK_MOUT_CORE 58 80270866Simp#define CLK_MOUT_APLL 59 81270866Simp#define CLK_MOUT_ACLK_266_SUB 60 82270866Simp 83270866Simp/* Dividers */ 84270866Simp#define CLK_DIV_GPL 64 85270866Simp#define CLK_DIV_GDL 65 86270866Simp#define CLK_DIV_GPR 66 87270866Simp#define CLK_DIV_GDR 67 88270866Simp#define CLK_DIV_MPLL_PRE 68 89270866Simp#define CLK_DIV_ACLK_400_MCUISP 69 90270866Simp#define CLK_DIV_EBI 70 91270866Simp#define CLK_DIV_ACLK_200 71 92270866Simp#define CLK_DIV_ACLK_160 72 93270866Simp#define CLK_DIV_ACLK_100 73 94270866Simp#define CLK_DIV_ACLK_266 74 95270866Simp#define CLK_DIV_CAM1 75 96270866Simp#define CLK_DIV_CAM_BLK 76 97270866Simp#define CLK_DIV_MFC 77 98270866Simp#define CLK_DIV_G3D 78 99270866Simp#define CLK_DIV_MIPI0_PRE 79 100270866Simp#define CLK_DIV_MIPI0 80 101270866Simp#define CLK_DIV_FIMD0 81 102270866Simp#define CLK_DIV_UART_ISP 82 103270866Simp#define CLK_DIV_SPI1_ISP_PRE 83 104270866Simp#define CLK_DIV_SPI1_ISP 84 105270866Simp#define CLK_DIV_SPI0_ISP_PRE 85 106270866Simp#define CLK_DIV_SPI0_ISP 86 107270866Simp#define CLK_DIV_TSADC_PRE 87 108270866Simp#define CLK_DIV_TSADC 88 109270866Simp#define CLK_DIV_MMC1_PRE 89 110270866Simp#define CLK_DIV_MMC1 90 111270866Simp#define CLK_DIV_MMC0_PRE 91 112270866Simp#define CLK_DIV_MMC0 92 113270866Simp#define CLK_DIV_UART1 93 114270866Simp#define CLK_DIV_UART0 94 115270866Simp#define CLK_DIV_SPI1_PRE 95 116270866Simp#define CLK_DIV_SPI1 96 117270866Simp#define CLK_DIV_SPI0_PRE 97 118270866Simp#define CLK_DIV_SPI0 98 119270866Simp#define CLK_DIV_PCM 99 120270866Simp#define CLK_DIV_AUDIO 100 121270866Simp#define CLK_DIV_I2S 101 122270866Simp#define CLK_DIV_CORE2 102 123270866Simp#define CLK_DIV_APLL 103 124270866Simp#define CLK_DIV_PCLK_DBG 104 125270866Simp#define CLK_DIV_ATB 105 126270866Simp#define CLK_DIV_COREM 106 127270866Simp#define CLK_DIV_CORE 107 128270866Simp#define CLK_DIV_HPM 108 129270866Simp#define CLK_DIV_COPY 109 130270866Simp 131270866Simp/* Gates */ 132270866Simp#define CLK_ASYNC_G3D 128 133270866Simp#define CLK_ASYNC_MFCL 129 134270866Simp#define CLK_PPMULEFT 130 135270866Simp#define CLK_GPIO_LEFT 131 136270866Simp#define CLK_ASYNC_ISPMX 132 137270866Simp#define CLK_ASYNC_FSYSD 133 138270866Simp#define CLK_ASYNC_LCD0X 134 139270866Simp#define CLK_ASYNC_CAMX 135 140270866Simp#define CLK_PPMURIGHT 136 141270866Simp#define CLK_GPIO_RIGHT 137 142270866Simp#define CLK_MONOCNT 138 143270866Simp#define CLK_TZPC6 139 144270866Simp#define CLK_PROVISIONKEY1 140 145270866Simp#define CLK_PROVISIONKEY0 141 146270866Simp#define CLK_CMU_ISPPART 142 147270866Simp#define CLK_TMU_APBIF 143 148270866Simp#define CLK_KEYIF 144 149270866Simp#define CLK_RTC 145 150270866Simp#define CLK_WDT 146 151270866Simp#define CLK_MCT 147 152270866Simp#define CLK_SECKEY 148 153270866Simp#define CLK_TZPC5 149 154270866Simp#define CLK_TZPC4 150 155270866Simp#define CLK_TZPC3 151 156270866Simp#define CLK_TZPC2 152 157270866Simp#define CLK_TZPC1 153 158270866Simp#define CLK_TZPC0 154 159270866Simp#define CLK_CMU_COREPART 155 160270866Simp#define CLK_CMU_TOPPART 156 161270866Simp#define CLK_PMU_APBIF 157 162270866Simp#define CLK_SYSREG 158 163270866Simp#define CLK_CHIP_ID 159 164270866Simp#define CLK_QEJPEG 160 165270866Simp#define CLK_PIXELASYNCM1 161 166270866Simp#define CLK_PIXELASYNCM0 162 167270866Simp#define CLK_PPMUCAMIF 163 168270866Simp#define CLK_QEM2MSCALER 164 169270866Simp#define CLK_QEGSCALER1 165 170270866Simp#define CLK_QEGSCALER0 166 171270866Simp#define CLK_SMMUJPEG 167 172270866Simp#define CLK_SMMUM2M2SCALER 168 173270866Simp#define CLK_SMMUGSCALER1 169 174270866Simp#define CLK_SMMUGSCALER0 170 175270866Simp#define CLK_JPEG 171 176270866Simp#define CLK_M2MSCALER 172 177270866Simp#define CLK_GSCALER1 173 178270866Simp#define CLK_GSCALER0 174 179270866Simp#define CLK_QEMFC 175 180270866Simp#define CLK_PPMUMFC_L 176 181270866Simp#define CLK_SMMUMFC_L 177 182270866Simp#define CLK_MFC 178 183270866Simp#define CLK_SMMUG3D 179 184270866Simp#define CLK_QEG3D 180 185270866Simp#define CLK_PPMUG3D 181 186270866Simp#define CLK_G3D 182 187270866Simp#define CLK_QE_CH1_LCD 183 188270866Simp#define CLK_QE_CH0_LCD 184 189270866Simp#define CLK_PPMULCD0 185 190270866Simp#define CLK_SMMUFIMD0 186 191270866Simp#define CLK_DSIM0 187 192270866Simp#define CLK_FIMD0 188 193270866Simp#define CLK_CAM1 189 194270866Simp#define CLK_UART_ISP_TOP 190 195270866Simp#define CLK_SPI1_ISP_TOP 191 196270866Simp#define CLK_SPI0_ISP_TOP 192 197270866Simp#define CLK_TSADC 193 198270866Simp#define CLK_PPMUFILE 194 199270866Simp#define CLK_USBOTG 195 200270866Simp#define CLK_USBHOST 196 201270866Simp#define CLK_SROMC 197 202270866Simp#define CLK_SDMMC1 198 203270866Simp#define CLK_SDMMC0 199 204270866Simp#define CLK_PDMA1 200 205270866Simp#define CLK_PDMA0 201 206270866Simp#define CLK_PWM 202 207270866Simp#define CLK_PCM 203 208270866Simp#define CLK_I2S 204 209270866Simp#define CLK_SPI1 205 210270866Simp#define CLK_SPI0 206 211270866Simp#define CLK_I2C7 207 212270866Simp#define CLK_I2C6 208 213270866Simp#define CLK_I2C5 209 214270866Simp#define CLK_I2C4 210 215270866Simp#define CLK_I2C3 211 216270866Simp#define CLK_I2C2 212 217270866Simp#define CLK_I2C1 213 218270866Simp#define CLK_I2C0 214 219270866Simp#define CLK_UART1 215 220270866Simp#define CLK_UART0 216 221270866Simp#define CLK_BLOCK_LCD 217 222270866Simp#define CLK_BLOCK_G3D 218 223270866Simp#define CLK_BLOCK_MFC 219 224270866Simp#define CLK_BLOCK_CAM 220 225270866Simp#define CLK_SMIES 221 226270866Simp 227270866Simp/* Special clocks */ 228270866Simp#define CLK_SCLK_JPEG 224 229270866Simp#define CLK_SCLK_M2MSCALER 225 230270866Simp#define CLK_SCLK_GSCALER1 226 231270866Simp#define CLK_SCLK_GSCALER0 227 232270866Simp#define CLK_SCLK_MFC 228 233270866Simp#define CLK_SCLK_G3D 229 234270866Simp#define CLK_SCLK_MIPIDPHY2L 230 235270866Simp#define CLK_SCLK_MIPI0 231 236270866Simp#define CLK_SCLK_FIMD0 232 237270866Simp#define CLK_SCLK_CAM1 233 238270866Simp#define CLK_SCLK_UART_ISP 234 239270866Simp#define CLK_SCLK_SPI1_ISP 235 240270866Simp#define CLK_SCLK_SPI0_ISP 236 241270866Simp#define CLK_SCLK_UPLL 237 242270866Simp#define CLK_SCLK_TSADC 238 243270866Simp#define CLK_SCLK_EBI 239 244270866Simp#define CLK_SCLK_MMC1 240 245270866Simp#define CLK_SCLK_MMC0 241 246270866Simp#define CLK_SCLK_I2S 242 247270866Simp#define CLK_SCLK_PCM 243 248270866Simp#define CLK_SCLK_SPI1 244 249270866Simp#define CLK_SCLK_SPI0 245 250270866Simp#define CLK_SCLK_UART1 246 251270866Simp#define CLK_SCLK_UART0 247 252270866Simp 253270866Simp/* 254270866Simp * Total number of clocks of main CMU. 255270866Simp * NOTE: Must be equal to last clock ID increased by one. 256270866Simp */ 257270866Simp#define CLK_NR_CLKS 248 258270866Simp 259279385Simp/* 260279385Simp * CMU DMC 261279385Simp */ 262279385Simp 263279385Simp#define CLK_FOUT_BPLL 1 264279385Simp#define CLK_FOUT_EPLL 2 265279385Simp 266279385Simp/* Muxes */ 267279385Simp#define CLK_MOUT_MPLL_MIF 8 268279385Simp#define CLK_MOUT_BPLL 9 269279385Simp#define CLK_MOUT_DPHY 10 270279385Simp#define CLK_MOUT_DMC_BUS 11 271279385Simp#define CLK_MOUT_EPLL 12 272279385Simp 273279385Simp/* Dividers */ 274279385Simp#define CLK_DIV_DMC 16 275279385Simp#define CLK_DIV_DPHY 17 276279385Simp#define CLK_DIV_DMC_PRE 18 277279385Simp#define CLK_DIV_DMCP 19 278279385Simp#define CLK_DIV_DMCD 20 279279385Simp 280279385Simp/* 281279385Simp * Total number of clocks of main CMU. 282279385Simp * NOTE: Must be equal to last clock ID increased by one. 283279385Simp */ 284279385Simp#define NR_CLKS_DMC 21 285279385Simp 286295436Sandrew/* 287295436Sandrew * CMU ISP 288295436Sandrew */ 289295436Sandrew 290295436Sandrew/* Dividers */ 291295436Sandrew 292295436Sandrew#define CLK_DIV_ISP1 1 293295436Sandrew#define CLK_DIV_ISP0 2 294295436Sandrew#define CLK_DIV_MCUISP1 3 295295436Sandrew#define CLK_DIV_MCUISP0 4 296295436Sandrew#define CLK_DIV_MPWM 5 297295436Sandrew 298295436Sandrew/* Gates */ 299295436Sandrew 300295436Sandrew#define CLK_UART_ISP 8 301295436Sandrew#define CLK_WDT_ISP 9 302295436Sandrew#define CLK_PWM_ISP 10 303295436Sandrew#define CLK_I2C1_ISP 11 304295436Sandrew#define CLK_I2C0_ISP 12 305295436Sandrew#define CLK_MPWM_ISP 13 306295436Sandrew#define CLK_MCUCTL_ISP 14 307295436Sandrew#define CLK_PPMUISPX 15 308295436Sandrew#define CLK_PPMUISPMX 16 309295436Sandrew#define CLK_QE_LITE1 17 310295436Sandrew#define CLK_QE_LITE0 18 311295436Sandrew#define CLK_QE_FD 19 312295436Sandrew#define CLK_QE_DRC 20 313295436Sandrew#define CLK_QE_ISP 21 314295436Sandrew#define CLK_CSIS1 22 315295436Sandrew#define CLK_SMMU_LITE1 23 316295436Sandrew#define CLK_SMMU_LITE0 24 317295436Sandrew#define CLK_SMMU_FD 25 318295436Sandrew#define CLK_SMMU_DRC 26 319295436Sandrew#define CLK_SMMU_ISP 27 320295436Sandrew#define CLK_GICISP 28 321295436Sandrew#define CLK_CSIS0 29 322295436Sandrew#define CLK_MCUISP 30 323295436Sandrew#define CLK_LITE1 31 324295436Sandrew#define CLK_LITE0 32 325295436Sandrew#define CLK_FD 33 326295436Sandrew#define CLK_DRC 34 327295436Sandrew#define CLK_ISP 35 328295436Sandrew#define CLK_QE_ISPCX 36 329295436Sandrew#define CLK_QE_SCALERP 37 330295436Sandrew#define CLK_QE_SCALERC 38 331295436Sandrew#define CLK_SMMU_SCALERP 39 332295436Sandrew#define CLK_SMMU_SCALERC 40 333295436Sandrew#define CLK_SCALERP 41 334295436Sandrew#define CLK_SCALERC 42 335295436Sandrew#define CLK_SPI1_ISP 43 336295436Sandrew#define CLK_SPI0_ISP 44 337295436Sandrew#define CLK_SMMU_ISPCX 45 338295436Sandrew#define CLK_ASYNCAXIM 46 339295436Sandrew#define CLK_SCLK_MPWM_ISP 47 340295436Sandrew 341295436Sandrew/* 342295436Sandrew * Total number of clocks of CMU_ISP. 343295436Sandrew * NOTE: Must be equal to last clock ID increased by one. 344295436Sandrew */ 345295436Sandrew#define NR_CLKS_ISP 48 346295436Sandrew 347270866Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 348