if_xlreg.h revision 82446
138363Swpaul/* 238363Swpaul * Copyright (c) 1997, 1998 338363Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438363Swpaul * 538363Swpaul * Redistribution and use in source and binary forms, with or without 638363Swpaul * modification, are permitted provided that the following conditions 738363Swpaul * are met: 838363Swpaul * 1. Redistributions of source code must retain the above copyright 938363Swpaul * notice, this list of conditions and the following disclaimer. 1038363Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1138363Swpaul * notice, this list of conditions and the following disclaimer in the 1238363Swpaul * documentation and/or other materials provided with the distribution. 1338363Swpaul * 3. All advertising materials mentioning features or use of this software 1438363Swpaul * must display the following acknowledgement: 1538363Swpaul * This product includes software developed by Bill Paul. 1638363Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1738363Swpaul * may be used to endorse or promote products derived from this software 1838363Swpaul * without specific prior written permission. 1938363Swpaul * 2038363Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138363Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238363Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338363Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438363Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538363Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638363Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738363Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838363Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938363Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038363Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3138363Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_xlreg.h 82446 2001-08-28 00:40:18Z wpaul $ 3338363Swpaul */ 3438363Swpaul 3538363Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3638363Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3738363Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3838363Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3967233Simp#define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */ 4038363Swpaul#define XL_EE_BUSY 0x8000 4138363Swpaul 4238363Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4338363Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4438363Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4538363Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4638363Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4738363Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4838363Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4938363Swpaul#define XL_EE_MFG_ID 0x07 5038363Swpaul#define XL_EE_PCI_PARM 0x08 5138363Swpaul#define XL_EE_ROM_ONFO 0x09 5238363Swpaul#define XL_EE_OEM_ADR0 0x0A 5338363Swpaul#define XL_EE_OEM_ADR1 0x0B 5438363Swpaul#define XL_EE_OEM_ADR2 0x0C 5538363Swpaul#define XL_EE_SOFTINFO1 0x0D 5638363Swpaul#define XL_EE_COMPAT 0x0E 5738363Swpaul#define XL_EE_SOFTINFO2 0x0F 5838363Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5938363Swpaul#define XL_EE_RSVD0 0x11 6038363Swpaul#define XL_EE_ICFG_0 0x12 6138363Swpaul#define XL_EE_ICFG_1 0x13 6238363Swpaul#define XL_EE_RSVD1 0x14 6338363Swpaul#define XL_EE_SOFTINFO3 0x15 6438363Swpaul#define XL_EE_RSVD_2 0x16 6538363Swpaul 6638363Swpaul/* 6738363Swpaul * Bits in the capabilities word 6838363Swpaul */ 6938363Swpaul#define XL_CAPS_PNP 0x0001 7038363Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7138363Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7238363Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7338363Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7438363Swpaul#define XL_CAPS_FULL_BM 0x0020 7538363Swpaul#define XL_CAPS_FRAG_BM 0x0040 7638363Swpaul#define XL_CAPS_CRC_PASSTHRU 0x0080 7738363Swpaul#define XL_CAPS_TXDONE 0x0100 7838363Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7938363Swpaul#define XL_CAPS_RX_REPEAT 0x0400 8038363Swpaul#define XL_CAPS_SNOOPING 0x0800 8138363Swpaul#define XL_CAPS_100MBPS 0x1000 8238363Swpaul#define XL_CAPS_PWRMGMT 0x2000 8338363Swpaul 8477548Swpaul#define XL_PACKET_SIZE 1540 8538363Swpaul 8638363Swpaul/* 8738363Swpaul * Register layouts. 8838363Swpaul */ 8938363Swpaul#define XL_COMMAND 0x0E 9038363Swpaul#define XL_STATUS 0x0E 9138363Swpaul 9238363Swpaul#define XL_TX_STATUS 0x1B 9338363Swpaul#define XL_TX_FREE 0x1C 9438363Swpaul#define XL_DMACTL 0x20 9538363Swpaul#define XL_DOWNLIST_PTR 0x24 9651441Swpaul#define XL_DOWN_POLL 0x2D /* 3c90xB only */ 9738363Swpaul#define XL_TX_FREETHRESH 0x2F 9838363Swpaul#define XL_UPLIST_PTR 0x38 9938363Swpaul#define XL_UPLIST_STATUS 0x30 10051441Swpaul#define XL_UP_POLL 0x3D /* 3c90xB only */ 10138363Swpaul 10238363Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 10338363Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 10438363Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 10538363Swpaul 10638363Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10738363Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 10838363Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 10938363Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 11038363Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 11138363Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 11238363Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 11338363Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 11438363Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11538363Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 11638363Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 11738363Swpaul 11838363Swpaul/* 11938363Swpaul * Command codes. Some command codes require that we wait for 12038363Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 12138363Swpaul */ 12238363Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 12338363Swpaul#define XL_CMD_WINSEL 0x0800 12438363Swpaul#define XL_CMD_COAX_START 0x1000 12538363Swpaul#define XL_CMD_RX_DISABLE 0x1800 12638363Swpaul#define XL_CMD_RX_ENABLE 0x2000 12738363Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 12838363Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 12938363Swpaul#define XL_CMD_UP_UNSTALL 0x3001 13038363Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 13138363Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 13238363Swpaul#define XL_CMD_RX_DISCARD 0x4000 13338363Swpaul#define XL_CMD_TX_ENABLE 0x4800 13438363Swpaul#define XL_CMD_TX_DISABLE 0x5000 13538363Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 13638363Swpaul#define XL_CMD_INTR_FAKE 0x6000 13738363Swpaul#define XL_CMD_INTR_ACK 0x6800 13838363Swpaul#define XL_CMD_INTR_ENB 0x7000 13938363Swpaul#define XL_CMD_STAT_ENB 0x7800 14038363Swpaul#define XL_CMD_RX_SET_FILT 0x8000 14138363Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 14238363Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 14338363Swpaul#define XL_CMD_TX_SET_START 0x9800 14438363Swpaul#define XL_CMD_DMA_UP 0xA000 14538363Swpaul#define XL_CMD_DMA_STOP 0xA001 14638363Swpaul#define XL_CMD_STATS_ENABLE 0xA800 14738363Swpaul#define XL_CMD_STATS_DISABLE 0xB000 14838363Swpaul#define XL_CMD_COAX_STOP 0xB800 14938363Swpaul 15038363Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 15138363Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 15238363Swpaul 15338363Swpaul#define XL_HASH_SET 0x0400 15438363Swpaul#define XL_HASHFILT_SIZE 256 15538363Swpaul 15638363Swpaul/* 15738363Swpaul * status codes 15838363Swpaul * Note that bits 15 to 13 indicate the currently visible register window 15938363Swpaul * which may be anything from 0 to 7. 16038363Swpaul */ 16138363Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 16238363Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 16338363Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 16438363Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 16538363Swpaul#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 16638363Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 16738363Swpaul#define XL_STAT_INTREQ 0x0040 /* 6 */ 16838363Swpaul#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16938363Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 17038363Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 17138363Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 17238363Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 17338363Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 17438363Swpaul#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 17538363Swpaul 17638363Swpaul/* 17738526Swpaul * Interrupts we normally want enabled. 17838526Swpaul */ 17938526Swpaul#define XL_INTRS \ 18076480Swpaul (XL_STAT_UP_COMPLETE|/*XL_STAT_STATSOFLOW|*/XL_STAT_ADFAIL| \ 18138526Swpaul XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 18238526Swpaul 18338526Swpaul/* 18438363Swpaul * Window 0 registers 18538363Swpaul */ 18638363Swpaul#define XL_W0_EE_DATA 0x0C 18738363Swpaul#define XL_W0_EE_CMD 0x0A 18838363Swpaul#define XL_W0_RSRC_CFG 0x08 18938363Swpaul#define XL_W0_ADDR_CFG 0x06 19038363Swpaul#define XL_W0_CFG_CTRL 0x04 19138363Swpaul 19238363Swpaul#define XL_W0_PROD_ID 0x02 19338363Swpaul#define XL_W0_MFG_ID 0x00 19438363Swpaul 19538363Swpaul/* 19638363Swpaul * Window 1 19738363Swpaul */ 19838363Swpaul 19938363Swpaul#define XL_W1_TX_FIFO 0x10 20038363Swpaul 20138363Swpaul#define XL_W1_FREE_TX 0x0C 20238363Swpaul#define XL_W1_TX_STATUS 0x0B 20338363Swpaul#define XL_W1_TX_TIMER 0x0A 20438363Swpaul#define XL_W1_RX_STATUS 0x08 20538363Swpaul#define XL_W1_RX_FIFO 0x00 20638363Swpaul 20738363Swpaul/* 20838363Swpaul * RX status codes 20938363Swpaul */ 21038363Swpaul#define XL_RXSTATUS_OVERRUN 0x01 21138363Swpaul#define XL_RXSTATUS_RUNT 0x02 21238363Swpaul#define XL_RXSTATUS_ALIGN 0x04 21338363Swpaul#define XL_RXSTATUS_CRC 0x08 21438363Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 21538363Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 21638363Swpaul 21738363Swpaul/* 21838363Swpaul * TX status codes 21938363Swpaul */ 22038363Swpaul#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 22138363Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 22238363Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 22338363Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 22438363Swpaul#define XL_TXSTATUS_JABBER 0x20 22538363Swpaul#define XL_TXSTATUS_INTREQ 0x40 22638363Swpaul#define XL_TXSTATUS_COMPLETE 0x80 22738363Swpaul 22838363Swpaul/* 22938363Swpaul * Window 2 23038363Swpaul */ 23138363Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 23238363Swpaul#define XL_W2_STATION_MASK_HI 0x0A 23338363Swpaul#define XL_W2_STATION_MASK_MID 0x08 23438363Swpaul#define XL_W2_STATION_MASK_LO 0x06 23538363Swpaul#define XL_W2_STATION_ADDR_HI 0x04 23638363Swpaul#define XL_W2_STATION_ADDR_MID 0x02 23738363Swpaul#define XL_W2_STATION_ADDR_LO 0x00 23838363Swpaul 23938363Swpaul#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 24038363Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 24138363Swpaul#define XL_RESETOPT_DISADVFD 0x0010 24238363Swpaul#define XL_RESETOPT_DISADV100 0x0020 24338363Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 24438363Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 24538363Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 24638363Swpaul#define XL_RESETOPT_FASTEE 0x0200 24738363Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 24838363Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 24938363Swpaul#define XL_RESETOPT_TEST100TX 0x1000 25038363Swpaul#define XL_RESETOPT_TEST100RX 0x2000 25138363Swpaul 25267233Simp#define XL_RESETOPT_INVERT_LED 0x0010 25367233Simp#define XL_RESETOPT_INVERT_MII 0x4000 25467233Simp 25538363Swpaul/* 25638363Swpaul * Window 3 (fifo management) 25738363Swpaul */ 25838363Swpaul#define XL_W3_INTERNAL_CFG 0x00 25977548Swpaul#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */ 26038363Swpaul#define XL_W3_RESET_OPT 0x08 26138363Swpaul#define XL_W3_FREE_TX 0x0C 26238363Swpaul#define XL_W3_FREE_RX 0x0A 26338363Swpaul#define XL_W3_MAC_CTRL 0x06 26438363Swpaul 26538363Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 26638363Swpaul#define XL_ICFG_CONNECTOR_BITS 20 26738363Swpaul 26838363Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 26938363Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 27038363Swpaul#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 27138363Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 27238363Swpaul#define XL_ICFG_RAMLOC 0x00000200 27338363Swpaul#define XL_ICFG_RAMPART (0x00010000|0x00020000) 27438363Swpaul#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 27538363Swpaul#define XL_ICFG_AUTOSEL 0x01000000 27638363Swpaul 27738363Swpaul#define XL_XCVR_10BT 0x00 27838363Swpaul#define XL_XCVR_AUI 0x01 27938363Swpaul#define XL_XCVR_RSVD_0 0x02 28038363Swpaul#define XL_XCVR_COAX 0x03 28138363Swpaul#define XL_XCVR_100BTX 0x04 28238363Swpaul#define XL_XCVR_100BFX 0x05 28338363Swpaul#define XL_XCVR_MII 0x06 28438363Swpaul#define XL_XCVR_RSVD_1 0x07 28538363Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 28638363Swpaul 28738363Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 28838363Swpaul#define XL_MACCTRL_DEFER_0 0x0002 28938363Swpaul#define XL_MACCTRL_DEFER_1 0x0004 29038363Swpaul#define XL_MACCTRL_DEFER_2 0x0008 29138363Swpaul#define XL_MACCTRL_DEFER_3 0x0010 29238363Swpaul#define XL_MACCTRL_DUPLEX 0x0020 29338363Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 29438363Swpaul#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 29538363Swpaul#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 29638363Swpaul#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 29738363Swpaul 29838363Swpaul/* 29938363Swpaul * The 'reset options' register contains power-on reset values 30038363Swpaul * loaded from the EEPROM. This includes the supported media 30138363Swpaul * types on the card. It is also known as the media options register. 30238363Swpaul */ 30338363Swpaul#define XL_W3_MEDIA_OPT 0x08 30438363Swpaul 30538363Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 30638363Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 30738363Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 30838363Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 30938363Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 31038363Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 31138363Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 31238363Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 31338363Swpaul 31438363Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 31538363Swpaul#define XL_MEDIAOPT_MASK 0x01FF 31638363Swpaul 31738363Swpaul/* 31838363Swpaul * Window 4 (diagnostics) 31938363Swpaul */ 32038363Swpaul#define XL_W4_UPPERBYTESOK 0x0D 32138363Swpaul#define XL_W4_BADSSD 0x0C 32238363Swpaul#define XL_W4_MEDIA_STATUS 0x0A 32338363Swpaul#define XL_W4_PHY_MGMT 0x08 32438363Swpaul#define XL_W4_NET_DIAG 0x06 32538363Swpaul#define XL_W4_FIFO_DIAG 0x04 32638363Swpaul#define XL_W4_VCO_DIAG 0x02 32738363Swpaul 32838363Swpaul#define XL_W4_CTRLR_STAT 0x08 32938363Swpaul#define XL_W4_TX_DIAG 0x00 33038363Swpaul 33138363Swpaul#define XL_MII_CLK 0x01 33238363Swpaul#define XL_MII_DATA 0x02 33338363Swpaul#define XL_MII_DIR 0x04 33438363Swpaul 33538363Swpaul#define XL_MEDIA_SQE 0x0008 33638363Swpaul#define XL_MEDIA_10TP 0x00C0 33738363Swpaul#define XL_MEDIA_LNK 0x0080 33838363Swpaul#define XL_MEDIA_LNKBEAT 0x0800 33938363Swpaul 34038363Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 34138363Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 34238363Swpaul#define XL_MEDIASTAT_COLDET 0x0010 34338363Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 34438363Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 34538363Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 34638363Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 34738363Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 34838363Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 34938363Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 35038363Swpaul#define XL_MEDIASTAT_DCENB 0x4000 35138363Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 35238363Swpaul 35338363Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 35438363Swpaul#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 35538363Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 35638363Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 35738363Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 35838363Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 35938363Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 36038363Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 36138363Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 36238363Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 36338363Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 36438363Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 36538363Swpaul 36638363Swpaul/* 36738363Swpaul * Window 5 36838363Swpaul */ 36938363Swpaul#define XL_W5_STAT_ENB 0x0C 37038363Swpaul#define XL_W5_INTR_ENB 0x0A 37140588Swpaul#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 37238363Swpaul#define XL_W5_RX_FILTER 0x08 37338363Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 37438363Swpaul#define XL_W5_TX_AVAILTHRESH 0x02 37538363Swpaul#define XL_W5_TX_STARTTHRESH 0x00 37638363Swpaul 37738363Swpaul/* 37838363Swpaul * RX filter bits 37938363Swpaul */ 38038363Swpaul#define XL_RXFILTER_INDIVIDUAL 0x01 38138363Swpaul#define XL_RXFILTER_ALLMULTI 0x02 38238363Swpaul#define XL_RXFILTER_BROADCAST 0x04 38338363Swpaul#define XL_RXFILTER_ALLFRAMES 0x08 38438363Swpaul#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 38538363Swpaul 38638363Swpaul/* 38738363Swpaul * Window 6 (stats) 38838363Swpaul */ 38938363Swpaul#define XL_W6_TX_BYTES_OK 0x0C 39038363Swpaul#define XL_W6_RX_BYTES_OK 0x0A 39138363Swpaul#define XL_W6_UPPER_FRAMES_OK 0x09 39238363Swpaul#define XL_W6_DEFERRED 0x08 39338363Swpaul#define XL_W6_RX_OK 0x07 39438363Swpaul#define XL_W6_TX_OK 0x06 39538363Swpaul#define XL_W6_RX_OVERRUN 0x05 39638363Swpaul#define XL_W6_COL_LATE 0x04 39738363Swpaul#define XL_W6_COL_SINGLE 0x03 39838363Swpaul#define XL_W6_COL_MULTIPLE 0x02 39938363Swpaul#define XL_W6_SQE_ERRORS 0x01 40038363Swpaul#define XL_W6_CARRIER_LOST 0x00 40138363Swpaul 40238363Swpaul/* 40338363Swpaul * Window 7 (bus master control) 40438363Swpaul */ 40538363Swpaul#define XL_W7_BM_ADDR 0x00 40638363Swpaul#define XL_W7_BM_LEN 0x06 40738363Swpaul#define XL_W7_BM_STATUS 0x0B 40838363Swpaul#define XL_W7_BM_TIMEr 0x0A 40938363Swpaul 41038363Swpaul/* 41138363Swpaul * bus master control registers 41238363Swpaul */ 41338363Swpaul#define XL_BM_PKTSTAT 0x20 41438363Swpaul#define XL_BM_DOWNLISTPTR 0x24 41538363Swpaul#define XL_BM_FRAGADDR 0x28 41638363Swpaul#define XL_BM_FRAGLEN 0x2C 41738363Swpaul#define XL_BM_TXFREETHRESH 0x2F 41838363Swpaul#define XL_BM_UPPKTSTAT 0x30 41938363Swpaul#define XL_BM_UPLISTPTR 0x38 42038363Swpaul 42138363Swpaul#define XL_LAST_FRAG 0x80000000 42238363Swpaul 42338363Swpaul/* 42438363Swpaul * Boomerang/Cyclone TX/RX list structure. 42538363Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 42638363Swpaul * length. 42738363Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 42838363Swpaul */ 42938363Swpaulstruct xl_frag { 43038363Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 43138363Swpaul u_int32_t xl_len; 43238363Swpaul}; 43338363Swpaul 43438363Swpaulstruct xl_list { 43538363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 43638363Swpaul u_int32_t xl_status; 43738363Swpaul struct xl_frag xl_frag[63]; 43838363Swpaul}; 43938363Swpaul 44038363Swpaulstruct xl_list_onefrag { 44138363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 44238363Swpaul u_int32_t xl_status; 44338363Swpaul struct xl_frag xl_frag; 44438363Swpaul}; 44538363Swpaul 44638363Swpaul#define XL_MAXFRAGS 63 44746204Swpaul#define XL_RX_LIST_CNT 128 44846204Swpaul#define XL_TX_LIST_CNT 256 44938363Swpaul#define XL_MIN_FRAMELEN 60 45051441Swpaul#define ETHER_ALIGN 2 45151441Swpaul#define XL_INC(x, y) (x) = (x + 1) % y 45238363Swpaul 45338363Swpaulstruct xl_list_data { 45438363Swpaul struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 45538363Swpaul struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 45638363Swpaul unsigned char xl_pad[XL_MIN_FRAMELEN]; 45738363Swpaul}; 45838363Swpaul 45938363Swpaulstruct xl_chain { 46038363Swpaul struct xl_list *xl_ptr; 46138363Swpaul struct mbuf *xl_mbuf; 46238363Swpaul struct xl_chain *xl_next; 46351441Swpaul struct xl_chain *xl_prev; 46451441Swpaul u_int32_t xl_phys; 46538363Swpaul}; 46638363Swpaul 46738363Swpaulstruct xl_chain_onefrag { 46838363Swpaul struct xl_list_onefrag *xl_ptr; 46938363Swpaul struct mbuf *xl_mbuf; 47038363Swpaul struct xl_chain_onefrag *xl_next; 47138363Swpaul}; 47238363Swpaul 47338363Swpaulstruct xl_chain_data { 47438363Swpaul struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 47538363Swpaul struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 47638363Swpaul 47738363Swpaul struct xl_chain_onefrag *xl_rx_head; 47838363Swpaul 47951441Swpaul /* 3c90x "boomerang" queuing stuff */ 48038363Swpaul struct xl_chain *xl_tx_head; 48138363Swpaul struct xl_chain *xl_tx_tail; 48238363Swpaul struct xl_chain *xl_tx_free; 48351441Swpaul 48451441Swpaul /* 3c90xB "cyclone/hurricane/tornado" stuff */ 48551441Swpaul int xl_tx_prod; 48651441Swpaul int xl_tx_cons; 48751441Swpaul int xl_tx_cnt; 48838363Swpaul}; 48938363Swpaul 49038363Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 49138363Swpaul#define XL_RXSTAT_UP_ERROR 0x00004000 49238363Swpaul#define XL_RXSTAT_UP_CMPLT 0x00008000 49338363Swpaul#define XL_RXSTAT_UP_OVERRUN 0x00010000 49438363Swpaul#define XL_RXSTAT_RUNT 0x00020000 49538363Swpaul#define XL_RXSTAT_ALIGN 0x00040000 49638363Swpaul#define XL_RXSTAT_CRC 0x00080000 49738363Swpaul#define XL_RXSTAT_OVERSIZE 0x00100000 49838363Swpaul#define XL_RXSTAT_DRIBBLE 0x00800000 49938363Swpaul#define XL_RXSTAT_UP_OFLOW 0x01000000 50038363Swpaul#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 50138363Swpaul#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 50238363Swpaul#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 50338363Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 50438363Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 50538363Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 50638363Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 50738363Swpaul 50838363Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 50938363Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 51038363Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 51138363Swpaul#define XL_TXSTAT_DL_COMPLETE 0x00010000 51238363Swpaul#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 51338363Swpaul#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 51438363Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 51551441Swpaul#define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 51651441Swpaul#define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 51738363Swpaul#define XL_TXSTAT_DL_INTR 0x80000000 51838363Swpaul 51938363Swpaul#define XL_CAPABILITY_BM 0x20 52038363Swpaul 52138363Swpaulstruct xl_type { 52238363Swpaul u_int16_t xl_vid; 52338363Swpaul u_int16_t xl_did; 52438363Swpaul char *xl_name; 52538363Swpaul}; 52638363Swpaul 52738363Swpaulstruct xl_mii_frame { 52838363Swpaul u_int8_t mii_stdelim; 52938363Swpaul u_int8_t mii_opcode; 53038363Swpaul u_int8_t mii_phyaddr; 53138363Swpaul u_int8_t mii_regaddr; 53238363Swpaul u_int8_t mii_turnaround; 53338363Swpaul u_int16_t mii_data; 53438363Swpaul}; 53538363Swpaul 53638363Swpaul/* 53738363Swpaul * MII constants 53838363Swpaul */ 53938363Swpaul#define XL_MII_STARTDELIM 0x01 54038363Swpaul#define XL_MII_READOP 0x02 54138363Swpaul#define XL_MII_WRITEOP 0x01 54238363Swpaul#define XL_MII_TURNAROUND 0x02 54338363Swpaul 54438363Swpaul/* 54538363Swpaul * The 3C905B adapters implement a few features that we want to 54638363Swpaul * take advantage of, namely the multicast hash filter. With older 54738363Swpaul * chips, you only have the option of turning on reception of all 54838363Swpaul * multicast frames, which is kind of lame. 54951441Swpaul * 55051441Swpaul * We also use this to decide on a transmit strategy. For the 3c90xB 55151441Swpaul * cards, we can use polled descriptor mode, which reduces CPU overhead. 55238363Swpaul */ 55338363Swpaul#define XL_TYPE_905B 1 55438363Swpaul#define XL_TYPE_90X 2 55538363Swpaul 55665170Swpaul#define XL_FLAG_FUNCREG 0x0001 55765170Swpaul#define XL_FLAG_PHYOK 0x0002 55865170Swpaul#define XL_FLAG_EEPROM_OFFSET_30 0x0004 55965170Swpaul#define XL_FLAG_WEIRDRESET 0x0008 56065170Swpaul#define XL_FLAG_8BITROM 0x0010 56167233Simp#define XL_FLAG_INVERT_LED_PWR 0x0020 56267233Simp#define XL_FLAG_INVERT_MII_PWR 0x0040 56365170Swpaul 56438363Swpaulstruct xl_softc { 56538363Swpaul struct arpcom arpcom; /* interface info */ 56638363Swpaul struct ifmedia ifmedia; /* media info */ 56745062Swpaul bus_space_handle_t xl_bhandle; 56845062Swpaul bus_space_tag_t xl_btag; 56948947Swpaul void *xl_intrhand; 57048947Swpaul struct resource *xl_irq; 57148947Swpaul struct resource *xl_res; 57250579Swpaul device_t xl_miibus; 57338363Swpaul struct xl_type *xl_info; /* 3Com adapter info */ 57438363Swpaul u_int8_t xl_unit; /* interface number */ 57538363Swpaul u_int8_t xl_type; 57638363Swpaul u_int32_t xl_xcvr; 57738363Swpaul u_int16_t xl_media; 57838363Swpaul u_int16_t xl_caps; 57938363Swpaul u_int8_t xl_stats_no_timeout; 58046514Swpaul u_int16_t xl_tx_thresh; 58152244Swpaul int xl_if_flags; 58238363Swpaul struct xl_list_data *xl_ldata; 58338363Swpaul struct xl_chain_data xl_cdata; 58438363Swpaul struct callout_handle xl_stat_ch; 58565170Swpaul int xl_flags; 58665170Swpaul struct resource *xl_fres; 58765170Swpaul bus_space_handle_t xl_fhandle; 58865170Swpaul bus_space_tag_t xl_ftag; 58967087Swpaul struct mtx xl_mtx; 59038363Swpaul}; 59138363Swpaul 59272200Sbmilekic#define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx) 59372200Sbmilekic#define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx) 59467087Swpaul 59538363Swpaul#define xl_rx_goodframes(x) \ 59638363Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 59738363Swpaul 59838363Swpaul#define xl_tx_goodframes(x) \ 59938363Swpaul ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 60038363Swpaul 60138363Swpaulstruct xl_stats { 60238363Swpaul u_int8_t xl_carrier_lost; 60338363Swpaul u_int8_t xl_sqe_errs; 60438363Swpaul u_int8_t xl_tx_multi_collision; 60538363Swpaul u_int8_t xl_tx_single_collision; 60638363Swpaul u_int8_t xl_tx_late_collision; 60738363Swpaul u_int8_t xl_rx_overrun; 60838363Swpaul u_int8_t xl_tx_frames_ok; 60938363Swpaul u_int8_t xl_rx_frames_ok; 61038363Swpaul u_int8_t xl_tx_deferred; 61138363Swpaul u_int8_t xl_upper_frames_ok; 61238363Swpaul u_int16_t xl_rx_bytes_ok; 61338363Swpaul u_int16_t xl_tx_bytes_ok; 61438363Swpaul u_int16_t status; 61538363Swpaul}; 61638363Swpaul 61738363Swpaul/* 61838363Swpaul * register space access macros 61938363Swpaul */ 62038363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 62145062Swpaul bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 62238363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 62345062Swpaul bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 62438363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 62545062Swpaul bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 62638363Swpaul 62745062Swpaul#define CSR_READ_4(sc, reg) \ 62845062Swpaul bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 62945062Swpaul#define CSR_READ_2(sc, reg) \ 63045062Swpaul bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 63145062Swpaul#define CSR_READ_1(sc, reg) \ 63245062Swpaul bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 63338363Swpaul 63438363Swpaul#define XL_SEL_WIN(x) \ 63538363Swpaul CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 63638363Swpaul#define XL_TIMEOUT 1000 63738363Swpaul 63838363Swpaul/* 63938363Swpaul * General constants that are fun to know. 64038363Swpaul * 64138363Swpaul * 3Com PCI vendor ID 64238363Swpaul */ 64338363Swpaul#define TC_VENDORID 0x10B7 64438363Swpaul 64538363Swpaul/* 64638363Swpaul * 3Com chip device IDs. 64738363Swpaul */ 64838363Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 64938363Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 65038363Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 65138363Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 65246204Swpaul#define TC_DEVICEID_KRAKATOA_10BT 0x9004 65346204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 65446204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 65545693Swpaul#define TC_DEVICEID_CYCLONE_10FL 0x900A 65646204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 65738363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 65845601Swpaul#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 65940097Swpaul#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 66047627Swpaul#define TC_DEVICEID_TORNADO_10_100BT 0x9200 66146204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 66251301Swpaul#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 66345629Swpaul#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 66454697Swpaul#define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500 66565170Swpaul#define TC_DEVICEID_HURRICANE_556 0x6055 66665170Swpaul#define TC_DEVICEID_HURRICANE_556B 0x6056 66768227Ssanpei#define TC_DEVICEID_HURRICANE_575A 0x5057 66867233Simp#define TC_DEVICEID_HURRICANE_575B 0x5157 66967233Simp#define TC_DEVICEID_HURRICANE_575C 0x5257 67082446Swpaul#define TC_DEVICEID_HURRICANE_656 0x6560 67182446Swpaul#define TC_DEVICEID_HURRICANE_656B 0x6562 67282446Swpaul#define TC_DEVICEID_TORNADO_656C 0x6564 67338363Swpaul 67438363Swpaul/* 67538363Swpaul * PCI low memory base and low I/O base register, and 67638363Swpaul * other PCI registers. Note: some are only available on 67738363Swpaul * the 3c905B, in particular those that related to power management. 67838363Swpaul */ 67938363Swpaul 68038363Swpaul#define XL_PCI_VENDOR_ID 0x00 68138363Swpaul#define XL_PCI_DEVICE_ID 0x02 68238363Swpaul#define XL_PCI_COMMAND 0x04 68338363Swpaul#define XL_PCI_STATUS 0x06 68438363Swpaul#define XL_PCI_CLASSCODE 0x09 68538363Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 68638363Swpaul#define XL_PCI_HEADER_TYPE 0x0E 68738363Swpaul#define XL_PCI_LOIO 0x10 68838363Swpaul#define XL_PCI_LOMEM 0x14 68965170Swpaul#define XL_PCI_FUNCMEM 0x18 69038363Swpaul#define XL_PCI_BIOSROM 0x30 69138363Swpaul#define XL_PCI_INTLINE 0x3C 69238363Swpaul#define XL_PCI_INTPIN 0x3D 69338363Swpaul#define XL_PCI_MINGNT 0x3E 69438363Swpaul#define XL_PCI_MINLAT 0x0F 69538363Swpaul#define XL_PCI_RESETOPT 0x48 69638363Swpaul#define XL_PCI_EEPROM_DATA 0x4C 69738363Swpaul 69838363Swpaul/* 3c905B-only registers */ 69938363Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 70038363Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 70138363Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 70238363Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 70338363Swpaul 70438363Swpaul#define XL_PSTATE_MASK 0x0003 70538363Swpaul#define XL_PSTATE_D0 0x0000 70638363Swpaul#define XL_PSTATE_D1 0x0002 70738363Swpaul#define XL_PSTATE_D2 0x0002 70838363Swpaul#define XL_PSTATE_D3 0x0003 70938363Swpaul#define XL_PME_EN 0x0010 71038363Swpaul#define XL_PME_STATUS 0x8000 71138363Swpaul 71245062Swpaul#ifdef __alpha__ 71345062Swpaul#undef vtophys 71447529Sgallatin#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 71547529Sgallatin 71645062Swpaul#endif 71746204Swpaul 71846204Swpaul#ifndef IFM_10_FL 71946204Swpaul#define IFM_10_FL 13 /* 10baseFL - Fiber */ 72046204Swpaul#endif 721