if_xlreg.h revision 51441
138363Swpaul/* 238363Swpaul * Copyright (c) 1997, 1998 338363Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438363Swpaul * 538363Swpaul * Redistribution and use in source and binary forms, with or without 638363Swpaul * modification, are permitted provided that the following conditions 738363Swpaul * are met: 838363Swpaul * 1. Redistributions of source code must retain the above copyright 938363Swpaul * notice, this list of conditions and the following disclaimer. 1038363Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1138363Swpaul * notice, this list of conditions and the following disclaimer in the 1238363Swpaul * documentation and/or other materials provided with the distribution. 1338363Swpaul * 3. All advertising materials mentioning features or use of this software 1438363Swpaul * must display the following acknowledgement: 1538363Swpaul * This product includes software developed by Bill Paul. 1638363Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1738363Swpaul * may be used to endorse or promote products derived from this software 1838363Swpaul * without specific prior written permission. 1938363Swpaul * 2038363Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138363Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238363Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338363Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438363Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538363Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638363Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738363Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838363Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938363Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038363Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3138363Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_xlreg.h 51441 1999-09-20 00:24:11Z wpaul $ 3338363Swpaul */ 3438363Swpaul 3538363Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3638363Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3738363Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3838363Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3938363Swpaul#define XL_EE_BUSY 0x8000 4038363Swpaul 4138363Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4238363Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4338363Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4438363Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4538363Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4638363Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4738363Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4838363Swpaul#define XL_EE_MFG_ID 0x07 4938363Swpaul#define XL_EE_PCI_PARM 0x08 5038363Swpaul#define XL_EE_ROM_ONFO 0x09 5138363Swpaul#define XL_EE_OEM_ADR0 0x0A 5238363Swpaul#define XL_EE_OEM_ADR1 0x0B 5338363Swpaul#define XL_EE_OEM_ADR2 0x0C 5438363Swpaul#define XL_EE_SOFTINFO1 0x0D 5538363Swpaul#define XL_EE_COMPAT 0x0E 5638363Swpaul#define XL_EE_SOFTINFO2 0x0F 5738363Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5838363Swpaul#define XL_EE_RSVD0 0x11 5938363Swpaul#define XL_EE_ICFG_0 0x12 6038363Swpaul#define XL_EE_ICFG_1 0x13 6138363Swpaul#define XL_EE_RSVD1 0x14 6238363Swpaul#define XL_EE_SOFTINFO3 0x15 6338363Swpaul#define XL_EE_RSVD_2 0x16 6438363Swpaul 6538363Swpaul/* 6638363Swpaul * Bits in the capabilities word 6738363Swpaul */ 6838363Swpaul#define XL_CAPS_PNP 0x0001 6938363Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7038363Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7138363Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7238363Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7338363Swpaul#define XL_CAPS_FULL_BM 0x0020 7438363Swpaul#define XL_CAPS_FRAG_BM 0x0040 7538363Swpaul#define XL_CAPS_CRC_PASSTHRU 0x0080 7638363Swpaul#define XL_CAPS_TXDONE 0x0100 7738363Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7838363Swpaul#define XL_CAPS_RX_REPEAT 0x0400 7938363Swpaul#define XL_CAPS_SNOOPING 0x0800 8038363Swpaul#define XL_CAPS_100MBPS 0x1000 8138363Swpaul#define XL_CAPS_PWRMGMT 0x2000 8238363Swpaul 8338363Swpaul#define XL_PACKET_SIZE 1536 8438363Swpaul 8538363Swpaul/* 8638363Swpaul * Register layouts. 8738363Swpaul */ 8838363Swpaul#define XL_COMMAND 0x0E 8938363Swpaul#define XL_STATUS 0x0E 9038363Swpaul 9138363Swpaul#define XL_TX_STATUS 0x1B 9238363Swpaul#define XL_TX_FREE 0x1C 9338363Swpaul#define XL_DMACTL 0x20 9438363Swpaul#define XL_DOWNLIST_PTR 0x24 9551441Swpaul#define XL_DOWN_POLL 0x2D /* 3c90xB only */ 9638363Swpaul#define XL_TX_FREETHRESH 0x2F 9738363Swpaul#define XL_UPLIST_PTR 0x38 9838363Swpaul#define XL_UPLIST_STATUS 0x30 9951441Swpaul#define XL_UP_POLL 0x3D /* 3c90xB only */ 10038363Swpaul 10138363Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 10238363Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 10338363Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 10438363Swpaul 10538363Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10638363Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 10738363Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 10838363Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 10938363Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 11038363Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 11138363Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 11238363Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 11338363Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11438363Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 11538363Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 11638363Swpaul 11738363Swpaul/* 11838363Swpaul * Command codes. Some command codes require that we wait for 11938363Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 12038363Swpaul */ 12138363Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 12238363Swpaul#define XL_CMD_WINSEL 0x0800 12338363Swpaul#define XL_CMD_COAX_START 0x1000 12438363Swpaul#define XL_CMD_RX_DISABLE 0x1800 12538363Swpaul#define XL_CMD_RX_ENABLE 0x2000 12638363Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 12738363Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 12838363Swpaul#define XL_CMD_UP_UNSTALL 0x3001 12938363Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 13038363Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 13138363Swpaul#define XL_CMD_RX_DISCARD 0x4000 13238363Swpaul#define XL_CMD_TX_ENABLE 0x4800 13338363Swpaul#define XL_CMD_TX_DISABLE 0x5000 13438363Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 13538363Swpaul#define XL_CMD_INTR_FAKE 0x6000 13638363Swpaul#define XL_CMD_INTR_ACK 0x6800 13738363Swpaul#define XL_CMD_INTR_ENB 0x7000 13838363Swpaul#define XL_CMD_STAT_ENB 0x7800 13938363Swpaul#define XL_CMD_RX_SET_FILT 0x8000 14038363Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 14138363Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 14238363Swpaul#define XL_CMD_TX_SET_START 0x9800 14338363Swpaul#define XL_CMD_DMA_UP 0xA000 14438363Swpaul#define XL_CMD_DMA_STOP 0xA001 14538363Swpaul#define XL_CMD_STATS_ENABLE 0xA800 14638363Swpaul#define XL_CMD_STATS_DISABLE 0xB000 14738363Swpaul#define XL_CMD_COAX_STOP 0xB800 14838363Swpaul 14938363Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 15038363Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 15138363Swpaul 15238363Swpaul#define XL_HASH_SET 0x0400 15338363Swpaul#define XL_HASHFILT_SIZE 256 15438363Swpaul 15538363Swpaul/* 15638363Swpaul * status codes 15738363Swpaul * Note that bits 15 to 13 indicate the currently visible register window 15838363Swpaul * which may be anything from 0 to 7. 15938363Swpaul */ 16038363Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 16138363Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 16238363Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 16338363Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 16438363Swpaul#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 16538363Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 16638363Swpaul#define XL_STAT_INTREQ 0x0040 /* 6 */ 16738363Swpaul#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16838363Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 16938363Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 17038363Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 17138363Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 17238363Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 17338363Swpaul#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 17438363Swpaul 17538363Swpaul/* 17638526Swpaul * Interrupts we normally want enabled. 17738526Swpaul */ 17838526Swpaul#define XL_INTRS \ 17938526Swpaul (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 18038526Swpaul XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 18138526Swpaul 18238526Swpaul/* 18338363Swpaul * Window 0 registers 18438363Swpaul */ 18538363Swpaul#define XL_W0_EE_DATA 0x0C 18638363Swpaul#define XL_W0_EE_CMD 0x0A 18738363Swpaul#define XL_W0_RSRC_CFG 0x08 18838363Swpaul#define XL_W0_ADDR_CFG 0x06 18938363Swpaul#define XL_W0_CFG_CTRL 0x04 19038363Swpaul 19138363Swpaul#define XL_W0_PROD_ID 0x02 19238363Swpaul#define XL_W0_MFG_ID 0x00 19338363Swpaul 19438363Swpaul/* 19538363Swpaul * Window 1 19638363Swpaul */ 19738363Swpaul 19838363Swpaul#define XL_W1_TX_FIFO 0x10 19938363Swpaul 20038363Swpaul#define XL_W1_FREE_TX 0x0C 20138363Swpaul#define XL_W1_TX_STATUS 0x0B 20238363Swpaul#define XL_W1_TX_TIMER 0x0A 20338363Swpaul#define XL_W1_RX_STATUS 0x08 20438363Swpaul#define XL_W1_RX_FIFO 0x00 20538363Swpaul 20638363Swpaul/* 20738363Swpaul * RX status codes 20838363Swpaul */ 20938363Swpaul#define XL_RXSTATUS_OVERRUN 0x01 21038363Swpaul#define XL_RXSTATUS_RUNT 0x02 21138363Swpaul#define XL_RXSTATUS_ALIGN 0x04 21238363Swpaul#define XL_RXSTATUS_CRC 0x08 21338363Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 21438363Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 21538363Swpaul 21638363Swpaul/* 21738363Swpaul * TX status codes 21838363Swpaul */ 21938363Swpaul#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 22038363Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 22138363Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 22238363Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 22338363Swpaul#define XL_TXSTATUS_JABBER 0x20 22438363Swpaul#define XL_TXSTATUS_INTREQ 0x40 22538363Swpaul#define XL_TXSTATUS_COMPLETE 0x80 22638363Swpaul 22738363Swpaul/* 22838363Swpaul * Window 2 22938363Swpaul */ 23038363Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 23138363Swpaul#define XL_W2_STATION_MASK_HI 0x0A 23238363Swpaul#define XL_W2_STATION_MASK_MID 0x08 23338363Swpaul#define XL_W2_STATION_MASK_LO 0x06 23438363Swpaul#define XL_W2_STATION_ADDR_HI 0x04 23538363Swpaul#define XL_W2_STATION_ADDR_MID 0x02 23638363Swpaul#define XL_W2_STATION_ADDR_LO 0x00 23738363Swpaul 23838363Swpaul#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 23938363Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 24038363Swpaul#define XL_RESETOPT_DISADVFD 0x0010 24138363Swpaul#define XL_RESETOPT_DISADV100 0x0020 24238363Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 24338363Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 24438363Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 24538363Swpaul#define XL_RESETOPT_FASTEE 0x0200 24638363Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 24738363Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 24838363Swpaul#define XL_RESETOPT_TEST100TX 0x1000 24938363Swpaul#define XL_RESETOPT_TEST100RX 0x2000 25038363Swpaul 25138363Swpaul/* 25238363Swpaul * Window 3 (fifo management) 25338363Swpaul */ 25438363Swpaul#define XL_W3_INTERNAL_CFG 0x00 25538363Swpaul#define XL_W3_RESET_OPT 0x08 25638363Swpaul#define XL_W3_FREE_TX 0x0C 25738363Swpaul#define XL_W3_FREE_RX 0x0A 25838363Swpaul#define XL_W3_MAC_CTRL 0x06 25938363Swpaul 26038363Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 26138363Swpaul#define XL_ICFG_CONNECTOR_BITS 20 26238363Swpaul 26338363Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 26438363Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 26538363Swpaul#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 26638363Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 26738363Swpaul#define XL_ICFG_RAMLOC 0x00000200 26838363Swpaul#define XL_ICFG_RAMPART (0x00010000|0x00020000) 26938363Swpaul#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 27038363Swpaul#define XL_ICFG_AUTOSEL 0x01000000 27138363Swpaul 27238363Swpaul#define XL_XCVR_10BT 0x00 27338363Swpaul#define XL_XCVR_AUI 0x01 27438363Swpaul#define XL_XCVR_RSVD_0 0x02 27538363Swpaul#define XL_XCVR_COAX 0x03 27638363Swpaul#define XL_XCVR_100BTX 0x04 27738363Swpaul#define XL_XCVR_100BFX 0x05 27838363Swpaul#define XL_XCVR_MII 0x06 27938363Swpaul#define XL_XCVR_RSVD_1 0x07 28038363Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 28138363Swpaul 28238363Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 28338363Swpaul#define XL_MACCTRL_DEFER_0 0x0002 28438363Swpaul#define XL_MACCTRL_DEFER_1 0x0004 28538363Swpaul#define XL_MACCTRL_DEFER_2 0x0008 28638363Swpaul#define XL_MACCTRL_DEFER_3 0x0010 28738363Swpaul#define XL_MACCTRL_DUPLEX 0x0020 28838363Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 28938363Swpaul#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 29038363Swpaul#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 29138363Swpaul#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 29238363Swpaul 29338363Swpaul/* 29438363Swpaul * The 'reset options' register contains power-on reset values 29538363Swpaul * loaded from the EEPROM. This includes the supported media 29638363Swpaul * types on the card. It is also known as the media options register. 29738363Swpaul */ 29838363Swpaul#define XL_W3_MEDIA_OPT 0x08 29938363Swpaul 30038363Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 30138363Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 30238363Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 30338363Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 30438363Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 30538363Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 30638363Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 30738363Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 30838363Swpaul 30938363Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 31038363Swpaul#define XL_MEDIAOPT_MASK 0x01FF 31138363Swpaul 31238363Swpaul/* 31338363Swpaul * Window 4 (diagnostics) 31438363Swpaul */ 31538363Swpaul#define XL_W4_UPPERBYTESOK 0x0D 31638363Swpaul#define XL_W4_BADSSD 0x0C 31738363Swpaul#define XL_W4_MEDIA_STATUS 0x0A 31838363Swpaul#define XL_W4_PHY_MGMT 0x08 31938363Swpaul#define XL_W4_NET_DIAG 0x06 32038363Swpaul#define XL_W4_FIFO_DIAG 0x04 32138363Swpaul#define XL_W4_VCO_DIAG 0x02 32238363Swpaul 32338363Swpaul#define XL_W4_CTRLR_STAT 0x08 32438363Swpaul#define XL_W4_TX_DIAG 0x00 32538363Swpaul 32638363Swpaul#define XL_MII_CLK 0x01 32738363Swpaul#define XL_MII_DATA 0x02 32838363Swpaul#define XL_MII_DIR 0x04 32938363Swpaul 33038363Swpaul#define XL_MEDIA_SQE 0x0008 33138363Swpaul#define XL_MEDIA_10TP 0x00C0 33238363Swpaul#define XL_MEDIA_LNK 0x0080 33338363Swpaul#define XL_MEDIA_LNKBEAT 0x0800 33438363Swpaul 33538363Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 33638363Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 33738363Swpaul#define XL_MEDIASTAT_COLDET 0x0010 33838363Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 33938363Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 34038363Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 34138363Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 34238363Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 34338363Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 34438363Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 34538363Swpaul#define XL_MEDIASTAT_DCENB 0x4000 34638363Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 34738363Swpaul 34838363Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 34938363Swpaul#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 35038363Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 35138363Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 35238363Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 35338363Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 35438363Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 35538363Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 35638363Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 35738363Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 35838363Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 35938363Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 36038363Swpaul 36138363Swpaul/* 36238363Swpaul * Window 5 36338363Swpaul */ 36438363Swpaul#define XL_W5_STAT_ENB 0x0C 36538363Swpaul#define XL_W5_INTR_ENB 0x0A 36640588Swpaul#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 36738363Swpaul#define XL_W5_RX_FILTER 0x08 36838363Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 36938363Swpaul#define XL_W5_TX_AVAILTHRESH 0x02 37038363Swpaul#define XL_W5_TX_STARTTHRESH 0x00 37138363Swpaul 37238363Swpaul/* 37338363Swpaul * RX filter bits 37438363Swpaul */ 37538363Swpaul#define XL_RXFILTER_INDIVIDUAL 0x01 37638363Swpaul#define XL_RXFILTER_ALLMULTI 0x02 37738363Swpaul#define XL_RXFILTER_BROADCAST 0x04 37838363Swpaul#define XL_RXFILTER_ALLFRAMES 0x08 37938363Swpaul#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 38038363Swpaul 38138363Swpaul/* 38238363Swpaul * Window 6 (stats) 38338363Swpaul */ 38438363Swpaul#define XL_W6_TX_BYTES_OK 0x0C 38538363Swpaul#define XL_W6_RX_BYTES_OK 0x0A 38638363Swpaul#define XL_W6_UPPER_FRAMES_OK 0x09 38738363Swpaul#define XL_W6_DEFERRED 0x08 38838363Swpaul#define XL_W6_RX_OK 0x07 38938363Swpaul#define XL_W6_TX_OK 0x06 39038363Swpaul#define XL_W6_RX_OVERRUN 0x05 39138363Swpaul#define XL_W6_COL_LATE 0x04 39238363Swpaul#define XL_W6_COL_SINGLE 0x03 39338363Swpaul#define XL_W6_COL_MULTIPLE 0x02 39438363Swpaul#define XL_W6_SQE_ERRORS 0x01 39538363Swpaul#define XL_W6_CARRIER_LOST 0x00 39638363Swpaul 39738363Swpaul/* 39838363Swpaul * Window 7 (bus master control) 39938363Swpaul */ 40038363Swpaul#define XL_W7_BM_ADDR 0x00 40138363Swpaul#define XL_W7_BM_LEN 0x06 40238363Swpaul#define XL_W7_BM_STATUS 0x0B 40338363Swpaul#define XL_W7_BM_TIMEr 0x0A 40438363Swpaul 40538363Swpaul/* 40638363Swpaul * bus master control registers 40738363Swpaul */ 40838363Swpaul#define XL_BM_PKTSTAT 0x20 40938363Swpaul#define XL_BM_DOWNLISTPTR 0x24 41038363Swpaul#define XL_BM_FRAGADDR 0x28 41138363Swpaul#define XL_BM_FRAGLEN 0x2C 41238363Swpaul#define XL_BM_TXFREETHRESH 0x2F 41338363Swpaul#define XL_BM_UPPKTSTAT 0x30 41438363Swpaul#define XL_BM_UPLISTPTR 0x38 41538363Swpaul 41638363Swpaul#define XL_LAST_FRAG 0x80000000 41738363Swpaul 41838363Swpaul/* 41938363Swpaul * Boomerang/Cyclone TX/RX list structure. 42038363Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 42138363Swpaul * length. 42238363Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 42338363Swpaul */ 42438363Swpaulstruct xl_frag { 42538363Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 42638363Swpaul u_int32_t xl_len; 42738363Swpaul}; 42838363Swpaul 42938363Swpaulstruct xl_list { 43038363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 43138363Swpaul u_int32_t xl_status; 43238363Swpaul struct xl_frag xl_frag[63]; 43338363Swpaul}; 43438363Swpaul 43538363Swpaulstruct xl_list_onefrag { 43638363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 43738363Swpaul u_int32_t xl_status; 43838363Swpaul struct xl_frag xl_frag; 43938363Swpaul}; 44038363Swpaul 44138363Swpaul#define XL_MAXFRAGS 63 44246204Swpaul#define XL_RX_LIST_CNT 128 44346204Swpaul#define XL_TX_LIST_CNT 256 44438363Swpaul#define XL_MIN_FRAMELEN 60 44551441Swpaul#define ETHER_ALIGN 2 44651441Swpaul#define XL_INC(x, y) (x) = (x + 1) % y 44738363Swpaul 44838363Swpaulstruct xl_list_data { 44938363Swpaul struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 45038363Swpaul struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 45138363Swpaul unsigned char xl_pad[XL_MIN_FRAMELEN]; 45238363Swpaul}; 45338363Swpaul 45438363Swpaulstruct xl_chain { 45538363Swpaul struct xl_list *xl_ptr; 45638363Swpaul struct mbuf *xl_mbuf; 45738363Swpaul struct xl_chain *xl_next; 45851441Swpaul struct xl_chain *xl_prev; 45951441Swpaul u_int32_t xl_phys; 46038363Swpaul}; 46138363Swpaul 46238363Swpaulstruct xl_chain_onefrag { 46338363Swpaul struct xl_list_onefrag *xl_ptr; 46438363Swpaul struct mbuf *xl_mbuf; 46538363Swpaul struct xl_chain_onefrag *xl_next; 46638363Swpaul}; 46738363Swpaul 46838363Swpaulstruct xl_chain_data { 46938363Swpaul struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 47038363Swpaul struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 47138363Swpaul 47238363Swpaul struct xl_chain_onefrag *xl_rx_head; 47338363Swpaul 47451441Swpaul /* 3c90x "boomerang" queuing stuff */ 47538363Swpaul struct xl_chain *xl_tx_head; 47638363Swpaul struct xl_chain *xl_tx_tail; 47738363Swpaul struct xl_chain *xl_tx_free; 47851441Swpaul 47951441Swpaul /* 3c90xB "cyclone/hurricane/tornado" stuff */ 48051441Swpaul int xl_tx_prod; 48151441Swpaul int xl_tx_cons; 48251441Swpaul int xl_tx_cnt; 48338363Swpaul}; 48438363Swpaul 48538363Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 48638363Swpaul#define XL_RXSTAT_UP_ERROR 0x00004000 48738363Swpaul#define XL_RXSTAT_UP_CMPLT 0x00008000 48838363Swpaul#define XL_RXSTAT_UP_OVERRUN 0x00010000 48938363Swpaul#define XL_RXSTAT_RUNT 0x00020000 49038363Swpaul#define XL_RXSTAT_ALIGN 0x00040000 49138363Swpaul#define XL_RXSTAT_CRC 0x00080000 49238363Swpaul#define XL_RXSTAT_OVERSIZE 0x00100000 49338363Swpaul#define XL_RXSTAT_DRIBBLE 0x00800000 49438363Swpaul#define XL_RXSTAT_UP_OFLOW 0x01000000 49538363Swpaul#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 49638363Swpaul#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 49738363Swpaul#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 49838363Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 49938363Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 50038363Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 50138363Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 50238363Swpaul 50338363Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 50438363Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 50538363Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 50638363Swpaul#define XL_TXSTAT_DL_COMPLETE 0x00010000 50738363Swpaul#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 50838363Swpaul#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 50938363Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 51051441Swpaul#define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 51151441Swpaul#define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 51238363Swpaul#define XL_TXSTAT_DL_INTR 0x80000000 51338363Swpaul 51438363Swpaul#define XL_CAPABILITY_BM 0x20 51538363Swpaul 51638363Swpaulstruct xl_type { 51738363Swpaul u_int16_t xl_vid; 51838363Swpaul u_int16_t xl_did; 51938363Swpaul char *xl_name; 52038363Swpaul}; 52138363Swpaul 52238363Swpaulstruct xl_mii_frame { 52338363Swpaul u_int8_t mii_stdelim; 52438363Swpaul u_int8_t mii_opcode; 52538363Swpaul u_int8_t mii_phyaddr; 52638363Swpaul u_int8_t mii_regaddr; 52738363Swpaul u_int8_t mii_turnaround; 52838363Swpaul u_int16_t mii_data; 52938363Swpaul}; 53038363Swpaul 53138363Swpaul/* 53238363Swpaul * MII constants 53338363Swpaul */ 53438363Swpaul#define XL_MII_STARTDELIM 0x01 53538363Swpaul#define XL_MII_READOP 0x02 53638363Swpaul#define XL_MII_WRITEOP 0x01 53738363Swpaul#define XL_MII_TURNAROUND 0x02 53838363Swpaul 53938363Swpaul/* 54038363Swpaul * The 3C905B adapters implement a few features that we want to 54138363Swpaul * take advantage of, namely the multicast hash filter. With older 54238363Swpaul * chips, you only have the option of turning on reception of all 54338363Swpaul * multicast frames, which is kind of lame. 54451441Swpaul * 54551441Swpaul * We also use this to decide on a transmit strategy. For the 3c90xB 54651441Swpaul * cards, we can use polled descriptor mode, which reduces CPU overhead. 54738363Swpaul */ 54838363Swpaul#define XL_TYPE_905B 1 54938363Swpaul#define XL_TYPE_90X 2 55038363Swpaul 55138363Swpaulstruct xl_softc { 55238363Swpaul struct arpcom arpcom; /* interface info */ 55338363Swpaul struct ifmedia ifmedia; /* media info */ 55445062Swpaul bus_space_handle_t xl_bhandle; 55545062Swpaul bus_space_tag_t xl_btag; 55648947Swpaul void *xl_intrhand; 55748947Swpaul struct resource *xl_irq; 55848947Swpaul struct resource *xl_res; 55950579Swpaul device_t xl_miibus; 56038363Swpaul struct xl_type *xl_info; /* 3Com adapter info */ 56138363Swpaul u_int8_t xl_unit; /* interface number */ 56238363Swpaul u_int8_t xl_type; 56338363Swpaul u_int32_t xl_xcvr; 56438363Swpaul u_int16_t xl_media; 56538363Swpaul u_int16_t xl_caps; 56638363Swpaul u_int8_t xl_stats_no_timeout; 56746514Swpaul u_int16_t xl_tx_thresh; 56838363Swpaul struct xl_list_data *xl_ldata; 56938363Swpaul struct xl_chain_data xl_cdata; 57038363Swpaul struct callout_handle xl_stat_ch; 57138363Swpaul}; 57238363Swpaul 57338363Swpaul#define xl_rx_goodframes(x) \ 57438363Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 57538363Swpaul 57638363Swpaul#define xl_tx_goodframes(x) \ 57738363Swpaul ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 57838363Swpaul 57938363Swpaulstruct xl_stats { 58038363Swpaul u_int8_t xl_carrier_lost; 58138363Swpaul u_int8_t xl_sqe_errs; 58238363Swpaul u_int8_t xl_tx_multi_collision; 58338363Swpaul u_int8_t xl_tx_single_collision; 58438363Swpaul u_int8_t xl_tx_late_collision; 58538363Swpaul u_int8_t xl_rx_overrun; 58638363Swpaul u_int8_t xl_tx_frames_ok; 58738363Swpaul u_int8_t xl_rx_frames_ok; 58838363Swpaul u_int8_t xl_tx_deferred; 58938363Swpaul u_int8_t xl_upper_frames_ok; 59038363Swpaul u_int16_t xl_rx_bytes_ok; 59138363Swpaul u_int16_t xl_tx_bytes_ok; 59238363Swpaul u_int16_t status; 59338363Swpaul}; 59438363Swpaul 59538363Swpaul/* 59638363Swpaul * register space access macros 59738363Swpaul */ 59838363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 59945062Swpaul bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 60038363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 60145062Swpaul bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 60238363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 60345062Swpaul bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 60438363Swpaul 60545062Swpaul#define CSR_READ_4(sc, reg) \ 60645062Swpaul bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 60745062Swpaul#define CSR_READ_2(sc, reg) \ 60845062Swpaul bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 60945062Swpaul#define CSR_READ_1(sc, reg) \ 61045062Swpaul bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 61138363Swpaul 61238363Swpaul#define XL_SEL_WIN(x) \ 61338363Swpaul CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 61438363Swpaul#define XL_TIMEOUT 1000 61538363Swpaul 61638363Swpaul/* 61738363Swpaul * General constants that are fun to know. 61838363Swpaul * 61938363Swpaul * 3Com PCI vendor ID 62038363Swpaul */ 62138363Swpaul#define TC_VENDORID 0x10B7 62238363Swpaul 62338363Swpaul/* 62438363Swpaul * 3Com chip device IDs. 62538363Swpaul */ 62638363Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 62738363Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 62838363Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 62938363Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 63046204Swpaul#define TC_DEVICEID_KRAKATOA_10BT 0x9004 63146204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 63246204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 63345693Swpaul#define TC_DEVICEID_CYCLONE_10FL 0x900A 63446204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 63538363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 63645601Swpaul#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 63740097Swpaul#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 63847627Swpaul#define TC_DEVICEID_TORNADO_10_100BT 0x9200 63946204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 64051301Swpaul#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 64145629Swpaul#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 64238363Swpaul 64338363Swpaul/* 64438363Swpaul * PCI low memory base and low I/O base register, and 64538363Swpaul * other PCI registers. Note: some are only available on 64638363Swpaul * the 3c905B, in particular those that related to power management. 64738363Swpaul */ 64838363Swpaul 64938363Swpaul#define XL_PCI_VENDOR_ID 0x00 65038363Swpaul#define XL_PCI_DEVICE_ID 0x02 65138363Swpaul#define XL_PCI_COMMAND 0x04 65238363Swpaul#define XL_PCI_STATUS 0x06 65338363Swpaul#define XL_PCI_CLASSCODE 0x09 65438363Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 65538363Swpaul#define XL_PCI_HEADER_TYPE 0x0E 65638363Swpaul#define XL_PCI_LOIO 0x10 65738363Swpaul#define XL_PCI_LOMEM 0x14 65838363Swpaul#define XL_PCI_BIOSROM 0x30 65938363Swpaul#define XL_PCI_INTLINE 0x3C 66038363Swpaul#define XL_PCI_INTPIN 0x3D 66138363Swpaul#define XL_PCI_MINGNT 0x3E 66238363Swpaul#define XL_PCI_MINLAT 0x0F 66338363Swpaul#define XL_PCI_RESETOPT 0x48 66438363Swpaul#define XL_PCI_EEPROM_DATA 0x4C 66538363Swpaul 66638363Swpaul/* 3c905B-only registers */ 66738363Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 66838363Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 66938363Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 67038363Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 67138363Swpaul 67238363Swpaul#define XL_PSTATE_MASK 0x0003 67338363Swpaul#define XL_PSTATE_D0 0x0000 67438363Swpaul#define XL_PSTATE_D1 0x0002 67538363Swpaul#define XL_PSTATE_D2 0x0002 67638363Swpaul#define XL_PSTATE_D3 0x0003 67738363Swpaul#define XL_PME_EN 0x0010 67838363Swpaul#define XL_PME_STATUS 0x8000 67938363Swpaul 68045062Swpaul#ifdef __alpha__ 68145062Swpaul#undef vtophys 68247529Sgallatin#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 68347529Sgallatin 68445062Swpaul#endif 68546204Swpaul 68646204Swpaul#ifndef IFM_10_FL 68746204Swpaul#define IFM_10_FL 13 /* 10baseFL - Fiber */ 68846204Swpaul#endif 689