if_xlreg.h revision 50477
11541Srgrimes/* 21541Srgrimes * Copyright (c) 1997, 1998 31541Srgrimes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 41541Srgrimes * 51541Srgrimes * Redistribution and use in source and binary forms, with or without 61541Srgrimes * modification, are permitted provided that the following conditions 71541Srgrimes * are met: 81541Srgrimes * 1. Redistributions of source code must retain the above copyright 91541Srgrimes * notice, this list of conditions and the following disclaimer. 101541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111541Srgrimes * notice, this list of conditions and the following disclaimer in the 121541Srgrimes * documentation and/or other materials provided with the distribution. 131541Srgrimes * 3. All advertising materials mentioning features or use of this software 141541Srgrimes * must display the following acknowledgement: 151541Srgrimes * This product includes software developed by Bill Paul. 161541Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 171541Srgrimes * may be used to endorse or promote products derived from this software 181541Srgrimes * without specific prior written permission. 191541Srgrimes * 201541Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 211541Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221541Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231541Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 241541Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251541Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261541Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271541Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281541Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291541Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 301541Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 311541Srgrimes * 321541Srgrimes * $FreeBSD: head/sys/pci/if_xlreg.h 50477 1999-08-28 01:08:13Z peter $ 331541Srgrimes */ 341541Srgrimes 351541Srgrimes#define XL_EE_READ 0x0080 /* read, 5 bit address */ 361541Srgrimes#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 371541Srgrimes#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 381541Srgrimes#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 393148Sphk#define XL_EE_BUSY 0x8000 401541Srgrimes 411541Srgrimes#define XL_EE_EADDR0 0x00 /* station address, first word */ 421541Srgrimes#define XL_EE_EADDR1 0x01 /* station address, next word, */ 432112Swollman#define XL_EE_EADDR2 0x02 /* station address, last word */ 441541Srgrimes#define XL_EE_PRODID 0x03 /* product ID code */ 451541Srgrimes#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 461541Srgrimes#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 471541Srgrimes#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 481541Srgrimes#define XL_EE_MFG_ID 0x07 491541Srgrimes#define XL_EE_PCI_PARM 0x08 501541Srgrimes#define XL_EE_ROM_ONFO 0x09 511541Srgrimes#define XL_EE_OEM_ADR0 0x0A 521541Srgrimes#define XL_EE_OEM_ADR1 0x0B 531541Srgrimes#define XL_EE_OEM_ADR2 0x0C 541541Srgrimes#define XL_EE_SOFTINFO1 0x0D 551541Srgrimes#define XL_EE_COMPAT 0x0E 561541Srgrimes#define XL_EE_SOFTINFO2 0x0F 571541Srgrimes#define XL_EE_CAPS 0x10 /* capabilities word */ 581541Srgrimes#define XL_EE_RSVD0 0x11 591541Srgrimes#define XL_EE_ICFG_0 0x12 601541Srgrimes#define XL_EE_ICFG_1 0x13 611541Srgrimes#define XL_EE_RSVD1 0x14 621541Srgrimes#define XL_EE_SOFTINFO3 0x15 631541Srgrimes#define XL_EE_RSVD_2 0x16 641541Srgrimes 651541Srgrimes/* 661541Srgrimes * Bits in the capabilities word 671541Srgrimes */ 681541Srgrimes#define XL_CAPS_PNP 0x0001 691541Srgrimes#define XL_CAPS_FULL_DUPLEX 0x0002 701541Srgrimes#define XL_CAPS_LARGE_PKTS 0x0004 711541Srgrimes#define XL_CAPS_SLAVE_DMA 0x0008 721541Srgrimes#define XL_CAPS_SECOND_DMA 0x0010 731541Srgrimes#define XL_CAPS_FULL_BM 0x0020 741541Srgrimes#define XL_CAPS_FRAG_BM 0x0040 751541Srgrimes#define XL_CAPS_CRC_PASSTHRU 0x0080 761541Srgrimes#define XL_CAPS_TXDONE 0x0100 771541Srgrimes#define XL_CAPS_NO_TXLENGTH 0x0200 781541Srgrimes#define XL_CAPS_RX_REPEAT 0x0400 791541Srgrimes#define XL_CAPS_SNOOPING 0x0800 801541Srgrimes#define XL_CAPS_100MBPS 0x1000 811541Srgrimes#define XL_CAPS_PWRMGMT 0x2000 821541Srgrimes 831541Srgrimes#define XL_PACKET_SIZE 1536 841541Srgrimes 851541Srgrimes/* 861541Srgrimes * Register layouts. 871541Srgrimes */ 881541Srgrimes#define XL_COMMAND 0x0E 891541Srgrimes#define XL_STATUS 0x0E 901541Srgrimes 911541Srgrimes#define XL_TX_STATUS 0x1B 921541Srgrimes#define XL_TX_FREE 0x1C 931541Srgrimes#define XL_DMACTL 0x20 941541Srgrimes#define XL_DOWNLIST_PTR 0x24 951541Srgrimes#define XL_TX_FREETHRESH 0x2F 961541Srgrimes#define XL_UPLIST_PTR 0x38 971541Srgrimes#define XL_UPLIST_STATUS 0x30 981541Srgrimes 991541Srgrimes#define XL_PKTSTAT_UP_STALLED 0x00002000 1001541Srgrimes#define XL_PKTSTAT_UP_ERROR 0x00004000 1011541Srgrimes#define XL_PKTSTAT_UP_CMPLT 0x00008000 1021541Srgrimes 1031541Srgrimes#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 1041541Srgrimes#define XL_DMACTL_DOWN_STALLED 0x00000004 1051541Srgrimes#define XL_DMACTL_UP_CMPLT 0x00000008 1061541Srgrimes#define XL_DMACTL_DOWN_CMPLT 0x00000010 1071541Srgrimes#define XL_DMACTL_UP_RX_EARLY 0x00000020 1081541Srgrimes#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 1092142Sdg#define XL_DMACTL_DOWN_INPROG 0x00000080 1101541Srgrimes#define XL_DMACTL_COUNTER_SPEED 0x00000100 1111541Srgrimes#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 1122142Sdg#define XL_DMACTL_TARGET_ABORT 0x40000000 1131541Srgrimes#define XL_DMACTL_MASTER_ABORT 0x80000000 1141541Srgrimes 1151541Srgrimes/* 1161541Srgrimes * Command codes. Some command codes require that we wait for 1171541Srgrimes * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 1181541Srgrimes */ 1191541Srgrimes#define XL_CMD_RESET 0x0000 /* mustwait */ 1201541Srgrimes#define XL_CMD_WINSEL 0x0800 1211541Srgrimes#define XL_CMD_COAX_START 0x1000 1221541Srgrimes#define XL_CMD_RX_DISABLE 0x1800 1231541Srgrimes#define XL_CMD_RX_ENABLE 0x2000 1241541Srgrimes#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 1251541Srgrimes#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 1261541Srgrimes#define XL_CMD_UP_UNSTALL 0x3001 1271541Srgrimes#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 1281541Srgrimes#define XL_CMD_DOWN_UNSTALL 0x3003 1291541Srgrimes#define XL_CMD_RX_DISCARD 0x4000 1301541Srgrimes#define XL_CMD_TX_ENABLE 0x4800 1311541Srgrimes#define XL_CMD_TX_DISABLE 0x5000 1321541Srgrimes#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 1331541Srgrimes#define XL_CMD_INTR_FAKE 0x6000 1341541Srgrimes#define XL_CMD_INTR_ACK 0x6800 1351541Srgrimes#define XL_CMD_INTR_ENB 0x7000 1361541Srgrimes#define XL_CMD_STAT_ENB 0x7800 1371541Srgrimes#define XL_CMD_RX_SET_FILT 0x8000 1381541Srgrimes#define XL_CMD_RX_SET_THRESH 0x8800 1391541Srgrimes#define XL_CMD_TX_SET_THRESH 0x9000 1401541Srgrimes#define XL_CMD_TX_SET_START 0x9800 1411541Srgrimes#define XL_CMD_DMA_UP 0xA000 1421541Srgrimes#define XL_CMD_DMA_STOP 0xA001 1431541Srgrimes#define XL_CMD_STATS_ENABLE 0xA800 1441541Srgrimes#define XL_CMD_STATS_DISABLE 0xB000 1451541Srgrimes#define XL_CMD_COAX_STOP 0xB800 1461541Srgrimes 1473148Sphk#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 1483148Sphk#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 1491541Srgrimes 1501541Srgrimes#define XL_HASH_SET 0x0400 1511541Srgrimes#define XL_HASHFILT_SIZE 256 1521541Srgrimes 1531541Srgrimes/* 1541541Srgrimes * status codes 1551541Srgrimes * Note that bits 15 to 13 indicate the currently visible register window 1561541Srgrimes * which may be anything from 0 to 7. 1571541Srgrimes */ 1581541Srgrimes#define XL_STAT_INTLATCH 0x0001 /* 0 */ 1591541Srgrimes#define XL_STAT_ADFAIL 0x0002 /* 1 */ 1601541Srgrimes#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 1611541Srgrimes#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 1621541Srgrimes#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 1631541Srgrimes#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 1641541Srgrimes#define XL_STAT_INTREQ 0x0040 /* 6 */ 1651541Srgrimes#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 1661541Srgrimes#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 1671541Srgrimes#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 1681541Srgrimes#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 1691541Srgrimes#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 1701541Srgrimes#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 1711541Srgrimes#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 1721541Srgrimes 1731541Srgrimes/* 1741541Srgrimes * Interrupts we normally want enabled. 1751541Srgrimes */ 1761541Srgrimes#define XL_INTRS \ 1771541Srgrimes (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 1781541Srgrimes XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 1791541Srgrimes 1801541Srgrimes/* 1813148Sphk * Window 0 registers 1823148Sphk */ 1831541Srgrimes#define XL_W0_EE_DATA 0x0C 1841541Srgrimes#define XL_W0_EE_CMD 0x0A 1851541Srgrimes#define XL_W0_RSRC_CFG 0x08 1861541Srgrimes#define XL_W0_ADDR_CFG 0x06 1871541Srgrimes#define XL_W0_CFG_CTRL 0x04 1881541Srgrimes 1891541Srgrimes#define XL_W0_PROD_ID 0x02 1901541Srgrimes#define XL_W0_MFG_ID 0x00 1911541Srgrimes 1921541Srgrimes/* 1931541Srgrimes * Window 1 1941541Srgrimes */ 1951541Srgrimes 1961541Srgrimes#define XL_W1_TX_FIFO 0x10 1971541Srgrimes 1981541Srgrimes#define XL_W1_FREE_TX 0x0C 1991541Srgrimes#define XL_W1_TX_STATUS 0x0B 2001541Srgrimes#define XL_W1_TX_TIMER 0x0A 2011541Srgrimes#define XL_W1_RX_STATUS 0x08 2021541Srgrimes#define XL_W1_RX_FIFO 0x00 2031541Srgrimes 2041541Srgrimes/* 2051541Srgrimes * RX status codes 2061541Srgrimes */ 2071541Srgrimes#define XL_RXSTATUS_OVERRUN 0x01 2081541Srgrimes#define XL_RXSTATUS_RUNT 0x02 2091541Srgrimes#define XL_RXSTATUS_ALIGN 0x04 2101541Srgrimes#define XL_RXSTATUS_CRC 0x08 2111541Srgrimes#define XL_RXSTATUS_OVERSIZE 0x10 2121541Srgrimes#define XL_RXSTATUS_DRIBBLE 0x20 2131541Srgrimes 2141541Srgrimes/* 2151541Srgrimes * TX status codes 2161541Srgrimes */ 2171541Srgrimes#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 2181541Srgrimes#define XL_TXSTATUS_OVERFLOW 0x04 2191541Srgrimes#define XL_TXSTATUS_MAXCOLS 0x08 2201541Srgrimes#define XL_TXSTATUS_UNDERRUN 0x10 2211541Srgrimes#define XL_TXSTATUS_JABBER 0x20 2221541Srgrimes#define XL_TXSTATUS_INTREQ 0x40 2231541Srgrimes#define XL_TXSTATUS_COMPLETE 0x80 2241541Srgrimes 2251541Srgrimes/* 2261541Srgrimes * Window 2 2271541Srgrimes */ 2281541Srgrimes#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 2291541Srgrimes#define XL_W2_STATION_MASK_HI 0x0A 2301541Srgrimes#define XL_W2_STATION_MASK_MID 0x08 2311541Srgrimes#define XL_W2_STATION_MASK_LO 0x06 2321541Srgrimes#define XL_W2_STATION_ADDR_HI 0x04 2331541Srgrimes#define XL_W2_STATION_ADDR_MID 0x02 2341541Srgrimes#define XL_W2_STATION_ADDR_LO 0x00 2351541Srgrimes 2361541Srgrimes#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 2371541Srgrimes#define XL_RESETOPT_D3RESETDIS 0x0008 2381541Srgrimes#define XL_RESETOPT_DISADVFD 0x0010 2391541Srgrimes#define XL_RESETOPT_DISADV100 0x0020 2401541Srgrimes#define XL_RESETOPT_DISAUTONEG 0x0040 2411541Srgrimes#define XL_RESETOPT_DEBUGMODE 0x0080 2421541Srgrimes#define XL_RESETOPT_FASTAUTO 0x0100 2431541Srgrimes#define XL_RESETOPT_FASTEE 0x0200 2441541Srgrimes#define XL_RESETOPT_FORCEDCONF 0x0400 2451541Srgrimes#define XL_RESETOPT_TESTPDTPDR 0x0800 2461541Srgrimes#define XL_RESETOPT_TEST100TX 0x1000 2471541Srgrimes#define XL_RESETOPT_TEST100RX 0x2000 2481541Srgrimes 2491541Srgrimes/* 2501541Srgrimes * Window 3 (fifo management) 2511541Srgrimes */ 2521541Srgrimes#define XL_W3_INTERNAL_CFG 0x00 2531541Srgrimes#define XL_W3_RESET_OPT 0x08 2541541Srgrimes#define XL_W3_FREE_TX 0x0C 2551541Srgrimes#define XL_W3_FREE_RX 0x0A 2561541Srgrimes#define XL_W3_MAC_CTRL 0x06 2571541Srgrimes 2581541Srgrimes#define XL_ICFG_CONNECTOR_MASK 0x00F00000 2591541Srgrimes#define XL_ICFG_CONNECTOR_BITS 20 2601541Srgrimes 2611541Srgrimes#define XL_ICFG_RAMSIZE_MASK 0x00000007 2621541Srgrimes#define XL_ICFG_RAMWIDTH 0x00000008 2631541Srgrimes#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 2641541Srgrimes#define XL_ICFG_DISABLE_BASSD 0x00000100 2651541Srgrimes#define XL_ICFG_RAMLOC 0x00000200 2661541Srgrimes#define XL_ICFG_RAMPART (0x00010000|0x00020000) 2671541Srgrimes#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 2681541Srgrimes#define XL_ICFG_AUTOSEL 0x01000000 2691541Srgrimes 2701541Srgrimes#define XL_XCVR_10BT 0x00 2711541Srgrimes#define XL_XCVR_AUI 0x01 2721541Srgrimes#define XL_XCVR_RSVD_0 0x02 2731541Srgrimes#define XL_XCVR_COAX 0x03 2741541Srgrimes#define XL_XCVR_100BTX 0x04 2751541Srgrimes#define XL_XCVR_100BFX 0x05 2761541Srgrimes#define XL_XCVR_MII 0x06 2771541Srgrimes#define XL_XCVR_RSVD_1 0x07 2781541Srgrimes#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 2791541Srgrimes 2801541Srgrimes#define XL_MACCTRL_DEFER_EXT_END 0x0001 2811541Srgrimes#define XL_MACCTRL_DEFER_0 0x0002 2821541Srgrimes#define XL_MACCTRL_DEFER_1 0x0004 2831541Srgrimes#define XL_MACCTRL_DEFER_2 0x0008 2841541Srgrimes#define XL_MACCTRL_DEFER_3 0x0010 2851541Srgrimes#define XL_MACCTRL_DUPLEX 0x0020 2861541Srgrimes#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 2871541Srgrimes#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 2881541Srgrimes#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 2891541Srgrimes#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 2901541Srgrimes 2911541Srgrimes/* 2921541Srgrimes * The 'reset options' register contains power-on reset values 2931541Srgrimes * loaded from the EEPROM. This includes the supported media 2941541Srgrimes * types on the card. It is also known as the media options register. 2951541Srgrimes */ 2961541Srgrimes#define XL_W3_MEDIA_OPT 0x08 2971541Srgrimes 2981541Srgrimes#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 2991541Srgrimes#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 3001541Srgrimes#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 3011541Srgrimes#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 3021541Srgrimes#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 3031541Srgrimes#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 3041541Srgrimes#define XL_MEDIAOPT_MII 0x0040 /* MII */ 3051541Srgrimes#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 3061541Srgrimes 3071541Srgrimes#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 3081541Srgrimes#define XL_MEDIAOPT_MASK 0x01FF 3091541Srgrimes 3101541Srgrimes/* 3111541Srgrimes * Window 4 (diagnostics) 3121541Srgrimes */ 3131541Srgrimes#define XL_W4_UPPERBYTESOK 0x0D 3141541Srgrimes#define XL_W4_BADSSD 0x0C 3151541Srgrimes#define XL_W4_MEDIA_STATUS 0x0A 3161541Srgrimes#define XL_W4_PHY_MGMT 0x08 3171541Srgrimes#define XL_W4_NET_DIAG 0x06 3181541Srgrimes#define XL_W4_FIFO_DIAG 0x04 3191541Srgrimes#define XL_W4_VCO_DIAG 0x02 3201541Srgrimes 3211541Srgrimes#define XL_W4_CTRLR_STAT 0x08 3221541Srgrimes#define XL_W4_TX_DIAG 0x00 3231541Srgrimes 3241541Srgrimes#define XL_MII_CLK 0x01 3251541Srgrimes#define XL_MII_DATA 0x02 3261541Srgrimes#define XL_MII_DIR 0x04 3271541Srgrimes 3281541Srgrimes#define XL_MEDIA_SQE 0x0008 3291541Srgrimes#define XL_MEDIA_10TP 0x00C0 3301541Srgrimes#define XL_MEDIA_LNK 0x0080 3311541Srgrimes#define XL_MEDIA_LNKBEAT 0x0800 3321541Srgrimes 3331541Srgrimes#define XL_MEDIASTAT_CRCSTRIP 0x0004 3341541Srgrimes#define XL_MEDIASTAT_SQEENB 0x0008 3351541Srgrimes#define XL_MEDIASTAT_COLDET 0x0010 3361541Srgrimes#define XL_MEDIASTAT_CARRIER 0x0020 3371541Srgrimes#define XL_MEDIASTAT_JABGUARD 0x0040 3381541Srgrimes#define XL_MEDIASTAT_LINKBEAT 0x0080 3391541Srgrimes#define XL_MEDIASTAT_JABDETECT 0x0200 3401541Srgrimes#define XL_MEDIASTAT_POLREVERS 0x0400 3411541Srgrimes#define XL_MEDIASTAT_LINKDETECT 0x0800 3421541Srgrimes#define XL_MEDIASTAT_TXINPROG 0x1000 3431541Srgrimes#define XL_MEDIASTAT_DCENB 0x4000 3441541Srgrimes#define XL_MEDIASTAT_AUIDIS 0x8000 3451541Srgrimes 3461541Srgrimes#define XL_NETDIAG_TEST_LOWVOLT 0x0001 3471541Srgrimes#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 3481541Srgrimes#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 3491541Srgrimes#define XL_NETDIAG_STATS_ENABLED 0x0080 3501541Srgrimes#define XL_NETDIAG_TX_FATALERR 0x0100 3511541Srgrimes#define XL_NETDIAG_TRANSMITTING 0x0200 3521541Srgrimes#define XL_NETDIAG_RX_ENABLED 0x0400 3531541Srgrimes#define XL_NETDIAG_TX_ENABLED 0x0800 3541541Srgrimes#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 3551541Srgrimes#define XL_NETDIAG_MAC_LOOPBACK 0x2000 3561541Srgrimes#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 3571541Srgrimes#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 3581541Srgrimes 3591541Srgrimes/* 3601541Srgrimes * Window 5 3611541Srgrimes */ 3621541Srgrimes#define XL_W5_STAT_ENB 0x0C 3631541Srgrimes#define XL_W5_INTR_ENB 0x0A 3641541Srgrimes#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 3651541Srgrimes#define XL_W5_RX_FILTER 0x08 3661541Srgrimes#define XL_W5_RX_EARLYTHRESH 0x06 3671541Srgrimes#define XL_W5_TX_AVAILTHRESH 0x02 3681541Srgrimes#define XL_W5_TX_STARTTHRESH 0x00 3691541Srgrimes 3701541Srgrimes/* 3711541Srgrimes * RX filter bits 3721541Srgrimes */ 3731541Srgrimes#define XL_RXFILTER_INDIVIDUAL 0x01 3741541Srgrimes#define XL_RXFILTER_ALLMULTI 0x02 3751541Srgrimes#define XL_RXFILTER_BROADCAST 0x04 3761541Srgrimes#define XL_RXFILTER_ALLFRAMES 0x08 3771541Srgrimes#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 3781541Srgrimes 3793148Sphk/* 3803148Sphk * Window 6 (stats) 3811541Srgrimes */ 3821541Srgrimes#define XL_W6_TX_BYTES_OK 0x0C 3831541Srgrimes#define XL_W6_RX_BYTES_OK 0x0A 3841541Srgrimes#define XL_W6_UPPER_FRAMES_OK 0x09 3851541Srgrimes#define XL_W6_DEFERRED 0x08 3861541Srgrimes#define XL_W6_RX_OK 0x07 3871541Srgrimes#define XL_W6_TX_OK 0x06 3881541Srgrimes#define XL_W6_RX_OVERRUN 0x05 3891541Srgrimes#define XL_W6_COL_LATE 0x04 3901541Srgrimes#define XL_W6_COL_SINGLE 0x03 3911541Srgrimes#define XL_W6_COL_MULTIPLE 0x02 3921541Srgrimes#define XL_W6_SQE_ERRORS 0x01 3931541Srgrimes#define XL_W6_CARRIER_LOST 0x00 3941541Srgrimes 3951541Srgrimes/* 3961541Srgrimes * Window 7 (bus master control) 3971541Srgrimes */ 3981541Srgrimes#define XL_W7_BM_ADDR 0x00 3991541Srgrimes#define XL_W7_BM_LEN 0x06 4001541Srgrimes#define XL_W7_BM_STATUS 0x0B 4011541Srgrimes#define XL_W7_BM_TIMEr 0x0A 4021541Srgrimes 4031541Srgrimes/* 4041541Srgrimes * bus master control registers 4051541Srgrimes */ 4061541Srgrimes#define XL_BM_PKTSTAT 0x20 4071541Srgrimes#define XL_BM_DOWNLISTPTR 0x24 4081541Srgrimes#define XL_BM_FRAGADDR 0x28 4091541Srgrimes#define XL_BM_FRAGLEN 0x2C 4101541Srgrimes#define XL_BM_TXFREETHRESH 0x2F 4111541Srgrimes#define XL_BM_UPPKTSTAT 0x30 4121541Srgrimes#define XL_BM_UPLISTPTR 0x38 4131541Srgrimes 4141541Srgrimes#define XL_LAST_FRAG 0x80000000 4151541Srgrimes 4161541Srgrimes/* 4171541Srgrimes * Boomerang/Cyclone TX/RX list structure. 4181541Srgrimes * For the TX lists, bits 0 to 12 of the status word indicate 4191541Srgrimes * length. 4201541Srgrimes * This looks suspiciously like the ThunderLAN, doesn't it. 4211541Srgrimes */ 4221541Srgrimesstruct xl_frag { 4231541Srgrimes u_int32_t xl_addr; /* 63 addr/len pairs */ 4241541Srgrimes u_int32_t xl_len; 4251541Srgrimes}; 4261541Srgrimes 4271541Srgrimesstruct xl_list { 4281541Srgrimes u_int32_t xl_next; /* final entry has 0 nextptr */ 4291541Srgrimes u_int32_t xl_status; 4301541Srgrimes struct xl_frag xl_frag[63]; 4311541Srgrimes}; 4321541Srgrimes 4331541Srgrimesstruct xl_list_onefrag { 4341541Srgrimes u_int32_t xl_next; /* final entry has 0 nextptr */ 4351541Srgrimes u_int32_t xl_status; 4361541Srgrimes struct xl_frag xl_frag; 4371541Srgrimes}; 4381541Srgrimes 4391541Srgrimes#define XL_MAXFRAGS 63 4401541Srgrimes#define XL_RX_LIST_CNT 128 4411541Srgrimes#define XL_TX_LIST_CNT 256 4421541Srgrimes#define XL_MIN_FRAMELEN 60 4431541Srgrimes 4441541Srgrimesstruct xl_list_data { 4451541Srgrimes struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 4461541Srgrimes struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 4471541Srgrimes unsigned char xl_pad[XL_MIN_FRAMELEN]; 4481541Srgrimes}; 4491541Srgrimes 4501541Srgrimesstruct xl_chain { 4511541Srgrimes struct xl_list *xl_ptr; 4521541Srgrimes struct mbuf *xl_mbuf; 4531541Srgrimes struct xl_chain *xl_next; 4541541Srgrimes}; 4551541Srgrimes 4563148Sphkstruct xl_chain_onefrag { 4573148Sphk struct xl_list_onefrag *xl_ptr; 4581541Srgrimes struct mbuf *xl_mbuf; 4591541Srgrimes struct xl_chain_onefrag *xl_next; 4601541Srgrimes}; 4611541Srgrimes 4621541Srgrimesstruct xl_chain_data { 4631541Srgrimes struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 4641541Srgrimes struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 4651541Srgrimes 4661541Srgrimes struct xl_chain_onefrag *xl_rx_head; 4671541Srgrimes 4681541Srgrimes struct xl_chain *xl_tx_head; 4691541Srgrimes struct xl_chain *xl_tx_tail; 4701541Srgrimes struct xl_chain *xl_tx_free; 4711541Srgrimes}; 4721541Srgrimes 4731541Srgrimes#define XL_RXSTAT_LENMASK 0x00001FFF 4741541Srgrimes#define XL_RXSTAT_UP_ERROR 0x00004000 4751541Srgrimes#define XL_RXSTAT_UP_CMPLT 0x00008000 4761541Srgrimes#define XL_RXSTAT_UP_OVERRUN 0x00010000 4771541Srgrimes#define XL_RXSTAT_RUNT 0x00020000 4781541Srgrimes#define XL_RXSTAT_ALIGN 0x00040000 4791541Srgrimes#define XL_RXSTAT_CRC 0x00080000 4801541Srgrimes#define XL_RXSTAT_OVERSIZE 0x00100000 4811541Srgrimes#define XL_RXSTAT_DRIBBLE 0x00800000 4821541Srgrimes#define XL_RXSTAT_UP_OFLOW 0x01000000 4831541Srgrimes#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 4841541Srgrimes#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 4851541Srgrimes#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 4861541Srgrimes#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 4871541Srgrimes#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 4881541Srgrimes#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 4891541Srgrimes#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 4901541Srgrimes 4911541Srgrimes#define XL_TXSTAT_LENMASK 0x00001FFF 4921541Srgrimes#define XL_TXSTAT_CRCDIS 0x00002000 4931541Srgrimes#define XL_TXSTAT_TX_INTR 0x00008000 4941541Srgrimes#define XL_TXSTAT_DL_COMPLETE 0x00010000 4951541Srgrimes#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 4961541Srgrimes#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 4971541Srgrimes#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 4981541Srgrimes#define XL_TXSTAT_DL_INTR 0x80000000 4991541Srgrimes 5001541Srgrimes#define XL_CAPABILITY_BM 0x20 5011541Srgrimes 5021541Srgrimes 5031541Srgrimesstruct xl_type { 5041541Srgrimes u_int16_t xl_vid; 5051541Srgrimes u_int16_t xl_did; 5061541Srgrimes char *xl_name; 5071541Srgrimes}; 5081541Srgrimes 5091541Srgrimesstruct xl_mii_frame { 5101541Srgrimes u_int8_t mii_stdelim; 5111541Srgrimes u_int8_t mii_opcode; 5123148Sphk u_int8_t mii_phyaddr; 5133148Sphk u_int8_t mii_regaddr; 5143148Sphk u_int8_t mii_turnaround; 5153148Sphk u_int16_t mii_data; 5163148Sphk}; 5173148Sphk 5183148Sphk/* 5193148Sphk * MII constants 5203148Sphk */ 5213148Sphk#define XL_MII_STARTDELIM 0x01 5223148Sphk#define XL_MII_READOP 0x02 5233148Sphk#define XL_MII_WRITEOP 0x01 5243148Sphk#define XL_MII_TURNAROUND 0x02 5253148Sphk 5263148Sphk/* 5273148Sphk * The 3C905B adapters implement a few features that we want to 5283148Sphk * take advantage of, namely the multicast hash filter. With older 5293148Sphk * chips, you only have the option of turning on reception of all 5301541Srgrimes * multicast frames, which is kind of lame. 5313148Sphk */ 5323148Sphk#define XL_TYPE_905B 1 5333148Sphk#define XL_TYPE_90X 2 5343148Sphk 5353148Sphk#define XL_FLAG_FORCEDELAY 1 5363148Sphk#define XL_FLAG_SCHEDDELAY 2 5373148Sphk#define XL_FLAG_DELAYTIMEO 3 5383148Sphk 5393148Sphkstruct xl_softc { 5403148Sphk struct arpcom arpcom; /* interface info */ 5413148Sphk struct ifmedia ifmedia; /* media info */ 5423148Sphk bus_space_handle_t xl_bhandle; 5433148Sphk bus_space_tag_t xl_btag; 5443148Sphk void *xl_intrhand; 5453148Sphk struct resource *xl_irq; 5463148Sphk struct resource *xl_res; 5473148Sphk struct xl_type *xl_info; /* 3Com adapter info */ 5483148Sphk struct xl_type *xl_pinfo; /* phy info */ 5493148Sphk u_int8_t xl_unit; /* interface number */ 5503148Sphk u_int8_t xl_type; 5513148Sphk u_int8_t xl_phy_addr; /* PHY address */ 5523148Sphk u_int32_t xl_xcvr; 5533148Sphk u_int16_t xl_media; 5543148Sphk u_int16_t xl_caps; 5553148Sphk u_int8_t xl_tx_pend; /* TX pending */ 5563148Sphk u_int8_t xl_want_auto; 5573148Sphk u_int8_t xl_autoneg; 5583148Sphk u_int8_t xl_stats_no_timeout; 5593148Sphk u_int16_t xl_tx_thresh; 5603148Sphk caddr_t xl_ldata_ptr; 5613148Sphk struct xl_list_data *xl_ldata; 5623148Sphk struct xl_chain_data xl_cdata; 5633148Sphk struct callout_handle xl_stat_ch; 5643148Sphk}; 5653148Sphk 5663148Sphk#define xl_rx_goodframes(x) \ 5673148Sphk ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 5683148Sphk 5693148Sphk#define xl_tx_goodframes(x) \ 5703148Sphk ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 5713148Sphk 5723148Sphkstruct xl_stats { 5733148Sphk u_int8_t xl_carrier_lost; 5743148Sphk u_int8_t xl_sqe_errs; 5753148Sphk u_int8_t xl_tx_multi_collision; 5763148Sphk u_int8_t xl_tx_single_collision; 5773148Sphk u_int8_t xl_tx_late_collision; 5783148Sphk u_int8_t xl_rx_overrun; 5793148Sphk u_int8_t xl_tx_frames_ok; 5803148Sphk u_int8_t xl_rx_frames_ok; 5813148Sphk u_int8_t xl_tx_deferred; 5823148Sphk u_int8_t xl_upper_frames_ok; 5833148Sphk u_int16_t xl_rx_bytes_ok; 5843148Sphk u_int16_t xl_tx_bytes_ok; 5853148Sphk u_int16_t status; 5863148Sphk}; 5873148Sphk 5883148Sphk/* 5893148Sphk * register space access macros 5903148Sphk */ 5913148Sphk#define CSR_WRITE_4(sc, reg, val) \ 5923148Sphk bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 5933148Sphk#define CSR_WRITE_2(sc, reg, val) \ 5943148Sphk bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 5953148Sphk#define CSR_WRITE_1(sc, reg, val) \ 5963148Sphk bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 5973148Sphk 5983148Sphk#define CSR_READ_4(sc, reg) \ 5993148Sphk bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 6003148Sphk#define CSR_READ_2(sc, reg) \ 6013148Sphk bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 6023148Sphk#define CSR_READ_1(sc, reg) \ 6033148Sphk bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 6043148Sphk 6053148Sphk#define XL_SEL_WIN(x) \ 6063148Sphk CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 6073148Sphk#define XL_TIMEOUT 1000 6083148Sphk 6093148Sphk/* 6103148Sphk * General constants that are fun to know. 6113148Sphk * 6123148Sphk * 3Com PCI vendor ID 6133148Sphk */ 6143148Sphk#define TC_VENDORID 0x10B7 6153148Sphk 6163148Sphk/* 6173148Sphk * 3Com chip device IDs. 6183148Sphk */ 6193148Sphk#define TC_DEVICEID_BOOMERANG_10BT 0x9000 6203148Sphk#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 6213148Sphk#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 6223148Sphk#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 6233148Sphk#define TC_DEVICEID_KRAKATOA_10BT 0x9004 6243148Sphk#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 6253148Sphk#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 6263148Sphk#define TC_DEVICEID_CYCLONE_10FL 0x900A 6273148Sphk#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 6283148Sphk#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 6293148Sphk#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 6303148Sphk#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 6313148Sphk#define TC_DEVICEID_TORNADO_10_100BT 0x9200 6323148Sphk#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 6333148Sphk#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 6343148Sphk 6353148Sphk/* 6363148Sphk * Texas Instruments PHY identifiers 6373148Sphk * 6383148Sphk * The ThunderLAN manual has a curious and confusing error in it. 6393148Sphk * In chapter 7, which describes PHYs, it says that TI PHYs have 6403148Sphk * the following ID codes, where xx denotes a revision: 6413148Sphk * 6423148Sphk * 0x4000501xx internal 10baseT PHY 6433148Sphk * 0x4000502xx TNETE211 100VG-AnyLan PMI 6443148Sphk * 6453148Sphk * The problem here is that these are not valid 32-bit hex numbers: 6463148Sphk * there's one digit too many. My guess is that they mean the internal 6473148Sphk * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 6483148Sphk * are the only numbers that make sense. 6493148Sphk */ 6503148Sphk#define TI_PHY_VENDORID 0x4000 6513148Sphk#define TI_PHY_10BT 0x501F 6523148Sphk#define TI_PHY_100VGPMI 0x502F 6533148Sphk 6543148Sphk/* 6553148Sphk * These ID values are for the NS DP83840A 10/100 PHY 6563148Sphk */ 6573148Sphk#define NS_PHY_VENDORID 0x2000 6583148Sphk#define NS_PHY_83840A 0x5C0F 6593148Sphk 6603148Sphk/* 6613148Sphk * Level 1 10/100 PHY 6623148Sphk */ 6633148Sphk#define LEVEL1_PHY_VENDORID 0x7810 664#define LEVEL1_PHY_LXT970 0x000F 665 666/* 667 * Intel 82555 10/100 PHY 668 */ 669#define INTEL_PHY_VENDORID 0x0A28 670#define INTEL_PHY_82555 0x015F 671 672/* 673 * SEEQ 80220 10/100 PHY 674 */ 675#define SEEQ_PHY_VENDORID 0x0016 676#define SEEQ_PHY_80220 0xF83F 677 678 679/* 680 * PCI low memory base and low I/O base register, and 681 * other PCI registers. Note: some are only available on 682 * the 3c905B, in particular those that related to power management. 683 */ 684 685#define XL_PCI_VENDOR_ID 0x00 686#define XL_PCI_DEVICE_ID 0x02 687#define XL_PCI_COMMAND 0x04 688#define XL_PCI_STATUS 0x06 689#define XL_PCI_CLASSCODE 0x09 690#define XL_PCI_LATENCY_TIMER 0x0D 691#define XL_PCI_HEADER_TYPE 0x0E 692#define XL_PCI_LOIO 0x10 693#define XL_PCI_LOMEM 0x14 694#define XL_PCI_BIOSROM 0x30 695#define XL_PCI_INTLINE 0x3C 696#define XL_PCI_INTPIN 0x3D 697#define XL_PCI_MINGNT 0x3E 698#define XL_PCI_MINLAT 0x0F 699#define XL_PCI_RESETOPT 0x48 700#define XL_PCI_EEPROM_DATA 0x4C 701 702/* 3c905B-only registers */ 703#define XL_PCI_CAPID 0xDC /* 8 bits */ 704#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 705#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 706#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 707 708#define XL_PSTATE_MASK 0x0003 709#define XL_PSTATE_D0 0x0000 710#define XL_PSTATE_D1 0x0002 711#define XL_PSTATE_D2 0x0002 712#define XL_PSTATE_D3 0x0003 713#define XL_PME_EN 0x0010 714#define XL_PME_STATUS 0x8000 715 716#define PHY_UNKNOWN 6 717 718#define XL_PHYADDR_MIN 0x00 719#define XL_PHYADDR_MAX 0x1F 720 721#define XL_PHY_GENCTL 0x00 722#define XL_PHY_GENSTS 0x01 723#define XL_PHY_VENID 0x02 724#define XL_PHY_DEVID 0x03 725#define XL_PHY_ANAR 0x04 726#define XL_PHY_LPAR 0x05 727#define XL_PHY_ANEXP 0x06 728 729#define PHY_ANAR_NEXTPAGE 0x8000 730#define PHY_ANAR_RSVD0 0x4000 731#define PHY_ANAR_TLRFLT 0x2000 732#define PHY_ANAR_RSVD1 0x1000 733#define PHY_ANAR_RSVD2 0x0800 734#define PHY_ANAR_RSVD3 0x0400 735#define PHY_ANAR_100BT4 0x0200 736#define PHY_ANAR_100BTXFULL 0x0100 737#define PHY_ANAR_100BTXHALF 0x0080 738#define PHY_ANAR_10BTFULL 0x0040 739#define PHY_ANAR_10BTHALF 0x0020 740#define PHY_ANAR_PROTO4 0x0010 741#define PHY_ANAR_PROTO3 0x0008 742#define PHY_ANAR_PROTO2 0x0004 743#define PHY_ANAR_PROTO1 0x0002 744#define PHY_ANAR_PROTO0 0x0001 745 746/* 747 * These are the register definitions for the PHY (physical layer 748 * interface chip). 749 */ 750/* 751 * PHY BMCR Basic Mode Control Register 752 */ 753#define PHY_BMCR 0x00 754#define PHY_BMCR_RESET 0x8000 755#define PHY_BMCR_LOOPBK 0x4000 756#define PHY_BMCR_SPEEDSEL 0x2000 757#define PHY_BMCR_AUTONEGENBL 0x1000 758#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 759#define PHY_BMCR_ISOLATE 0x0400 760#define PHY_BMCR_AUTONEGRSTR 0x0200 761#define PHY_BMCR_DUPLEX 0x0100 762#define PHY_BMCR_COLLTEST 0x0080 763#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 764#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 765#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 766#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 767#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 768#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 769#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 770/* 771 * RESET: 1 == software reset, 0 == normal operation 772 * Resets status and control registers to default values. 773 * Relatches all hardware config values. 774 * 775 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 776 * 777 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 778 * Link speed is selected byt his bit or if auto-negotiation if bit 779 * 12 (AUTONEGENBL) is set (in which case the value of this register 780 * is ignored). 781 * 782 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 783 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 784 * determine speed and mode. Should be cleared and then set if PHY configured 785 * for no autoneg on startup. 786 * 787 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 788 * 789 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 790 * 791 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 792 * 793 * COLLTEST: 1 == collision test enabled, 0 == normal operation 794 */ 795 796/* 797 * PHY, BMSR Basic Mode Status Register 798 */ 799#define PHY_BMSR 0x01 800#define PHY_BMSR_100BT4 0x8000 801#define PHY_BMSR_100BTXFULL 0x4000 802#define PHY_BMSR_100BTXHALF 0x2000 803#define PHY_BMSR_10BTFULL 0x1000 804#define PHY_BMSR_10BTHALF 0x0800 805#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 806#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 807#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 808#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 809#define PHY_BMSR_MFPRESUP 0x0040 810#define PHY_BMSR_AUTONEGCOMP 0x0020 811#define PHY_BMSR_REMFAULT 0x0010 812#define PHY_BMSR_CANAUTONEG 0x0008 813#define PHY_BMSR_LINKSTAT 0x0004 814#define PHY_BMSR_JABBER 0x0002 815#define PHY_BMSR_EXTENDED 0x0001 816 817#ifdef __alpha__ 818#undef vtophys 819#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 820 821#endif 822 823#ifndef IFM_10_FL 824#define IFM_10_FL 13 /* 10baseFL - Fiber */ 825#endif 826