if_xlreg.h revision 45062
138363Swpaul/* 238363Swpaul * Copyright (c) 1997, 1998 338363Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438363Swpaul * 538363Swpaul * Redistribution and use in source and binary forms, with or without 638363Swpaul * modification, are permitted provided that the following conditions 738363Swpaul * are met: 838363Swpaul * 1. Redistributions of source code must retain the above copyright 938363Swpaul * notice, this list of conditions and the following disclaimer. 1038363Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1138363Swpaul * notice, this list of conditions and the following disclaimer in the 1238363Swpaul * documentation and/or other materials provided with the distribution. 1338363Swpaul * 3. All advertising materials mentioning features or use of this software 1438363Swpaul * must display the following acknowledgement: 1538363Swpaul * This product includes software developed by Bill Paul. 1638363Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1738363Swpaul * may be used to endorse or promote products derived from this software 1838363Swpaul * without specific prior written permission. 1938363Swpaul * 2038363Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138363Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238363Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338363Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438363Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538363Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638363Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738363Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838363Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938363Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038363Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3138363Swpaul * 3245062Swpaul * $Id: if_xlreg.h,v 1.20 1999/03/27 20:10:10 wpaul Exp $ 3338363Swpaul */ 3438363Swpaul 3538363Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3638363Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3738363Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3838363Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3938363Swpaul#define XL_EE_BUSY 0x8000 4038363Swpaul 4138363Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4238363Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4338363Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4438363Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4538363Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4638363Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4738363Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4838363Swpaul#define XL_EE_MFG_ID 0x07 4938363Swpaul#define XL_EE_PCI_PARM 0x08 5038363Swpaul#define XL_EE_ROM_ONFO 0x09 5138363Swpaul#define XL_EE_OEM_ADR0 0x0A 5238363Swpaul#define XL_EE_OEM_ADR1 0x0B 5338363Swpaul#define XL_EE_OEM_ADR2 0x0C 5438363Swpaul#define XL_EE_SOFTINFO1 0x0D 5538363Swpaul#define XL_EE_COMPAT 0x0E 5638363Swpaul#define XL_EE_SOFTINFO2 0x0F 5738363Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5838363Swpaul#define XL_EE_RSVD0 0x11 5938363Swpaul#define XL_EE_ICFG_0 0x12 6038363Swpaul#define XL_EE_ICFG_1 0x13 6138363Swpaul#define XL_EE_RSVD1 0x14 6238363Swpaul#define XL_EE_SOFTINFO3 0x15 6338363Swpaul#define XL_EE_RSVD_2 0x16 6438363Swpaul 6538363Swpaul/* 6638363Swpaul * Bits in the capabilities word 6738363Swpaul */ 6838363Swpaul#define XL_CAPS_PNP 0x0001 6938363Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7038363Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7138363Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7238363Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7338363Swpaul#define XL_CAPS_FULL_BM 0x0020 7438363Swpaul#define XL_CAPS_FRAG_BM 0x0040 7538363Swpaul#define XL_CAPS_CRC_PASSTHRU 0x0080 7638363Swpaul#define XL_CAPS_TXDONE 0x0100 7738363Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7838363Swpaul#define XL_CAPS_RX_REPEAT 0x0400 7938363Swpaul#define XL_CAPS_SNOOPING 0x0800 8038363Swpaul#define XL_CAPS_100MBPS 0x1000 8138363Swpaul#define XL_CAPS_PWRMGMT 0x2000 8238363Swpaul 8338363Swpaul#define XL_PACKET_SIZE 1536 8438363Swpaul 8538363Swpaul/* 8638363Swpaul * Register layouts. 8738363Swpaul */ 8838363Swpaul#define XL_COMMAND 0x0E 8938363Swpaul#define XL_STATUS 0x0E 9038363Swpaul 9138363Swpaul#define XL_TX_STATUS 0x1B 9238363Swpaul#define XL_TX_FREE 0x1C 9338363Swpaul#define XL_DMACTL 0x20 9438363Swpaul#define XL_DOWNLIST_PTR 0x24 9538363Swpaul#define XL_TX_FREETHRESH 0x2F 9638363Swpaul#define XL_UPLIST_PTR 0x38 9738363Swpaul#define XL_UPLIST_STATUS 0x30 9838363Swpaul 9938363Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 10038363Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 10138363Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 10238363Swpaul 10338363Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10438363Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 10538363Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 10638363Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 10738363Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 10838363Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 10938363Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 11038363Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 11138363Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11238363Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 11338363Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 11438363Swpaul 11538363Swpaul/* 11638363Swpaul * Command codes. Some command codes require that we wait for 11738363Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 11838363Swpaul */ 11938363Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 12038363Swpaul#define XL_CMD_WINSEL 0x0800 12138363Swpaul#define XL_CMD_COAX_START 0x1000 12238363Swpaul#define XL_CMD_RX_DISABLE 0x1800 12338363Swpaul#define XL_CMD_RX_ENABLE 0x2000 12438363Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 12538363Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 12638363Swpaul#define XL_CMD_UP_UNSTALL 0x3001 12738363Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 12838363Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 12938363Swpaul#define XL_CMD_RX_DISCARD 0x4000 13038363Swpaul#define XL_CMD_TX_ENABLE 0x4800 13138363Swpaul#define XL_CMD_TX_DISABLE 0x5000 13238363Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 13338363Swpaul#define XL_CMD_INTR_FAKE 0x6000 13438363Swpaul#define XL_CMD_INTR_ACK 0x6800 13538363Swpaul#define XL_CMD_INTR_ENB 0x7000 13638363Swpaul#define XL_CMD_STAT_ENB 0x7800 13738363Swpaul#define XL_CMD_RX_SET_FILT 0x8000 13838363Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 13938363Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 14038363Swpaul#define XL_CMD_TX_SET_START 0x9800 14138363Swpaul#define XL_CMD_DMA_UP 0xA000 14238363Swpaul#define XL_CMD_DMA_STOP 0xA001 14338363Swpaul#define XL_CMD_STATS_ENABLE 0xA800 14438363Swpaul#define XL_CMD_STATS_DISABLE 0xB000 14538363Swpaul#define XL_CMD_COAX_STOP 0xB800 14638363Swpaul 14738363Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 14838363Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 14938363Swpaul 15038363Swpaul#define XL_HASH_SET 0x0400 15138363Swpaul#define XL_HASHFILT_SIZE 256 15238363Swpaul 15338363Swpaul/* 15438363Swpaul * status codes 15538363Swpaul * Note that bits 15 to 13 indicate the currently visible register window 15638363Swpaul * which may be anything from 0 to 7. 15738363Swpaul */ 15838363Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 15938363Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 16038363Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 16138363Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 16238363Swpaul#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 16338363Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 16438363Swpaul#define XL_STAT_INTREQ 0x0040 /* 6 */ 16538363Swpaul#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16638363Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 16738363Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 16838363Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 16938363Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 17038363Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 17138363Swpaul#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 17238363Swpaul 17338363Swpaul/* 17438526Swpaul * Interrupts we normally want enabled. 17538526Swpaul */ 17638526Swpaul#define XL_INTRS \ 17738526Swpaul (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 17838526Swpaul XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 17938526Swpaul 18038526Swpaul/* 18138363Swpaul * Window 0 registers 18238363Swpaul */ 18338363Swpaul#define XL_W0_EE_DATA 0x0C 18438363Swpaul#define XL_W0_EE_CMD 0x0A 18538363Swpaul#define XL_W0_RSRC_CFG 0x08 18638363Swpaul#define XL_W0_ADDR_CFG 0x06 18738363Swpaul#define XL_W0_CFG_CTRL 0x04 18838363Swpaul 18938363Swpaul#define XL_W0_PROD_ID 0x02 19038363Swpaul#define XL_W0_MFG_ID 0x00 19138363Swpaul 19238363Swpaul/* 19338363Swpaul * Window 1 19438363Swpaul */ 19538363Swpaul 19638363Swpaul#define XL_W1_TX_FIFO 0x10 19738363Swpaul 19838363Swpaul#define XL_W1_FREE_TX 0x0C 19938363Swpaul#define XL_W1_TX_STATUS 0x0B 20038363Swpaul#define XL_W1_TX_TIMER 0x0A 20138363Swpaul#define XL_W1_RX_STATUS 0x08 20238363Swpaul#define XL_W1_RX_FIFO 0x00 20338363Swpaul 20438363Swpaul/* 20538363Swpaul * RX status codes 20638363Swpaul */ 20738363Swpaul#define XL_RXSTATUS_OVERRUN 0x01 20838363Swpaul#define XL_RXSTATUS_RUNT 0x02 20938363Swpaul#define XL_RXSTATUS_ALIGN 0x04 21038363Swpaul#define XL_RXSTATUS_CRC 0x08 21138363Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 21238363Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 21338363Swpaul 21438363Swpaul/* 21538363Swpaul * TX status codes 21638363Swpaul */ 21738363Swpaul#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 21838363Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 21938363Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 22038363Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 22138363Swpaul#define XL_TXSTATUS_JABBER 0x20 22238363Swpaul#define XL_TXSTATUS_INTREQ 0x40 22338363Swpaul#define XL_TXSTATUS_COMPLETE 0x80 22438363Swpaul 22538363Swpaul/* 22638363Swpaul * Window 2 22738363Swpaul */ 22838363Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 22938363Swpaul#define XL_W2_STATION_MASK_HI 0x0A 23038363Swpaul#define XL_W2_STATION_MASK_MID 0x08 23138363Swpaul#define XL_W2_STATION_MASK_LO 0x06 23238363Swpaul#define XL_W2_STATION_ADDR_HI 0x04 23338363Swpaul#define XL_W2_STATION_ADDR_MID 0x02 23438363Swpaul#define XL_W2_STATION_ADDR_LO 0x00 23538363Swpaul 23638363Swpaul#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 23738363Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 23838363Swpaul#define XL_RESETOPT_DISADVFD 0x0010 23938363Swpaul#define XL_RESETOPT_DISADV100 0x0020 24038363Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 24138363Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 24238363Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 24338363Swpaul#define XL_RESETOPT_FASTEE 0x0200 24438363Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 24538363Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 24638363Swpaul#define XL_RESETOPT_TEST100TX 0x1000 24738363Swpaul#define XL_RESETOPT_TEST100RX 0x2000 24838363Swpaul 24938363Swpaul/* 25038363Swpaul * Window 3 (fifo management) 25138363Swpaul */ 25238363Swpaul#define XL_W3_INTERNAL_CFG 0x00 25338363Swpaul#define XL_W3_RESET_OPT 0x08 25438363Swpaul#define XL_W3_FREE_TX 0x0C 25538363Swpaul#define XL_W3_FREE_RX 0x0A 25638363Swpaul#define XL_W3_MAC_CTRL 0x06 25738363Swpaul 25838363Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 25938363Swpaul#define XL_ICFG_CONNECTOR_BITS 20 26038363Swpaul 26138363Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 26238363Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 26338363Swpaul#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 26438363Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 26538363Swpaul#define XL_ICFG_RAMLOC 0x00000200 26638363Swpaul#define XL_ICFG_RAMPART (0x00010000|0x00020000) 26738363Swpaul#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 26838363Swpaul#define XL_ICFG_AUTOSEL 0x01000000 26938363Swpaul 27038363Swpaul#define XL_XCVR_10BT 0x00 27138363Swpaul#define XL_XCVR_AUI 0x01 27238363Swpaul#define XL_XCVR_RSVD_0 0x02 27338363Swpaul#define XL_XCVR_COAX 0x03 27438363Swpaul#define XL_XCVR_100BTX 0x04 27538363Swpaul#define XL_XCVR_100BFX 0x05 27638363Swpaul#define XL_XCVR_MII 0x06 27738363Swpaul#define XL_XCVR_RSVD_1 0x07 27838363Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 27938363Swpaul 28038363Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 28138363Swpaul#define XL_MACCTRL_DEFER_0 0x0002 28238363Swpaul#define XL_MACCTRL_DEFER_1 0x0004 28338363Swpaul#define XL_MACCTRL_DEFER_2 0x0008 28438363Swpaul#define XL_MACCTRL_DEFER_3 0x0010 28538363Swpaul#define XL_MACCTRL_DUPLEX 0x0020 28638363Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 28738363Swpaul#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 28838363Swpaul#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 28938363Swpaul#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 29038363Swpaul 29138363Swpaul/* 29238363Swpaul * The 'reset options' register contains power-on reset values 29338363Swpaul * loaded from the EEPROM. This includes the supported media 29438363Swpaul * types on the card. It is also known as the media options register. 29538363Swpaul */ 29638363Swpaul#define XL_W3_MEDIA_OPT 0x08 29738363Swpaul 29838363Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 29938363Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 30038363Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 30138363Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 30238363Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 30338363Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 30438363Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 30538363Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 30638363Swpaul 30738363Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 30838363Swpaul#define XL_MEDIAOPT_MASK 0x01FF 30938363Swpaul 31038363Swpaul/* 31138363Swpaul * Window 4 (diagnostics) 31238363Swpaul */ 31338363Swpaul#define XL_W4_UPPERBYTESOK 0x0D 31438363Swpaul#define XL_W4_BADSSD 0x0C 31538363Swpaul#define XL_W4_MEDIA_STATUS 0x0A 31638363Swpaul#define XL_W4_PHY_MGMT 0x08 31738363Swpaul#define XL_W4_NET_DIAG 0x06 31838363Swpaul#define XL_W4_FIFO_DIAG 0x04 31938363Swpaul#define XL_W4_VCO_DIAG 0x02 32038363Swpaul 32138363Swpaul#define XL_W4_CTRLR_STAT 0x08 32238363Swpaul#define XL_W4_TX_DIAG 0x00 32338363Swpaul 32438363Swpaul#define XL_MII_CLK 0x01 32538363Swpaul#define XL_MII_DATA 0x02 32638363Swpaul#define XL_MII_DIR 0x04 32738363Swpaul 32838363Swpaul#define XL_MEDIA_SQE 0x0008 32938363Swpaul#define XL_MEDIA_10TP 0x00C0 33038363Swpaul#define XL_MEDIA_LNK 0x0080 33138363Swpaul#define XL_MEDIA_LNKBEAT 0x0800 33238363Swpaul 33338363Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 33438363Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 33538363Swpaul#define XL_MEDIASTAT_COLDET 0x0010 33638363Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 33738363Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 33838363Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 33938363Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 34038363Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 34138363Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 34238363Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 34338363Swpaul#define XL_MEDIASTAT_DCENB 0x4000 34438363Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 34538363Swpaul 34638363Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 34738363Swpaul#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 34838363Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 34938363Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 35038363Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 35138363Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 35238363Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 35338363Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 35438363Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 35538363Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 35638363Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 35738363Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 35838363Swpaul 35938363Swpaul/* 36038363Swpaul * Window 5 36138363Swpaul */ 36238363Swpaul#define XL_W5_STAT_ENB 0x0C 36338363Swpaul#define XL_W5_INTR_ENB 0x0A 36440588Swpaul#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 36538363Swpaul#define XL_W5_RX_FILTER 0x08 36638363Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 36738363Swpaul#define XL_W5_TX_AVAILTHRESH 0x02 36838363Swpaul#define XL_W5_TX_STARTTHRESH 0x00 36938363Swpaul 37038363Swpaul/* 37138363Swpaul * RX filter bits 37238363Swpaul */ 37338363Swpaul#define XL_RXFILTER_INDIVIDUAL 0x01 37438363Swpaul#define XL_RXFILTER_ALLMULTI 0x02 37538363Swpaul#define XL_RXFILTER_BROADCAST 0x04 37638363Swpaul#define XL_RXFILTER_ALLFRAMES 0x08 37738363Swpaul#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 37838363Swpaul 37938363Swpaul/* 38038363Swpaul * Window 6 (stats) 38138363Swpaul */ 38238363Swpaul#define XL_W6_TX_BYTES_OK 0x0C 38338363Swpaul#define XL_W6_RX_BYTES_OK 0x0A 38438363Swpaul#define XL_W6_UPPER_FRAMES_OK 0x09 38538363Swpaul#define XL_W6_DEFERRED 0x08 38638363Swpaul#define XL_W6_RX_OK 0x07 38738363Swpaul#define XL_W6_TX_OK 0x06 38838363Swpaul#define XL_W6_RX_OVERRUN 0x05 38938363Swpaul#define XL_W6_COL_LATE 0x04 39038363Swpaul#define XL_W6_COL_SINGLE 0x03 39138363Swpaul#define XL_W6_COL_MULTIPLE 0x02 39238363Swpaul#define XL_W6_SQE_ERRORS 0x01 39338363Swpaul#define XL_W6_CARRIER_LOST 0x00 39438363Swpaul 39538363Swpaul/* 39638363Swpaul * Window 7 (bus master control) 39738363Swpaul */ 39838363Swpaul#define XL_W7_BM_ADDR 0x00 39938363Swpaul#define XL_W7_BM_LEN 0x06 40038363Swpaul#define XL_W7_BM_STATUS 0x0B 40138363Swpaul#define XL_W7_BM_TIMEr 0x0A 40238363Swpaul 40338363Swpaul/* 40438363Swpaul * bus master control registers 40538363Swpaul */ 40638363Swpaul#define XL_BM_PKTSTAT 0x20 40738363Swpaul#define XL_BM_DOWNLISTPTR 0x24 40838363Swpaul#define XL_BM_FRAGADDR 0x28 40938363Swpaul#define XL_BM_FRAGLEN 0x2C 41038363Swpaul#define XL_BM_TXFREETHRESH 0x2F 41138363Swpaul#define XL_BM_UPPKTSTAT 0x30 41238363Swpaul#define XL_BM_UPLISTPTR 0x38 41338363Swpaul 41438363Swpaul#define XL_LAST_FRAG 0x80000000 41538363Swpaul 41638363Swpaul/* 41738363Swpaul * Boomerang/Cyclone TX/RX list structure. 41838363Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 41938363Swpaul * length. 42038363Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 42138363Swpaul */ 42238363Swpaulstruct xl_frag { 42338363Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 42438363Swpaul u_int32_t xl_len; 42538363Swpaul}; 42638363Swpaul 42738363Swpaulstruct xl_list { 42838363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 42938363Swpaul u_int32_t xl_status; 43038363Swpaul struct xl_frag xl_frag[63]; 43138363Swpaul}; 43238363Swpaul 43338363Swpaulstruct xl_list_onefrag { 43438363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 43538363Swpaul u_int32_t xl_status; 43638363Swpaul struct xl_frag xl_frag; 43738363Swpaul}; 43838363Swpaul 43938363Swpaul#define XL_MAXFRAGS 63 44038469Swpaul#define XL_RX_LIST_CNT 16 44139647Swpaul#define XL_TX_LIST_CNT 16 44238363Swpaul#define XL_MIN_FRAMELEN 60 44338363Swpaul 44438363Swpaulstruct xl_list_data { 44538363Swpaul struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 44638363Swpaul struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 44738363Swpaul unsigned char xl_pad[XL_MIN_FRAMELEN]; 44838363Swpaul}; 44938363Swpaul 45038363Swpaulstruct xl_chain { 45138363Swpaul struct xl_list *xl_ptr; 45238363Swpaul struct mbuf *xl_mbuf; 45338363Swpaul struct xl_chain *xl_next; 45438363Swpaul}; 45538363Swpaul 45638363Swpaulstruct xl_chain_onefrag { 45738363Swpaul struct xl_list_onefrag *xl_ptr; 45838363Swpaul struct mbuf *xl_mbuf; 45938363Swpaul struct xl_chain_onefrag *xl_next; 46038363Swpaul}; 46138363Swpaul 46238363Swpaulstruct xl_chain_data { 46338363Swpaul struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 46438363Swpaul struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 46538363Swpaul 46638363Swpaul struct xl_chain_onefrag *xl_rx_head; 46738363Swpaul 46838363Swpaul struct xl_chain *xl_tx_head; 46938363Swpaul struct xl_chain *xl_tx_tail; 47038363Swpaul struct xl_chain *xl_tx_free; 47138363Swpaul}; 47238363Swpaul 47338363Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 47438363Swpaul#define XL_RXSTAT_UP_ERROR 0x00004000 47538363Swpaul#define XL_RXSTAT_UP_CMPLT 0x00008000 47638363Swpaul#define XL_RXSTAT_UP_OVERRUN 0x00010000 47738363Swpaul#define XL_RXSTAT_RUNT 0x00020000 47838363Swpaul#define XL_RXSTAT_ALIGN 0x00040000 47938363Swpaul#define XL_RXSTAT_CRC 0x00080000 48038363Swpaul#define XL_RXSTAT_OVERSIZE 0x00100000 48138363Swpaul#define XL_RXSTAT_DRIBBLE 0x00800000 48238363Swpaul#define XL_RXSTAT_UP_OFLOW 0x01000000 48338363Swpaul#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 48438363Swpaul#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 48538363Swpaul#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 48638363Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 48738363Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 48838363Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 48938363Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 49038363Swpaul 49138363Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 49238363Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 49338363Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 49438363Swpaul#define XL_TXSTAT_DL_COMPLETE 0x00010000 49538363Swpaul#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 49638363Swpaul#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 49738363Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 49838363Swpaul#define XL_TXSTAT_DL_INTR 0x80000000 49938363Swpaul 50038363Swpaul#define XL_CAPABILITY_BM 0x20 50138363Swpaul 50238363Swpaul 50338363Swpaulstruct xl_type { 50438363Swpaul u_int16_t xl_vid; 50538363Swpaul u_int16_t xl_did; 50638363Swpaul char *xl_name; 50738363Swpaul}; 50838363Swpaul 50938363Swpaulstruct xl_mii_frame { 51038363Swpaul u_int8_t mii_stdelim; 51138363Swpaul u_int8_t mii_opcode; 51238363Swpaul u_int8_t mii_phyaddr; 51338363Swpaul u_int8_t mii_regaddr; 51438363Swpaul u_int8_t mii_turnaround; 51538363Swpaul u_int16_t mii_data; 51638363Swpaul}; 51738363Swpaul 51838363Swpaul/* 51938363Swpaul * MII constants 52038363Swpaul */ 52138363Swpaul#define XL_MII_STARTDELIM 0x01 52238363Swpaul#define XL_MII_READOP 0x02 52338363Swpaul#define XL_MII_WRITEOP 0x01 52438363Swpaul#define XL_MII_TURNAROUND 0x02 52538363Swpaul 52638363Swpaul/* 52738363Swpaul * The 3C905B adapters implement a few features that we want to 52838363Swpaul * take advantage of, namely the multicast hash filter. With older 52938363Swpaul * chips, you only have the option of turning on reception of all 53038363Swpaul * multicast frames, which is kind of lame. 53138363Swpaul */ 53238363Swpaul#define XL_TYPE_905B 1 53338363Swpaul#define XL_TYPE_90X 2 53438363Swpaul 53538363Swpaul#define XL_FLAG_FORCEDELAY 1 53638363Swpaul#define XL_FLAG_SCHEDDELAY 2 53738363Swpaul#define XL_FLAG_DELAYTIMEO 3 53838363Swpaul 53938363Swpaulstruct xl_softc { 54038363Swpaul struct arpcom arpcom; /* interface info */ 54138363Swpaul struct ifmedia ifmedia; /* media info */ 54245062Swpaul bus_space_handle_t xl_bhandle; 54345062Swpaul bus_space_tag_t xl_btag; 54438363Swpaul struct xl_type *xl_info; /* 3Com adapter info */ 54538363Swpaul struct xl_type *xl_pinfo; /* phy info */ 54638363Swpaul u_int8_t xl_unit; /* interface number */ 54738363Swpaul u_int8_t xl_type; 54838363Swpaul u_int8_t xl_phy_addr; /* PHY address */ 54938363Swpaul u_int32_t xl_xcvr; 55038363Swpaul u_int16_t xl_media; 55138363Swpaul u_int16_t xl_caps; 55238363Swpaul u_int8_t xl_tx_pend; /* TX pending */ 55338363Swpaul u_int8_t xl_want_auto; 55438363Swpaul u_int8_t xl_autoneg; 55538363Swpaul u_int8_t xl_stats_no_timeout; 55638363Swpaul caddr_t xl_ldata_ptr; 55738363Swpaul struct xl_list_data *xl_ldata; 55838363Swpaul struct xl_chain_data xl_cdata; 55938363Swpaul struct callout_handle xl_stat_ch; 56038363Swpaul}; 56138363Swpaul 56238363Swpaul#define xl_rx_goodframes(x) \ 56338363Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 56438363Swpaul 56538363Swpaul#define xl_tx_goodframes(x) \ 56638363Swpaul ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 56738363Swpaul 56838363Swpaulstruct xl_stats { 56938363Swpaul u_int8_t xl_carrier_lost; 57038363Swpaul u_int8_t xl_sqe_errs; 57138363Swpaul u_int8_t xl_tx_multi_collision; 57238363Swpaul u_int8_t xl_tx_single_collision; 57338363Swpaul u_int8_t xl_tx_late_collision; 57438363Swpaul u_int8_t xl_rx_overrun; 57538363Swpaul u_int8_t xl_tx_frames_ok; 57638363Swpaul u_int8_t xl_rx_frames_ok; 57738363Swpaul u_int8_t xl_tx_deferred; 57838363Swpaul u_int8_t xl_upper_frames_ok; 57938363Swpaul u_int16_t xl_rx_bytes_ok; 58038363Swpaul u_int16_t xl_tx_bytes_ok; 58138363Swpaul u_int16_t status; 58238363Swpaul}; 58338363Swpaul 58438363Swpaul/* 58538363Swpaul * register space access macros 58638363Swpaul */ 58738363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 58845062Swpaul bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 58938363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 59045062Swpaul bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 59138363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 59245062Swpaul bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 59338363Swpaul 59445062Swpaul#define CSR_READ_4(sc, reg) \ 59545062Swpaul bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 59645062Swpaul#define CSR_READ_2(sc, reg) \ 59745062Swpaul bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 59845062Swpaul#define CSR_READ_1(sc, reg) \ 59945062Swpaul bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 60038363Swpaul 60138363Swpaul#define XL_SEL_WIN(x) \ 60238363Swpaul CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 60338363Swpaul#define XL_TIMEOUT 1000 60438363Swpaul 60538363Swpaul/* 60638363Swpaul * General constants that are fun to know. 60738363Swpaul * 60838363Swpaul * 3Com PCI vendor ID 60938363Swpaul */ 61038363Swpaul#define TC_VENDORID 0x10B7 61138363Swpaul 61238363Swpaul/* 61338363Swpaul * 3Com chip device IDs. 61438363Swpaul */ 61538363Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 61638363Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 61738363Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 61838363Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 61938363Swpaul#define TC_DEVICEID_CYCLONE_10BT 0x9004 62038363Swpaul#define TC_DEVICEID_CYCLONE_10BT_COMBO 0x9005 62138363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT 0x9055 62238363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 62340097Swpaul#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 62438810Swpaul#define TC_DEVICEID_CYCLONE_10_100BT_SERV 0x9800 62538363Swpaul 62638363Swpaul/* 62738363Swpaul * Texas Instruments PHY identifiers 62838363Swpaul * 62938363Swpaul * The ThunderLAN manual has a curious and confusing error in it. 63038363Swpaul * In chapter 7, which describes PHYs, it says that TI PHYs have 63138363Swpaul * the following ID codes, where xx denotes a revision: 63238363Swpaul * 63338363Swpaul * 0x4000501xx internal 10baseT PHY 63438363Swpaul * 0x4000502xx TNETE211 100VG-AnyLan PMI 63538363Swpaul * 63638363Swpaul * The problem here is that these are not valid 32-bit hex numbers: 63738363Swpaul * there's one digit too many. My guess is that they mean the internal 63838363Swpaul * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 63938363Swpaul * are the only numbers that make sense. 64038363Swpaul */ 64138363Swpaul#define TI_PHY_VENDORID 0x4000 64238363Swpaul#define TI_PHY_10BT 0x501F 64338363Swpaul#define TI_PHY_100VGPMI 0x502F 64438363Swpaul 64538363Swpaul/* 64638363Swpaul * These ID values are for the NS DP83840A 10/100 PHY 64738363Swpaul */ 64838363Swpaul#define NS_PHY_VENDORID 0x2000 64938363Swpaul#define NS_PHY_83840A 0x5C0F 65038363Swpaul 65138363Swpaul/* 65238363Swpaul * Level 1 10/100 PHY 65338363Swpaul */ 65438363Swpaul#define LEVEL1_PHY_VENDORID 0x7810 65538363Swpaul#define LEVEL1_PHY_LXT970 0x000F 65638363Swpaul 65738363Swpaul/* 65838363Swpaul * Intel 82555 10/100 PHY 65938363Swpaul */ 66038363Swpaul#define INTEL_PHY_VENDORID 0x0A28 66138363Swpaul#define INTEL_PHY_82555 0x015F 66238363Swpaul 66338363Swpaul/* 66438363Swpaul * SEEQ 80220 10/100 PHY 66538363Swpaul */ 66638363Swpaul#define SEEQ_PHY_VENDORID 0x0016 66738363Swpaul#define SEEQ_PHY_80220 0xF83F 66838363Swpaul 66938363Swpaul 67038363Swpaul/* 67138363Swpaul * PCI low memory base and low I/O base register, and 67238363Swpaul * other PCI registers. Note: some are only available on 67338363Swpaul * the 3c905B, in particular those that related to power management. 67438363Swpaul */ 67538363Swpaul 67638363Swpaul#define XL_PCI_VENDOR_ID 0x00 67738363Swpaul#define XL_PCI_DEVICE_ID 0x02 67838363Swpaul#define XL_PCI_COMMAND 0x04 67938363Swpaul#define XL_PCI_STATUS 0x06 68038363Swpaul#define XL_PCI_CLASSCODE 0x09 68138363Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 68238363Swpaul#define XL_PCI_HEADER_TYPE 0x0E 68338363Swpaul#define XL_PCI_LOIO 0x10 68438363Swpaul#define XL_PCI_LOMEM 0x14 68538363Swpaul#define XL_PCI_BIOSROM 0x30 68638363Swpaul#define XL_PCI_INTLINE 0x3C 68738363Swpaul#define XL_PCI_INTPIN 0x3D 68838363Swpaul#define XL_PCI_MINGNT 0x3E 68938363Swpaul#define XL_PCI_MINLAT 0x0F 69038363Swpaul#define XL_PCI_RESETOPT 0x48 69138363Swpaul#define XL_PCI_EEPROM_DATA 0x4C 69238363Swpaul 69338363Swpaul/* 3c905B-only registers */ 69438363Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 69538363Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 69638363Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 69738363Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 69838363Swpaul 69938363Swpaul#define XL_PSTATE_MASK 0x0003 70038363Swpaul#define XL_PSTATE_D0 0x0000 70138363Swpaul#define XL_PSTATE_D1 0x0002 70238363Swpaul#define XL_PSTATE_D2 0x0002 70338363Swpaul#define XL_PSTATE_D3 0x0003 70438363Swpaul#define XL_PME_EN 0x0010 70538363Swpaul#define XL_PME_STATUS 0x8000 70638363Swpaul 70738363Swpaul#define PHY_UNKNOWN 6 70838363Swpaul 70938363Swpaul#define XL_PHYADDR_MIN 0x00 71038363Swpaul#define XL_PHYADDR_MAX 0x1F 71138363Swpaul 71238363Swpaul#define XL_PHY_GENCTL 0x00 71338363Swpaul#define XL_PHY_GENSTS 0x01 71438363Swpaul#define XL_PHY_VENID 0x02 71538363Swpaul#define XL_PHY_DEVID 0x03 71638363Swpaul#define XL_PHY_ANAR 0x04 71738363Swpaul#define XL_PHY_LPAR 0x05 71838363Swpaul#define XL_PHY_ANEXP 0x06 71938363Swpaul 72038363Swpaul#define PHY_ANAR_NEXTPAGE 0x8000 72138363Swpaul#define PHY_ANAR_RSVD0 0x4000 72238363Swpaul#define PHY_ANAR_TLRFLT 0x2000 72338363Swpaul#define PHY_ANAR_RSVD1 0x1000 72438363Swpaul#define PHY_ANAR_RSVD2 0x0800 72538363Swpaul#define PHY_ANAR_RSVD3 0x0400 72638363Swpaul#define PHY_ANAR_100BT4 0x0200 72738363Swpaul#define PHY_ANAR_100BTXFULL 0x0100 72838363Swpaul#define PHY_ANAR_100BTXHALF 0x0080 72938363Swpaul#define PHY_ANAR_10BTFULL 0x0040 73038363Swpaul#define PHY_ANAR_10BTHALF 0x0020 73138363Swpaul#define PHY_ANAR_PROTO4 0x0010 73238363Swpaul#define PHY_ANAR_PROTO3 0x0008 73338363Swpaul#define PHY_ANAR_PROTO2 0x0004 73438363Swpaul#define PHY_ANAR_PROTO1 0x0002 73538363Swpaul#define PHY_ANAR_PROTO0 0x0001 73638363Swpaul 73738363Swpaul/* 73838363Swpaul * These are the register definitions for the PHY (physical layer 73938363Swpaul * interface chip). 74038363Swpaul */ 74138363Swpaul/* 74238363Swpaul * PHY BMCR Basic Mode Control Register 74338363Swpaul */ 74438363Swpaul#define PHY_BMCR 0x00 74538363Swpaul#define PHY_BMCR_RESET 0x8000 74638363Swpaul#define PHY_BMCR_LOOPBK 0x4000 74738363Swpaul#define PHY_BMCR_SPEEDSEL 0x2000 74838363Swpaul#define PHY_BMCR_AUTONEGENBL 0x1000 74938363Swpaul#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 75038363Swpaul#define PHY_BMCR_ISOLATE 0x0400 75138363Swpaul#define PHY_BMCR_AUTONEGRSTR 0x0200 75238363Swpaul#define PHY_BMCR_DUPLEX 0x0100 75338363Swpaul#define PHY_BMCR_COLLTEST 0x0080 75438363Swpaul#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 75538363Swpaul#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 75638363Swpaul#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 75738363Swpaul#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 75838363Swpaul#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 75938363Swpaul#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 76038363Swpaul#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 76138363Swpaul/* 76238363Swpaul * RESET: 1 == software reset, 0 == normal operation 76338363Swpaul * Resets status and control registers to default values. 76438363Swpaul * Relatches all hardware config values. 76538363Swpaul * 76638363Swpaul * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 76738363Swpaul * 76838363Swpaul * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 76938363Swpaul * Link speed is selected byt his bit or if auto-negotiation if bit 77038363Swpaul * 12 (AUTONEGENBL) is set (in which case the value of this register 77138363Swpaul * is ignored). 77238363Swpaul * 77338363Swpaul * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 77438363Swpaul * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 77538363Swpaul * determine speed and mode. Should be cleared and then set if PHY configured 77638363Swpaul * for no autoneg on startup. 77738363Swpaul * 77838363Swpaul * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 77938363Swpaul * 78038363Swpaul * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 78138363Swpaul * 78238363Swpaul * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 78338363Swpaul * 78438363Swpaul * COLLTEST: 1 == collision test enabled, 0 == normal operation 78538363Swpaul */ 78638363Swpaul 78738363Swpaul/* 78838363Swpaul * PHY, BMSR Basic Mode Status Register 78938363Swpaul */ 79038363Swpaul#define PHY_BMSR 0x01 79138363Swpaul#define PHY_BMSR_100BT4 0x8000 79238363Swpaul#define PHY_BMSR_100BTXFULL 0x4000 79338363Swpaul#define PHY_BMSR_100BTXHALF 0x2000 79438363Swpaul#define PHY_BMSR_10BTFULL 0x1000 79538363Swpaul#define PHY_BMSR_10BTHALF 0x0800 79638363Swpaul#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 79738363Swpaul#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 79838363Swpaul#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 79938363Swpaul#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 80038363Swpaul#define PHY_BMSR_MFPRESUP 0x0040 80138363Swpaul#define PHY_BMSR_AUTONEGCOMP 0x0020 80238363Swpaul#define PHY_BMSR_REMFAULT 0x0010 80338363Swpaul#define PHY_BMSR_CANAUTONEG 0x0008 80438363Swpaul#define PHY_BMSR_LINKSTAT 0x0004 80538363Swpaul#define PHY_BMSR_JABBER 0x0002 80638363Swpaul#define PHY_BMSR_EXTENDED 0x0001 80745062Swpaul 80845062Swpaul#ifdef __alpha__ 80945062Swpaul#undef vtophys 81045062Swpaul#define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \ 81145062Swpaul + 1*1024*1024*1024) 81245062Swpaul#endif 813