if_xlreg.h revision 109503
1168404Spjd/*
2168404Spjd * Copyright (c) 1997, 1998
3168404Spjd *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4168404Spjd *
5168404Spjd * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_xlreg.h 109503 2003-01-19 00:23:59Z tmm $
33 */
34
35#define XL_EE_READ	0x0080	/* read, 5 bit address */
36#define XL_EE_WRITE	0x0040	/* write, 5 bit address */
37#define XL_EE_ERASE	0x00c0	/* erase, 5 bit address */
38#define XL_EE_EWEN	0x0030	/* erase, no data needed */
39#define XL_EE_8BIT_READ	0x0200	/* read, 8 bit address */
40#define XL_EE_BUSY	0x8000
41
42#define XL_EE_EADDR0	0x00	/* station address, first word */
43#define XL_EE_EADDR1	0x01	/* station address, next word, */
44#define XL_EE_EADDR2	0x02	/* station address, last word */
45#define XL_EE_PRODID	0x03	/* product ID code */
46#define XL_EE_MDATA_DATE	0x04	/* manufacturing data, date */
47#define XL_EE_MDATA_DIV		0x05	/* manufacturing data, division */
48#define XL_EE_MDATA_PCODE	0x06	/* manufacturing data, product code */
49#define XL_EE_MFG_ID	0x07
50#define XL_EE_PCI_PARM	0x08
51#define XL_EE_ROM_ONFO	0x09
52#define XL_EE_OEM_ADR0	0x0A
53#define	XL_EE_OEM_ADR1	0x0B
54#define XL_EE_OEM_ADR2	0x0C
55#define XL_EE_SOFTINFO1	0x0D
56#define XL_EE_COMPAT	0x0E
57#define XL_EE_SOFTINFO2	0x0F
58#define XL_EE_CAPS	0x10	/* capabilities word */
59#define XL_EE_RSVD0	0x11
60#define XL_EE_ICFG_0	0x12
61#define XL_EE_ICFG_1	0x13
62#define XL_EE_RSVD1	0x14
63#define XL_EE_SOFTINFO3	0x15
64#define XL_EE_RSVD_2	0x16
65
66/*
67 * Bits in the capabilities word
68 */
69#define XL_CAPS_PNP		0x0001
70#define XL_CAPS_FULL_DUPLEX	0x0002
71#define XL_CAPS_LARGE_PKTS	0x0004
72#define XL_CAPS_SLAVE_DMA	0x0008
73#define XL_CAPS_SECOND_DMA	0x0010
74#define XL_CAPS_FULL_BM		0x0020
75#define XL_CAPS_FRAG_BM		0x0040
76#define XL_CAPS_CRC_PASSTHRU	0x0080
77#define XL_CAPS_TXDONE		0x0100
78#define XL_CAPS_NO_TXLENGTH	0x0200
79#define XL_CAPS_RX_REPEAT	0x0400
80#define XL_CAPS_SNOOPING	0x0800
81#define XL_CAPS_100MBPS		0x1000
82#define XL_CAPS_PWRMGMT		0x2000
83
84#define XL_PACKET_SIZE 1540
85
86/*
87 * Register layouts.
88 */
89#define XL_COMMAND		0x0E
90#define XL_STATUS		0x0E
91
92#define XL_TX_STATUS		0x1B
93#define XL_TX_FREE		0x1C
94#define XL_DMACTL		0x20
95#define XL_DOWNLIST_PTR		0x24
96#define XL_DOWN_POLL		0x2D /* 3c90xB only */
97#define XL_TX_FREETHRESH	0x2F
98#define XL_UPLIST_PTR		0x38
99#define XL_UPLIST_STATUS	0x30
100#define XL_UP_POLL		0x3D /* 3c90xB only */
101
102#define XL_PKTSTAT_UP_STALLED		0x00002000
103#define XL_PKTSTAT_UP_ERROR		0x00004000
104#define XL_PKTSTAT_UP_CMPLT		0x00008000
105
106#define XL_DMACTL_DN_CMPLT_REQ		0x00000002
107#define XL_DMACTL_DOWN_STALLED		0x00000004
108#define XL_DMACTL_UP_CMPLT		0x00000008
109#define XL_DMACTL_DOWN_CMPLT		0x00000010
110#define XL_DMACTL_UP_RX_EARLY		0x00000020
111#define XL_DMACTL_ARM_COUNTDOWN		0x00000040
112#define XL_DMACTL_DOWN_INPROG		0x00000080
113#define XL_DMACTL_COUNTER_SPEED		0x00000100
114#define XL_DMACTL_DOWNDOWN_MODE		0x00000200
115#define XL_DMACTL_TARGET_ABORT		0x40000000
116#define XL_DMACTL_MASTER_ABORT		0x80000000
117
118/*
119 * Command codes. Some command codes require that we wait for
120 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
121 */
122#define XL_CMD_RESET		0x0000	/* mustwait */
123#define XL_CMD_WINSEL		0x0800
124#define XL_CMD_COAX_START	0x1000
125#define XL_CMD_RX_DISABLE	0x1800
126#define XL_CMD_RX_ENABLE	0x2000
127#define XL_CMD_RX_RESET		0x2800	/* mustwait */
128#define XL_CMD_UP_STALL		0x3000	/* mustwait */
129#define XL_CMD_UP_UNSTALL	0x3001
130#define XL_CMD_DOWN_STALL	0x3002	/* mustwait */
131#define XL_CMD_DOWN_UNSTALL	0x3003
132#define XL_CMD_RX_DISCARD	0x4000
133#define XL_CMD_TX_ENABLE	0x4800
134#define XL_CMD_TX_DISABLE	0x5000
135#define XL_CMD_TX_RESET		0x5800	/* mustwait */
136#define XL_CMD_INTR_FAKE	0x6000
137#define XL_CMD_INTR_ACK		0x6800
138#define XL_CMD_INTR_ENB		0x7000
139#define XL_CMD_STAT_ENB		0x7800
140#define XL_CMD_RX_SET_FILT	0x8000
141#define XL_CMD_RX_SET_THRESH	0x8800
142#define XL_CMD_TX_SET_THRESH	0x9000
143#define XL_CMD_TX_SET_START	0x9800
144#define XL_CMD_DMA_UP		0xA000
145#define XL_CMD_DMA_STOP		0xA001
146#define XL_CMD_STATS_ENABLE	0xA800
147#define XL_CMD_STATS_DISABLE	0xB000
148#define XL_CMD_COAX_STOP	0xB800
149
150#define XL_CMD_SET_TX_RECLAIM	0xC000 /* 3c905B only */
151#define XL_CMD_RX_SET_HASH	0xC800 /* 3c905B only */
152
153#define XL_HASH_SET		0x0400
154#define XL_HASHFILT_SIZE	256
155
156/*
157 * status codes
158 * Note that bits 15 to 13 indicate the currently visible register window
159 * which may be anything from 0 to 7.
160 */
161#define XL_STAT_INTLATCH	0x0001	/* 0 */
162#define XL_STAT_ADFAIL		0x0002	/* 1 */
163#define XL_STAT_TX_COMPLETE	0x0004	/* 2 */
164#define XL_STAT_TX_AVAIL	0x0008	/* 3 first generation */
165#define XL_STAT_RX_COMPLETE	0x0010  /* 4 */
166#define XL_STAT_RX_EARLY	0x0020	/* 5 */
167#define XL_STAT_INTREQ		0x0040  /* 6 */
168#define XL_STAT_STATSOFLOW	0x0080  /* 7 */
169#define XL_STAT_DMADONE		0x0100	/* 8 first generation */
170#define XL_STAT_LINKSTAT	0x0100	/* 8 3c509B */
171#define XL_STAT_DOWN_COMPLETE	0x0200	/* 9 */
172#define XL_STAT_UP_COMPLETE	0x0400	/* 10 */
173#define XL_STAT_DMABUSY		0x0800	/* 11 first generation */
174#define XL_STAT_CMDBUSY		0x1000  /* 12 */
175
176/*
177 * Interrupts we normally want enabled.
178 */
179#define XL_INTRS							\
180	(XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL|	\
181	 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
182
183/*
184 * Window 0 registers
185 */
186#define XL_W0_EE_DATA		0x0C
187#define XL_W0_EE_CMD		0x0A
188#define XL_W0_RSRC_CFG		0x08
189#define XL_W0_ADDR_CFG		0x06
190#define XL_W0_CFG_CTRL		0x04
191
192#define XL_W0_PROD_ID		0x02
193#define XL_W0_MFG_ID		0x00
194
195/*
196 * Window 1
197 */
198
199#define XL_W1_TX_FIFO		0x10
200
201#define XL_W1_FREE_TX		0x0C
202#define XL_W1_TX_STATUS		0x0B
203#define XL_W1_TX_TIMER		0x0A
204#define XL_W1_RX_STATUS		0x08
205#define XL_W1_RX_FIFO		0x00
206
207/*
208 * RX status codes
209 */
210#define XL_RXSTATUS_OVERRUN	0x01
211#define XL_RXSTATUS_RUNT	0x02
212#define XL_RXSTATUS_ALIGN	0x04
213#define XL_RXSTATUS_CRC		0x08
214#define XL_RXSTATUS_OVERSIZE	0x10
215#define XL_RXSTATUS_DRIBBLE	0x20
216
217/*
218 * TX status codes
219 */
220#define XL_TXSTATUS_RECLAIM	0x02 /* 3c905B only */
221#define XL_TXSTATUS_OVERFLOW	0x04
222#define XL_TXSTATUS_MAXCOLS	0x08
223#define XL_TXSTATUS_UNDERRUN	0x10
224#define XL_TXSTATUS_JABBER	0x20
225#define XL_TXSTATUS_INTREQ	0x40
226#define XL_TXSTATUS_COMPLETE	0x80
227
228/*
229 * Window 2
230 */
231#define XL_W2_RESET_OPTIONS	0x0C	/* 3c905B only */
232#define XL_W2_STATION_MASK_HI	0x0A
233#define XL_W2_STATION_MASK_MID	0x08
234#define XL_W2_STATION_MASK_LO	0x06
235#define XL_W2_STATION_ADDR_HI	0x04
236#define XL_W2_STATION_ADDR_MID	0x02
237#define XL_W2_STATION_ADDR_LO	0x00
238
239#define XL_RESETOPT_FEATUREMASK	0x0001|0x0002|0x004
240#define XL_RESETOPT_D3RESETDIS	0x0008
241#define XL_RESETOPT_DISADVFD	0x0010
242#define XL_RESETOPT_DISADV100	0x0020
243#define XL_RESETOPT_DISAUTONEG	0x0040
244#define XL_RESETOPT_DEBUGMODE	0x0080
245#define XL_RESETOPT_FASTAUTO	0x0100
246#define XL_RESETOPT_FASTEE	0x0200
247#define XL_RESETOPT_FORCEDCONF	0x0400
248#define XL_RESETOPT_TESTPDTPDR	0x0800
249#define XL_RESETOPT_TEST100TX	0x1000
250#define XL_RESETOPT_TEST100RX	0x2000
251
252#define XL_RESETOPT_INVERT_LED	0x0010
253#define XL_RESETOPT_INVERT_MII	0x4000
254
255/*
256 * Window 3 (fifo management)
257 */
258#define XL_W3_INTERNAL_CFG	0x00
259#define XL_W3_MAXPKTSIZE	0x04    /* 3c905B only */
260#define XL_W3_RESET_OPT		0x08
261#define XL_W3_FREE_TX		0x0C
262#define XL_W3_FREE_RX		0x0A
263#define XL_W3_MAC_CTRL		0x06
264
265#define XL_ICFG_CONNECTOR_MASK	0x00F00000
266#define XL_ICFG_CONNECTOR_BITS	20
267
268#define XL_ICFG_RAMSIZE_MASK	0x00000007
269#define XL_ICFG_RAMWIDTH	0x00000008
270#define XL_ICFG_ROMSIZE_MASK	(0x00000040|0x00000080)
271#define XL_ICFG_DISABLE_BASSD	0x00000100
272#define XL_ICFG_RAMLOC		0x00000200
273#define XL_ICFG_RAMPART		(0x00010000|0x00020000)
274#define XL_ICFG_XCVRSEL		(0x00100000|0x00200000|0x00400000)
275#define XL_ICFG_AUTOSEL		0x01000000
276
277#define XL_XCVR_10BT		0x00
278#define XL_XCVR_AUI		0x01
279#define XL_XCVR_RSVD_0		0x02
280#define XL_XCVR_COAX		0x03
281#define XL_XCVR_100BTX		0x04
282#define XL_XCVR_100BFX		0x05
283#define XL_XCVR_MII		0x06
284#define XL_XCVR_RSVD_1		0x07
285#define XL_XCVR_AUTO		0x08	/* 3c905B only */
286
287#define XL_MACCTRL_DEFER_EXT_END	0x0001
288#define XL_MACCTRL_DEFER_0		0x0002
289#define XL_MACCTRL_DEFER_1		0x0004
290#define XL_MACCTRL_DEFER_2		0x0008
291#define XL_MACCTRL_DEFER_3		0x0010
292#define XL_MACCTRL_DUPLEX		0x0020
293#define XL_MACCTRL_ALLOW_LARGE_PACK	0x0040
294#define XL_MACCTRL_EXTEND_AFTER_COL	0x0080 (3c905B only)
295#define XL_MACCTRL_FLOW_CONTROL_ENB	0x0100 (3c905B only)
296#define XL_MACCTRL_VLT_END		0x0200 (3c905B only)
297
298/*
299 * The 'reset options' register contains power-on reset values
300 * loaded from the EEPROM. This includes the supported media
301 * types on the card. It is also known as the media options register.
302 */
303#define XL_W3_MEDIA_OPT		0x08
304
305#define XL_MEDIAOPT_BT4		0x0001	/* MII */
306#define XL_MEDIAOPT_BTX		0x0002	/* on-chip */
307#define XL_MEDIAOPT_BFX		0x0004	/* on-chip */
308#define XL_MEDIAOPT_BT		0x0008	/* on-chip */
309#define XL_MEDIAOPT_BNC		0x0010	/* on-chip */
310#define XL_MEDIAOPT_AUI		0x0020	/* on-chip */
311#define XL_MEDIAOPT_MII		0x0040	/* MII */
312#define XL_MEDIAOPT_VCO		0x0100	/* 1st gen chip only */
313
314#define XL_MEDIAOPT_10FL	0x0100	/* 3x905B only, on-chip */
315#define XL_MEDIAOPT_MASK	0x01FF
316
317/*
318 * Window 4 (diagnostics)
319 */
320#define XL_W4_UPPERBYTESOK	0x0D
321#define XL_W4_BADSSD		0x0C
322#define XL_W4_MEDIA_STATUS	0x0A
323#define XL_W4_PHY_MGMT		0x08
324#define XL_W4_NET_DIAG		0x06
325#define XL_W4_FIFO_DIAG		0x04
326#define XL_W4_VCO_DIAG		0x02
327
328#define XL_W4_CTRLR_STAT	0x08
329#define XL_W4_TX_DIAG		0x00
330
331#define XL_MII_CLK		0x01
332#define XL_MII_DATA		0x02
333#define XL_MII_DIR		0x04
334
335#define XL_MEDIA_SQE		0x0008
336#define XL_MEDIA_10TP		0x00C0
337#define XL_MEDIA_LNK		0x0080
338#define XL_MEDIA_LNKBEAT	0x0800
339
340#define XL_MEDIASTAT_CRCSTRIP	0x0004
341#define XL_MEDIASTAT_SQEENB	0x0008
342#define XL_MEDIASTAT_COLDET	0x0010
343#define XL_MEDIASTAT_CARRIER	0x0020
344#define XL_MEDIASTAT_JABGUARD	0x0040
345#define XL_MEDIASTAT_LINKBEAT	0x0080
346#define XL_MEDIASTAT_JABDETECT	0x0200
347#define XL_MEDIASTAT_POLREVERS	0x0400
348#define XL_MEDIASTAT_LINKDETECT	0x0800
349#define XL_MEDIASTAT_TXINPROG	0x1000
350#define XL_MEDIASTAT_DCENB	0x4000
351#define XL_MEDIASTAT_AUIDIS	0x8000
352
353#define XL_NETDIAG_TEST_LOWVOLT		0x0001
354#define XL_NETDIAG_ASIC_REVMASK		(0x0002|0x0004|0x0008|0x0010|0x0020)
355#define XL_NETDIAG_UPPER_BYTES_ENABLE	0x0040
356#define XL_NETDIAG_STATS_ENABLED	0x0080
357#define XL_NETDIAG_TX_FATALERR		0x0100
358#define XL_NETDIAG_TRANSMITTING		0x0200
359#define XL_NETDIAG_RX_ENABLED		0x0400
360#define XL_NETDIAG_TX_ENABLED		0x0800
361#define XL_NETDIAG_FIFO_LOOPBACK	0x1000
362#define XL_NETDIAG_MAC_LOOPBACK		0x2000
363#define XL_NETDIAG_ENDEC_LOOPBACK	0x4000
364#define XL_NETDIAG_EXTERNAL_LOOP	0x8000
365
366/*
367 * Window 5
368 */
369#define XL_W5_STAT_ENB		0x0C
370#define XL_W5_INTR_ENB		0x0A
371#define XL_W5_RECLAIM_THRESH	0x09	/* 3c905B only */
372#define XL_W5_RX_FILTER		0x08
373#define XL_W5_RX_EARLYTHRESH	0x06
374#define XL_W5_TX_AVAILTHRESH	0x02
375#define XL_W5_TX_STARTTHRESH	0x00
376
377/*
378 * RX filter bits
379 */
380#define XL_RXFILTER_INDIVIDUAL	0x01
381#define XL_RXFILTER_ALLMULTI	0x02
382#define XL_RXFILTER_BROADCAST	0x04
383#define XL_RXFILTER_ALLFRAMES	0x08
384#define XL_RXFILTER_MULTIHASH	0x10 /* 3c905B only */
385
386/*
387 * Window 6 (stats)
388 */
389#define XL_W6_TX_BYTES_OK	0x0C
390#define XL_W6_RX_BYTES_OK	0x0A
391#define XL_W6_UPPER_FRAMES_OK	0x09
392#define XL_W6_DEFERRED		0x08
393#define XL_W6_RX_OK		0x07
394#define XL_W6_TX_OK		0x06
395#define XL_W6_RX_OVERRUN	0x05
396#define XL_W6_COL_LATE		0x04
397#define XL_W6_COL_SINGLE	0x03
398#define XL_W6_COL_MULTIPLE	0x02
399#define XL_W6_SQE_ERRORS	0x01
400#define XL_W6_CARRIER_LOST	0x00
401
402/*
403 * Window 7 (bus master control)
404 */
405#define XL_W7_BM_ADDR		0x00
406#define XL_W7_BM_LEN		0x06
407#define XL_W7_BM_STATUS		0x0B
408#define XL_W7_BM_TIMEr		0x0A
409
410/*
411 * bus master control registers
412 */
413#define XL_BM_PKTSTAT		0x20
414#define XL_BM_DOWNLISTPTR	0x24
415#define XL_BM_FRAGADDR		0x28
416#define XL_BM_FRAGLEN		0x2C
417#define XL_BM_TXFREETHRESH	0x2F
418#define XL_BM_UPPKTSTAT		0x30
419#define XL_BM_UPLISTPTR		0x38
420
421#define XL_LAST_FRAG		0x80000000
422
423#define XL_MAXFRAGS		63
424#define XL_RX_LIST_CNT		128
425#define XL_TX_LIST_CNT		256
426#define XL_RX_LIST_SZ		XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag)
427#define XL_TX_LIST_SZ		XL_TX_LIST_CNT * sizeof(struct xl_list)
428#define XL_MIN_FRAMELEN		60
429#define ETHER_ALIGN		2
430#define XL_INC(x, y)		(x) = (x + 1) % y
431
432/*
433 * Boomerang/Cyclone TX/RX list structure.
434 * For the TX lists, bits 0 to 12 of the status word indicate
435 * length.
436 * This looks suspiciously like the ThunderLAN, doesn't it.
437 */
438struct xl_frag {
439	u_int32_t		xl_addr;	/* 63 addr/len pairs */
440	u_int32_t		xl_len;
441};
442
443struct xl_list {
444	u_int32_t		xl_next;	/* final entry has 0 nextptr */
445	u_int32_t		xl_status;
446	struct xl_frag		xl_frag[XL_MAXFRAGS];
447};
448
449struct xl_list_onefrag {
450	u_int32_t		xl_next;	/* final entry has 0 nextptr */
451	u_int32_t		xl_status;
452	struct xl_frag		xl_frag;
453};
454
455struct xl_list_data {
456	struct xl_list_onefrag	*xl_rx_list;
457	struct xl_list		*xl_tx_list;
458	u_int32_t		xl_rx_dmaaddr;
459	bus_dma_tag_t		xl_rx_tag;
460	bus_dmamap_t		xl_rx_dmamap;
461	u_int32_t		xl_tx_dmaaddr;
462	bus_dma_tag_t		xl_tx_tag;
463	bus_dmamap_t		xl_tx_dmamap;
464};
465
466struct xl_chain {
467	struct xl_list		*xl_ptr;
468	struct mbuf		*xl_mbuf;
469	struct xl_chain		*xl_next;
470	struct xl_chain		*xl_prev;
471	u_int32_t		xl_phys;
472	bus_dmamap_t		xl_map;
473};
474
475struct xl_chain_onefrag {
476	struct xl_list_onefrag	*xl_ptr;
477	struct mbuf		*xl_mbuf;
478	struct xl_chain_onefrag	*xl_next;
479	bus_dmamap_t		xl_map;
480};
481
482struct xl_chain_data {
483	struct xl_chain_onefrag	xl_rx_chain[XL_RX_LIST_CNT];
484	struct xl_chain		xl_tx_chain[XL_TX_LIST_CNT];
485
486	struct xl_chain_onefrag	*xl_rx_head;
487
488	/* 3c90x "boomerang" queuing stuff */
489	struct xl_chain		*xl_tx_head;
490	struct xl_chain		*xl_tx_tail;
491	struct xl_chain		*xl_tx_free;
492
493	/* 3c90xB "cyclone/hurricane/tornado" stuff */
494	int			xl_tx_prod;
495	int			xl_tx_cons;
496	int			xl_tx_cnt;
497};
498
499#define XL_RXSTAT_LENMASK	0x00001FFF
500#define XL_RXSTAT_UP_ERROR	0x00004000
501#define XL_RXSTAT_UP_CMPLT	0x00008000
502#define XL_RXSTAT_UP_OVERRUN	0x00010000
503#define XL_RXSTAT_RUNT		0x00020000
504#define XL_RXSTAT_ALIGN		0x00040000
505#define XL_RXSTAT_CRC		0x00080000
506#define XL_RXSTAT_OVERSIZE	0x00100000
507#define XL_RXSTAT_DRIBBLE	0x00800000
508#define XL_RXSTAT_UP_OFLOW	0x01000000
509#define XL_RXSTAT_IPCKERR	0x02000000	/* 3c905B only */
510#define XL_RXSTAT_TCPCKERR	0x04000000	/* 3c905B only */
511#define XL_RXSTAT_UDPCKERR	0x08000000	/* 3c905B only */
512#define XL_RXSTAT_BUFEN		0x10000000	/* 3c905B only */
513#define XL_RXSTAT_IPCKOK	0x20000000	/* 3c905B only */
514#define XL_RXSTAT_TCPCOK	0x40000000	/* 3c905B only */
515#define XL_RXSTAT_UDPCKOK	0x80000000	/* 3c905B only */
516
517#define XL_TXSTAT_LENMASK	0x00001FFF
518#define XL_TXSTAT_CRCDIS	0x00002000
519#define XL_TXSTAT_TX_INTR	0x00008000
520#define XL_TXSTAT_DL_COMPLETE	0x00010000
521#define XL_TXSTAT_IPCKSUM	0x02000000	/* 3c905B only */
522#define XL_TXSTAT_TCPCKSUM	0x04000000	/* 3c905B only */
523#define XL_TXSTAT_UDPCKSUM	0x08000000	/* 3c905B only */
524#define XL_TXSTAT_RND_DEFEAT	0x10000000	/* 3c905B only */
525#define XL_TXSTAT_EMPTY		0x20000000	/* 3c905B only */
526#define XL_TXSTAT_DL_INTR	0x80000000
527
528#define XL_CAPABILITY_BM	0x20
529
530struct xl_type {
531	u_int16_t		xl_vid;
532	u_int16_t		xl_did;
533	char			*xl_name;
534};
535
536struct xl_mii_frame {
537	u_int8_t		mii_stdelim;
538	u_int8_t		mii_opcode;
539	u_int8_t		mii_phyaddr;
540	u_int8_t		mii_regaddr;
541	u_int8_t		mii_turnaround;
542	u_int16_t		mii_data;
543};
544
545/*
546 * MII constants
547 */
548#define XL_MII_STARTDELIM	0x01
549#define XL_MII_READOP		0x02
550#define XL_MII_WRITEOP		0x01
551#define XL_MII_TURNAROUND	0x02
552
553/*
554 * The 3C905B adapters implement a few features that we want to
555 * take advantage of, namely the multicast hash filter. With older
556 * chips, you only have the option of turning on reception of all
557 * multicast frames, which is kind of lame.
558 *
559 * We also use this to decide on a transmit strategy. For the 3c90xB
560 * cards, we can use polled descriptor mode, which reduces CPU overhead.
561 */
562#define XL_TYPE_905B	1
563#define XL_TYPE_90X	2
564
565#define XL_FLAG_FUNCREG			0x0001
566#define XL_FLAG_PHYOK			0x0002
567#define XL_FLAG_EEPROM_OFFSET_30	0x0004
568#define XL_FLAG_WEIRDRESET		0x0008
569#define XL_FLAG_8BITROM			0x0010
570#define XL_FLAG_INVERT_LED_PWR		0x0020
571#define XL_FLAG_INVERT_MII_PWR		0x0040
572#define XL_FLAG_NO_XCVR_PWR		0x0080
573
574#define XL_NO_XCVR_PWR_MAGICBITS	0x0900
575
576struct xl_softc {
577	struct arpcom		arpcom;		/* interface info */
578	struct ifmedia		ifmedia;	/* media info */
579	bus_space_handle_t	xl_bhandle;
580	bus_space_tag_t		xl_btag;
581	void			*xl_intrhand;
582	struct resource		*xl_irq;
583	struct resource		*xl_res;
584	device_t		xl_miibus;
585	struct xl_type		*xl_info;	/* 3Com adapter info */
586	bus_dma_tag_t		xl_mtag;
587	u_int8_t		xl_unit;	/* interface number */
588	u_int8_t		xl_type;
589	u_int32_t		xl_xcvr;
590	u_int16_t		xl_media;
591	u_int16_t		xl_caps;
592	u_int8_t		xl_stats_no_timeout;
593	u_int16_t		xl_tx_thresh;
594	int			xl_if_flags;
595	struct xl_list_data	xl_ldata;
596	struct xl_chain_data	xl_cdata;
597	struct callout_handle	xl_stat_ch;
598	int			xl_flags;
599	struct resource		*xl_fres;
600	bus_space_handle_t	xl_fhandle;
601	bus_space_tag_t		xl_ftag;
602	struct mtx		xl_mtx;
603};
604
605#if 0
606/* These are a bit premature.  The driver still tries to sleep with locks. */
607#define XL_LOCK(_sc)		mtx_lock(&(_sc)->xl_mtx)
608#define XL_UNLOCK(_sc)		mtx_unlock(&(_sc)->xl_mtx)
609#else
610#define XL_LOCK(x)		do { } while (0)
611#define XL_UNLOCK(x)		do { } while (0)
612#endif
613
614#define xl_rx_goodframes(x) \
615	((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
616
617#define xl_tx_goodframes(x) \
618	((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
619
620struct xl_stats {
621	u_int8_t		xl_carrier_lost;
622	u_int8_t		xl_sqe_errs;
623	u_int8_t		xl_tx_multi_collision;
624	u_int8_t		xl_tx_single_collision;
625	u_int8_t		xl_tx_late_collision;
626	u_int8_t		xl_rx_overrun;
627	u_int8_t		xl_tx_frames_ok;
628	u_int8_t		xl_rx_frames_ok;
629	u_int8_t		xl_tx_deferred;
630	u_int8_t		xl_upper_frames_ok;
631	u_int16_t		xl_rx_bytes_ok;
632	u_int16_t		xl_tx_bytes_ok;
633	u_int16_t		status;
634};
635
636/*
637 * register space access macros
638 */
639#define CSR_WRITE_4(sc, reg, val)	\
640	bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
641#define CSR_WRITE_2(sc, reg, val)	\
642	bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
643#define CSR_WRITE_1(sc, reg, val)	\
644	bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
645
646#define CSR_READ_4(sc, reg)		\
647	bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
648#define CSR_READ_2(sc, reg)		\
649	bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
650#define CSR_READ_1(sc, reg)		\
651	bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
652
653#define XL_SEL_WIN(x)	\
654	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
655#define XL_TIMEOUT		1000
656
657/*
658 * General constants that are fun to know.
659 *
660 * 3Com PCI vendor ID
661 */
662#define	TC_VENDORID		0x10B7
663
664/*
665 * 3Com chip device IDs.
666 */
667#define	TC_DEVICEID_BOOMERANG_10BT		0x9000
668#define TC_DEVICEID_BOOMERANG_10BT_COMBO	0x9001
669#define TC_DEVICEID_BOOMERANG_10_100BT		0x9050
670#define TC_DEVICEID_BOOMERANG_100BT4		0x9051
671#define TC_DEVICEID_KRAKATOA_10BT		0x9004
672#define TC_DEVICEID_KRAKATOA_10BT_COMBO		0x9005
673#define TC_DEVICEID_KRAKATOA_10BT_TPC		0x9006
674#define TC_DEVICEID_CYCLONE_10FL		0x900A
675#define TC_DEVICEID_HURRICANE_10_100BT		0x9055
676#define TC_DEVICEID_CYCLONE_10_100BT4		0x9056
677#define TC_DEVICEID_CYCLONE_10_100_COMBO	0x9058
678#define TC_DEVICEID_CYCLONE_10_100FX		0x905A
679#define TC_DEVICEID_TORNADO_10_100BT		0x9200
680#define TC_DEVICEID_TORNADO_10_100BT_NVIDIA     0x9201
681#define TC_DEVICEID_HURRICANE_10_100BT_SERV	0x9800
682#define TC_DEVICEID_TORNADO_10_100BT_SERV	0x9805
683#define TC_DEVICEID_HURRICANE_SOHO100TX		0x7646
684#define TC_DEVICEID_TORNADO_HOMECONNECT		0x4500
685#define TC_DEVICEID_HURRICANE_555		0x5055
686#define TC_DEVICEID_HURRICANE_556		0x6055
687#define TC_DEVICEID_HURRICANE_556B		0x6056
688#define TC_DEVICEID_HURRICANE_575A		0x5057
689#define TC_DEVICEID_HURRICANE_575B		0x5157
690#define TC_DEVICEID_HURRICANE_575C		0x5257
691#define TC_DEVICEID_HURRICANE_656		0x6560
692#define TC_DEVICEID_HURRICANE_656B		0x6562
693#define TC_DEVICEID_TORNADO_656C		0x6564
694
695/*
696 * PCI low memory base and low I/O base register, and
697 * other PCI registers. Note: some are only available on
698 * the 3c905B, in particular those that related to power management.
699 */
700
701#define XL_PCI_VENDOR_ID	0x00
702#define XL_PCI_DEVICE_ID	0x02
703#define XL_PCI_COMMAND		0x04
704#define XL_PCI_STATUS		0x06
705#define XL_PCI_CLASSCODE	0x09
706#define XL_PCI_LATENCY_TIMER	0x0D
707#define XL_PCI_HEADER_TYPE	0x0E
708#define XL_PCI_LOIO		0x10
709#define XL_PCI_LOMEM		0x14
710#define XL_PCI_FUNCMEM		0x18
711#define XL_PCI_BIOSROM		0x30
712#define XL_PCI_INTLINE		0x3C
713#define XL_PCI_INTPIN		0x3D
714#define XL_PCI_MINGNT		0x3E
715#define XL_PCI_MINLAT		0x0F
716#define XL_PCI_RESETOPT		0x48
717#define XL_PCI_EEPROM_DATA	0x4C
718
719/* 3c905B-only registers */
720#define XL_PCI_CAPID		0xDC /* 8 bits */
721#define XL_PCI_NEXTPTR		0xDD /* 8 bits */
722#define XL_PCI_PWRMGMTCAP	0xDE /* 16 bits */
723#define XL_PCI_PWRMGMTCTRL	0xE0 /* 16 bits */
724
725#define XL_PSTATE_MASK		0x0003
726#define XL_PSTATE_D0		0x0000
727#define XL_PSTATE_D1		0x0002
728#define XL_PSTATE_D2		0x0002
729#define XL_PSTATE_D3		0x0003
730#define XL_PME_EN		0x0010
731#define XL_PME_STATUS		0x8000
732
733#ifndef IFM_10_FL
734#define IFM_10_FL	13		/* 10baseFL - Fiber */
735#endif
736