if_xereg.h revision 47133
1/*- 2 * Copyright (c) 1998, 1999 Scott Mitchell 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: if_xereg.h,v 1.2 1999/01/24 22:15:30 root Exp $ 27 */ 28 29/* 30 * Register definitions for Xircom CreditCard Ethernet adapters. See if_xe.c 31 * for details of supported hardware. Adapted from Werner Koch's 'xirc2ps' 32 * driver for Linux. 33 */ 34 35#include "xe.h" 36#if NXE > 0 37 38 39/* 40 * Common registers 41 */ 42#define XE_CR 0 /* Command register (write) */ 43#define XE_ESR 0 /* Ethernet status register (read) */ 44#define XE_PSR 1 /* Page select register */ 45#define XE_EDP 4 /* Ethernet data port */ 46#define XE_ISR 6 /* Interrupt status register */ 47 48/* 49 * Command register values 50 */ 51#define XE_CR_TX_PACKET 0x01 52#define XE_CR_SOFT_RESET 0x02 53#define XE_CR_ENABLE_INTR 0x04 54#define XE_CR_FORCE_INTR 0x08 55#define XE_CR_CLEAR_FIFO 0x10 56#define XE_CR_CLEAR_OVERRUN 0x20 57#define XE_CR_RESTART_TX 0x40 58 59/* 60 * Status register values 61 */ 62#define XE_ESR_FULL_PKT_RX 0x01 63#define XE_ESR_PKT_REJECT 0x04 64#define XE_ESR_TX_PENDING 0x08 65#define XE_ESR_BAD_POLARITY 0x10 66#define XE_ESR_MEDIA_SELECT 0x20 67 68/* 69 * Interrupt register values 70 */ 71#define XE_ISR_TX_OVERFLOW 0x01 72#define XE_ISR_TX_PACKET 0x02 73#define XE_ISR_MAC_INTR 0x04 74#define XE_ISR_TX_RES 0x08 75#define XE_ISR_RX_PACKET 0x20 76#define XE_ISR_RX_REJECT 0x40 77#define XE_ISR_FORCE_INTR 0x80 78 79 80/* 81 * Page 0 registers 82 */ 83#define XE_TSO 8 /* Transmit space open */ 84#define XE_TRS 10 /* Transmit reservation size */ 85#define XE_DOR 12 /* Data offset register (write) */ 86#define XE_RSR 12 /* Receive status register (read) */ 87#define XE_PTR 13 /* Packets transmitted register (read) */ 88#define XE_RBC 14 /* Received byte count (read) */ 89 90/* 91 * RSR values 92 */ 93#define XE_RSR_PHYS_PKT 0x01 94#define XE_RSR_BCAST_PKT 0x02 95#define XE_RSR_LONG_PKT 0x04 96#define XE_RSR_ALIGN_ERR 0x10 97#define XE_RSR_CRC_ERR 0x20 98#define XE_RSR_RX_OK 0x80 99 100 101/* 102 * Page 1 registers 103 */ 104#define XE_IMR0 12 /* Interrupt mask register, part 1 */ 105#define XE_IMR1 13 /* Interrupt mask register, part 2 */ 106#define XE_ECR 14 /* Ethernet configuration register */ 107 108/* 109 * ECR values 110 */ 111#define XE_ECR_FULL_DUPLEX 0x04 112#define XE_ECR_LONG_TPCABLE 0x08 113#define XE_ECR_NO_POLCOL 0x10 114#define XE_ECR_NO_LINKPULSE 0x20 115#define XE_ECR_NO_AUTOTX 0x40 116 117 118/* 119 * Page 2 registers 120 */ 121#define XE_RBS 8 /* Receive buffer start */ 122#define XE_LED 10 /* LED configuration register */ 123#define XE_MSR 12 /* Mohawk specfic register (Mohawk = CE3) */ 124#define XE_GPR2 13 /* General purpose register 2 */ 125 126 127/* 128 * Page 4 registers 129 */ 130#define XE_GPR0 8 /* General purpose register 0 */ 131#define XE_GPR1 9 /* General purpose register 1 */ 132#define XE_BOV 10 /* Bonding version register */ 133#define XE_LMA 12 /* Local memory address */ 134#define XE_LMD 14 /* Local memory data */ 135 136 137/* 138 * Page 5 registers 139 */ 140#define XE_RHS 10 /* Receive host start address */ 141 142 143/* 144 * Page 0x40 registers 145 */ 146#define XE_OCR 8 /* The Other command register */ 147#define XE_RXS0 9 /* Receive status 0 */ 148#define XE_TXS0 11 /* Transmit status 0 */ 149#define XE_TXS1 12 /* Transmit status 1 */ 150#define XE_RXM0 13 /* Receive mask register 0 */ 151#define XE_TXM0 14 /* Transmit mask register 0 */ 152#define XE_TXM1 15 /* Transmit mask register 1 */ 153 154/* 155 * OCR values 156 */ 157#define XE_OCR_TX 0x01 158#define XE_OCR_RX_ENABLE 0x04 159#define XE_OCR_RX_DISABLE 0x08 160#define XE_OCR_ABORT 0x10 161#define XE_OCR_ONLINE 0x20 162#define XE_OCR_ACK_INTR 0x40 163#define XE_OCR_OFFLINE 0x80 164 165 166/* 167 * Page 0x42 registers 168 */ 169#define XE_SWC0 8 /* Software configuration register 0 */ 170#define XE_SWC1 9 /* Software configuration register 1 */ 171#define XE_BOC 10 /* Back-off configuration */ 172 173 174/* 175 * Page 0x44 registers 176 */ 177#define XE_TDR0 8 /* Time domain reflectometry register 0 */ 178#define XE_TDR1 9 /* Time domain reflectometry register 1 */ 179#define XE_RXC0 10 /* Receive byte count low */ 180#define XE_RXC1 11 /* Receive byte count high */ 181 182 183/* 184 * Page 0x45 registers 185 */ 186#define XE_REV 15 /* Revision (read) */ 187 188 189/* 190 * Page 0x50 registers 191 */ 192#define XE_IAR 8 /* Individual address register */ 193 194 195/* 196 * Pages 0x43, 0x46-0x4f and 0x51-0x5e apparently don't exist. 197 * The remainder of 0x0-0x8 and 0x40-0x5f exist, but I have no 198 * idea what's on most of them. 199 */ 200 201 202/* 203 * MII/PHY defines adapted from the xl driver. These need cleaning up a 204 * little if we end up using them. 205 */ 206#define XE_MII_CLK 0x01 207#define XE_MII_DIR 0x08 208#define XE_MII_WRD 0x02 209#define XE_MII_RDD 0x20 210#define XE_MII_STARTDELIM 0x01 211#define XE_MII_READOP 0x02 212#define XE_MII_WRITEOP 0x01 213#define XE_MII_TURNAROUND 0x02 214 215#define XE_MII_SET(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) | (x)) 216#define XE_MII_CLR(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) & ~(x)) 217 218#define XL_PHY_GENCTL 0x00 219#define XL_PHY_GENSTS 0x01 220#define XL_PHY_VENID 0x02 221#define XL_PHY_DEVID 0x03 222#define XL_PHY_ANAR 0x04 223#define XL_PHY_LPAR 0x05 224#define XL_PHY_ANER 0x06 225 226#define PHY_ANAR_NEXTPAGE 0x8000 227#define PHY_ANAR_RSVD0 0x4000 228#define PHY_ANAR_TLRFLT 0x2000 229#define PHY_ANAR_RSVD1 0x1000 230#define PHY_ANAR_RSVD2 0x0800 231#define PHY_ANAR_RSVD3 0x0400 232#define PHY_ANAR_100BT4 0x0200 233#define PHY_ANAR_100BTXFULL 0x0100 234#define PHY_ANAR_100BTXHALF 0x0080 235#define PHY_ANAR_10BTFULL 0x0040 236#define PHY_ANAR_10BTHALF 0x0020 237#define PHY_ANAR_PROTO4 0x0010 238#define PHY_ANAR_PROTO3 0x0008 239#define PHY_ANAR_PROTO2 0x0004 240#define PHY_ANAR_PROTO1 0x0002 241#define PHY_ANAR_PROTO0 0x0001 242 243/* 244 * PHY BMCR Basic Mode Control Register 245 */ 246#define PHY_BMCR 0x00 247#define PHY_BMCR_RESET 0x8000 248#define PHY_BMCR_LOOPBK 0x4000 249#define PHY_BMCR_SPEEDSEL 0x2000 250#define PHY_BMCR_AUTONEGENBL 0x1000 251#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 252#define PHY_BMCR_ISOLATE 0x0400 253#define PHY_BMCR_AUTONEGRSTR 0x0200 254#define PHY_BMCR_DUPLEX 0x0100 255#define PHY_BMCR_COLLTEST 0x0080 256#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 257#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 258#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 259#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 260#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 261#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 262#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 263 264/* 265 * PHY, BMSR Basic Mode Status Register 266 */ 267#define PHY_BMSR 0x01 268#define PHY_BMSR_100BT4 0x8000 269#define PHY_BMSR_100BTXFULL 0x4000 270#define PHY_BMSR_100BTXHALF 0x2000 271#define PHY_BMSR_10BTFULL 0x1000 272#define PHY_BMSR_10BTHALF 0x0800 273#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 274#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 275#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 276#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 277#define PHY_BMSR_MFPRESUP 0x0040 278#define PHY_BMSR_AUTONEGCOMP 0x0020 279#define PHY_BMSR_REMFAULT 0x0010 280#define PHY_BMSR_CANAUTONEG 0x0008 281#define PHY_BMSR_LINKSTAT 0x0004 282#define PHY_BMSR_JABBER 0x0002 283#define PHY_BMSR_EXTENDED 0x0001 284 285 286#endif /* NXE > 0 */ 287