if_wpireg.h revision 289124
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 289124 2015-10-11 01:31:18Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23 24#ifdef DIAGNOSTIC 25#define WPI_RX_RING_COUNT_LOG 8 26#else 27#define WPI_RX_RING_COUNT_LOG 6 28#endif 29 30#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31 32#define WPI_NTXQUEUES 8 33#define WPI_DRV_NTXQUEUES 5 34#define WPI_CMD_QUEUE_NUM 4 35 36#define WPI_NDMACHNLS 6 37 38/* Maximum scatter/gather. */ 39#define WPI_MAX_SCATTER 4 40 41/* 42 * Rings must be aligned on a 16K boundary. 43 */ 44#define WPI_RING_DMA_ALIGN 0x4000 45 46/* Maximum Rx buffer size. */ 47#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48 49/* 50 * Control and status registers. 51 */ 52#define WPI_HW_IF_CONFIG 0x000 53#define WPI_INT 0x008 54#define WPI_INT_MASK 0x00c 55#define WPI_FH_INT 0x010 56#define WPI_GPIO_IN 0x018 57#define WPI_RESET 0x020 58#define WPI_GP_CNTRL 0x024 59#define WPI_EEPROM 0x02c 60#define WPI_EEPROM_GP 0x030 61#define WPI_GIO 0x03c 62#define WPI_UCODE_GP1 0x054 63#define WPI_UCODE_GP1_SET 0x058 64#define WPI_UCODE_GP1_CLR 0x05c 65#define WPI_UCODE_GP2 0x060 66#define WPI_GIO_CHICKEN 0x100 67#define WPI_ANA_PLL 0x20c 68#define WPI_DBG_HPET_MEM 0x240 69#define WPI_MEM_RADDR 0x40c 70#define WPI_MEM_WADDR 0x410 71#define WPI_MEM_WDATA 0x418 72#define WPI_MEM_RDATA 0x41c 73#define WPI_PRPH_WADDR 0x444 74#define WPI_PRPH_RADDR 0x448 75#define WPI_PRPH_WDATA 0x44c 76#define WPI_PRPH_RDATA 0x450 77#define WPI_HBUS_TARG_WRPTR 0x460 78 79/* 80 * Flow-Handler registers. 81 */ 82#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84#define WPI_FH_RX_CONFIG 0xc00 85#define WPI_FH_RX_BASE 0xc04 86#define WPI_FH_RX_WPTR 0xc20 87#define WPI_FH_RX_RPTR_ADDR 0xc24 88#define WPI_FH_RSSR_TBL 0xcc0 89#define WPI_FH_RX_STATUS 0xcc4 90#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91#define WPI_FH_TX_BASE 0xe80 92#define WPI_FH_MSG_CONFIG 0xe88 93#define WPI_FH_TX_STATUS 0xe90 94 95 96/* 97 * NIC internal memory offsets. 98 */ 99#define WPI_ALM_SCHED_MODE 0x2e00 100#define WPI_ALM_SCHED_ARASTAT 0x2e04 101#define WPI_ALM_SCHED_TXFACT 0x2e10 102#define WPI_ALM_SCHED_TXF4MF 0x2e14 103#define WPI_ALM_SCHED_TXF5MF 0x2e20 104#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106#define WPI_APMG_CLK_CTRL 0x3000 107#define WPI_APMG_CLK_EN 0x3004 108#define WPI_APMG_CLK_DIS 0x3008 109#define WPI_APMG_PS 0x300c 110#define WPI_APMG_PCI_STT 0x3010 111#define WPI_APMG_RFKILL 0x3014 112#define WPI_BSM_WR_CTRL 0x3400 113#define WPI_BSM_WR_MEM_SRC 0x3404 114#define WPI_BSM_WR_MEM_DST 0x3408 115#define WPI_BSM_WR_DWCOUNT 0x340c 116#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120#define WPI_BSM_SRAM_BASE 0x3800 121 122 123/* Possible flags for register WPI_HW_IF_CONFIG. */ 124#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129 130/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132 133/* Possible values for WPI_BSM_WR_MEM_DST. */ 134#define WPI_FW_TEXT_BASE 0x00000000 135#define WPI_FW_DATA_BASE 0x00800000 136 137/* Possible flags for WPI_GPIO_IN. */ 138#define WPI_GPIO_IN_VMAIN (1 << 9) 139 140/* Possible flags for register WPI_RESET. */ 141#define WPI_RESET_NEVO (1 << 0) 142#define WPI_RESET_SW (1 << 7) 143#define WPI_RESET_MASTER_DISABLED (1 << 8) 144#define WPI_RESET_STOP_MASTER (1 << 9) 145 146/* Possible flags for register WPI_GP_CNTRL. */ 147#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151#define WPI_GP_CNTRL_SLEEP (1 << 4) 152#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154#define WPI_GP_CNTRL_RFKILL (1 << 27) 155 156/* Possible flags for register WPI_GIO_CHICKEN. */ 157#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159 160/* Possible flags for register WPI_GIO. */ 161#define WPI_GIO_L0S_ENA (1 << 1) 162 163/* Possible flags for register WPI_FH_RX_CONFIG. */ 164#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171 172/* Possible flags for register WPI_ANA_PLL. */ 173#define WPI_ANA_PLL_INIT (1 << 24) 174 175/* Possible flags for register WPI_UCODE_GP1*. */ 176#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177#define WPI_UCODE_GP1_RFKILL (1 << 1) 178#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179 180/* Possible flags for register WPI_FH_RX_STATUS. */ 181#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182 183/* Possible flags for register WPI_BSM_WR_CTRL. */ 184#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185#define WPI_BSM_WR_CTRL_START (1U << 31) 186 187/* Possible flags for register WPI_INT. */ 188#define WPI_INT_ALIVE (1 << 0) 189#define WPI_INT_WAKEUP (1 << 1) 190#define WPI_INT_SW_RX (1 << 3) 191#define WPI_INT_SW_ERR (1 << 25) 192#define WPI_INT_FH_TX (1 << 27) 193#define WPI_INT_HW_ERR (1 << 29) 194#define WPI_INT_FH_RX (1U << 31) 195 196/* Shortcut. */ 197#define WPI_INT_MASK_DEF \ 198 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200 WPI_INT_SW_RX) 201 202/* Possible flags for register WPI_FH_INT. */ 203#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204#define WPI_FH_INT_HI_PRIOR (1 << 30) 205/* Shortcuts for the above. */ 206#define WPI_FH_INT_RX \ 207 (WPI_FH_INT_RX_CHNL(0) | \ 208 WPI_FH_INT_RX_CHNL(1) | \ 209 WPI_FH_INT_RX_CHNL(2) | \ 210 WPI_FH_INT_HI_PRIOR) 211 212/* Possible flags for register WPI_FH_TX_STATUS. */ 213#define WPI_FH_TX_STATUS_IDLE(qid) \ 214 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215 216/* Possible flags for register WPI_EEPROM. */ 217#define WPI_EEPROM_READ_VALID (1 << 0) 218 219/* Possible flags for register WPI_EEPROM_GP. */ 220#define WPI_EEPROM_VERSION 0x00000007 221#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222 223/* Possible flags for register WPI_APMG_PS. */ 224#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225 226/* Possible flags for registers WPI_APMG_CLK_*. */ 227#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229 230/* Possible flags for register WPI_APMG_PCI_STT. */ 231#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232 233struct wpi_shared { 234 uint32_t txbase[WPI_NTXQUEUES]; 235 uint32_t next; 236 uint32_t reserved[2]; 237} __packed; 238 239#define WPI_MAX_SEG_LEN 65520 240struct wpi_tx_desc { 241 uint8_t reserved1[3]; 242 uint8_t nsegs; 243#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244 245 struct { 246 uint32_t addr; 247 uint32_t len; 248 } __packed segs[WPI_MAX_SCATTER]; 249 uint8_t reserved2[28]; 250} __packed; 251 252struct wpi_tx_stat { 253 uint8_t rtsfailcnt; 254 uint8_t ackfailcnt; 255 uint8_t btkillcnt; 256 uint8_t rate; 257 uint32_t duration; 258 uint32_t status; 259#define WPI_TX_STATUS_SUCCESS 0x01 260#define WPI_TX_STATUS_DIRECT_DONE 0x02 261#define WPI_TX_STATUS_FAIL 0x80 262#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 263#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 264#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 265#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 266#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 267#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 268#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 269#define WPI_TX_STATUS_FAIL_ABORTED 0x89 270#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 271#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 272#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 273#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 274#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 275#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 276#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 277#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 278 279} __packed; 280 281struct wpi_rx_desc { 282 uint32_t len; 283 uint8_t type; 284#define WPI_UC_READY 1 285#define WPI_RX_DONE 27 286#define WPI_TX_DONE 28 287#define WPI_START_SCAN 130 288#define WPI_SCAN_RESULTS 131 289#define WPI_STOP_SCAN 132 290#define WPI_BEACON_SENT 144 291#define WPI_RX_STATISTICS 156 292#define WPI_BEACON_STATISTICS 157 293#define WPI_STATE_CHANGED 161 294#define WPI_BEACON_MISSED 162 295 296 uint8_t flags; 297 uint8_t idx; 298 uint8_t qid; 299} __packed; 300 301#define WPI_RX_DESC_QID_MSK 0x07 302#define WPI_UNSOLICITED_RX_NOTIF 0x80 303 304struct wpi_rx_stat { 305 uint8_t len; 306#define WPI_STAT_MAXLEN 20 307 308 uint8_t id; 309 uint8_t rssi; /* received signal strength */ 310#define WPI_RSSI_OFFSET -95 311 312 uint8_t agc; /* access gain control */ 313 uint16_t signal; 314 uint16_t noise; 315} __packed; 316 317struct wpi_rx_head { 318 uint16_t chan; 319 uint16_t flags; 320#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 321 322 uint8_t reserved; 323 uint8_t plcp; 324 uint16_t len; 325} __packed; 326 327struct wpi_rx_tail { 328 uint32_t flags; 329#define WPI_RX_NO_CRC_ERR (1 << 0) 330#define WPI_RX_NO_OVFL_ERR (1 << 1) 331/* shortcut for the above */ 332#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 333#define WPI_RX_CIPHER_MASK (7 << 8) 334#define WPI_RX_CIPHER_CCMP (2 << 8) 335#define WPI_RX_DECRYPT_MASK (3 << 11) 336#define WPI_RX_DECRYPT_OK (3 << 11) 337 338 uint64_t tstamp; 339 uint32_t tbeacon; 340} __packed; 341 342struct wpi_tx_cmd { 343 uint8_t code; 344#define WPI_CMD_RXON 16 345#define WPI_CMD_RXON_ASSOC 17 346#define WPI_CMD_EDCA_PARAMS 19 347#define WPI_CMD_TIMING 20 348#define WPI_CMD_ADD_NODE 24 349#define WPI_CMD_DEL_NODE 25 350#define WPI_CMD_TX_DATA 28 351#define WPI_CMD_MRR_SETUP 71 352#define WPI_CMD_SET_LED 72 353#define WPI_CMD_SET_POWER_MODE 119 354#define WPI_CMD_SCAN 128 355#define WPI_CMD_SCAN_ABORT 129 356#define WPI_CMD_SET_BEACON 145 357#define WPI_CMD_TXPOWER 151 358#define WPI_CMD_BT_COEX 155 359#define WPI_CMD_GET_STATISTICS 156 360 361 uint8_t flags; 362 uint8_t idx; 363 uint8_t qid; 364 uint8_t data[124]; 365} __packed; 366 367/* Structure for command WPI_CMD_RXON. */ 368struct wpi_rxon { 369 uint8_t myaddr[IEEE80211_ADDR_LEN]; 370 uint16_t reserved1; 371 uint8_t bssid[IEEE80211_ADDR_LEN]; 372 uint16_t reserved2; 373 uint8_t wlap[IEEE80211_ADDR_LEN]; 374 uint16_t reserved3; 375 uint8_t mode; 376#define WPI_MODE_HOSTAP 1 377#define WPI_MODE_STA 3 378#define WPI_MODE_IBSS 4 379#define WPI_MODE_MONITOR 6 380 381 uint8_t air; 382 uint16_t reserved4; 383 uint8_t ofdm_mask; 384 uint8_t cck_mask; 385 uint16_t associd; 386 uint32_t flags; 387#define WPI_RXON_24GHZ (1 << 0) 388#define WPI_RXON_CCK (1 << 1) 389#define WPI_RXON_AUTO (1 << 2) 390#define WPI_RXON_SHSLOT (1 << 4) 391#define WPI_RXON_SHPREAMBLE (1 << 5) 392#define WPI_RXON_NODIVERSITY (1 << 7) 393#define WPI_RXON_ANTENNA_A (1 << 8) 394#define WPI_RXON_ANTENNA_B (1 << 9) 395#define WPI_RXON_TSF (1 << 15) 396#define WPI_RXON_CTS_TO_SELF (1 << 30) 397 398 uint32_t filter; 399#define WPI_FILTER_PROMISC (1 << 0) 400#define WPI_FILTER_CTL (1 << 1) 401#define WPI_FILTER_MULTICAST (1 << 2) 402#define WPI_FILTER_NODECRYPT (1 << 3) 403#define WPI_FILTER_BSS (1 << 5) 404#define WPI_FILTER_BEACON (1 << 6) 405#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 406 407 uint8_t chan; 408 uint16_t reserved5; 409} __packed; 410 411/* Structure for command WPI_CMD_RXON_ASSOC. */ 412struct wpi_assoc { 413 uint32_t flags; 414 uint32_t filter; 415 uint8_t ofdm_mask; 416 uint8_t cck_mask; 417 uint16_t reserved; 418} __packed; 419 420/* Structure for command WPI_CMD_EDCA_PARAMS. */ 421struct wpi_edca_params { 422 uint32_t flags; 423#define WPI_EDCA_UPDATE (1 << 0) 424 425 struct { 426 uint16_t cwmin; 427 uint16_t cwmax; 428 uint8_t aifsn; 429 uint8_t reserved; 430 uint16_t txoplimit; 431 } __packed ac[WME_NUM_AC]; 432} __packed; 433 434/* Structure for command WPI_CMD_TIMING. */ 435struct wpi_cmd_timing { 436 uint64_t tstamp; 437 uint16_t bintval; 438 uint16_t atim; 439 uint32_t binitval; 440 uint16_t lintval; 441 uint16_t reserved; 442} __packed; 443 444/* Structure for command WPI_CMD_ADD_NODE. */ 445struct wpi_node_info { 446 uint8_t control; 447#define WPI_NODE_UPDATE (1 << 0) 448 449 uint8_t reserved1[3]; 450 uint8_t macaddr[IEEE80211_ADDR_LEN]; 451 uint16_t reserved2; 452 uint8_t id; 453#define WPI_ID_BSS 0 454#define WPI_ID_IBSS_MIN 2 455#define WPI_ID_IBSS_MAX 23 456#define WPI_ID_BROADCAST 24 457#define WPI_ID_UNDEFINED (uint8_t)-1 458 459 uint8_t flags; 460#define WPI_FLAG_KEY_SET (1 << 0) 461 462 uint16_t reserved3; 463 uint16_t kflags; 464#define WPI_KFLAG_CCMP (1 << 1) 465#define WPI_KFLAG_KID(kid) ((kid) << 8) 466#define WPI_KFLAG_MULTICAST (1 << 14) 467 468 uint8_t tsc2; 469 uint8_t reserved4; 470 uint16_t ttak[5]; 471 uint16_t reserved5; 472 uint8_t key[IEEE80211_KEYBUF_SIZE]; 473 uint32_t action; 474#define WPI_ACTION_SET_RATE (1 << 2) 475 476 uint32_t mask; 477 uint16_t tid; 478 uint8_t plcp; 479 uint8_t antenna; 480#define WPI_ANTENNA_A (1 << 6) 481#define WPI_ANTENNA_B (1 << 7) 482#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 483 484 uint8_t add_imm; 485 uint8_t del_imm; 486 uint16_t add_imm_start; 487} __packed; 488 489/* Structure for command WPI_CMD_DEL_NODE. */ 490struct wpi_cmd_del_node { 491 uint8_t count; 492 uint8_t reserved1[3]; 493 uint8_t macaddr[IEEE80211_ADDR_LEN]; 494 uint16_t reserved2; 495} __packed; 496 497/* Structure for command WPI_CMD_TX_DATA. */ 498struct wpi_cmd_data { 499 uint16_t len; 500 uint16_t lnext; 501 uint32_t flags; 502#define WPI_TX_NEED_RTS (1 << 1) 503#define WPI_TX_NEED_CTS (1 << 2) 504#define WPI_TX_NEED_ACK (1 << 3) 505#define WPI_TX_FULL_TXOP (1 << 7) 506#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 507#define WPI_TX_AUTO_SEQ (1 << 13) 508#define WPI_TX_MORE_FRAG (1 << 14) 509#define WPI_TX_INSERT_TSTAMP (1 << 16) 510 511 uint8_t plcp; 512 uint8_t id; 513 uint8_t tid; 514 uint8_t security; 515#define WPI_CIPHER_WEP 1 516#define WPI_CIPHER_CCMP 2 517#define WPI_CIPHER_TKIP 3 518#define WPI_CIPHER_WEP104 9 519 520 uint8_t key[IEEE80211_KEYBUF_SIZE]; 521 uint8_t tkip[IEEE80211_WEP_MICLEN]; 522 uint32_t fnext; 523 uint32_t lifetime; 524#define WPI_LIFETIME_INFINITE 0xffffffff 525 526 uint8_t ofdm_mask; 527 uint8_t cck_mask; 528 uint8_t rts_ntries; 529 uint8_t data_ntries; 530 uint16_t timeout; 531 uint16_t txop; 532} __packed; 533 534/* Structure for command WPI_CMD_SET_BEACON. */ 535struct wpi_cmd_beacon { 536 uint16_t len; 537 uint16_t reserved1; 538 uint32_t flags; /* same as wpi_cmd_data */ 539 uint8_t plcp; 540 uint8_t id; 541 uint8_t reserved2[30]; 542 uint32_t lifetime; 543 uint8_t ofdm_mask; 544 uint8_t cck_mask; 545 uint16_t reserved3[3]; 546 uint16_t tim; 547 uint8_t timsz; 548 uint8_t reserved4; 549} __packed; 550 551/* Structure for notification WPI_BEACON_MISSED. */ 552struct wpi_beacon_missed { 553 uint32_t consecutive; 554 uint32_t total; 555 uint32_t expected; 556 uint32_t received; 557} __packed; 558 559 560/* Structure for command WPI_CMD_MRR_SETUP. */ 561#define WPI_RIDX_MAX 11 562struct wpi_mrr_setup { 563 uint32_t which; 564#define WPI_MRR_CTL 0 565#define WPI_MRR_DATA 1 566 567 struct { 568 uint8_t plcp; 569 uint8_t flags; 570 uint8_t ntries; 571#define WPI_NTRIES_DEFAULT 2 572 573 uint8_t next; 574 } __packed rates[WPI_RIDX_MAX + 1]; 575} __packed; 576 577/* Structure for command WPI_CMD_SET_LED. */ 578struct wpi_cmd_led { 579 uint32_t unit; /* multiplier (in usecs) */ 580 uint8_t which; 581#define WPI_LED_ACTIVITY 1 582#define WPI_LED_LINK 2 583 584 uint8_t off; 585 uint8_t on; 586 uint8_t reserved; 587} __packed; 588 589/* Structure for command WPI_CMD_SET_POWER_MODE. */ 590struct wpi_pmgt_cmd { 591 uint16_t flags; 592#define WPI_PS_ALLOW_SLEEP (1 << 0) 593#define WPI_PS_NOTIFY (1 << 1) 594#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 595#define WPI_PS_PCI_PMGT (1 << 3) 596 597 uint8_t reserved[2]; 598 uint32_t rxtimeout; 599 uint32_t txtimeout; 600 uint32_t intval[5]; 601} __packed; 602 603/* Structures for command WPI_CMD_SCAN. */ 604#define WPI_SCAN_MAX_ESSIDS 4 605struct wpi_scan_essid { 606 uint8_t id; 607 uint8_t len; 608 uint8_t data[IEEE80211_NWID_LEN]; 609} __packed; 610 611struct wpi_scan_hdr { 612 uint16_t len; 613 uint8_t reserved1; 614 uint8_t nchan; 615 uint16_t quiet_time; /* timeout in milliseconds */ 616#define WPI_QUIET_TIME_DEFAULT 10 617 618 uint16_t quiet_threshold; /* min # of packets */ 619 uint16_t crc_threshold; 620 uint16_t reserved2; 621 uint32_t max_svc; /* background scans */ 622 uint32_t pause_svc; /* background scans */ 623#define WPI_PAUSE_MAX_TIME ((1 << 20) - 1) 624#define WPI_PAUSE_SCAN(nbeacons, time) ((nbeacons << 24) | time) 625 626 uint32_t flags; 627 uint32_t filter; 628 629 /* Followed by a struct wpi_cmd_data. */ 630 /* Followed by an array of 4 structs wpi_scan_essid. */ 631 /* Followed by probe request body. */ 632 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 633} __packed; 634 635struct wpi_scan_chan { 636 uint8_t flags; 637#define WPI_CHAN_ACTIVE (1 << 0) 638#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 639 640 uint8_t chan; 641 uint8_t rf_gain; 642 uint8_t dsp_gain; 643 uint16_t active; /* msecs */ 644 uint16_t passive; /* msecs */ 645} __packed; 646 647#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 648#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 649 650/* Maximum size of a scan command. */ 651#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 652 653#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 654#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 655#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 656#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 657 658#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 659#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 660#define WPI_PASSIVE_DWELL_BASE (100) 661#define WPI_CHANNEL_TUNE_TIME ( 6) 662 663/* Structure for command WPI_CMD_TXPOWER. */ 664struct wpi_cmd_txpower { 665 uint8_t band; 666#define WPI_BAND_5GHZ 0 667#define WPI_BAND_2GHZ 1 668 669 uint8_t reserved; 670 uint16_t chan; 671 672 struct { 673 uint8_t plcp; 674 uint8_t rf_gain; 675 uint8_t dsp_gain; 676 uint8_t reserved; 677 } __packed rates[WPI_RIDX_MAX + 1]; 678 679} __packed; 680 681/* Structure for command WPI_CMD_BT_COEX. */ 682struct wpi_bluetooth { 683 uint8_t flags; 684#define WPI_BT_COEX_DISABLE 0 685#define WPI_BT_COEX_MODE_2WIRE 1 686#define WPI_BT_COEX_MODE_3WIRE 2 687#define WPI_BT_COEX_MODE_4WIRE 3 688 689 uint8_t lead_time; 690#define WPI_BT_LEAD_TIME_DEF 30 691 692 uint8_t max_kill; 693#define WPI_BT_MAX_KILL_DEF 5 694 695 uint8_t reserved; 696 uint32_t kill_ack; 697 uint32_t kill_cts; 698} __packed; 699 700/* Structure for WPI_UC_READY notification. */ 701struct wpi_ucode_info { 702 uint8_t minor; 703 uint8_t major; 704 uint16_t reserved1; 705 uint8_t revision[8]; 706 uint8_t type; 707 uint8_t subtype; 708 uint16_t reserved2; 709 uint32_t logptr; 710 uint32_t errptr; 711 uint32_t tstamp; 712 uint32_t valid; 713} __packed; 714 715/* Structure for WPI_START_SCAN notification. */ 716struct wpi_start_scan { 717 uint64_t tstamp; 718 uint32_t tbeacon; 719 uint8_t chan; 720 uint8_t band; 721 uint16_t reserved; 722 uint32_t status; 723} __packed; 724 725/* Structure for WPI_STOP_SCAN notification. */ 726struct wpi_stop_scan { 727 uint8_t nchan; 728 uint8_t status; 729#define WPI_SCAN_COMPLETED 1 730#define WPI_SCAN_ABORTED 2 731 732 uint8_t reserved; 733 uint8_t chan; 734 uint64_t tsf; 735} __packed; 736 737/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 738struct wpi_rx_phy_stats { 739 uint32_t ina; 740 uint32_t fina; 741 uint32_t bad_plcp; 742 uint32_t bad_crc32; 743 uint32_t overrun; 744 uint32_t eoverrun; 745 uint32_t good_crc32; 746 uint32_t fa; 747 uint32_t bad_fina_sync; 748 uint32_t sfd_timeout; 749 uint32_t fina_timeout; 750 uint32_t no_rts_ack; 751 uint32_t rxe_limit; 752 uint32_t ack; 753 uint32_t cts; 754} __packed; 755 756struct wpi_rx_general_stats { 757 uint32_t bad_cts; 758 uint32_t bad_ack; 759 uint32_t not_bss; 760 uint32_t filtered; 761 uint32_t bad_chan; 762} __packed; 763 764struct wpi_rx_stats { 765 struct wpi_rx_phy_stats ofdm; 766 struct wpi_rx_phy_stats cck; 767 struct wpi_rx_general_stats general; 768} __packed; 769 770struct wpi_tx_stats { 771 uint32_t preamble; 772 uint32_t rx_detected; 773 uint32_t bt_defer; 774 uint32_t bt_kill; 775 uint32_t short_len; 776 uint32_t cts_timeout; 777 uint32_t ack_timeout; 778 uint32_t exp_ack; 779 uint32_t ack; 780} __packed; 781 782struct wpi_general_stats { 783 uint32_t temp; 784 uint32_t burst_check; 785 uint32_t burst; 786 uint32_t reserved[4]; 787 uint32_t sleep; 788 uint32_t slot_out; 789 uint32_t slot_idle; 790 uint32_t ttl_tstamp; 791 uint32_t tx_ant_a; 792 uint32_t tx_ant_b; 793 uint32_t exec; 794 uint32_t probe; 795} __packed; 796 797struct wpi_stats { 798 uint32_t flags; 799 struct wpi_rx_stats rx; 800 struct wpi_tx_stats tx; 801 struct wpi_general_stats general; 802} __packed; 803 804/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 805#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 806 807 808/* Firmware error dump entry. */ 809struct wpi_fw_dump { 810 uint32_t desc; 811 uint32_t time; 812 uint32_t blink[2]; 813 uint32_t ilink[2]; 814 uint32_t data; 815} __packed; 816 817/* Firmware image file header. */ 818struct wpi_firmware_hdr { 819 820#define WPI_FW_MINVERSION 2144 821#define WPI_FW_NAME "wpifw" 822 823 uint16_t driver; 824 uint8_t minor; 825 uint8_t major; 826 uint32_t rtextsz; 827 uint32_t rdatasz; 828 uint32_t itextsz; 829 uint32_t idatasz; 830 uint32_t btextsz; 831} __packed; 832 833#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 834#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 835#define WPI_FW_BOOT_TEXT_MAXSZ 1024 836 837#define WPI_FW_UPDATED (1U << 31 ) 838 839/* 840 * Offsets into EEPROM. 841 */ 842#define WPI_EEPROM_MAC 0x015 843#define WPI_EEPROM_REVISION 0x035 844#define WPI_EEPROM_SKU_CAP 0x045 845#define WPI_EEPROM_TYPE 0x04a 846#define WPI_EEPROM_DOMAIN 0x060 847#define WPI_EEPROM_BAND1 0x063 848#define WPI_EEPROM_BAND2 0x072 849#define WPI_EEPROM_BAND3 0x080 850#define WPI_EEPROM_BAND4 0x08d 851#define WPI_EEPROM_BAND5 0x099 852#define WPI_EEPROM_POWER_GRP 0x100 853 854struct wpi_eeprom_chan { 855 uint8_t flags; 856#define WPI_EEPROM_CHAN_VALID (1 << 0) 857#define WPI_EEPROM_CHAN_IBSS (1 << 1) 858#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 859#define WPI_EEPROM_CHAN_RADAR (1 << 4) 860 861 int8_t maxpwr; 862} __packed; 863 864struct wpi_eeprom_sample { 865 uint8_t index; 866 int8_t power; 867 uint16_t volt; 868} __packed; 869 870#define WPI_POWER_GROUPS_COUNT 5 871struct wpi_eeprom_group { 872 struct wpi_eeprom_sample samples[5]; 873 int32_t coef[5]; 874 int32_t corr[5]; 875 int8_t maxpwr; 876 uint8_t chan; 877 int16_t temp; 878} __packed; 879 880#define WPI_CHAN_BANDS_COUNT 5 881#define WPI_MAX_CHAN_PER_BAND 14 882static const struct wpi_chan_band { 883 uint32_t addr; /* offset in EEPROM */ 884 uint8_t nchan; 885 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 886} wpi_bands[] = { 887 /* 20MHz channels, 2GHz band. */ 888 { WPI_EEPROM_BAND1, 14, 889 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 890 /* 20MHz channels, 5GHz band. */ 891 { WPI_EEPROM_BAND2, 13, 892 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 893 { WPI_EEPROM_BAND3, 12, 894 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 895 { WPI_EEPROM_BAND4, 11, 896 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 897 { WPI_EEPROM_BAND5, 6, 898 { 145, 149, 153, 157, 161, 165 } } 899}; 900 901/* HW rate indices. */ 902#define WPI_RIDX_OFDM6 0 903#define WPI_RIDX_OFDM36 5 904#define WPI_RIDX_OFDM48 6 905#define WPI_RIDX_OFDM54 7 906#define WPI_RIDX_CCK1 8 907#define WPI_RIDX_CCK2 9 908#define WPI_RIDX_CCK11 11 909 910static const uint8_t wpi_ridx_to_plcp[] = { 911 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 912 /* R1-R4 (ral/ural is R4-R1) */ 913 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 914 /* CCK: device-dependent */ 915 10, 20, 55, 110 916}; 917 918#define WPI_MAX_PWR_INDEX 77 919 920/* 921 * RF Tx gain values from highest to lowest power (values obtained from 922 * the reference driver.) 923 */ 924static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 925 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 926 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 927 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 928 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 929 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 930 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 931 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 932 0x03 933}; 934 935static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 936 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 937 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 938 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 939 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 940 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 941 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 942 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 943 0x03 944}; 945 946/* 947 * DSP pre-DAC gain values from highest to lowest power (values obtained 948 * from the reference driver.) 949 */ 950static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 951 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 952 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 953 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 954 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 955 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 956 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 957 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 958 0x5f 959}; 960 961static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 962 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 963 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 964 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 965 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 966 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 967 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 968 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 969 0x78 970}; 971 972/* 973 * Power saving settings (values obtained from the reference driver.) 974 */ 975#define WPI_NDTIMRANGES 2 976#define WPI_NPOWERLEVELS 6 977static const struct wpi_pmgt { 978 uint32_t rxtimeout; 979 uint32_t txtimeout; 980 uint32_t intval[5]; 981 uint8_t skip_dtim; 982} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 983 /* DTIM <= 10 */ 984 { 985 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 986 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 987 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 988 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 989 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 990 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 991 }, 992 /* DTIM >= 11 */ 993 { 994 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 995 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 996 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 997 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 998 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 999 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1000 } 1001}; 1002 1003/* Firmware errors. */ 1004static const char * const wpi_fw_errmsg[] = { 1005 "OK", 1006 "FAIL", 1007 "BAD_PARAM", 1008 "BAD_CHECKSUM", 1009 "NMI_INTERRUPT", 1010 "SYSASSERT", 1011 "FATAL_ERROR" 1012}; 1013 1014#define WPI_READ(sc, reg) \ 1015 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1016 1017#define WPI_WRITE(sc, reg, val) \ 1018 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1019 1020#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1021 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1022 (datap), (count)) 1023 1024#define WPI_SETBITS(sc, reg, mask) \ 1025 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1026 1027#define WPI_CLRBITS(sc, reg, mask) \ 1028 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1029 1030#define WPI_BARRIER_WRITE(sc) \ 1031 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1032 BUS_SPACE_BARRIER_WRITE) 1033 1034#define WPI_BARRIER_READ_WRITE(sc) \ 1035 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1036 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1037