if_wpireg.h revision 280119
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 280119 2015-03-15 21:30:20Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23 24#ifdef DIAGNOSTIC 25#define WPI_RX_RING_COUNT_LOG 8 26#else 27#define WPI_RX_RING_COUNT_LOG 6 28#endif 29 30#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31 32#define WPI_NTXQUEUES 8 33#define WPI_DRV_NTXQUEUES 5 34#define WPI_CMD_QUEUE_NUM 4 35 36#define WPI_NDMACHNLS 6 37 38/* Maximum scatter/gather. */ 39#define WPI_MAX_SCATTER 4 40 41/* 42 * Rings must be aligned on a 16K boundary. 43 */ 44#define WPI_RING_DMA_ALIGN 0x4000 45 46/* Maximum Rx buffer size. */ 47#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48 49/* 50 * Control and status registers. 51 */ 52#define WPI_HW_IF_CONFIG 0x000 53#define WPI_INT 0x008 54#define WPI_INT_MASK 0x00c 55#define WPI_FH_INT 0x010 56#define WPI_GPIO_IN 0x018 57#define WPI_RESET 0x020 58#define WPI_GP_CNTRL 0x024 59#define WPI_EEPROM 0x02c 60#define WPI_EEPROM_GP 0x030 61#define WPI_GIO 0x03c 62#define WPI_UCODE_GP1 0x054 63#define WPI_UCODE_GP1_SET 0x058 64#define WPI_UCODE_GP1_CLR 0x05c 65#define WPI_UCODE_GP2 0x060 66#define WPI_GIO_CHICKEN 0x100 67#define WPI_ANA_PLL 0x20c 68#define WPI_DBG_HPET_MEM 0x240 69#define WPI_MEM_RADDR 0x40c 70#define WPI_MEM_WADDR 0x410 71#define WPI_MEM_WDATA 0x418 72#define WPI_MEM_RDATA 0x41c 73#define WPI_PRPH_WADDR 0x444 74#define WPI_PRPH_RADDR 0x448 75#define WPI_PRPH_WDATA 0x44c 76#define WPI_PRPH_RDATA 0x450 77#define WPI_HBUS_TARG_WRPTR 0x460 78 79/* 80 * Flow-Handler registers. 81 */ 82#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84#define WPI_FH_RX_CONFIG 0xc00 85#define WPI_FH_RX_BASE 0xc04 86#define WPI_FH_RX_WPTR 0xc20 87#define WPI_FH_RX_RPTR_ADDR 0xc24 88#define WPI_FH_RSSR_TBL 0xcc0 89#define WPI_FH_RX_STATUS 0xcc4 90#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91#define WPI_FH_TX_BASE 0xe80 92#define WPI_FH_MSG_CONFIG 0xe88 93#define WPI_FH_TX_STATUS 0xe90 94 95 96/* 97 * NIC internal memory offsets. 98 */ 99#define WPI_ALM_SCHED_MODE 0x2e00 100#define WPI_ALM_SCHED_ARASTAT 0x2e04 101#define WPI_ALM_SCHED_TXFACT 0x2e10 102#define WPI_ALM_SCHED_TXF4MF 0x2e14 103#define WPI_ALM_SCHED_TXF5MF 0x2e20 104#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106#define WPI_APMG_CLK_CTRL 0x3000 107#define WPI_APMG_CLK_EN 0x3004 108#define WPI_APMG_CLK_DIS 0x3008 109#define WPI_APMG_PS 0x300c 110#define WPI_APMG_PCI_STT 0x3010 111#define WPI_APMG_RFKILL 0x3014 112#define WPI_BSM_WR_CTRL 0x3400 113#define WPI_BSM_WR_MEM_SRC 0x3404 114#define WPI_BSM_WR_MEM_DST 0x3408 115#define WPI_BSM_WR_DWCOUNT 0x340c 116#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120#define WPI_BSM_SRAM_BASE 0x3800 121 122 123/* Possible flags for register WPI_HW_IF_CONFIG. */ 124#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129 130/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132 133/* Possible values for WPI_BSM_WR_MEM_DST. */ 134#define WPI_FW_TEXT_BASE 0x00000000 135#define WPI_FW_DATA_BASE 0x00800000 136 137/* Possible flags for WPI_GPIO_IN. */ 138#define WPI_GPIO_IN_VMAIN (1 << 9) 139 140/* Possible flags for register WPI_RESET. */ 141#define WPI_RESET_NEVO (1 << 0) 142#define WPI_RESET_SW (1 << 7) 143#define WPI_RESET_MASTER_DISABLED (1 << 8) 144#define WPI_RESET_STOP_MASTER (1 << 9) 145 146/* Possible flags for register WPI_GP_CNTRL. */ 147#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151#define WPI_GP_CNTRL_SLEEP (1 << 4) 152#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154#define WPI_GP_CNTRL_RFKILL (1 << 27) 155 156/* Possible flags for register WPI_GIO_CHICKEN. */ 157#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159 160/* Possible flags for register WPI_GIO. */ 161#define WPI_GIO_L0S_ENA (1 << 1) 162 163/* Possible flags for register WPI_FH_RX_CONFIG. */ 164#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171 172/* Possible flags for register WPI_ANA_PLL. */ 173#define WPI_ANA_PLL_INIT (1 << 24) 174 175/* Possible flags for register WPI_UCODE_GP1*. */ 176#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177#define WPI_UCODE_GP1_RFKILL (1 << 1) 178#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179 180/* Possible flags for register WPI_FH_RX_STATUS. */ 181#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182 183/* Possible flags for register WPI_BSM_WR_CTRL. */ 184#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185#define WPI_BSM_WR_CTRL_START (1U << 31) 186 187/* Possible flags for register WPI_INT. */ 188#define WPI_INT_ALIVE (1 << 0) 189#define WPI_INT_WAKEUP (1 << 1) 190#define WPI_INT_SW_RX (1 << 3) 191#define WPI_INT_SW_ERR (1 << 25) 192#define WPI_INT_FH_TX (1 << 27) 193#define WPI_INT_HW_ERR (1 << 29) 194#define WPI_INT_FH_RX (1U << 31) 195 196/* Shortcut. */ 197#define WPI_INT_MASK_DEF \ 198 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200 WPI_INT_SW_RX) 201 202/* Possible flags for register WPI_FH_INT. */ 203#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204#define WPI_FH_INT_HI_PRIOR (1 << 30) 205/* Shortcuts for the above. */ 206#define WPI_FH_INT_RX \ 207 (WPI_FH_INT_RX_CHNL(0) | \ 208 WPI_FH_INT_RX_CHNL(1) | \ 209 WPI_FH_INT_RX_CHNL(2) | \ 210 WPI_FH_INT_HI_PRIOR) 211 212/* Possible flags for register WPI_FH_TX_STATUS. */ 213#define WPI_FH_TX_STATUS_IDLE(qid) \ 214 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215 216/* Possible flags for register WPI_EEPROM. */ 217#define WPI_EEPROM_READ_VALID (1 << 0) 218 219/* Possible flags for register WPI_EEPROM_GP. */ 220#define WPI_EEPROM_VERSION 0x00000007 221#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222 223/* Possible flags for register WPI_APMG_PS. */ 224#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225 226/* Possible flags for registers WPI_APMG_CLK_*. */ 227#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229 230/* Possible flags for register WPI_APMG_PCI_STT. */ 231#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232 233struct wpi_shared { 234 uint32_t txbase[WPI_NTXQUEUES]; 235 uint32_t next; 236 uint32_t reserved[2]; 237} __packed; 238 239#define WPI_MAX_SEG_LEN 65520 240struct wpi_tx_desc { 241 uint8_t reserved1[3]; 242 uint8_t nsegs; 243#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244 245 struct { 246 uint32_t addr; 247 uint32_t len; 248 } __packed segs[WPI_MAX_SCATTER]; 249 uint8_t reserved2[28]; 250} __packed; 251 252struct wpi_tx_stat { 253 uint8_t rtsfailcnt; 254 uint8_t ackfailcnt; 255 uint8_t btkillcnt; 256 uint8_t rate; 257 uint32_t duration; 258 uint32_t status; 259} __packed; 260 261struct wpi_rx_desc { 262 uint32_t len; 263 uint8_t type; 264#define WPI_UC_READY 1 265#define WPI_RX_DONE 27 266#define WPI_TX_DONE 28 267#define WPI_START_SCAN 130 268#define WPI_SCAN_RESULTS 131 269#define WPI_STOP_SCAN 132 270#define WPI_BEACON_SENT 144 271#define WPI_RX_STATISTICS 156 272#define WPI_BEACON_STATISTICS 157 273#define WPI_STATE_CHANGED 161 274#define WPI_BEACON_MISSED 162 275 276 uint8_t flags; 277 uint8_t idx; 278 uint8_t qid; 279} __packed; 280 281#define WPI_RX_DESC_QID_MSK 0x07 282#define WPI_UNSOLICITED_RX_NOTIF 0x80 283 284struct wpi_rx_stat { 285 uint8_t len; 286#define WPI_STAT_MAXLEN 20 287 288 uint8_t id; 289 uint8_t rssi; /* received signal strength */ 290#define WPI_RSSI_OFFSET -95 291 292 uint8_t agc; /* access gain control */ 293 uint16_t signal; 294 uint16_t noise; 295} __packed; 296 297struct wpi_rx_head { 298 uint16_t chan; 299 uint16_t flags; 300#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 301 302 uint8_t reserved; 303 uint8_t plcp; 304 uint16_t len; 305} __packed; 306 307struct wpi_rx_tail { 308 uint32_t flags; 309#define WPI_RX_NO_CRC_ERR (1 << 0) 310#define WPI_RX_NO_OVFL_ERR (1 << 1) 311/* shortcut for the above */ 312#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 313#define WPI_RX_CIPHER_MASK (7 << 8) 314#define WPI_RX_CIPHER_CCMP (2 << 8) 315#define WPI_RX_DECRYPT_MASK (3 << 11) 316#define WPI_RX_DECRYPT_OK (3 << 11) 317 318 uint64_t tstamp; 319 uint32_t tbeacon; 320} __packed; 321 322struct wpi_tx_cmd { 323 uint8_t code; 324#define WPI_CMD_RXON 16 325#define WPI_CMD_RXON_ASSOC 17 326#define WPI_CMD_EDCA_PARAMS 19 327#define WPI_CMD_TIMING 20 328#define WPI_CMD_ADD_NODE 24 329#define WPI_CMD_DEL_NODE 25 330#define WPI_CMD_TX_DATA 28 331#define WPI_CMD_MRR_SETUP 71 332#define WPI_CMD_SET_LED 72 333#define WPI_CMD_SET_POWER_MODE 119 334#define WPI_CMD_SCAN 128 335#define WPI_CMD_SET_BEACON 145 336#define WPI_CMD_TXPOWER 151 337#define WPI_CMD_BT_COEX 155 338#define WPI_CMD_GET_STATISTICS 156 339 340 uint8_t flags; 341 uint8_t idx; 342 uint8_t qid; 343 uint8_t data[124]; 344} __packed; 345 346/* Structure for command WPI_CMD_RXON. */ 347struct wpi_rxon { 348 uint8_t myaddr[IEEE80211_ADDR_LEN]; 349 uint16_t reserved1; 350 uint8_t bssid[IEEE80211_ADDR_LEN]; 351 uint16_t reserved2; 352 uint8_t wlap[IEEE80211_ADDR_LEN]; 353 uint16_t reserved3; 354 uint8_t mode; 355#define WPI_MODE_HOSTAP 1 356#define WPI_MODE_STA 3 357#define WPI_MODE_IBSS 4 358#define WPI_MODE_MONITOR 6 359 360 uint8_t air; 361 uint16_t reserved4; 362 uint8_t ofdm_mask; 363 uint8_t cck_mask; 364 uint16_t associd; 365 uint32_t flags; 366#define WPI_RXON_24GHZ (1 << 0) 367#define WPI_RXON_CCK (1 << 1) 368#define WPI_RXON_AUTO (1 << 2) 369#define WPI_RXON_SHSLOT (1 << 4) 370#define WPI_RXON_SHPREAMBLE (1 << 5) 371#define WPI_RXON_NODIVERSITY (1 << 7) 372#define WPI_RXON_ANTENNA_A (1 << 8) 373#define WPI_RXON_ANTENNA_B (1 << 9) 374#define WPI_RXON_TSF (1 << 15) 375#define WPI_RXON_CTS_TO_SELF (1 << 30) 376 377 uint32_t filter; 378#define WPI_FILTER_PROMISC (1 << 0) 379#define WPI_FILTER_CTL (1 << 1) 380#define WPI_FILTER_MULTICAST (1 << 2) 381#define WPI_FILTER_NODECRYPT (1 << 3) 382#define WPI_FILTER_BSS (1 << 5) 383#define WPI_FILTER_BEACON (1 << 6) 384#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 385 386 uint8_t chan; 387 uint16_t reserved5; 388} __packed; 389 390/* Structure for command WPI_CMD_RXON_ASSOC. */ 391struct wpi_assoc { 392 uint32_t flags; 393 uint32_t filter; 394 uint8_t ofdm_mask; 395 uint8_t cck_mask; 396 uint16_t reserved; 397} __packed; 398 399/* Structure for command WPI_CMD_EDCA_PARAMS. */ 400struct wpi_edca_params { 401 uint32_t flags; 402#define WPI_EDCA_UPDATE (1 << 0) 403 404 struct { 405 uint16_t cwmin; 406 uint16_t cwmax; 407 uint8_t aifsn; 408 uint8_t reserved; 409 uint16_t txoplimit; 410 } __packed ac[WME_NUM_AC]; 411} __packed; 412 413/* Structure for command WPI_CMD_TIMING. */ 414struct wpi_cmd_timing { 415 uint64_t tstamp; 416 uint16_t bintval; 417 uint16_t atim; 418 uint32_t binitval; 419 uint16_t lintval; 420 uint16_t reserved; 421} __packed; 422 423/* Structure for command WPI_CMD_ADD_NODE. */ 424struct wpi_node_info { 425 uint8_t control; 426#define WPI_NODE_UPDATE (1 << 0) 427 428 uint8_t reserved1[3]; 429 uint8_t macaddr[IEEE80211_ADDR_LEN]; 430 uint16_t reserved2; 431 uint8_t id; 432#define WPI_ID_BSS 0 433#define WPI_ID_IBSS_MIN 2 434#define WPI_ID_IBSS_MAX 23 435#define WPI_ID_BROADCAST 24 436#define WPI_ID_UNDEFINED (uint8_t)-1 437 438 uint8_t flags; 439#define WPI_FLAG_KEY_SET (1 << 0) 440 441 uint16_t reserved3; 442 uint16_t kflags; 443#define WPI_KFLAG_CCMP (1 << 1) 444#define WPI_KFLAG_KID(kid) ((kid) << 8) 445#define WPI_KFLAG_MULTICAST (1 << 14) 446 447 uint8_t tsc2; 448 uint8_t reserved4; 449 uint16_t ttak[5]; 450 uint16_t reserved5; 451 uint8_t key[IEEE80211_KEYBUF_SIZE]; 452 uint32_t action; 453#define WPI_ACTION_SET_RATE (1 << 2) 454 455 uint32_t mask; 456 uint16_t tid; 457 uint8_t plcp; 458 uint8_t antenna; 459#define WPI_ANTENNA_A (1 << 6) 460#define WPI_ANTENNA_B (1 << 7) 461#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 462 463 uint8_t add_imm; 464 uint8_t del_imm; 465 uint16_t add_imm_start; 466} __packed; 467 468/* Structure for command WPI_CMD_DEL_NODE. */ 469struct wpi_cmd_del_node { 470 uint8_t count; 471 uint8_t reserved1[3]; 472 uint8_t macaddr[IEEE80211_ADDR_LEN]; 473 uint16_t reserved2; 474} __packed; 475 476/* Structure for command WPI_CMD_TX_DATA. */ 477struct wpi_cmd_data { 478 uint16_t len; 479 uint16_t lnext; 480 uint32_t flags; 481#define WPI_TX_NEED_RTS (1 << 1) 482#define WPI_TX_NEED_CTS (1 << 2) 483#define WPI_TX_NEED_ACK (1 << 3) 484#define WPI_TX_FULL_TXOP (1 << 7) 485#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 486#define WPI_TX_AUTO_SEQ (1 << 13) 487#define WPI_TX_MORE_FRAG (1 << 14) 488#define WPI_TX_INSERT_TSTAMP (1 << 16) 489 490 uint8_t plcp; 491 uint8_t id; 492 uint8_t tid; 493 uint8_t security; 494#define WPI_CIPHER_WEP 1 495#define WPI_CIPHER_CCMP 2 496#define WPI_CIPHER_TKIP 3 497#define WPI_CIPHER_WEP104 9 498 499 uint8_t key[IEEE80211_KEYBUF_SIZE]; 500 uint8_t tkip[IEEE80211_WEP_MICLEN]; 501 uint32_t fnext; 502 uint32_t lifetime; 503#define WPI_LIFETIME_INFINITE 0xffffffff 504 505 uint8_t ofdm_mask; 506 uint8_t cck_mask; 507 uint8_t rts_ntries; 508 uint8_t data_ntries; 509 uint16_t timeout; 510 uint16_t txop; 511} __packed; 512 513/* Structure for command WPI_CMD_SET_BEACON. */ 514struct wpi_cmd_beacon { 515 uint16_t len; 516 uint16_t reserved1; 517 uint32_t flags; /* same as wpi_cmd_data */ 518 uint8_t plcp; 519 uint8_t id; 520 uint8_t reserved2[30]; 521 uint32_t lifetime; 522 uint8_t ofdm_mask; 523 uint8_t cck_mask; 524 uint16_t reserved3[3]; 525 uint16_t tim; 526 uint8_t timsz; 527 uint8_t reserved4; 528} __packed; 529 530/* Structure for notification WPI_BEACON_MISSED. */ 531struct wpi_beacon_missed { 532 uint32_t consecutive; 533 uint32_t total; 534 uint32_t expected; 535 uint32_t received; 536} __packed; 537 538 539/* Structure for command WPI_CMD_MRR_SETUP. */ 540#define WPI_RIDX_MAX 11 541struct wpi_mrr_setup { 542 uint32_t which; 543#define WPI_MRR_CTL 0 544#define WPI_MRR_DATA 1 545 546 struct { 547 uint8_t plcp; 548 uint8_t flags; 549 uint8_t ntries; 550 uint8_t next; 551 } __packed rates[WPI_RIDX_MAX + 1]; 552} __packed; 553 554/* Structure for command WPI_CMD_SET_LED. */ 555struct wpi_cmd_led { 556 uint32_t unit; /* multiplier (in usecs) */ 557 uint8_t which; 558#define WPI_LED_ACTIVITY 1 559#define WPI_LED_LINK 2 560 561 uint8_t off; 562 uint8_t on; 563 uint8_t reserved; 564} __packed; 565 566/* Structure for command WPI_CMD_SET_POWER_MODE. */ 567struct wpi_pmgt_cmd { 568 uint16_t flags; 569#define WPI_PS_ALLOW_SLEEP (1 << 0) 570#define WPI_PS_NOTIFY (1 << 1) 571#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 572#define WPI_PS_PCI_PMGT (1 << 3) 573 574 uint8_t reserved[2]; 575 uint32_t rxtimeout; 576 uint32_t txtimeout; 577 uint32_t intval[5]; 578} __packed; 579 580/* Structures for command WPI_CMD_SCAN. */ 581#define WPI_SCAN_MAX_ESSIDS 4 582struct wpi_scan_essid { 583 uint8_t id; 584 uint8_t len; 585 uint8_t data[IEEE80211_NWID_LEN]; 586} __packed; 587 588struct wpi_scan_hdr { 589 uint16_t len; 590 uint8_t reserved1; 591 uint8_t nchan; 592 uint16_t quiet_time; 593 uint16_t quiet_threshold; 594 uint16_t crc_threshold; 595 uint16_t reserved2; 596 uint32_t max_svc; /* background scans */ 597 uint32_t pause_svc; /* background scans */ 598 uint32_t flags; 599 uint32_t filter; 600 601 /* Followed by a struct wpi_cmd_data. */ 602 /* Followed by an array of 4 structs wpi_scan_essid. */ 603 /* Followed by probe request body. */ 604 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 605} __packed; 606 607struct wpi_scan_chan { 608 uint8_t flags; 609#define WPI_CHAN_ACTIVE (1 << 0) 610#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 611 612 uint8_t chan; 613 uint8_t rf_gain; 614 uint8_t dsp_gain; 615 uint16_t active; /* msecs */ 616 uint16_t passive; /* msecs */ 617} __packed; 618 619#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 620#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 621 622/* Maximum size of a scan command. */ 623#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 624 625#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 626#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 627#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 628#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 629 630#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 631#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 632#define WPI_PASSIVE_DWELL_BASE (100) 633 634/* Structure for command WPI_CMD_TXPOWER. */ 635struct wpi_cmd_txpower { 636 uint8_t band; 637#define WPI_BAND_5GHZ 0 638#define WPI_BAND_2GHZ 1 639 640 uint8_t reserved; 641 uint16_t chan; 642 643 struct { 644 uint8_t plcp; 645 uint8_t rf_gain; 646 uint8_t dsp_gain; 647 uint8_t reserved; 648 } __packed rates[WPI_RIDX_MAX + 1]; 649 650} __packed; 651 652/* Structure for command WPI_CMD_BT_COEX. */ 653struct wpi_bluetooth { 654 uint8_t flags; 655#define WPI_BT_COEX_DISABLE 0 656#define WPI_BT_COEX_MODE_2WIRE 1 657#define WPI_BT_COEX_MODE_3WIRE 2 658#define WPI_BT_COEX_MODE_4WIRE 3 659 660 uint8_t lead_time; 661#define WPI_BT_LEAD_TIME_DEF 30 662 663 uint8_t max_kill; 664#define WPI_BT_MAX_KILL_DEF 5 665 666 uint8_t reserved; 667 uint32_t kill_ack; 668 uint32_t kill_cts; 669} __packed; 670 671/* Structure for WPI_UC_READY notification. */ 672struct wpi_ucode_info { 673 uint8_t minor; 674 uint8_t major; 675 uint16_t reserved1; 676 uint8_t revision[8]; 677 uint8_t type; 678 uint8_t subtype; 679 uint16_t reserved2; 680 uint32_t logptr; 681 uint32_t errptr; 682 uint32_t tstamp; 683 uint32_t valid; 684} __packed; 685 686/* Structure for WPI_START_SCAN notification. */ 687struct wpi_start_scan { 688 uint64_t tstamp; 689 uint32_t tbeacon; 690 uint8_t chan; 691 uint8_t band; 692 uint16_t reserved; 693 uint32_t status; 694} __packed; 695 696/* Structure for WPI_STOP_SCAN notification. */ 697struct wpi_stop_scan { 698 uint8_t nchan; 699 uint8_t status; 700 uint8_t reserved; 701 uint8_t chan; 702 uint64_t tsf; 703} __packed; 704 705/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 706struct wpi_rx_phy_stats { 707 uint32_t ina; 708 uint32_t fina; 709 uint32_t bad_plcp; 710 uint32_t bad_crc32; 711 uint32_t overrun; 712 uint32_t eoverrun; 713 uint32_t good_crc32; 714 uint32_t fa; 715 uint32_t bad_fina_sync; 716 uint32_t sfd_timeout; 717 uint32_t fina_timeout; 718 uint32_t no_rts_ack; 719 uint32_t rxe_limit; 720 uint32_t ack; 721 uint32_t cts; 722} __packed; 723 724struct wpi_rx_general_stats { 725 uint32_t bad_cts; 726 uint32_t bad_ack; 727 uint32_t not_bss; 728 uint32_t filtered; 729 uint32_t bad_chan; 730} __packed; 731 732struct wpi_rx_stats { 733 struct wpi_rx_phy_stats ofdm; 734 struct wpi_rx_phy_stats cck; 735 struct wpi_rx_general_stats general; 736} __packed; 737 738struct wpi_tx_stats { 739 uint32_t preamble; 740 uint32_t rx_detected; 741 uint32_t bt_defer; 742 uint32_t bt_kill; 743 uint32_t short_len; 744 uint32_t cts_timeout; 745 uint32_t ack_timeout; 746 uint32_t exp_ack; 747 uint32_t ack; 748} __packed; 749 750struct wpi_general_stats { 751 uint32_t temp; 752 uint32_t burst_check; 753 uint32_t burst; 754 uint32_t reserved[4]; 755 uint32_t sleep; 756 uint32_t slot_out; 757 uint32_t slot_idle; 758 uint32_t ttl_tstamp; 759 uint32_t tx_ant_a; 760 uint32_t tx_ant_b; 761 uint32_t exec; 762 uint32_t probe; 763} __packed; 764 765struct wpi_stats { 766 uint32_t flags; 767 struct wpi_rx_stats rx; 768 struct wpi_tx_stats tx; 769 struct wpi_general_stats general; 770} __packed; 771 772/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 773#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 774 775 776/* Firmware error dump entry. */ 777struct wpi_fw_dump { 778 uint32_t desc; 779 uint32_t time; 780 uint32_t blink[2]; 781 uint32_t ilink[2]; 782 uint32_t data; 783} __packed; 784 785/* Firmware image file header. */ 786struct wpi_firmware_hdr { 787 788#define WPI_FW_MINVERSION 2144 789#define WPI_FW_NAME "wpifw" 790 791 uint16_t driver; 792 uint8_t minor; 793 uint8_t major; 794 uint32_t rtextsz; 795 uint32_t rdatasz; 796 uint32_t itextsz; 797 uint32_t idatasz; 798 uint32_t btextsz; 799} __packed; 800 801#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 802#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 803#define WPI_FW_BOOT_TEXT_MAXSZ 1024 804 805#define WPI_FW_UPDATED (1U << 31 ) 806 807/* 808 * Offsets into EEPROM. 809 */ 810#define WPI_EEPROM_MAC 0x015 811#define WPI_EEPROM_REVISION 0x035 812#define WPI_EEPROM_SKU_CAP 0x045 813#define WPI_EEPROM_TYPE 0x04a 814#define WPI_EEPROM_DOMAIN 0x060 815#define WPI_EEPROM_BAND1 0x063 816#define WPI_EEPROM_BAND2 0x072 817#define WPI_EEPROM_BAND3 0x080 818#define WPI_EEPROM_BAND4 0x08d 819#define WPI_EEPROM_BAND5 0x099 820#define WPI_EEPROM_POWER_GRP 0x100 821 822struct wpi_eeprom_chan { 823 uint8_t flags; 824#define WPI_EEPROM_CHAN_VALID (1 << 0) 825#define WPI_EEPROM_CHAN_IBSS (1 << 1) 826#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 827#define WPI_EEPROM_CHAN_RADAR (1 << 4) 828 829 int8_t maxpwr; 830} __packed; 831 832struct wpi_eeprom_sample { 833 uint8_t index; 834 int8_t power; 835 uint16_t volt; 836} __packed; 837 838#define WPI_POWER_GROUPS_COUNT 5 839struct wpi_eeprom_group { 840 struct wpi_eeprom_sample samples[5]; 841 int32_t coef[5]; 842 int32_t corr[5]; 843 int8_t maxpwr; 844 uint8_t chan; 845 int16_t temp; 846} __packed; 847 848#define WPI_CHAN_BANDS_COUNT 5 849#define WPI_MAX_CHAN_PER_BAND 14 850static const struct wpi_chan_band { 851 uint32_t addr; /* offset in EEPROM */ 852 uint8_t nchan; 853 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 854} wpi_bands[] = { 855 /* 20MHz channels, 2GHz band. */ 856 { WPI_EEPROM_BAND1, 14, 857 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 858 /* 20MHz channels, 5GHz band. */ 859 { WPI_EEPROM_BAND2, 13, 860 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 861 { WPI_EEPROM_BAND3, 12, 862 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 863 { WPI_EEPROM_BAND4, 11, 864 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 865 { WPI_EEPROM_BAND5, 6, 866 { 145, 149, 153, 157, 161, 165 } } 867}; 868 869/* HW rate indices. */ 870#define WPI_RIDX_OFDM6 0 871#define WPI_RIDX_OFDM36 5 872#define WPI_RIDX_OFDM48 6 873#define WPI_RIDX_OFDM54 7 874#define WPI_RIDX_CCK1 8 875#define WPI_RIDX_CCK2 9 876#define WPI_RIDX_CCK11 11 877 878static const uint8_t wpi_ridx_to_plcp[] = { 879 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 880 /* R1-R4 (ral/ural is R4-R1) */ 881 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 882 /* CCK: device-dependent */ 883 10, 20, 55, 110 884}; 885 886#define WPI_MAX_PWR_INDEX 77 887 888/* 889 * RF Tx gain values from highest to lowest power (values obtained from 890 * the reference driver.) 891 */ 892static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 893 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 894 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 895 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 896 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 897 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 898 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 899 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 900 0x03 901}; 902 903static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 904 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 905 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 906 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 907 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 908 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 909 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 910 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 911 0x03 912}; 913 914/* 915 * DSP pre-DAC gain values from highest to lowest power (values obtained 916 * from the reference driver.) 917 */ 918static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 919 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 920 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 921 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 922 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 923 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 924 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 925 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 926 0x5f 927}; 928 929static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 930 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 931 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 932 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 933 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 934 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 935 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 936 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 937 0x78 938}; 939 940/* 941 * Power saving settings (values obtained from the reference driver.) 942 */ 943#define WPI_NDTIMRANGES 2 944#define WPI_NPOWERLEVELS 6 945static const struct wpi_pmgt { 946 uint32_t rxtimeout; 947 uint32_t txtimeout; 948 uint32_t intval[5]; 949 int skip_dtim; 950} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 951 /* DTIM <= 10 */ 952 { 953 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 954 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 955 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 956 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 957 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 958 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 959 }, 960 /* DTIM >= 11 */ 961 { 962 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 963 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 964 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 965 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 966 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 967 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 968 } 969}; 970 971/* Firmware errors. */ 972static const char * const wpi_fw_errmsg[] = { 973 "OK", 974 "FAIL", 975 "BAD_PARAM", 976 "BAD_CHECKSUM", 977 "NMI_INTERRUPT", 978 "SYSASSERT", 979 "FATAL_ERROR" 980}; 981 982#define WPI_READ(sc, reg) \ 983 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 984 985#define WPI_WRITE(sc, reg, val) \ 986 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 987 988#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 989 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 990 (datap), (count)) 991 992#define WPI_SETBITS(sc, reg, mask) \ 993 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 994 995#define WPI_CLRBITS(sc, reg, mask) \ 996 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 997 998#define WPI_BARRIER_WRITE(sc) \ 999 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1000 BUS_SPACE_BARRIER_WRITE) 1001 1002#define WPI_BARRIER_READ_WRITE(sc) \ 1003 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1004 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1005