if_wpireg.h revision 280058
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 280058 2015-03-15 20:19:01Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23#define WPI_RX_RING_COUNT_LOG 6 24#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 25 26#define WPI_NTXQUEUES 8 27#define WPI_DRV_NTXQUEUES 5 28#define WPI_NDMACHNLS 6 29 30/* Maximum scatter/gather. */ 31#define WPI_MAX_SCATTER 4 32 33/* 34 * Rings must be aligned on a 16K boundary. 35 */ 36#define WPI_RING_DMA_ALIGN 0x4000 37 38/* Maximum Rx buffer size. */ 39#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 40 41/* 42 * Control and status registers. 43 */ 44#define WPI_HW_IF_CONFIG 0x000 45#define WPI_INT 0x008 46#define WPI_INT_MASK 0x00c 47#define WPI_FH_INT 0x010 48#define WPI_GPIO_IN 0x018 49#define WPI_RESET 0x020 50#define WPI_GP_CNTRL 0x024 51#define WPI_EEPROM 0x02c 52#define WPI_EEPROM_GP 0x030 53#define WPI_GIO 0x03c 54#define WPI_UCODE_GP1 0x054 55#define WPI_UCODE_GP1_SET 0x058 56#define WPI_UCODE_GP1_CLR 0x05c 57#define WPI_UCODE_GP2 0x060 58#define WPI_GIO_CHICKEN 0x100 59#define WPI_ANA_PLL 0x20c 60#define WPI_DBG_HPET_MEM 0x240 61#define WPI_MEM_RADDR 0x40c 62#define WPI_MEM_WADDR 0x410 63#define WPI_MEM_WDATA 0x418 64#define WPI_MEM_RDATA 0x41c 65#define WPI_PRPH_WADDR 0x444 66#define WPI_PRPH_RADDR 0x448 67#define WPI_PRPH_WDATA 0x44c 68#define WPI_PRPH_RDATA 0x450 69#define WPI_HBUS_TARG_WRPTR 0x460 70 71/* 72 * Flow-Handler registers. 73 */ 74#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 75#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 76#define WPI_FH_RX_CONFIG 0xc00 77#define WPI_FH_RX_BASE 0xc04 78#define WPI_FH_RX_WPTR 0xc20 79#define WPI_FH_RX_RPTR_ADDR 0xc24 80#define WPI_FH_RSSR_TBL 0xcc0 81#define WPI_FH_RX_STATUS 0xcc4 82#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 83#define WPI_FH_TX_BASE 0xe80 84#define WPI_FH_MSG_CONFIG 0xe88 85#define WPI_FH_TX_STATUS 0xe90 86 87 88/* 89 * NIC internal memory offsets. 90 */ 91#define WPI_ALM_SCHED_MODE 0x2e00 92#define WPI_ALM_SCHED_ARASTAT 0x2e04 93#define WPI_ALM_SCHED_TXFACT 0x2e10 94#define WPI_ALM_SCHED_TXF4MF 0x2e14 95#define WPI_ALM_SCHED_TXF5MF 0x2e20 96#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 97#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 98#define WPI_APMG_CLK_EN 0x3004 99#define WPI_APMG_CLK_DIS 0x3008 100#define WPI_APMG_PS 0x300c 101#define WPI_APMG_PCI_STT 0x3010 102#define WPI_APMG_RFKILL 0x3014 103#define WPI_BSM_WR_CTRL 0x3400 104#define WPI_BSM_WR_MEM_SRC 0x3404 105#define WPI_BSM_WR_MEM_DST 0x3408 106#define WPI_BSM_WR_DWCOUNT 0x340c 107#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 108#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 109#define WPI_BSM_DRAM_DATA_ADDR 0x3498 110#define WPI_BSM_DRAM_DATA_SIZE 0x349c 111#define WPI_BSM_SRAM_BASE 0x3800 112 113 114/* Possible flags for register WPI_HW_IF_CONFIG. */ 115#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 116#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 117#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 118#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 119#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 120 121/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 122#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 123 124/* Possible values for WPI_BSM_WR_MEM_DST. */ 125#define WPI_FW_TEXT_BASE 0x00000000 126#define WPI_FW_DATA_BASE 0x00800000 127 128/* Possible flags for WPI_GPIO_IN. */ 129#define WPI_GPIO_IN_VMAIN (1 << 9) 130 131/* Possible flags for register WPI_RESET. */ 132#define WPI_RESET_NEVO (1 << 0) 133#define WPI_RESET_SW (1 << 7) 134#define WPI_RESET_MASTER_DISABLED (1 << 8) 135#define WPI_RESET_STOP_MASTER (1 << 9) 136 137/* Possible flags for register WPI_GP_CNTRL. */ 138#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 139#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 140#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 141#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 142#define WPI_GP_CNTRL_SLEEP (1 << 4) 143#define WPI_GP_CNTRL_PS_MASK (7 << 24) 144#define WPI_GP_CNTRL_MAC_PS (4 << 24) 145#define WPI_GP_CNTRL_RFKILL (1 << 27) 146 147/* Possible flags for register WPI_GIO_CHICKEN. */ 148#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 149#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 150 151/* Possible flags for register WPI_GIO. */ 152#define WPI_GIO_L0S_ENA (1 << 1) 153 154/* Possible flags for register WPI_FH_RX_CONFIG. */ 155#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 156#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 157#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 158#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 159#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 160#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 161#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 162 163/* Possible flags for register WPI_ANA_PLL. */ 164#define WPI_ANA_PLL_INIT (1 << 24) 165 166/* Possible flags for register WPI_UCODE_GP1*. */ 167#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 168#define WPI_UCODE_GP1_RFKILL (1 << 1) 169#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 170 171/* Possible flags for register WPI_FH_RX_STATUS. */ 172#define WPI_FH_RX_STATUS_IDLE (1 << 24) 173 174/* Possible flags for register WPI_BSM_WR_CTRL. */ 175#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 176#define WPI_BSM_WR_CTRL_START (1U << 31) 177 178/* Possible flags for register WPI_INT. */ 179#define WPI_INT_ALIVE (1 << 0) 180#define WPI_INT_WAKEUP (1 << 1) 181#define WPI_INT_SW_RX (1 << 3) 182#define WPI_INT_SW_ERR (1 << 25) 183#define WPI_INT_FH_TX (1 << 27) 184#define WPI_INT_HW_ERR (1 << 29) 185#define WPI_INT_FH_RX (1U << 31) 186 187/* Shortcut. */ 188#define WPI_INT_MASK_DEF \ 189 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 190 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 191 WPI_INT_SW_RX) 192 193/* Possible flags for register WPI_FH_INT. */ 194#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 195#define WPI_FH_INT_HI_PRIOR (1 << 30) 196/* Shortcuts for the above. */ 197#define WPI_FH_INT_RX \ 198 (WPI_FH_INT_RX_CHNL(0) | \ 199 WPI_FH_INT_RX_CHNL(1) | \ 200 WPI_FH_INT_RX_CHNL(2) | \ 201 WPI_FH_INT_HI_PRIOR) 202 203/* Possible flags for register WPI_FH_TX_STATUS. */ 204#define WPI_FH_TX_STATUS_IDLE(qid) \ 205 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 206 207/* Possible flags for register WPI_EEPROM. */ 208#define WPI_EEPROM_READ_VALID (1 << 0) 209 210/* Possible flags for register WPI_EEPROM_GP. */ 211#define WPI_EEPROM_VERSION 0x00000007 212#define WPI_EEPROM_GP_IF_OWNER 0x00000180 213 214/* Possible flags for register WPI_APMG_PS. */ 215#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 216 217/* Possible flags for registers WPI_APMG_CLK_*. */ 218#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 219#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 220 221/* Possible flags for register WPI_APMG_PCI_STT. */ 222#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 223 224struct wpi_shared { 225 uint32_t txbase[8]; 226 uint32_t next; 227 uint32_t reserved[2]; 228} __packed; 229 230#define WPI_MAX_SEG_LEN 65520 231struct wpi_tx_desc { 232 uint8_t reserved1[3]; 233 uint8_t nsegs; 234#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 235 236 struct { 237 uint32_t addr; 238 uint32_t len; 239 } __packed segs[WPI_MAX_SCATTER]; 240 uint8_t reserved2[28]; 241} __packed; 242 243struct wpi_tx_stat { 244 uint8_t rtsfailcnt; 245 uint8_t ackfailcnt; 246 uint8_t btkillcnt; 247 uint8_t rate; 248 uint32_t duration; 249 uint32_t status; 250} __packed; 251 252struct wpi_rx_desc { 253 uint32_t len; 254 uint8_t type; 255#define WPI_UC_READY 1 256#define WPI_RX_DONE 27 257#define WPI_TX_DONE 28 258#define WPI_START_SCAN 130 259#define WPI_SCAN_RESULTS 131 260#define WPI_STOP_SCAN 132 261#define WPI_BEACON_SENT 144 262#define WPI_RX_STATISTICS 156 263#define WPI_BEACON_STATISTICS 157 264#define WPI_STATE_CHANGED 161 265#define WPI_BEACON_MISSED 162 266 267 uint8_t flags; 268 uint8_t idx; 269 uint8_t qid; 270} __packed; 271 272struct wpi_rx_stat { 273 uint8_t len; 274#define WPI_STAT_MAXLEN 20 275 276 uint8_t id; 277 uint8_t rssi; /* received signal strength */ 278#define WPI_RSSI_OFFSET 95 279 280 uint8_t agc; /* access gain control */ 281 uint16_t signal; 282 uint16_t noise; 283} __packed; 284 285struct wpi_rx_head { 286 uint16_t chan; 287 uint16_t flags; 288#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 289 290 uint8_t reserved; 291 uint8_t plcp; 292 uint16_t len; 293} __packed; 294 295struct wpi_rx_tail { 296 uint32_t flags; 297#define WPI_RX_NO_CRC_ERR (1 << 0) 298#define WPI_RX_NO_OVFL_ERR (1 << 1) 299/* shortcut for the above */ 300#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 301#define WPI_RX_CIPHER_MASK (7 << 8) 302#define WPI_RX_CIPHER_CCMP (2 << 8) 303#define WPI_RX_DECRYPT_MASK (3 << 11) 304#define WPI_RX_DECRYPT_OK (3 << 11) 305 306 uint64_t tstamp; 307 uint32_t tbeacon; 308} __packed; 309 310struct wpi_tx_cmd { 311 uint8_t code; 312#define WPI_CMD_RXON 16 313#define WPI_CMD_RXON_ASSOC 17 314#define WPI_CMD_EDCA_PARAMS 19 315#define WPI_CMD_TIMING 20 316#define WPI_CMD_ADD_NODE 24 317#define WPI_CMD_DEL_NODE 25 318#define WPI_CMD_TX_DATA 28 319#define WPI_CMD_MRR_SETUP 71 320#define WPI_CMD_SET_LED 72 321#define WPI_CMD_SET_POWER_MODE 119 322#define WPI_CMD_SCAN 128 323#define WPI_CMD_SET_BEACON 145 324#define WPI_CMD_TXPOWER 151 325#define WPI_CMD_BT_COEX 155 326#define WPI_CMD_GET_STATISTICS 156 327 328 uint8_t flags; 329 uint8_t idx; 330 uint8_t qid; 331 uint8_t data[124]; 332} __packed; 333 334/* Structure for command WPI_CMD_RXON. */ 335struct wpi_rxon { 336 uint8_t myaddr[IEEE80211_ADDR_LEN]; 337 uint16_t reserved1; 338 uint8_t bssid[IEEE80211_ADDR_LEN]; 339 uint16_t reserved2; 340 uint8_t wlap[IEEE80211_ADDR_LEN]; 341 uint16_t reserved3; 342 uint8_t mode; 343#define WPI_MODE_HOSTAP 1 344#define WPI_MODE_STA 3 345#define WPI_MODE_IBSS 4 346#define WPI_MODE_MONITOR 6 347 348 uint8_t air; 349 uint16_t reserved4; 350 uint8_t ofdm_mask; 351 uint8_t cck_mask; 352 uint16_t associd; 353 uint32_t flags; 354#define WPI_RXON_24GHZ (1 << 0) 355#define WPI_RXON_CCK (1 << 1) 356#define WPI_RXON_AUTO (1 << 2) 357#define WPI_RXON_SHSLOT (1 << 4) 358#define WPI_RXON_SHPREAMBLE (1 << 5) 359#define WPI_RXON_NODIVERSITY (1 << 7) 360#define WPI_RXON_ANTENNA_A (1 << 8) 361#define WPI_RXON_ANTENNA_B (1 << 9) 362#define WPI_RXON_TSF (1 << 15) 363#define WPI_RXON_CTS_TO_SELF (1 << 30) 364 365 uint32_t filter; 366#define WPI_FILTER_PROMISC (1 << 0) 367#define WPI_FILTER_CTL (1 << 1) 368#define WPI_FILTER_MULTICAST (1 << 2) 369#define WPI_FILTER_NODECRYPT (1 << 3) 370#define WPI_FILTER_BSS (1 << 5) 371#define WPI_FILTER_BEACON (1 << 6) 372 373 uint8_t chan; 374 uint16_t reserved5; 375} __packed; 376 377/* Structure for command WPI_CMD_RXON_ASSOC. */ 378struct wpi_assoc { 379 uint32_t flags; 380 uint32_t filter; 381 uint8_t ofdm_mask; 382 uint8_t cck_mask; 383 uint16_t reserved; 384} __packed; 385 386/* Structure for command WPI_CMD_EDCA_PARAMS. */ 387struct wpi_edca_params { 388 uint32_t flags; 389#define WPI_EDCA_UPDATE (1 << 0) 390 391 struct { 392 uint16_t cwmin; 393 uint16_t cwmax; 394 uint8_t aifsn; 395 uint8_t reserved; 396 uint16_t txoplimit; 397 } __packed ac[WME_NUM_AC]; 398} __packed; 399 400/* Structure for command WPI_CMD_TIMING. */ 401struct wpi_cmd_timing { 402 uint64_t tstamp; 403 uint16_t bintval; 404 uint16_t atim; 405 uint32_t binitval; 406 uint16_t lintval; 407 uint16_t reserved; 408} __packed; 409 410/* Structure for command WPI_CMD_ADD_NODE. */ 411struct wpi_node_info { 412 uint8_t control; 413#define WPI_NODE_UPDATE (1 << 0) 414 415 uint8_t reserved1[3]; 416 uint8_t macaddr[IEEE80211_ADDR_LEN]; 417 uint16_t reserved2; 418 uint8_t id; 419#define WPI_ID_BSS 0 420#define WPI_ID_IBSS_MIN 2 421#define WPI_ID_IBSS_MAX 23 422#define WPI_ID_BROADCAST 24 423#define WPI_ID_UNDEFINED (uint8_t)-1 424 425 uint8_t flags; 426#define WPI_FLAG_KEY_SET (1 << 0) 427 428 uint16_t reserved3; 429 uint16_t kflags; 430#define WPI_KFLAG_CCMP (1 << 1) 431#define WPI_KFLAG_KID(kid) ((kid) << 8) 432#define WPI_KFLAG_MULTICAST (1 << 14) 433 434 uint8_t tsc2; 435 uint8_t reserved4; 436 uint16_t ttak[5]; 437 uint16_t reserved5; 438 uint8_t key[IEEE80211_KEYBUF_SIZE]; 439 uint32_t action; 440#define WPI_ACTION_SET_RATE (1 << 2) 441 442 uint32_t mask; 443 uint16_t tid; 444 uint8_t plcp; 445 uint8_t antenna; 446#define WPI_ANTENNA_A (1 << 6) 447#define WPI_ANTENNA_B (1 << 7) 448#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 449 450 uint8_t add_imm; 451 uint8_t del_imm; 452 uint16_t add_imm_start; 453} __packed; 454 455/* Structure for command WPI_CMD_DEL_NODE. */ 456struct wpi_cmd_del_node { 457 uint8_t count; 458 uint8_t reserved1[3]; 459 uint8_t macaddr[IEEE80211_ADDR_LEN]; 460 uint16_t reserved2; 461} __packed; 462 463/* Structure for command WPI_CMD_TX_DATA. */ 464struct wpi_cmd_data { 465 uint16_t len; 466 uint16_t lnext; 467 uint32_t flags; 468#define WPI_TX_NEED_RTS (1 << 1) 469#define WPI_TX_NEED_CTS (1 << 2) 470#define WPI_TX_NEED_ACK (1 << 3) 471#define WPI_TX_FULL_TXOP (1 << 7) 472#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 473#define WPI_TX_AUTO_SEQ (1 << 13) 474#define WPI_TX_MORE_FRAG (1 << 14) 475#define WPI_TX_INSERT_TSTAMP (1 << 16) 476 477 uint8_t plcp; 478 uint8_t id; 479 uint8_t tid; 480 uint8_t security; 481#define WPI_CIPHER_WEP 1 482#define WPI_CIPHER_CCMP 2 483#define WPI_CIPHER_TKIP 3 484#define WPI_CIPHER_WEP104 9 485 486 uint8_t key[IEEE80211_KEYBUF_SIZE]; 487 uint8_t tkip[IEEE80211_WEP_MICLEN]; 488 uint32_t fnext; 489 uint32_t lifetime; 490#define WPI_LIFETIME_INFINITE 0xffffffff 491 492 uint8_t ofdm_mask; 493 uint8_t cck_mask; 494 uint8_t rts_ntries; 495 uint8_t data_ntries; 496 uint16_t timeout; 497 uint16_t txop; 498} __packed; 499 500/* Structure for command WPI_CMD_SET_BEACON. */ 501struct wpi_cmd_beacon { 502 uint16_t len; 503 uint16_t reserved1; 504 uint32_t flags; /* same as wpi_cmd_data */ 505 uint8_t plcp; 506 uint8_t id; 507 uint8_t reserved2[30]; 508 uint32_t lifetime; 509 uint8_t ofdm_mask; 510 uint8_t cck_mask; 511 uint16_t reserved3[3]; 512 uint16_t tim; 513 uint8_t timsz; 514 uint8_t reserved4; 515} __packed; 516 517/* Structure for notification WPI_BEACON_MISSED. */ 518struct wpi_beacon_missed { 519 uint32_t consecutive; 520 uint32_t total; 521 uint32_t expected; 522 uint32_t received; 523} __packed; 524 525 526/* Structure for command WPI_CMD_MRR_SETUP. */ 527#define WPI_RIDX_MAX 11 528struct wpi_mrr_setup { 529 uint32_t which; 530#define WPI_MRR_CTL 0 531#define WPI_MRR_DATA 1 532 533 struct { 534 uint8_t plcp; 535 uint8_t flags; 536 uint8_t ntries; 537 uint8_t next; 538 } __packed rates[WPI_RIDX_MAX + 1]; 539} __packed; 540 541/* Structure for command WPI_CMD_SET_LED. */ 542struct wpi_cmd_led { 543 uint32_t unit; /* multiplier (in usecs) */ 544 uint8_t which; 545#define WPI_LED_ACTIVITY 1 546#define WPI_LED_LINK 2 547 548 uint8_t off; 549 uint8_t on; 550 uint8_t reserved; 551} __packed; 552 553/* Structure for command WPI_CMD_SET_POWER_MODE. */ 554struct wpi_pmgt_cmd { 555 uint16_t flags; 556#define WPI_PS_ALLOW_SLEEP (1 << 0) 557#define WPI_PS_NOTIFY (1 << 1) 558#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 559#define WPI_PS_PCI_PMGT (1 << 3) 560 561 uint8_t reserved[2]; 562 uint32_t rxtimeout; 563 uint32_t txtimeout; 564 uint32_t intval[5]; 565} __packed; 566 567/* Structures for command WPI_CMD_SCAN. */ 568#define WPI_SCAN_MAX_ESSIDS 4 569struct wpi_scan_essid { 570 uint8_t id; 571 uint8_t len; 572 uint8_t data[IEEE80211_NWID_LEN]; 573} __packed; 574 575struct wpi_scan_hdr { 576 uint16_t len; 577 uint8_t reserved1; 578 uint8_t nchan; 579 uint16_t quiet_time; 580 uint16_t quiet_threshold; 581 uint16_t crc_threshold; 582 uint16_t reserved2; 583 uint32_t max_svc; /* background scans */ 584 uint32_t pause_svc; /* background scans */ 585 uint32_t flags; 586 uint32_t filter; 587 588 /* Followed by a struct wpi_cmd_data. */ 589 /* Followed by an array of 4 structs wpi_scan_essid. */ 590 /* Followed by probe request body. */ 591 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 592} __packed; 593 594struct wpi_scan_chan { 595 uint8_t flags; 596#define WPI_CHAN_ACTIVE (1 << 0) 597#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 598 599 uint8_t chan; 600 uint8_t rf_gain; 601 uint8_t dsp_gain; 602 uint16_t active; /* msecs */ 603 uint16_t passive; /* msecs */ 604} __packed; 605 606#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 607#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 608 609/* Maximum size of a scan command. */ 610#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 611 612#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 613#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 614#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 615#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 616 617#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 618#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 619#define WPI_PASSIVE_DWELL_BASE (100) 620 621/* Structure for command WPI_CMD_TXPOWER. */ 622struct wpi_cmd_txpower { 623 uint8_t band; 624#define WPI_BAND_5GHZ 0 625#define WPI_BAND_2GHZ 1 626 627 uint8_t reserved; 628 uint16_t chan; 629 630 struct { 631 uint8_t plcp; 632 uint8_t rf_gain; 633 uint8_t dsp_gain; 634 uint8_t reserved; 635 } __packed rates[WPI_RIDX_MAX + 1]; 636 637} __packed; 638 639/* Structure for command WPI_CMD_BT_COEX. */ 640struct wpi_bluetooth { 641 uint8_t flags; 642#define WPI_BT_COEX_DISABLE 0 643#define WPI_BT_COEX_MODE_2WIRE 1 644#define WPI_BT_COEX_MODE_3WIRE 2 645#define WPI_BT_COEX_MODE_4WIRE 3 646 647 uint8_t lead_time; 648#define WPI_BT_LEAD_TIME_DEF 30 649 650 uint8_t max_kill; 651#define WPI_BT_MAX_KILL_DEF 5 652 653 uint8_t reserved; 654 uint32_t kill_ack; 655 uint32_t kill_cts; 656} __packed; 657 658/* Structure for WPI_UC_READY notification. */ 659struct wpi_ucode_info { 660 uint8_t minor; 661 uint8_t major; 662 uint16_t reserved1; 663 uint8_t revision[8]; 664 uint8_t type; 665 uint8_t subtype; 666 uint16_t reserved2; 667 uint32_t logptr; 668 uint32_t errptr; 669 uint32_t tstamp; 670 uint32_t valid; 671} __packed; 672 673/* Structure for WPI_START_SCAN notification. */ 674struct wpi_start_scan { 675 uint64_t tstamp; 676 uint32_t tbeacon; 677 uint8_t chan; 678 uint8_t band; 679 uint16_t reserved; 680 uint32_t status; 681} __packed; 682 683/* Structure for WPI_STOP_SCAN notification. */ 684struct wpi_stop_scan { 685 uint8_t nchan; 686 uint8_t status; 687 uint8_t reserved; 688 uint8_t chan; 689 uint64_t tsf; 690} __packed; 691 692/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 693struct wpi_rx_phy_stats { 694 uint32_t ina; 695 uint32_t fina; 696 uint32_t bad_plcp; 697 uint32_t bad_crc32; 698 uint32_t overrun; 699 uint32_t eoverrun; 700 uint32_t good_crc32; 701 uint32_t fa; 702 uint32_t bad_fina_sync; 703 uint32_t sfd_timeout; 704 uint32_t fina_timeout; 705 uint32_t no_rts_ack; 706 uint32_t rxe_limit; 707 uint32_t ack; 708 uint32_t cts; 709} __packed; 710 711struct wpi_rx_general_stats { 712 uint32_t bad_cts; 713 uint32_t bad_ack; 714 uint32_t not_bss; 715 uint32_t filtered; 716 uint32_t bad_chan; 717} __packed; 718 719struct wpi_rx_stats { 720 struct wpi_rx_phy_stats ofdm; 721 struct wpi_rx_phy_stats cck; 722 struct wpi_rx_general_stats general; 723} __packed; 724 725struct wpi_tx_stats { 726 uint32_t preamble; 727 uint32_t rx_detected; 728 uint32_t bt_defer; 729 uint32_t bt_kill; 730 uint32_t short_len; 731 uint32_t cts_timeout; 732 uint32_t ack_timeout; 733 uint32_t exp_ack; 734 uint32_t ack; 735} __packed; 736 737struct wpi_general_stats { 738 uint32_t temp; 739 uint32_t burst_check; 740 uint32_t burst; 741 uint32_t reserved[4]; 742 uint32_t sleep; 743 uint32_t slot_out; 744 uint32_t slot_idle; 745 uint32_t ttl_tstamp; 746 uint32_t tx_ant_a; 747 uint32_t tx_ant_b; 748 uint32_t exec; 749 uint32_t probe; 750} __packed; 751 752struct wpi_stats { 753 uint32_t flags; 754 struct wpi_rx_stats rx; 755 struct wpi_tx_stats tx; 756 struct wpi_general_stats general; 757} __packed; 758 759/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 760#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 761 762 763/* Firmware error dump entry. */ 764struct wpi_fw_dump { 765 uint32_t desc; 766 uint32_t time; 767 uint32_t blink[2]; 768 uint32_t ilink[2]; 769 uint32_t data; 770} __packed; 771 772/* Firmware image file header. */ 773struct wpi_firmware_hdr { 774 775#define WPI_FW_MINVERSION 2144 776#define WPI_FW_NAME "wpifw" 777 778 uint16_t driver; 779 uint8_t minor; 780 uint8_t major; 781 uint32_t rtextsz; 782 uint32_t rdatasz; 783 uint32_t itextsz; 784 uint32_t idatasz; 785 uint32_t btextsz; 786} __packed; 787 788#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 789#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 790#define WPI_FW_BOOT_TEXT_MAXSZ 1024 791 792#define WPI_FW_UPDATED (1U << 31 ) 793 794/* 795 * Offsets into EEPROM. 796 */ 797#define WPI_EEPROM_MAC 0x015 798#define WPI_EEPROM_REVISION 0x035 799#define WPI_EEPROM_SKU_CAP 0x045 800#define WPI_EEPROM_TYPE 0x04a 801#define WPI_EEPROM_DOMAIN 0x060 802#define WPI_EEPROM_BAND1 0x063 803#define WPI_EEPROM_BAND2 0x072 804#define WPI_EEPROM_BAND3 0x080 805#define WPI_EEPROM_BAND4 0x08d 806#define WPI_EEPROM_BAND5 0x099 807#define WPI_EEPROM_POWER_GRP 0x100 808 809struct wpi_eeprom_chan { 810 uint8_t flags; 811#define WPI_EEPROM_CHAN_VALID (1 << 0) 812#define WPI_EEPROM_CHAN_IBSS (1 << 1) 813#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 814#define WPI_EEPROM_CHAN_RADAR (1 << 4) 815 816 int8_t maxpwr; 817} __packed; 818 819struct wpi_eeprom_sample { 820 uint8_t index; 821 int8_t power; 822 uint16_t volt; 823} __packed; 824 825#define WPI_POWER_GROUPS_COUNT 5 826struct wpi_eeprom_group { 827 struct wpi_eeprom_sample samples[5]; 828 int32_t coef[5]; 829 int32_t corr[5]; 830 int8_t maxpwr; 831 uint8_t chan; 832 int16_t temp; 833} __packed; 834 835#define WPI_CHAN_BANDS_COUNT 5 836#define WPI_MAX_CHAN_PER_BAND 14 837static const struct wpi_chan_band { 838 uint32_t addr; /* offset in EEPROM */ 839 uint8_t nchan; 840 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 841} wpi_bands[] = { 842 /* 20MHz channels, 2GHz band. */ 843 { WPI_EEPROM_BAND1, 14, 844 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 845 /* 20MHz channels, 5GHz band. */ 846 { WPI_EEPROM_BAND2, 13, 847 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 848 { WPI_EEPROM_BAND3, 12, 849 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 850 { WPI_EEPROM_BAND4, 11, 851 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 852 { WPI_EEPROM_BAND5, 6, 853 { 145, 149, 153, 157, 161, 165 } } 854}; 855 856/* HW rate indices. */ 857#define WPI_RIDX_OFDM6 0 858#define WPI_RIDX_OFDM36 5 859#define WPI_RIDX_OFDM48 6 860#define WPI_RIDX_OFDM54 7 861#define WPI_RIDX_CCK1 8 862#define WPI_RIDX_CCK2 9 863#define WPI_RIDX_CCK11 11 864 865static const uint8_t wpi_ridx_to_plcp[] = { 866 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 867 /* R1-R4 (ral/ural is R4-R1) */ 868 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 869 /* CCK: device-dependent */ 870 10, 20, 55, 110 871}; 872 873#define WPI_MAX_PWR_INDEX 77 874 875/* 876 * RF Tx gain values from highest to lowest power (values obtained from 877 * the reference driver.) 878 */ 879static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 880 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 881 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 882 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 883 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 884 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 885 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 886 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 887 0x03 888}; 889 890static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 891 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 892 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 893 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 894 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 895 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 896 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 897 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 898 0x03 899}; 900 901/* 902 * DSP pre-DAC gain values from highest to lowest power (values obtained 903 * from the reference driver.) 904 */ 905static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 906 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 907 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 908 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 909 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 910 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 911 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 912 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 913 0x5f 914}; 915 916static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 917 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 918 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 919 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 920 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 921 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 922 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 923 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 924 0x78 925}; 926 927/* 928 * Power saving settings (values obtained from the reference driver.) 929 */ 930#define WPI_NDTIMRANGES 2 931#define WPI_NPOWERLEVELS 6 932static const struct wpi_pmgt { 933 uint32_t rxtimeout; 934 uint32_t txtimeout; 935 uint32_t intval[5]; 936 int skip_dtim; 937} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 938 /* DTIM <= 10 */ 939 { 940 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 941 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 942 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 943 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 944 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 945 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 946 }, 947 /* DTIM >= 11 */ 948 { 949 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 950 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 951 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 952 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 953 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 954 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 955 } 956}; 957 958/* Firmware errors. */ 959static const char * const wpi_fw_errmsg[] = { 960 "OK", 961 "FAIL", 962 "BAD_PARAM", 963 "BAD_CHECKSUM", 964 "NMI_INTERRUPT", 965 "SYSASSERT", 966 "FATAL_ERROR" 967}; 968 969#define WPI_READ(sc, reg) \ 970 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 971 972#define WPI_WRITE(sc, reg, val) \ 973 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 974 975#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 976 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 977 (datap), (count)) 978 979#define WPI_SETBITS(sc, reg, mask) \ 980 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 981 982#define WPI_CLRBITS(sc, reg, mask) \ 983 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 984 985#define WPI_BARRIER_WRITE(sc) \ 986 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 987 BUS_SPACE_BARRIER_WRITE) 988 989#define WPI_BARRIER_READ_WRITE(sc) \ 990 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 991 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 992