if_wpireg.h revision 278764
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 278764 2015-02-14 17:45:53Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23#define WPI_RX_RING_COUNT_LOG 6 24#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 25 26#define WPI_NTXQUEUES 8 27#define WPI_NDMACHNLS 6 28 29/* Maximum scatter/gather. */ 30#define WPI_MAX_SCATTER 4 31 32/* 33 * Rings must be aligned on a 16K boundary. 34 */ 35#define WPI_RING_DMA_ALIGN 0x4000 36 37/* Maximum Rx buffer size. */ 38#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 39 40/* 41 * Control and status registers. 42 */ 43#define WPI_HW_IF_CONFIG 0x000 44#define WPI_INT 0x008 45#define WPI_INT_MASK 0x00c 46#define WPI_FH_INT 0x010 47#define WPI_GPIO_IN 0x018 48#define WPI_RESET 0x020 49#define WPI_GP_CNTRL 0x024 50#define WPI_EEPROM 0x02c 51#define WPI_EEPROM_GP 0x030 52#define WPI_GIO 0x03c 53#define WPI_UCODE_GP1 0x054 54#define WPI_UCODE_GP1_SET 0x058 55#define WPI_UCODE_GP1_CLR 0x05c 56#define WPI_UCODE_GP2 0x060 57#define WPI_GIO_CHICKEN 0x100 58#define WPI_ANA_PLL 0x20c 59#define WPI_DBG_HPET_MEM 0x240 60#define WPI_MEM_RADDR 0x40c 61#define WPI_MEM_WADDR 0x410 62#define WPI_MEM_WDATA 0x418 63#define WPI_MEM_RDATA 0x41c 64#define WPI_PRPH_WADDR 0x444 65#define WPI_PRPH_RADDR 0x448 66#define WPI_PRPH_WDATA 0x44c 67#define WPI_PRPH_RDATA 0x450 68#define WPI_HBUS_TARG_WRPTR 0x460 69 70/* 71 * Flow-Handler registers. 72 */ 73#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 74#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 75#define WPI_FH_RX_CONFIG 0xc00 76#define WPI_FH_RX_BASE 0xc04 77#define WPI_FH_RX_WPTR 0xc20 78#define WPI_FH_RX_RPTR_ADDR 0xc24 79#define WPI_FH_RSSR_TBL 0xcc0 80#define WPI_FH_RX_STATUS 0xcc4 81#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 82#define WPI_FH_TX_BASE 0xe80 83#define WPI_FH_MSG_CONFIG 0xe88 84#define WPI_FH_TX_STATUS 0xe90 85 86 87/* 88 * NIC internal memory offsets. 89 */ 90#define WPI_ALM_SCHED_MODE 0x2e00 91#define WPI_ALM_SCHED_ARASTAT 0x2e04 92#define WPI_ALM_SCHED_TXFACT 0x2e10 93#define WPI_ALM_SCHED_TXF4MF 0x2e14 94#define WPI_ALM_SCHED_TXF5MF 0x2e20 95#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 96#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 97#define WPI_APMG_CLK_EN 0x3004 98#define WPI_APMG_CLK_DIS 0x3008 99#define WPI_APMG_PS 0x300c 100#define WPI_APMG_PCI_STT 0x3010 101#define WPI_APMG_RFKILL 0x3014 102#define WPI_BSM_WR_CTRL 0x3400 103#define WPI_BSM_WR_MEM_SRC 0x3404 104#define WPI_BSM_WR_MEM_DST 0x3408 105#define WPI_BSM_WR_DWCOUNT 0x340c 106#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 107#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 108#define WPI_BSM_DRAM_DATA_ADDR 0x3498 109#define WPI_BSM_DRAM_DATA_SIZE 0x349c 110#define WPI_BSM_SRAM_BASE 0x3800 111 112 113/* Possible flags for register WPI_HW_IF_CONFIG. */ 114#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 115#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 116#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 117#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 118#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 119 120/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 121#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 122 123/* Possible values for WPI_BSM_WR_MEM_DST. */ 124#define WPI_FW_TEXT_BASE 0x00000000 125#define WPI_FW_DATA_BASE 0x00800000 126 127/* Possible flags for WPI_GPIO_IN. */ 128#define WPI_GPIO_IN_VMAIN (1 << 9) 129 130/* Possible flags for register WPI_RESET. */ 131#define WPI_RESET_NEVO (1 << 0) 132#define WPI_RESET_SW (1 << 7) 133#define WPI_RESET_MASTER_DISABLED (1 << 8) 134#define WPI_RESET_STOP_MASTER (1 << 9) 135 136/* Possible flags for register WPI_GP_CNTRL. */ 137#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 138#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 139#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 140#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 141#define WPI_GP_CNTRL_SLEEP (1 << 4) 142#define WPI_GP_CNTRL_PS_MASK (7 << 24) 143#define WPI_GP_CNTRL_MAC_PS (4 << 24) 144#define WPI_GP_CNTRL_RFKILL (1 << 27) 145 146/* Possible flags for register WPI_GIO_CHICKEN. */ 147#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 148#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 149 150/* Possible flags for register WPI_GIO. */ 151#define WPI_GIO_L0S_ENA (1 << 1) 152 153/* Possible flags for register WPI_FH_RX_CONFIG. */ 154#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 155#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 156#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 157#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 158#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 159#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 160#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 161 162/* Possible flags for register WPI_ANA_PLL. */ 163#define WPI_ANA_PLL_INIT (1 << 24) 164 165/* Possible flags for register WPI_UCODE_GP1*. */ 166#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 167#define WPI_UCODE_GP1_RFKILL (1 << 1) 168#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 169 170/* Possible flags for register WPI_FH_RX_STATUS. */ 171#define WPI_FH_RX_STATUS_IDLE (1 << 24) 172 173/* Possible flags for register WPI_BSM_WR_CTRL. */ 174#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 175#define WPI_BSM_WR_CTRL_START (1U << 31) 176 177/* Possible flags for register WPI_INT. */ 178#define WPI_INT_ALIVE (1 << 0) 179#define WPI_INT_WAKEUP (1 << 1) 180#define WPI_INT_SW_RX (1 << 3) 181#define WPI_INT_SW_ERR (1 << 25) 182#define WPI_INT_FH_TX (1 << 27) 183#define WPI_INT_HW_ERR (1 << 29) 184#define WPI_INT_FH_RX (1U << 31) 185 186/* Shortcut. */ 187#define WPI_INT_MASK_DEF \ 188 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 189 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 190 WPI_INT_SW_RX) 191 192/* Possible flags for register WPI_FH_INT. */ 193#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 194#define WPI_FH_INT_HI_PRIOR (1 << 30) 195/* Shortcuts for the above. */ 196#define WPI_FH_INT_RX \ 197 (WPI_FH_INT_RX_CHNL(0) | \ 198 WPI_FH_INT_RX_CHNL(1) | \ 199 WPI_FH_INT_RX_CHNL(2) | \ 200 WPI_FH_INT_HI_PRIOR) 201 202/* Possible flags for register WPI_FH_TX_STATUS. */ 203#define WPI_FH_TX_STATUS_IDLE(qid) \ 204 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 205 206/* Possible flags for register WPI_EEPROM. */ 207#define WPI_EEPROM_READ_VALID (1 << 0) 208 209/* Possible flags for register WPI_EEPROM_GP. */ 210#define WPI_EEPROM_VERSION 0x00000007 211#define WPI_EEPROM_GP_IF_OWNER 0x00000180 212 213/* Possible flags for register WPI_APMG_PS. */ 214#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 215 216/* Possible flags for registers WPI_APMG_CLK_*. */ 217#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 218#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 219 220/* Possible flags for register WPI_APMG_PCI_STT. */ 221#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 222 223struct wpi_shared { 224 uint32_t txbase[8]; 225 uint32_t next; 226 uint32_t reserved[2]; 227} __packed; 228 229#define WPI_MAX_SEG_LEN 65520 230struct wpi_tx_desc { 231 uint8_t reserved1[3]; 232 uint8_t nsegs; 233#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 234 235 struct { 236 uint32_t addr; 237 uint32_t len; 238 } __packed segs[WPI_MAX_SCATTER]; 239 uint8_t reserved2[28]; 240} __packed; 241 242struct wpi_tx_stat { 243 uint8_t rtsfailcnt; 244 uint8_t ackfailcnt; 245 uint8_t btkillcnt; 246 uint8_t rate; 247 uint32_t duration; 248 uint32_t status; 249} __packed; 250 251struct wpi_rx_desc { 252 uint32_t len; 253 uint8_t type; 254#define WPI_UC_READY 1 255#define WPI_RX_DONE 27 256#define WPI_TX_DONE 28 257#define WPI_START_SCAN 130 258#define WPI_SCAN_RESULTS 131 259#define WPI_STOP_SCAN 132 260#define WPI_BEACON_SENT 144 261#define WPI_RX_STATISTICS 156 262#define WPI_BEACON_STATISTICS 157 263#define WPI_STATE_CHANGED 161 264#define WPI_BEACON_MISSED 162 265 266 uint8_t flags; 267 uint8_t idx; 268 uint8_t qid; 269} __packed; 270 271struct wpi_rx_stat { 272 uint8_t len; 273#define WPI_STAT_MAXLEN 20 274 275 uint8_t id; 276 uint8_t rssi; /* received signal strength */ 277#define WPI_RSSI_OFFSET 95 278 279 uint8_t agc; /* access gain control */ 280 uint16_t signal; 281 uint16_t noise; 282} __packed; 283 284struct wpi_rx_head { 285 uint16_t chan; 286 uint16_t flags; 287#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 288 289 uint8_t reserved; 290 uint8_t plcp; 291 uint16_t len; 292} __packed; 293 294struct wpi_rx_tail { 295 uint32_t flags; 296#define WPI_RX_NO_CRC_ERR (1 << 0) 297#define WPI_RX_NO_OVFL_ERR (1 << 1) 298/* shortcut for the above */ 299#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 300#define WPI_RX_CIPHER_MASK (7 << 8) 301#define WPI_RX_CIPHER_CCMP (2 << 8) 302#define WPI_RX_DECRYPT_MASK (3 << 11) 303#define WPI_RX_DECRYPT_OK (3 << 11) 304 305 uint64_t tstamp; 306 uint32_t tbeacon; 307} __packed; 308 309struct wpi_tx_cmd { 310 uint8_t code; 311#define WPI_CMD_RXON 16 312#define WPI_CMD_RXON_ASSOC 17 313#define WPI_CMD_EDCA_PARAMS 19 314#define WPI_CMD_TIMING 20 315#define WPI_CMD_ADD_NODE 24 316#define WPI_CMD_DEL_NODE 25 317#define WPI_CMD_TX_DATA 28 318#define WPI_CMD_MRR_SETUP 71 319#define WPI_CMD_SET_LED 72 320#define WPI_CMD_SET_POWER_MODE 119 321#define WPI_CMD_SCAN 128 322#define WPI_CMD_SET_BEACON 145 323#define WPI_CMD_TXPOWER 151 324#define WPI_CMD_BT_COEX 155 325#define WPI_CMD_GET_STATISTICS 156 326 327 uint8_t flags; 328 uint8_t idx; 329 uint8_t qid; 330 uint8_t data[124]; 331} __packed; 332 333/* Structure for command WPI_CMD_RXON. */ 334struct wpi_rxon { 335 uint8_t myaddr[IEEE80211_ADDR_LEN]; 336 uint16_t reserved1; 337 uint8_t bssid[IEEE80211_ADDR_LEN]; 338 uint16_t reserved2; 339 uint8_t wlap[IEEE80211_ADDR_LEN]; 340 uint16_t reserved3; 341 uint8_t mode; 342#define WPI_MODE_HOSTAP 1 343#define WPI_MODE_STA 3 344#define WPI_MODE_IBSS 4 345#define WPI_MODE_MONITOR 6 346 347 uint8_t air; 348 uint16_t reserved4; 349 uint8_t ofdm_mask; 350 uint8_t cck_mask; 351 uint16_t associd; 352 uint32_t flags; 353#define WPI_RXON_24GHZ (1 << 0) 354#define WPI_RXON_CCK (1 << 1) 355#define WPI_RXON_AUTO (1 << 2) 356#define WPI_RXON_SHSLOT (1 << 4) 357#define WPI_RXON_SHPREAMBLE (1 << 5) 358#define WPI_RXON_NODIVERSITY (1 << 7) 359#define WPI_RXON_ANTENNA_A (1 << 8) 360#define WPI_RXON_ANTENNA_B (1 << 9) 361#define WPI_RXON_TSF (1 << 15) 362#define WPI_RXON_CTS_TO_SELF (1 << 30) 363 364 uint32_t filter; 365#define WPI_FILTER_PROMISC (1 << 0) 366#define WPI_FILTER_CTL (1 << 1) 367#define WPI_FILTER_MULTICAST (1 << 2) 368#define WPI_FILTER_NODECRYPT (1 << 3) 369#define WPI_FILTER_BSS (1 << 5) 370#define WPI_FILTER_BEACON (1 << 6) 371 372 uint8_t chan; 373 uint16_t reserved5; 374} __packed; 375 376/* Structure for command WPI_CMD_RXON_ASSOC. */ 377struct wpi_assoc { 378 uint32_t flags; 379 uint32_t filter; 380 uint8_t ofdm_mask; 381 uint8_t cck_mask; 382 uint16_t reserved; 383} __packed; 384 385/* Structure for command WPI_CMD_EDCA_PARAMS. */ 386struct wpi_edca_params { 387 uint32_t flags; 388#define WPI_EDCA_UPDATE (1 << 0) 389 390 struct { 391 uint16_t cwmin; 392 uint16_t cwmax; 393 uint8_t aifsn; 394 uint8_t reserved; 395 uint16_t txoplimit; 396 } __packed ac[WME_NUM_AC]; 397} __packed; 398 399/* Structure for command WPI_CMD_TIMING. */ 400struct wpi_cmd_timing { 401 uint64_t tstamp; 402 uint16_t bintval; 403 uint16_t atim; 404 uint32_t binitval; 405 uint16_t lintval; 406 uint16_t reserved; 407} __packed; 408 409/* Structure for command WPI_CMD_ADD_NODE. */ 410struct wpi_node_info { 411 uint8_t control; 412#define WPI_NODE_UPDATE (1 << 0) 413 414 uint8_t reserved1[3]; 415 uint8_t macaddr[IEEE80211_ADDR_LEN]; 416 uint16_t reserved2; 417 uint8_t id; 418#define WPI_ID_BSS 0 419#define WPI_ID_IBSS_MIN 2 420#define WPI_ID_IBSS_MAX 23 421#define WPI_ID_BROADCAST 24 422#define WPI_ID_UNDEFINED (uint8_t)-1 423 424 uint8_t flags; 425#define WPI_FLAG_KEY_SET (1 << 0) 426 427 uint16_t reserved3; 428 uint16_t kflags; 429#define WPI_KFLAG_CCMP (1 << 1) 430#define WPI_KFLAG_KID(kid) ((kid) << 8) 431#define WPI_KFLAG_MULTICAST (1 << 14) 432 433 uint8_t tsc2; 434 uint8_t reserved4; 435 uint16_t ttak[5]; 436 uint16_t reserved5; 437 uint8_t key[IEEE80211_KEYBUF_SIZE]; 438 uint32_t action; 439#define WPI_ACTION_SET_RATE (1 << 2) 440 441 uint32_t mask; 442 uint16_t tid; 443 uint8_t plcp; 444 uint8_t antenna; 445#define WPI_ANTENNA_A (1 << 6) 446#define WPI_ANTENNA_B (1 << 7) 447#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 448 449 uint8_t add_imm; 450 uint8_t del_imm; 451 uint16_t add_imm_start; 452} __packed; 453 454/* Structure for command WPI_CMD_DEL_NODE. */ 455struct wpi_cmd_del_node { 456 uint8_t count; 457 uint8_t reserved1[3]; 458 uint8_t macaddr[IEEE80211_ADDR_LEN]; 459 uint16_t reserved2; 460} __packed; 461 462/* Structure for command WPI_CMD_TX_DATA. */ 463struct wpi_cmd_data { 464 uint16_t len; 465 uint16_t lnext; 466 uint32_t flags; 467#define WPI_TX_NEED_RTS (1 << 1) 468#define WPI_TX_NEED_CTS (1 << 2) 469#define WPI_TX_NEED_ACK (1 << 3) 470#define WPI_TX_FULL_TXOP (1 << 7) 471#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 472#define WPI_TX_AUTO_SEQ (1 << 13) 473#define WPI_TX_MORE_FRAG (1 << 14) 474#define WPI_TX_INSERT_TSTAMP (1 << 16) 475 476 uint8_t plcp; 477 uint8_t id; 478 uint8_t tid; 479 uint8_t security; 480#define WPI_CIPHER_WEP 1 481#define WPI_CIPHER_CCMP 2 482#define WPI_CIPHER_TKIP 3 483#define WPI_CIPHER_WEP104 9 484 485 uint8_t key[IEEE80211_KEYBUF_SIZE]; 486 uint8_t tkip[IEEE80211_WEP_MICLEN]; 487 uint32_t fnext; 488 uint32_t lifetime; 489#define WPI_LIFETIME_INFINITE 0xffffffff 490 491 uint8_t ofdm_mask; 492 uint8_t cck_mask; 493 uint8_t rts_ntries; 494 uint8_t data_ntries; 495 uint16_t timeout; 496 uint16_t txop; 497} __packed; 498 499/* Structure for command WPI_CMD_SET_BEACON. */ 500struct wpi_cmd_beacon { 501 uint16_t len; 502 uint16_t reserved1; 503 uint32_t flags; /* same as wpi_cmd_data */ 504 uint8_t plcp; 505 uint8_t id; 506 uint8_t reserved2[30]; 507 uint32_t lifetime; 508 uint8_t ofdm_mask; 509 uint8_t cck_mask; 510 uint16_t reserved3[3]; 511 uint16_t tim; 512 uint8_t timsz; 513 uint8_t reserved4; 514} __packed; 515 516/* Structure for notification WPI_BEACON_MISSED. */ 517struct wpi_beacon_missed { 518 uint32_t consecutive; 519 uint32_t total; 520 uint32_t expected; 521 uint32_t received; 522} __packed; 523 524 525/* Structure for command WPI_CMD_MRR_SETUP. */ 526#define WPI_RIDX_MAX 11 527struct wpi_mrr_setup { 528 uint32_t which; 529#define WPI_MRR_CTL 0 530#define WPI_MRR_DATA 1 531 532 struct { 533 uint8_t plcp; 534 uint8_t flags; 535 uint8_t ntries; 536 uint8_t next; 537 } __packed rates[WPI_RIDX_MAX + 1]; 538} __packed; 539 540/* Structure for command WPI_CMD_SET_LED. */ 541struct wpi_cmd_led { 542 uint32_t unit; /* multiplier (in usecs) */ 543 uint8_t which; 544#define WPI_LED_ACTIVITY 1 545#define WPI_LED_LINK 2 546 547 uint8_t off; 548 uint8_t on; 549 uint8_t reserved; 550} __packed; 551 552/* Structure for command WPI_CMD_SET_POWER_MODE. */ 553struct wpi_pmgt_cmd { 554 uint16_t flags; 555#define WPI_PS_ALLOW_SLEEP (1 << 0) 556#define WPI_PS_NOTIFY (1 << 1) 557#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 558#define WPI_PS_PCI_PMGT (1 << 3) 559 560 uint8_t reserved[2]; 561 uint32_t rxtimeout; 562 uint32_t txtimeout; 563 uint32_t intval[5]; 564} __packed; 565 566/* Structures for command WPI_CMD_SCAN. */ 567#define WPI_SCAN_MAX_ESSIDS 4 568struct wpi_scan_essid { 569 uint8_t id; 570 uint8_t len; 571 uint8_t data[IEEE80211_NWID_LEN]; 572} __packed; 573 574struct wpi_scan_hdr { 575 uint16_t len; 576 uint8_t reserved1; 577 uint8_t nchan; 578 uint16_t quiet_time; 579 uint16_t quiet_threshold; 580 uint16_t crc_threshold; 581 uint16_t reserved2; 582 uint32_t max_svc; /* background scans */ 583 uint32_t pause_svc; /* background scans */ 584 uint32_t flags; 585 uint32_t filter; 586 587 /* Followed by a struct wpi_cmd_data. */ 588 /* Followed by an array of 4 structs wpi_scan_essid. */ 589 /* Followed by probe request body. */ 590 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 591} __packed; 592 593struct wpi_scan_chan { 594 uint8_t flags; 595#define WPI_CHAN_ACTIVE (1 << 0) 596#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 597 598 uint8_t chan; 599 uint8_t rf_gain; 600 uint8_t dsp_gain; 601 uint16_t active; /* msecs */ 602 uint16_t passive; /* msecs */ 603} __packed; 604 605#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 606#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 607 608/* Maximum size of a scan command. */ 609#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 610 611#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 612#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 613#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 614#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 615 616#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 617#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 618#define WPI_PASSIVE_DWELL_BASE (100) 619 620/* Structure for command WPI_CMD_TXPOWER. */ 621struct wpi_cmd_txpower { 622 uint8_t band; 623#define WPI_BAND_5GHZ 0 624#define WPI_BAND_2GHZ 1 625 626 uint8_t reserved; 627 uint16_t chan; 628 629 struct { 630 uint8_t plcp; 631 uint8_t rf_gain; 632 uint8_t dsp_gain; 633 uint8_t reserved; 634 } __packed rates[WPI_RIDX_MAX + 1]; 635 636} __packed; 637 638/* Structure for command WPI_CMD_BT_COEX. */ 639struct wpi_bluetooth { 640 uint8_t flags; 641#define WPI_BT_COEX_DISABLE 0 642#define WPI_BT_COEX_MODE_2WIRE 1 643#define WPI_BT_COEX_MODE_3WIRE 2 644#define WPI_BT_COEX_MODE_4WIRE 3 645 646 uint8_t lead_time; 647#define WPI_BT_LEAD_TIME_DEF 30 648 649 uint8_t max_kill; 650#define WPI_BT_MAX_KILL_DEF 5 651 652 uint8_t reserved; 653 uint32_t kill_ack; 654 uint32_t kill_cts; 655} __packed; 656 657/* Structure for WPI_UC_READY notification. */ 658struct wpi_ucode_info { 659 uint8_t minor; 660 uint8_t major; 661 uint16_t reserved1; 662 uint8_t revision[8]; 663 uint8_t type; 664 uint8_t subtype; 665 uint16_t reserved2; 666 uint32_t logptr; 667 uint32_t errptr; 668 uint32_t tstamp; 669 uint32_t valid; 670} __packed; 671 672/* Structure for WPI_START_SCAN notification. */ 673struct wpi_start_scan { 674 uint64_t tstamp; 675 uint32_t tbeacon; 676 uint8_t chan; 677 uint8_t band; 678 uint16_t reserved; 679 uint32_t status; 680} __packed; 681 682/* Structure for WPI_STOP_SCAN notification. */ 683struct wpi_stop_scan { 684 uint8_t nchan; 685 uint8_t status; 686 uint8_t reserved; 687 uint8_t chan; 688 uint64_t tsf; 689} __packed; 690 691/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 692struct wpi_rx_phy_stats { 693 uint32_t ina; 694 uint32_t fina; 695 uint32_t bad_plcp; 696 uint32_t bad_crc32; 697 uint32_t overrun; 698 uint32_t eoverrun; 699 uint32_t good_crc32; 700 uint32_t fa; 701 uint32_t bad_fina_sync; 702 uint32_t sfd_timeout; 703 uint32_t fina_timeout; 704 uint32_t no_rts_ack; 705 uint32_t rxe_limit; 706 uint32_t ack; 707 uint32_t cts; 708} __packed; 709 710struct wpi_rx_general_stats { 711 uint32_t bad_cts; 712 uint32_t bad_ack; 713 uint32_t not_bss; 714 uint32_t filtered; 715 uint32_t bad_chan; 716} __packed; 717 718struct wpi_rx_stats { 719 struct wpi_rx_phy_stats ofdm; 720 struct wpi_rx_phy_stats cck; 721 struct wpi_rx_general_stats general; 722} __packed; 723 724struct wpi_tx_stats { 725 uint32_t preamble; 726 uint32_t rx_detected; 727 uint32_t bt_defer; 728 uint32_t bt_kill; 729 uint32_t short_len; 730 uint32_t cts_timeout; 731 uint32_t ack_timeout; 732 uint32_t exp_ack; 733 uint32_t ack; 734} __packed; 735 736struct wpi_general_stats { 737 uint32_t temp; 738 uint32_t burst_check; 739 uint32_t burst; 740 uint32_t reserved[4]; 741 uint32_t sleep; 742 uint32_t slot_out; 743 uint32_t slot_idle; 744 uint32_t ttl_tstamp; 745 uint32_t tx_ant_a; 746 uint32_t tx_ant_b; 747 uint32_t exec; 748 uint32_t probe; 749} __packed; 750 751struct wpi_stats { 752 uint32_t flags; 753 struct wpi_rx_stats rx; 754 struct wpi_tx_stats tx; 755 struct wpi_general_stats general; 756} __packed; 757 758/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 759#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 760 761 762/* Firmware error dump entry. */ 763struct wpi_fw_dump { 764 uint32_t desc; 765 uint32_t time; 766 uint32_t blink[2]; 767 uint32_t ilink[2]; 768 uint32_t data; 769} __packed; 770 771/* Firmware image file header. */ 772struct wpi_firmware_hdr { 773 774#define WPI_FW_MINVERSION 2144 775#define WPI_FW_NAME "wpifw" 776 777 uint16_t driver; 778 uint8_t minor; 779 uint8_t major; 780 uint32_t rtextsz; 781 uint32_t rdatasz; 782 uint32_t itextsz; 783 uint32_t idatasz; 784 uint32_t btextsz; 785} __packed; 786 787#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 788#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 789#define WPI_FW_BOOT_TEXT_MAXSZ 1024 790 791#define WPI_FW_UPDATED (1U << 31 ) 792 793/* 794 * Offsets into EEPROM. 795 */ 796#define WPI_EEPROM_MAC 0x015 797#define WPI_EEPROM_REVISION 0x035 798#define WPI_EEPROM_SKU_CAP 0x045 799#define WPI_EEPROM_TYPE 0x04a 800#define WPI_EEPROM_DOMAIN 0x060 801#define WPI_EEPROM_BAND1 0x063 802#define WPI_EEPROM_BAND2 0x072 803#define WPI_EEPROM_BAND3 0x080 804#define WPI_EEPROM_BAND4 0x08d 805#define WPI_EEPROM_BAND5 0x099 806#define WPI_EEPROM_POWER_GRP 0x100 807 808struct wpi_eeprom_chan { 809 uint8_t flags; 810#define WPI_EEPROM_CHAN_VALID (1 << 0) 811#define WPI_EEPROM_CHAN_IBSS (1 << 1) 812#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 813#define WPI_EEPROM_CHAN_RADAR (1 << 4) 814 815 int8_t maxpwr; 816} __packed; 817 818struct wpi_eeprom_sample { 819 uint8_t index; 820 int8_t power; 821 uint16_t volt; 822} __packed; 823 824#define WPI_POWER_GROUPS_COUNT 5 825struct wpi_eeprom_group { 826 struct wpi_eeprom_sample samples[5]; 827 int32_t coef[5]; 828 int32_t corr[5]; 829 int8_t maxpwr; 830 uint8_t chan; 831 int16_t temp; 832} __packed; 833 834#define WPI_CHAN_BANDS_COUNT 5 835#define WPI_MAX_CHAN_PER_BAND 14 836static const struct wpi_chan_band { 837 uint32_t addr; /* offset in EEPROM */ 838 uint8_t nchan; 839 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 840} wpi_bands[] = { 841 /* 20MHz channels, 2GHz band. */ 842 { WPI_EEPROM_BAND1, 14, 843 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 844 /* 20MHz channels, 5GHz band. */ 845 { WPI_EEPROM_BAND2, 13, 846 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 847 { WPI_EEPROM_BAND3, 12, 848 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 849 { WPI_EEPROM_BAND4, 11, 850 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 851 { WPI_EEPROM_BAND5, 6, 852 { 145, 149, 153, 157, 161, 165 } } 853}; 854 855/* HW rate indices. */ 856#define WPI_RIDX_OFDM6 0 857#define WPI_RIDX_OFDM36 5 858#define WPI_RIDX_OFDM48 6 859#define WPI_RIDX_OFDM54 7 860#define WPI_RIDX_CCK1 8 861#define WPI_RIDX_CCK2 9 862#define WPI_RIDX_CCK11 11 863 864static const uint8_t wpi_ridx_to_plcp[] = { 865 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 866 /* R1-R4 (ral/ural is R4-R1) */ 867 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 868 /* CCK: device-dependent */ 869 10, 20, 55, 110 870}; 871 872#define WPI_MAX_PWR_INDEX 77 873 874/* 875 * RF Tx gain values from highest to lowest power (values obtained from 876 * the reference driver.) 877 */ 878static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 879 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 880 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 881 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 882 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 883 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 884 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 885 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 886 0x03 887}; 888 889static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 890 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 891 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 892 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 893 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 894 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 895 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 896 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 897 0x03 898}; 899 900/* 901 * DSP pre-DAC gain values from highest to lowest power (values obtained 902 * from the reference driver.) 903 */ 904static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 905 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 906 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 907 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 908 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 909 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 910 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 911 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 912 0x5f 913}; 914 915static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 916 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 917 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 918 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 919 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 920 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 921 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 922 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 923 0x78 924}; 925 926/* 927 * Power saving settings (values obtained from the reference driver.) 928 */ 929#define WPI_NDTIMRANGES 2 930#define WPI_NPOWERLEVELS 6 931static const struct wpi_pmgt { 932 uint32_t rxtimeout; 933 uint32_t txtimeout; 934 uint32_t intval[5]; 935 int skip_dtim; 936} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 937 /* DTIM <= 10 */ 938 { 939 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 940 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 941 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 942 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 943 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 944 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 945 }, 946 /* DTIM >= 11 */ 947 { 948 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 949 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 950 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 951 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 952 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 953 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 954 } 955}; 956 957/* Firmware errors. */ 958static const char * const wpi_fw_errmsg[] = { 959 "OK", 960 "FAIL", 961 "BAD_PARAM", 962 "BAD_CHECKSUM", 963 "NMI_INTERRUPT", 964 "SYSASSERT", 965 "FATAL_ERROR" 966}; 967 968#define WPI_READ(sc, reg) \ 969 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 970 971#define WPI_WRITE(sc, reg, val) \ 972 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 973 974#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 975 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 976 (datap), (count)) 977 978#define WPI_SETBITS(sc, reg, mask) \ 979 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 980 981#define WPI_CLRBITS(sc, reg, mask) \ 982 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 983 984#define WPI_BARRIER_WRITE(sc) \ 985 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 986 BUS_SPACE_BARRIER_WRITE) 987 988#define WPI_BARRIER_READ_WRITE(sc) \ 989 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 990 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 991