if_wl.h revision 274758
1327952Sdim/*- 2259701Sdim * Redistribution and use in source and binary forms, with or without 3259701Sdim * modification, are permitted provided that the following conditions 4259701Sdim * are met: 5259701Sdim * 1. Redistributions of source code must retain all copyright 6259701Sdim * notices, this list of conditions and the following disclaimer. 7259701Sdim * 2. The names of the authors may not be used to endorse or promote products 8327952Sdim * derived from this software without specific prior written permission 9327952Sdim * 10259701Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 11341825Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 12327952Sdim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 13327952Sdim * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 14259701Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 15259701Sdim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 16259701Sdim * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 17327952Sdim * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 18259701Sdim * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 19327952Sdim * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 20327952Sdim * 21327952Sdim * $FreeBSD: head/sys/dev/wl/if_wl.h 274758 2014-11-20 20:09:18Z jhb $ 22296417Sdim */ 23259701Sdim/* Definitions for WaveLAN driver */ 24259701Sdim 25259701Sdim#ifndef _IF_WL_H 26327952Sdim#define _IF_WL_H 27327952Sdim 28327952Sdim#define STATUS_TRIES 15000 29327952Sdim 30276479Sdim#define N_FD 100 31327952Sdim#define N_RBD 100 32276479Sdim#define N_TBD 72 33327952Sdim#define RCVBUFSIZE 540 34259701Sdim#define I82586NULL 0xffff 35276479Sdim 36276479Sdim#define DSF_RUNNING 1 37259701Sdim 38259701Sdim#define MOD_ENAL 1 39259701Sdim#define MOD_PROM 2 40327952Sdim 41259701Sdimtypedef struct { 42259701Sdim rbd_t r; 43276479Sdim char rbd_pad[2]; 44259701Sdim char rbuffer[RCVBUFSIZE]; 45327952Sdim} ru_t; 46327952Sdim 47259701Sdim/* Board 64k RAM layout. Offsets from 0x0000 */ 48259701Sdim 49259701Sdim#define OFFSET_RU 0x0000 /* 0x64 * fd_t = 0x898 */ 50259701Sdim#define OFFSET_RBD 0x0900 /* 0x64 * ru_t = 0xd7a0 */ 51259701Sdim#define OFFSET_CU 0xe0a0 /* 0x100 */ 52259701Sdim#define OFFSET_TBD 0xe1a0 /* 0x48 * tbd_t = 0x240 */ 53259701Sdim#define OFFSET_TBUF 0xe3e0 /* 0x1bfe */ 54259701Sdim#define OFFSET_SCB 0xffde /* 0x1 * scb_t = 0x10 */ 55314564Sdim#define OFFSET_ISCP 0xffee /* 0x1 * iscp_t = 0x8 */ 56314564Sdim#define OFFSET_SCP 0xfff6 /* 0x1 * scp_t = 0xa */ 57314564Sdim 58259701Sdim/* WaveLAN host interface definitions */ 59259701Sdim 60259701Sdim#define HACR 0x0 /* Host Adapter Command Register */ 61327952Sdim#define HASR 0x0 /* Host Adapter Status Register */ 62327952Sdim#define MMCR 0x2 /* Modem Management Ctrl Register */ 63314564Sdim#define PIOR0 0x4 /* Program I/O Address Register 0 */ 64314564Sdim#define PIOP0 0x6 /* Program I/O Port 0 */ 65259701Sdim#define PIOR1 0x8 /* Program I/O Address Register 1 */ 66314564Sdim#define PIOP1 0xa /* Program I/O Port 1 */ 67259701Sdim#define PIOR2 0xc /* Program I/O Address Register 2 */ 68259701Sdim#define PIOP2 0xe /* Program I/O Port 2 */ 69259701Sdim 70259701Sdim/* Program I/O Mode Register values */ 71259701Sdim 72259701Sdim#define STATIC_PIO 0 /* Mode 1: static mode */ 73321369Sdim#define AUTOINCR_PIO 1 /* Mode 2: auto increment mode */ 74321369Sdim#define AUTODECR_PIO 2 /* Mode 3: auto decrement mode */ 75321369Sdim#define PARAM_ACCESS_PIO 3 /* Mode 4: LAN parameter access mode */ 76321369Sdim#define PIO_MASK 3 /* register mask */ 77259701Sdim#define PIOM(cmd,piono) ((u_short)cmd << 10 << (piono * 2)) 78314564Sdim 79259701Sdim/* Host Adapter status register definitions */ 80259701Sdim 81321369Sdim#define HASR_INTR 0x0001 /* Interrupt request from 82586 */ 82321369Sdim#define HASR_MMC_INTR 0x0002 /* Interrupt request from MMC */ 83321369Sdim#define HASR_MMC_BUSY 0x0004 /* MMC busy indication */ 84321369Sdim#define HASR_PARA_BUSY 0x0008 /* LAN parameter storage area busy */ 85259701Sdim 86259701Sdim/* Host Adapter command register definitions */ 87321369Sdim 88321369Sdim#define HACR_RESET 0x0001 /* Reset board */ 89321369Sdim#define HACR_CA 0x0002 /* Set Channel Attention for 82586 */ 90321369Sdim#define HACR_16BITS 0x0004 /* 1==16 bits operation, 0==8 bits */ 91327952Sdim#define HACR_OUT1 0x0008 /* General purpose output pin */ 92259701Sdim#define HACR_OUT2 0x0010 /* General purpose output pin */ 93341825Sdim#define HACR_MASK_82586 0x0020 /* Mask 82586 interrupts, 1==unmask */ 94259701Sdim#define HACR_MASK_MMC 0x0040 /* Mask MMC interrupts, 1==unmask */ 95259701Sdim#define HACR_INTR_CLEN 0x0080 /* interrupt status clear enable */ 96259701Sdim 97259701Sdim#define HACR_DEFAULT (HACR_OUT1 | HACR_OUT2 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2)) 98259701Sdim#define HACR_INTRON (HACR_MASK_82586 | HACR_MASK_MMC | HACR_INTR_CLEN) 99259701Sdim 100259701Sdim#define WL_READ_1(sc, reg) bus_read_1((sc)->res_ioport, (reg)) 101259701Sdim#define WL_READ_2(sc, reg) bus_read_2((sc)->res_ioport, (reg)) 102259701Sdim#define WL_READ_MULTI_2(sc, reg, buf, len) \ 103259701Sdim bus_read_multi_2((sc)->res_ioport, (reg), (uint16_t *)(buf), (len)) 104259701Sdim#define WL_WRITE_1(sc, reg, val) \ 105259701Sdim bus_write_1((sc)->res_ioport, (reg), (val)) 106259701Sdim#define WL_WRITE_2(sc, reg, val) \ 107259701Sdim bus_write_2((sc)->res_ioport, (reg), (val)) 108259701Sdim#define WL_WRITE_MULTI_2(sc, reg, buf, len) \ 109259701Sdim bus_write_multi_2((sc)->res_ioport, (reg), (uint16_t *)(buf), (len)) 110259701Sdim 111276479Sdim#define CMD(sc) \ 112259701Sdim { \ 113259701Sdim WL_WRITE_2(sc, HACR, sc->hacr); \ 114259701Sdim /* delay for 50 us, might only be needed sometimes */ \ 115259701Sdim DELAY(DELAYCONST); \ 116321369Sdim } 117321369Sdim 118321369Sdim/* macro for setting the channel attention bit. No delays here since 119321369Sdim * it is used in critical sections 120321369Sdim */ 121321369Sdim#define SET_CHAN_ATTN(sc) \ 122321369Sdim { \ 123259701Sdim WL_WRITE_2(sc, HACR, sc->hacr | HACR_CA); \ 124309124Sdim } 125259701Sdim 126259701Sdim 127259701Sdim#define MMC_WRITE(cmd,val) \ 128259701Sdim while (WL_READ_2(sc, HASR) & HASR_MMC_BUSY) ; \ 129259701Sdim WL_WRITE_2(sc, MMCR, \ 130259701Sdim (u_short)(((u_short)(val) << 8) | ((cmd) << 1) | 1)) 131259701Sdim 132280031Sdim#endif /* _IF_WL_H */ 133259701Sdim 134309124Sdim