if_wl.h revision 26003 
1/*
2 * Redistribution and use in source and binary forms, with or without
3 * modification, are permitted provided that the following conditions
4 * are met:
5 * 1. Redistributions of source code must retain all copyright
6 *    notices, this list of conditions and the following disclaimer.
7 * 2. The names of the authors may not be used to endorse or promote products
8 *    derived from this software withough specific prior written permission
9 *
10 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
13 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
16 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
17 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 */
22/* Definitions for WaveLAN driver */
23
24#ifndef	_IF_WL_H
25#define _IF_WL_H
26
27#define	STATUS_TRIES	15000
28
29#define N_FD			100
30#define N_RBD			100
31#define N_TBD			72
32#define RCVBUFSIZE		540
33#define I82586NULL		0xffff
34
35#define DSF_RUNNING	1
36
37#define MOD_ENAL 1
38#define MOD_PROM 2
39
40typedef struct {
41	rbd_t	r;
42	char	rbd_pad[2];
43	char	rbuffer[RCVBUFSIZE];
44} ru_t;
45
46/* Board 64k RAM layout. Offsets from 0x0000 */
47
48#define OFFSET_RU		0x0000		/* 0x64 * fd_t = 0x898 */
49#define OFFSET_RBD		0x0900		/* 0x64 * ru_t = 0xd7a0 */
50#define OFFSET_CU		0xe0a0		/* 0x100 */
51#define OFFSET_TBD		0xe1a0		/* 0x48 * tbd_t = 0x240 */
52#define OFFSET_TBUF		0xe3e0		/* 0x1bfe */
53#define OFFSET_SCB		0xffde		/* 0x1 * scb_t = 0x10 */
54#define OFFSET_ISCP		0xffee		/* 0x1 * iscp_t = 0x8 */
55#define OFFSET_SCP		0xfff6		/* 0x1 * scp_t = 0xa */
56
57/* WaveLAN host interface definitions */
58
59#define HACR(base)	(base)		/* Host Adapter Command Register */
60#define HASR(base)	(base)		/* Host Adapter Status Register */
61#define MMCR(base)	(base+0x2)	/* Modem Management Ctrl Register */
62#define PIOR0(base)	(base+0x4)	/* Program I/O Address Register 0 */
63#define PIOP0(base)	(base+0x6)	/* Program I/O Port 0 */
64#define PIOR1(base)	(base+0x8)	/* Program I/O Address Register 1 */
65#define PIOP1(base)	(base+0xa)	/* Program I/O Port 1 */
66#define PIOR2(base)	(base+0xc)	/* Program I/O Address Register 2 */
67#define PIOP2(base)	(base+0xe)	/* Program I/O Port 2 */
68
69/* Program I/O Mode Register values */
70
71#define STATIC_PIO		0	/* Mode 1: static mode */
72#define AUTOINCR_PIO		1	/* Mode 2: auto increment mode */
73#define AUTODECR_PIO		2	/* Mode 3: auto decrement mode */
74#define PARAM_ACCESS_PIO	3	/* Mode 4: LAN parameter access mode */
75#define PIO_MASK		3	/* register mask */
76#define PIOM(cmd,piono)		((u_short)cmd << 10 << (piono * 2))
77
78/* Host Adapter status register definitions */
79
80#define HASR_INTR		0x0001	/* Interrupt request from 82586 */
81#define HASR_MMC_INTR		0x0002	/* Interrupt request from MMC */
82#define HASR_MMC_BUSY		0x0004	/* MMC busy indication */
83#define HASR_PARA_BUSY		0x0008	/* LAN parameter storage area busy */
84
85/* Host Adapter command register definitions */
86
87#define HACR_RESET		0x0001	/* Reset board */
88#define HACR_CA			0x0002	/* Set Channel Attention for 82586 */
89#define HACR_16BITS		0x0004	/* 1==16 bits operation, 0==8 bits */
90#define HACR_OUT1		0x0008	/* General purpose output pin */
91#define HACR_OUT2		0x0010	/* General purpose output pin */
92#define HACR_MASK_82586		0x0020	/* Mask 82586 interrupts, 1==unmask */
93#define HACR_MASK_MMC		0x0040	/* Mask MMC interrupts, 1==unmask */
94#define HACR_INTR_CLEN		0x0080	/* interrupt status clear enable */
95
96#define HACR_DEFAULT	(HACR_OUT1 | HACR_OUT2 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2))
97#define HACR_INTRON	(HACR_MASK_82586 | HACR_MASK_MMC | HACR_INTR_CLEN)
98#define CMD(unit)	\
99		{ \
100		   outw(HACR(WLSOFTC(unit)->base),WLSOFTC(unit)->hacr); \
101		   /* delay for 50 us, might only be needed sometimes */ \
102		   DELAY(DELAYCONST); \
103	        }
104
105/* macro for setting the channel attention bit.  No delays here since
106 * it is used in critical sections
107 */
108#define SET_CHAN_ATTN(unit)   \
109      { \
110         outw(HACR(WLSOFTC(unit)->base),WLSOFTC(unit)->hacr | HACR_CA); \
111      }
112
113
114#define MMC_WRITE(cmd,val)	\
115	while(inw(HASR(WLSOFTC(unit)->base)) & HASR_MMC_BUSY) ; \
116	outw(MMCR(WLSOFTC(unit)->base), \
117	     (u_short)(((u_short)(val) << 8) | ((cmd) << 1) | 1))
118
119#endif	_IF_WL_H
120
121