if_wb.c revision 347962
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/dev/wb/if_wb.c 347962 2019-05-18 20:43:13Z brooks $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/module.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94#include <sys/queue.h> 95 96#include <net/if.h> 97#include <net/if_var.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#include <dev/mii/mii.h> 117#include <dev/mii/mii_bitbang.h> 118#include <dev/mii/miivar.h> 119 120/* "device miibus" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <dev/wb/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static const struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe(device_t); 143static int wb_attach(device_t); 144static int wb_detach(device_t); 145 146static void wb_bfree(struct mbuf *, void *addr, void *args); 147static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 148 struct mbuf *); 149static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 150 151static void wb_rxeof(struct wb_softc *); 152static void wb_rxeoc(struct wb_softc *); 153static void wb_txeof(struct wb_softc *); 154static void wb_txeoc(struct wb_softc *); 155static void wb_intr(void *); 156static void wb_tick(void *); 157static void wb_start(struct ifnet *); 158static void wb_start_locked(struct ifnet *); 159static int wb_ioctl(struct ifnet *, u_long, caddr_t); 160static void wb_init(void *); 161static void wb_init_locked(struct wb_softc *); 162static void wb_stop(struct wb_softc *); 163static void wb_watchdog(struct wb_softc *); 164static int wb_shutdown(device_t); 165static int wb_ifmedia_upd(struct ifnet *); 166static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 167 168static void wb_eeprom_putbyte(struct wb_softc *, int); 169static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 170static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 171 172static void wb_setcfg(struct wb_softc *, u_int32_t); 173static void wb_setmulti(struct wb_softc *); 174static void wb_reset(struct wb_softc *); 175static void wb_fixmedia(struct wb_softc *); 176static int wb_list_rx_init(struct wb_softc *); 177static int wb_list_tx_init(struct wb_softc *); 178 179static int wb_miibus_readreg(device_t, int, int); 180static int wb_miibus_writereg(device_t, int, int, int); 181static void wb_miibus_statchg(device_t); 182 183/* 184 * MII bit-bang glue 185 */ 186static uint32_t wb_mii_bitbang_read(device_t); 187static void wb_mii_bitbang_write(device_t, uint32_t); 188 189static const struct mii_bitbang_ops wb_mii_bitbang_ops = { 190 wb_mii_bitbang_read, 191 wb_mii_bitbang_write, 192 { 193 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 194 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */ 195 WB_SIO_MII_CLK, /* MII_BIT_MDC */ 196 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 197 0, /* MII_BIT_DIR_PHY_HOST */ 198 } 199}; 200 201#ifdef WB_USEIOSPACE 202#define WB_RES SYS_RES_IOPORT 203#define WB_RID WB_PCI_LOIO 204#else 205#define WB_RES SYS_RES_MEMORY 206#define WB_RID WB_PCI_LOMEM 207#endif 208 209static device_method_t wb_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, wb_probe), 212 DEVMETHOD(device_attach, wb_attach), 213 DEVMETHOD(device_detach, wb_detach), 214 DEVMETHOD(device_shutdown, wb_shutdown), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 218 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 219 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 220 221 DEVMETHOD_END 222}; 223 224static driver_t wb_driver = { 225 "wb", 226 wb_methods, 227 sizeof(struct wb_softc) 228}; 229 230static devclass_t wb_devclass; 231 232DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 233DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 234 235#define WB_SETBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, \ 237 CSR_READ_4(sc, reg) | (x)) 238 239#define WB_CLRBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, \ 241 CSR_READ_4(sc, reg) & ~(x)) 242 243#define SIO_SET(x) \ 244 CSR_WRITE_4(sc, WB_SIO, \ 245 CSR_READ_4(sc, WB_SIO) | (x)) 246 247#define SIO_CLR(x) \ 248 CSR_WRITE_4(sc, WB_SIO, \ 249 CSR_READ_4(sc, WB_SIO) & ~(x)) 250 251/* 252 * Send a read command and address to the EEPROM, check for ACK. 253 */ 254static void 255wb_eeprom_putbyte(sc, addr) 256 struct wb_softc *sc; 257 int addr; 258{ 259 int d, i; 260 261 d = addr | WB_EECMD_READ; 262 263 /* 264 * Feed in each bit and stobe the clock. 265 */ 266 for (i = 0x400; i; i >>= 1) { 267 if (d & i) { 268 SIO_SET(WB_SIO_EE_DATAIN); 269 } else { 270 SIO_CLR(WB_SIO_EE_DATAIN); 271 } 272 DELAY(100); 273 SIO_SET(WB_SIO_EE_CLK); 274 DELAY(150); 275 SIO_CLR(WB_SIO_EE_CLK); 276 DELAY(100); 277 } 278} 279 280/* 281 * Read a word of data stored in the EEPROM at address 'addr.' 282 */ 283static void 284wb_eeprom_getword(sc, addr, dest) 285 struct wb_softc *sc; 286 int addr; 287 u_int16_t *dest; 288{ 289 int i; 290 u_int16_t word = 0; 291 292 /* Enter EEPROM access mode. */ 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Send address of word we want to read. 297 */ 298 wb_eeprom_putbyte(sc, addr); 299 300 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 301 302 /* 303 * Start reading bits from EEPROM. 304 */ 305 for (i = 0x8000; i; i >>= 1) { 306 SIO_SET(WB_SIO_EE_CLK); 307 DELAY(100); 308 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 309 word |= i; 310 SIO_CLR(WB_SIO_EE_CLK); 311 DELAY(100); 312 } 313 314 /* Turn off EEPROM access mode. */ 315 CSR_WRITE_4(sc, WB_SIO, 0); 316 317 *dest = word; 318} 319 320/* 321 * Read a sequence of words from the EEPROM. 322 */ 323static void 324wb_read_eeprom(sc, dest, off, cnt, swap) 325 struct wb_softc *sc; 326 caddr_t dest; 327 int off; 328 int cnt; 329 int swap; 330{ 331 int i; 332 u_int16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 wb_eeprom_getword(sc, off + i, &word); 336 ptr = (u_int16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342} 343 344/* 345 * Read the MII serial port for the MII bit-bang module. 346 */ 347static uint32_t 348wb_mii_bitbang_read(device_t dev) 349{ 350 struct wb_softc *sc; 351 uint32_t val; 352 353 sc = device_get_softc(dev); 354 355 val = CSR_READ_4(sc, WB_SIO); 356 CSR_BARRIER(sc, WB_SIO, 4, 357 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 358 359 return (val); 360} 361 362/* 363 * Write the MII serial port for the MII bit-bang module. 364 */ 365static void 366wb_mii_bitbang_write(device_t dev, uint32_t val) 367{ 368 struct wb_softc *sc; 369 370 sc = device_get_softc(dev); 371 372 CSR_WRITE_4(sc, WB_SIO, val); 373 CSR_BARRIER(sc, WB_SIO, 4, 374 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 375} 376 377static int 378wb_miibus_readreg(dev, phy, reg) 379 device_t dev; 380 int phy, reg; 381{ 382 383 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg)); 384} 385 386static int 387wb_miibus_writereg(dev, phy, reg, data) 388 device_t dev; 389 int phy, reg, data; 390{ 391 392 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data); 393 394 return(0); 395} 396 397static void 398wb_miibus_statchg(dev) 399 device_t dev; 400{ 401 struct wb_softc *sc; 402 struct mii_data *mii; 403 404 sc = device_get_softc(dev); 405 mii = device_get_softc(sc->wb_miibus); 406 wb_setcfg(sc, mii->mii_media_active); 407} 408 409/* 410 * Program the 64-bit multicast hash filter. 411 */ 412static void 413wb_setmulti(sc) 414 struct wb_softc *sc; 415{ 416 struct ifnet *ifp; 417 int h = 0; 418 u_int32_t hashes[2] = { 0, 0 }; 419 struct ifmultiaddr *ifma; 420 u_int32_t rxfilt; 421 int mcnt = 0; 422 423 ifp = sc->wb_ifp; 424 425 rxfilt = CSR_READ_4(sc, WB_NETCFG); 426 427 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 428 rxfilt |= WB_NETCFG_RX_MULTI; 429 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 430 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 431 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 432 return; 433 } 434 435 /* first, zot all the existing hash bits */ 436 CSR_WRITE_4(sc, WB_MAR0, 0); 437 CSR_WRITE_4(sc, WB_MAR1, 0); 438 439 /* now program new ones */ 440 if_maddr_rlock(ifp); 441 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 442 if (ifma->ifma_addr->sa_family != AF_LINK) 443 continue; 444 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 445 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 446 if (h < 32) 447 hashes[0] |= (1 << h); 448 else 449 hashes[1] |= (1 << (h - 32)); 450 mcnt++; 451 } 452 if_maddr_runlock(ifp); 453 454 if (mcnt) 455 rxfilt |= WB_NETCFG_RX_MULTI; 456 else 457 rxfilt &= ~WB_NETCFG_RX_MULTI; 458 459 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 460 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 461 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 462} 463 464/* 465 * The Winbond manual states that in order to fiddle with the 466 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 467 * first have to put the transmit and/or receive logic in the idle state. 468 */ 469static void 470wb_setcfg(sc, media) 471 struct wb_softc *sc; 472 u_int32_t media; 473{ 474 int i, restart = 0; 475 476 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 477 restart = 1; 478 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 479 480 for (i = 0; i < WB_TIMEOUT; i++) { 481 DELAY(10); 482 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 483 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 484 break; 485 } 486 487 if (i == WB_TIMEOUT) 488 device_printf(sc->wb_dev, 489 "failed to force tx and rx to idle state\n"); 490 } 491 492 if (IFM_SUBTYPE(media) == IFM_10_T) 493 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 494 else 495 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 496 497 if ((media & IFM_GMASK) == IFM_FDX) 498 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 499 else 500 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 501 502 if (restart) 503 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 504} 505 506static void 507wb_reset(sc) 508 struct wb_softc *sc; 509{ 510 int i; 511 struct mii_data *mii; 512 struct mii_softc *miisc; 513 514 CSR_WRITE_4(sc, WB_NETCFG, 0); 515 CSR_WRITE_4(sc, WB_BUSCTL, 0); 516 CSR_WRITE_4(sc, WB_TXADDR, 0); 517 CSR_WRITE_4(sc, WB_RXADDR, 0); 518 519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 520 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 521 522 for (i = 0; i < WB_TIMEOUT; i++) { 523 DELAY(10); 524 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 525 break; 526 } 527 if (i == WB_TIMEOUT) 528 device_printf(sc->wb_dev, "reset never completed!\n"); 529 530 /* Wait a little while for the chip to get its brains in order. */ 531 DELAY(1000); 532 533 if (sc->wb_miibus == NULL) 534 return; 535 536 mii = device_get_softc(sc->wb_miibus); 537 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 538 PHY_RESET(miisc); 539} 540 541static void 542wb_fixmedia(sc) 543 struct wb_softc *sc; 544{ 545 struct mii_data *mii = NULL; 546 struct ifnet *ifp; 547 u_int32_t media; 548 549 mii = device_get_softc(sc->wb_miibus); 550 ifp = sc->wb_ifp; 551 552 mii_pollstat(mii); 553 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 554 media = mii->mii_media_active & ~IFM_10_T; 555 media |= IFM_100_TX; 556 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 557 media = mii->mii_media_active & ~IFM_100_TX; 558 media |= IFM_10_T; 559 } else 560 return; 561 562 ifmedia_set(&mii->mii_media, media); 563} 564 565/* 566 * Probe for a Winbond chip. Check the PCI vendor and device 567 * IDs against our list and return a device name if we find a match. 568 */ 569static int 570wb_probe(dev) 571 device_t dev; 572{ 573 const struct wb_type *t; 574 575 t = wb_devs; 576 577 while(t->wb_name != NULL) { 578 if ((pci_get_vendor(dev) == t->wb_vid) && 579 (pci_get_device(dev) == t->wb_did)) { 580 device_set_desc(dev, t->wb_name); 581 return (BUS_PROBE_DEFAULT); 582 } 583 t++; 584 } 585 586 return(ENXIO); 587} 588 589/* 590 * Attach the interface. Allocate softc structures, do ifmedia 591 * setup and ethernet/BPF attach. 592 */ 593static int 594wb_attach(dev) 595 device_t dev; 596{ 597 u_char eaddr[ETHER_ADDR_LEN]; 598 struct wb_softc *sc; 599 struct ifnet *ifp; 600 int error = 0, rid; 601 602 sc = device_get_softc(dev); 603 sc->wb_dev = dev; 604 605 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 606 MTX_DEF); 607 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 608 609 /* 610 * Map control/status registers. 611 */ 612 pci_enable_busmaster(dev); 613 614 rid = WB_RID; 615 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 616 617 if (sc->wb_res == NULL) { 618 device_printf(dev, "couldn't map ports/memory\n"); 619 error = ENXIO; 620 goto fail; 621 } 622 623 /* Allocate interrupt */ 624 rid = 0; 625 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 626 RF_SHAREABLE | RF_ACTIVE); 627 628 if (sc->wb_irq == NULL) { 629 device_printf(dev, "couldn't map interrupt\n"); 630 error = ENXIO; 631 goto fail; 632 } 633 634 /* Save the cache line size. */ 635 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 636 637 /* Reset the adapter. */ 638 wb_reset(sc); 639 640 /* 641 * Get station address from the EEPROM. 642 */ 643 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 644 645 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 646 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 647 648 if (sc->wb_ldata == NULL) { 649 device_printf(dev, "no memory for list buffers!\n"); 650 error = ENXIO; 651 goto fail; 652 } 653 654 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 655 656 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 657 if (ifp == NULL) { 658 device_printf(dev, "can not if_alloc()\n"); 659 error = ENOSPC; 660 goto fail; 661 } 662 ifp->if_softc = sc; 663 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 664 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 665 ifp->if_ioctl = wb_ioctl; 666 ifp->if_start = wb_start; 667 ifp->if_init = wb_init; 668 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 669 670 /* 671 * Do MII setup. 672 */ 673 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 674 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 675 if (error != 0) { 676 device_printf(dev, "attaching PHYs failed\n"); 677 goto fail; 678 } 679 680 /* 681 * Call MI attach routine. 682 */ 683 ether_ifattach(ifp, eaddr); 684 685 /* Hook interrupt last to avoid having to lock softc */ 686 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 687 NULL, wb_intr, sc, &sc->wb_intrhand); 688 689 if (error) { 690 device_printf(dev, "couldn't set up irq\n"); 691 ether_ifdetach(ifp); 692 goto fail; 693 } 694 695 gone_by_fcp101_dev(dev); 696 697fail: 698 if (error) 699 wb_detach(dev); 700 701 return(error); 702} 703 704/* 705 * Shutdown hardware and free up resources. This can be called any 706 * time after the mutex has been initialized. It is called in both 707 * the error case in attach and the normal detach case so it needs 708 * to be careful about only freeing resources that have actually been 709 * allocated. 710 */ 711static int 712wb_detach(dev) 713 device_t dev; 714{ 715 struct wb_softc *sc; 716 struct ifnet *ifp; 717 718 sc = device_get_softc(dev); 719 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 720 ifp = sc->wb_ifp; 721 722 /* 723 * Delete any miibus and phy devices attached to this interface. 724 * This should only be done if attach succeeded. 725 */ 726 if (device_is_attached(dev)) { 727 ether_ifdetach(ifp); 728 WB_LOCK(sc); 729 wb_stop(sc); 730 WB_UNLOCK(sc); 731 callout_drain(&sc->wb_stat_callout); 732 } 733 if (sc->wb_miibus) 734 device_delete_child(dev, sc->wb_miibus); 735 bus_generic_detach(dev); 736 737 if (sc->wb_intrhand) 738 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 739 if (sc->wb_irq) 740 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 741 if (sc->wb_res) 742 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 743 744 if (ifp) 745 if_free(ifp); 746 747 if (sc->wb_ldata) { 748 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 749 M_DEVBUF); 750 } 751 752 mtx_destroy(&sc->wb_mtx); 753 754 return(0); 755} 756 757/* 758 * Initialize the transmit descriptors. 759 */ 760static int 761wb_list_tx_init(sc) 762 struct wb_softc *sc; 763{ 764 struct wb_chain_data *cd; 765 struct wb_list_data *ld; 766 int i; 767 768 cd = &sc->wb_cdata; 769 ld = sc->wb_ldata; 770 771 for (i = 0; i < WB_TX_LIST_CNT; i++) { 772 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 773 if (i == (WB_TX_LIST_CNT - 1)) { 774 cd->wb_tx_chain[i].wb_nextdesc = 775 &cd->wb_tx_chain[0]; 776 } else { 777 cd->wb_tx_chain[i].wb_nextdesc = 778 &cd->wb_tx_chain[i + 1]; 779 } 780 } 781 782 cd->wb_tx_free = &cd->wb_tx_chain[0]; 783 cd->wb_tx_tail = cd->wb_tx_head = NULL; 784 785 return(0); 786} 787 788 789/* 790 * Initialize the RX descriptors and allocate mbufs for them. Note that 791 * we arrange the descriptors in a closed ring, so that the last descriptor 792 * points back to the first. 793 */ 794static int 795wb_list_rx_init(sc) 796 struct wb_softc *sc; 797{ 798 struct wb_chain_data *cd; 799 struct wb_list_data *ld; 800 int i; 801 802 cd = &sc->wb_cdata; 803 ld = sc->wb_ldata; 804 805 for (i = 0; i < WB_RX_LIST_CNT; i++) { 806 cd->wb_rx_chain[i].wb_ptr = 807 (struct wb_desc *)&ld->wb_rx_list[i]; 808 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 809 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 810 return(ENOBUFS); 811 if (i == (WB_RX_LIST_CNT - 1)) { 812 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 813 ld->wb_rx_list[i].wb_next = 814 vtophys(&ld->wb_rx_list[0]); 815 } else { 816 cd->wb_rx_chain[i].wb_nextdesc = 817 &cd->wb_rx_chain[i + 1]; 818 ld->wb_rx_list[i].wb_next = 819 vtophys(&ld->wb_rx_list[i + 1]); 820 } 821 } 822 823 cd->wb_rx_head = &cd->wb_rx_chain[0]; 824 825 return(0); 826} 827 828static void 829wb_bfree(struct mbuf *m, void *buf, void *args) 830{ 831} 832 833/* 834 * Initialize an RX descriptor and attach an MBUF cluster. 835 */ 836static int 837wb_newbuf(sc, c, m) 838 struct wb_softc *sc; 839 struct wb_chain_onefrag *c; 840 struct mbuf *m; 841{ 842 struct mbuf *m_new = NULL; 843 844 if (m == NULL) { 845 MGETHDR(m_new, M_NOWAIT, MT_DATA); 846 if (m_new == NULL) 847 return(ENOBUFS); 848 m_new->m_data = c->wb_buf; 849 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 850 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 851 NULL, 0, EXT_NET_DRV); 852 } else { 853 m_new = m; 854 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 855 m_new->m_data = m_new->m_ext.ext_buf; 856 } 857 858 m_adj(m_new, sizeof(u_int64_t)); 859 860 c->wb_mbuf = m_new; 861 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 862 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 863 c->wb_ptr->wb_status = WB_RXSTAT; 864 865 return(0); 866} 867 868/* 869 * A frame has been uploaded: pass the resulting mbuf chain up to 870 * the higher level protocols. 871 */ 872static void 873wb_rxeof(sc) 874 struct wb_softc *sc; 875{ 876 struct mbuf *m = NULL; 877 struct ifnet *ifp; 878 struct wb_chain_onefrag *cur_rx; 879 int total_len = 0; 880 u_int32_t rxstat; 881 882 WB_LOCK_ASSERT(sc); 883 884 ifp = sc->wb_ifp; 885 886 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 887 WB_RXSTAT_OWN)) { 888 struct mbuf *m0 = NULL; 889 890 cur_rx = sc->wb_cdata.wb_rx_head; 891 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 892 893 m = cur_rx->wb_mbuf; 894 895 if ((rxstat & WB_RXSTAT_MIIERR) || 896 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 897 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 898 !(rxstat & WB_RXSTAT_LASTFRAG) || 899 !(rxstat & WB_RXSTAT_RXCMP)) { 900 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 901 wb_newbuf(sc, cur_rx, m); 902 device_printf(sc->wb_dev, 903 "receiver babbling: possible chip bug," 904 " forcing reset\n"); 905 wb_fixmedia(sc); 906 wb_reset(sc); 907 wb_init_locked(sc); 908 return; 909 } 910 911 if (rxstat & WB_RXSTAT_RXERR) { 912 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 913 wb_newbuf(sc, cur_rx, m); 914 break; 915 } 916 917 /* No errors; receive the packet. */ 918 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 919 920 /* 921 * XXX The Winbond chip includes the CRC with every 922 * received frame, and there's no way to turn this 923 * behavior off (at least, I can't find anything in 924 * the manual that explains how to do it) so we have 925 * to trim off the CRC manually. 926 */ 927 total_len -= ETHER_CRC_LEN; 928 929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 930 NULL); 931 wb_newbuf(sc, cur_rx, m); 932 if (m0 == NULL) { 933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 934 break; 935 } 936 m = m0; 937 938 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 939 WB_UNLOCK(sc); 940 (*ifp->if_input)(ifp, m); 941 WB_LOCK(sc); 942 } 943} 944 945static void 946wb_rxeoc(sc) 947 struct wb_softc *sc; 948{ 949 wb_rxeof(sc); 950 951 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 952 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 953 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 954 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 955 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 956} 957 958/* 959 * A frame was downloaded to the chip. It's safe for us to clean up 960 * the list buffers. 961 */ 962static void 963wb_txeof(sc) 964 struct wb_softc *sc; 965{ 966 struct wb_chain *cur_tx; 967 struct ifnet *ifp; 968 969 ifp = sc->wb_ifp; 970 971 /* Clear the timeout timer. */ 972 sc->wb_timer = 0; 973 974 if (sc->wb_cdata.wb_tx_head == NULL) 975 return; 976 977 /* 978 * Go through our tx list and free mbufs for those 979 * frames that have been transmitted. 980 */ 981 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 982 u_int32_t txstat; 983 984 cur_tx = sc->wb_cdata.wb_tx_head; 985 txstat = WB_TXSTATUS(cur_tx); 986 987 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 988 break; 989 990 if (txstat & WB_TXSTAT_TXERR) { 991 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 992 if (txstat & WB_TXSTAT_ABORT) 993 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 994 if (txstat & WB_TXSTAT_LATECOLL) 995 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 996 } 997 998 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & WB_TXSTAT_COLLCNT) >> 3); 999 1000 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1001 m_freem(cur_tx->wb_mbuf); 1002 cur_tx->wb_mbuf = NULL; 1003 1004 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1005 sc->wb_cdata.wb_tx_head = NULL; 1006 sc->wb_cdata.wb_tx_tail = NULL; 1007 break; 1008 } 1009 1010 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1011 } 1012} 1013 1014/* 1015 * TX 'end of channel' interrupt handler. 1016 */ 1017static void 1018wb_txeoc(sc) 1019 struct wb_softc *sc; 1020{ 1021 struct ifnet *ifp; 1022 1023 ifp = sc->wb_ifp; 1024 1025 sc->wb_timer = 0; 1026 1027 if (sc->wb_cdata.wb_tx_head == NULL) { 1028 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1029 sc->wb_cdata.wb_tx_tail = NULL; 1030 } else { 1031 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1032 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1033 sc->wb_timer = 5; 1034 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1035 } 1036 } 1037} 1038 1039static void 1040wb_intr(arg) 1041 void *arg; 1042{ 1043 struct wb_softc *sc; 1044 struct ifnet *ifp; 1045 u_int32_t status; 1046 1047 sc = arg; 1048 WB_LOCK(sc); 1049 ifp = sc->wb_ifp; 1050 1051 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1052 WB_UNLOCK(sc); 1053 return; 1054 } 1055 1056 /* Disable interrupts. */ 1057 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1058 1059 for (;;) { 1060 1061 status = CSR_READ_4(sc, WB_ISR); 1062 if (status) 1063 CSR_WRITE_4(sc, WB_ISR, status); 1064 1065 if ((status & WB_INTRS) == 0) 1066 break; 1067 1068 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1069 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1070 wb_reset(sc); 1071 if (status & WB_ISR_RX_ERR) 1072 wb_fixmedia(sc); 1073 wb_init_locked(sc); 1074 continue; 1075 } 1076 1077 if (status & WB_ISR_RX_OK) 1078 wb_rxeof(sc); 1079 1080 if (status & WB_ISR_RX_IDLE) 1081 wb_rxeoc(sc); 1082 1083 if (status & WB_ISR_TX_OK) 1084 wb_txeof(sc); 1085 1086 if (status & WB_ISR_TX_NOBUF) 1087 wb_txeoc(sc); 1088 1089 if (status & WB_ISR_TX_IDLE) { 1090 wb_txeof(sc); 1091 if (sc->wb_cdata.wb_tx_head != NULL) { 1092 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1093 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1094 } 1095 } 1096 1097 if (status & WB_ISR_TX_UNDERRUN) { 1098 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1099 wb_txeof(sc); 1100 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1101 /* Jack up TX threshold */ 1102 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1103 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1104 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1105 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1106 } 1107 1108 if (status & WB_ISR_BUS_ERR) { 1109 wb_reset(sc); 1110 wb_init_locked(sc); 1111 } 1112 1113 } 1114 1115 /* Re-enable interrupts. */ 1116 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1117 1118 if (ifp->if_snd.ifq_head != NULL) { 1119 wb_start_locked(ifp); 1120 } 1121 1122 WB_UNLOCK(sc); 1123} 1124 1125static void 1126wb_tick(xsc) 1127 void *xsc; 1128{ 1129 struct wb_softc *sc; 1130 struct mii_data *mii; 1131 1132 sc = xsc; 1133 WB_LOCK_ASSERT(sc); 1134 mii = device_get_softc(sc->wb_miibus); 1135 1136 mii_tick(mii); 1137 1138 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1139 wb_watchdog(sc); 1140 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1141} 1142 1143/* 1144 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1145 * pointers to the fragment pointers. 1146 */ 1147static int 1148wb_encap(sc, c, m_head) 1149 struct wb_softc *sc; 1150 struct wb_chain *c; 1151 struct mbuf *m_head; 1152{ 1153 int frag = 0; 1154 struct wb_desc *f = NULL; 1155 int total_len; 1156 struct mbuf *m; 1157 1158 /* 1159 * Start packing the mbufs in this chain into 1160 * the fragment pointers. Stop when we run out 1161 * of fragments or hit the end of the mbuf chain. 1162 */ 1163 m = m_head; 1164 total_len = 0; 1165 1166 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1167 if (m->m_len != 0) { 1168 if (frag == WB_MAXFRAGS) 1169 break; 1170 total_len += m->m_len; 1171 f = &c->wb_ptr->wb_frag[frag]; 1172 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1173 if (frag == 0) { 1174 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1175 f->wb_status = 0; 1176 } else 1177 f->wb_status = WB_TXSTAT_OWN; 1178 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1179 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1180 frag++; 1181 } 1182 } 1183 1184 /* 1185 * Handle special case: we used up all 16 fragments, 1186 * but we have more mbufs left in the chain. Copy the 1187 * data into an mbuf cluster. Note that we don't 1188 * bother clearing the values in the other fragment 1189 * pointers/counters; it wouldn't gain us anything, 1190 * and would waste cycles. 1191 */ 1192 if (m != NULL) { 1193 struct mbuf *m_new = NULL; 1194 1195 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1196 if (m_new == NULL) 1197 return(1); 1198 if (m_head->m_pkthdr.len > MHLEN) { 1199 if (!(MCLGET(m_new, M_NOWAIT))) { 1200 m_freem(m_new); 1201 return(1); 1202 } 1203 } 1204 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1205 mtod(m_new, caddr_t)); 1206 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1207 m_freem(m_head); 1208 m_head = m_new; 1209 f = &c->wb_ptr->wb_frag[0]; 1210 f->wb_status = 0; 1211 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1212 f->wb_ctl = total_len = m_new->m_len; 1213 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1214 frag = 1; 1215 } 1216 1217 if (total_len < WB_MIN_FRAMELEN) { 1218 f = &c->wb_ptr->wb_frag[frag]; 1219 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1220 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1221 f->wb_ctl |= WB_TXCTL_TLINK; 1222 f->wb_status = WB_TXSTAT_OWN; 1223 frag++; 1224 } 1225 1226 c->wb_mbuf = m_head; 1227 c->wb_lastdesc = frag - 1; 1228 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1229 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1230 1231 return(0); 1232} 1233 1234/* 1235 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1236 * to the mbuf data regions directly in the transmit lists. We also save a 1237 * copy of the pointers since the transmit list fragment pointers are 1238 * physical addresses. 1239 */ 1240 1241static void 1242wb_start(ifp) 1243 struct ifnet *ifp; 1244{ 1245 struct wb_softc *sc; 1246 1247 sc = ifp->if_softc; 1248 WB_LOCK(sc); 1249 wb_start_locked(ifp); 1250 WB_UNLOCK(sc); 1251} 1252 1253static void 1254wb_start_locked(ifp) 1255 struct ifnet *ifp; 1256{ 1257 struct wb_softc *sc; 1258 struct mbuf *m_head = NULL; 1259 struct wb_chain *cur_tx = NULL, *start_tx; 1260 1261 sc = ifp->if_softc; 1262 WB_LOCK_ASSERT(sc); 1263 1264 /* 1265 * Check for an available queue slot. If there are none, 1266 * punt. 1267 */ 1268 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1269 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1270 return; 1271 } 1272 1273 start_tx = sc->wb_cdata.wb_tx_free; 1274 1275 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1276 IF_DEQUEUE(&ifp->if_snd, m_head); 1277 if (m_head == NULL) 1278 break; 1279 1280 /* Pick a descriptor off the free list. */ 1281 cur_tx = sc->wb_cdata.wb_tx_free; 1282 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1283 1284 /* Pack the data into the descriptor. */ 1285 wb_encap(sc, cur_tx, m_head); 1286 1287 if (cur_tx != start_tx) 1288 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1289 1290 /* 1291 * If there's a BPF listener, bounce a copy of this frame 1292 * to him. 1293 */ 1294 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1295 } 1296 1297 /* 1298 * If there are no packets queued, bail. 1299 */ 1300 if (cur_tx == NULL) 1301 return; 1302 1303 /* 1304 * Place the request for the upload interrupt 1305 * in the last descriptor in the chain. This way, if 1306 * we're chaining several packets at once, we'll only 1307 * get an interrupt once for the whole chain rather than 1308 * once for each packet. 1309 */ 1310 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1311 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1312 sc->wb_cdata.wb_tx_tail = cur_tx; 1313 1314 if (sc->wb_cdata.wb_tx_head == NULL) { 1315 sc->wb_cdata.wb_tx_head = start_tx; 1316 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1317 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1318 } else { 1319 /* 1320 * We need to distinguish between the case where 1321 * the own bit is clear because the chip cleared it 1322 * and where the own bit is clear because we haven't 1323 * set it yet. The magic value WB_UNSET is just some 1324 * ramdomly chosen number which doesn't have the own 1325 * bit set. When we actually transmit the frame, the 1326 * status word will have _only_ the own bit set, so 1327 * the txeoc handler will be able to tell if it needs 1328 * to initiate another transmission to flush out pending 1329 * frames. 1330 */ 1331 WB_TXOWN(start_tx) = WB_UNSENT; 1332 } 1333 1334 /* 1335 * Set a timeout in case the chip goes out to lunch. 1336 */ 1337 sc->wb_timer = 5; 1338} 1339 1340static void 1341wb_init(xsc) 1342 void *xsc; 1343{ 1344 struct wb_softc *sc = xsc; 1345 1346 WB_LOCK(sc); 1347 wb_init_locked(sc); 1348 WB_UNLOCK(sc); 1349} 1350 1351static void 1352wb_init_locked(sc) 1353 struct wb_softc *sc; 1354{ 1355 struct ifnet *ifp = sc->wb_ifp; 1356 int i; 1357 struct mii_data *mii; 1358 1359 WB_LOCK_ASSERT(sc); 1360 mii = device_get_softc(sc->wb_miibus); 1361 1362 /* 1363 * Cancel pending I/O and free all RX/TX buffers. 1364 */ 1365 wb_stop(sc); 1366 wb_reset(sc); 1367 1368 sc->wb_txthresh = WB_TXTHRESH_INIT; 1369 1370 /* 1371 * Set cache alignment and burst length. 1372 */ 1373#ifdef foo 1374 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1375 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1376 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1377#endif 1378 1379 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1380 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1381 switch(sc->wb_cachesize) { 1382 case 32: 1383 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1384 break; 1385 case 16: 1386 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1387 break; 1388 case 8: 1389 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1390 break; 1391 case 0: 1392 default: 1393 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1394 break; 1395 } 1396 1397 /* This doesn't tend to work too well at 100Mbps. */ 1398 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1399 1400 /* Init our MAC address */ 1401 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1402 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1403 } 1404 1405 /* Init circular RX list. */ 1406 if (wb_list_rx_init(sc) == ENOBUFS) { 1407 device_printf(sc->wb_dev, 1408 "initialization failed: no memory for rx buffers\n"); 1409 wb_stop(sc); 1410 return; 1411 } 1412 1413 /* Init TX descriptors. */ 1414 wb_list_tx_init(sc); 1415 1416 /* If we want promiscuous mode, set the allframes bit. */ 1417 if (ifp->if_flags & IFF_PROMISC) { 1418 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1419 } else { 1420 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1421 } 1422 1423 /* 1424 * Set capture broadcast bit to capture broadcast frames. 1425 */ 1426 if (ifp->if_flags & IFF_BROADCAST) { 1427 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1428 } else { 1429 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1430 } 1431 1432 /* 1433 * Program the multicast filter, if necessary. 1434 */ 1435 wb_setmulti(sc); 1436 1437 /* 1438 * Load the address of the RX list. 1439 */ 1440 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1441 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1442 1443 /* 1444 * Enable interrupts. 1445 */ 1446 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1447 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1448 1449 /* Enable receiver and transmitter. */ 1450 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1451 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1452 1453 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1454 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1455 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1456 1457 mii_mediachg(mii); 1458 1459 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1461 1462 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1463} 1464 1465/* 1466 * Set media options. 1467 */ 1468static int 1469wb_ifmedia_upd(ifp) 1470 struct ifnet *ifp; 1471{ 1472 struct wb_softc *sc; 1473 1474 sc = ifp->if_softc; 1475 1476 WB_LOCK(sc); 1477 if (ifp->if_flags & IFF_UP) 1478 wb_init_locked(sc); 1479 WB_UNLOCK(sc); 1480 1481 return(0); 1482} 1483 1484/* 1485 * Report current media status. 1486 */ 1487static void 1488wb_ifmedia_sts(ifp, ifmr) 1489 struct ifnet *ifp; 1490 struct ifmediareq *ifmr; 1491{ 1492 struct wb_softc *sc; 1493 struct mii_data *mii; 1494 1495 sc = ifp->if_softc; 1496 1497 WB_LOCK(sc); 1498 mii = device_get_softc(sc->wb_miibus); 1499 1500 mii_pollstat(mii); 1501 ifmr->ifm_active = mii->mii_media_active; 1502 ifmr->ifm_status = mii->mii_media_status; 1503 WB_UNLOCK(sc); 1504} 1505 1506static int 1507wb_ioctl(ifp, command, data) 1508 struct ifnet *ifp; 1509 u_long command; 1510 caddr_t data; 1511{ 1512 struct wb_softc *sc = ifp->if_softc; 1513 struct mii_data *mii; 1514 struct ifreq *ifr = (struct ifreq *) data; 1515 int error = 0; 1516 1517 switch(command) { 1518 case SIOCSIFFLAGS: 1519 WB_LOCK(sc); 1520 if (ifp->if_flags & IFF_UP) { 1521 wb_init_locked(sc); 1522 } else { 1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1524 wb_stop(sc); 1525 } 1526 WB_UNLOCK(sc); 1527 error = 0; 1528 break; 1529 case SIOCADDMULTI: 1530 case SIOCDELMULTI: 1531 WB_LOCK(sc); 1532 wb_setmulti(sc); 1533 WB_UNLOCK(sc); 1534 error = 0; 1535 break; 1536 case SIOCGIFMEDIA: 1537 case SIOCSIFMEDIA: 1538 mii = device_get_softc(sc->wb_miibus); 1539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1540 break; 1541 default: 1542 error = ether_ioctl(ifp, command, data); 1543 break; 1544 } 1545 1546 return(error); 1547} 1548 1549static void 1550wb_watchdog(sc) 1551 struct wb_softc *sc; 1552{ 1553 struct ifnet *ifp; 1554 1555 WB_LOCK_ASSERT(sc); 1556 ifp = sc->wb_ifp; 1557 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1558 if_printf(ifp, "watchdog timeout\n"); 1559#ifdef foo 1560 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1561 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1562#endif 1563 wb_stop(sc); 1564 wb_reset(sc); 1565 wb_init_locked(sc); 1566 1567 if (ifp->if_snd.ifq_head != NULL) 1568 wb_start_locked(ifp); 1569} 1570 1571/* 1572 * Stop the adapter and free any mbufs allocated to the 1573 * RX and TX lists. 1574 */ 1575static void 1576wb_stop(sc) 1577 struct wb_softc *sc; 1578{ 1579 int i; 1580 struct ifnet *ifp; 1581 1582 WB_LOCK_ASSERT(sc); 1583 ifp = sc->wb_ifp; 1584 sc->wb_timer = 0; 1585 1586 callout_stop(&sc->wb_stat_callout); 1587 1588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1589 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1590 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1591 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1592 1593 /* 1594 * Free data in the RX lists. 1595 */ 1596 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1597 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1598 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1599 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1600 } 1601 } 1602 bzero((char *)&sc->wb_ldata->wb_rx_list, 1603 sizeof(sc->wb_ldata->wb_rx_list)); 1604 1605 /* 1606 * Free the TX list buffers. 1607 */ 1608 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1609 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1610 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1611 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1612 } 1613 } 1614 1615 bzero((char *)&sc->wb_ldata->wb_tx_list, 1616 sizeof(sc->wb_ldata->wb_tx_list)); 1617 1618 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1619} 1620 1621/* 1622 * Stop all chip I/O so that the kernel's probe routines don't 1623 * get confused by errant DMAs when rebooting. 1624 */ 1625static int 1626wb_shutdown(dev) 1627 device_t dev; 1628{ 1629 struct wb_softc *sc; 1630 1631 sc = device_get_softc(dev); 1632 1633 WB_LOCK(sc); 1634 wb_stop(sc); 1635 WB_UNLOCK(sc); 1636 1637 return (0); 1638} 1639