1221167Sgnn/*-
2221167Sgnn * Copyright(c) 2002-2011 Exar Corp.
3221167Sgnn * All rights reserved.
4221167Sgnn *
5221167Sgnn * Redistribution and use in source and binary forms, with or without
6221167Sgnn * modification are permitted provided the following conditions are met:
7221167Sgnn *
8221167Sgnn *    1. Redistributions of source code must retain the above copyright notice,
9221167Sgnn *       this list of conditions and the following disclaimer.
10221167Sgnn *
11221167Sgnn *    2. Redistributions in binary form must reproduce the above copyright
12221167Sgnn *       notice, this list of conditions and the following disclaimer in the
13221167Sgnn *       documentation and/or other materials provided with the distribution.
14221167Sgnn *
15221167Sgnn *    3. Neither the name of the Exar Corporation nor the names of its
16221167Sgnn *       contributors may be used to endorse or promote products derived from
17221167Sgnn *       this software without specific prior written permission.
18221167Sgnn *
19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29221167Sgnn * POSSIBILITY OF SUCH DAMAGE.
30221167Sgnn */
31221167Sgnn/*$FreeBSD$*/
32221167Sgnn
33221167Sgnn#ifndef	VXGE_HAL_VIRTUALPATH_H
34221167Sgnn#define	VXGE_HAL_VIRTUALPATH_H
35221167Sgnn
36221167Sgnn__EXTERN_BEGIN_DECLS
37221167Sgnn
38221167Sgnnstruct __hal_device_t;
39221167Sgnn
40221167Sgnn
41221167Sgnn/*
42221167Sgnn * struct __hal_virtualpath_t - Virtual Path
43221167Sgnn *
44221167Sgnn * @vp_id: Virtual path id
45221167Sgnn * @vp_open: This flag specifies if vxge_hal_vp_open is called from LL Driver
46221167Sgnn * @hldev: Hal device
47221167Sgnn * @vp_config: Virtual Path Config
48221167Sgnn * @vp_reg: VPATH Register map address in BAR0
49221167Sgnn * @vpmgmt_reg: VPATH_MGMT register map address
50221167Sgnn * @is_first_vpath: 1 if this first vpath in this vfunc, 0 otherwise
51221167Sgnn * @promisc_en: Promisc mode state flag.
52221167Sgnn * @min_bandwidth: Guaranteed Band Width in Mbps
53221167Sgnn * @max_bandwidth: Maximum Band Width in Mbps
54221167Sgnn * @max_mtu: Max mtu that can be supported
55221167Sgnn * @sess_grps_available: The mask of available session groups for this vpath
56221167Sgnn * @bmap_root_assigned: The bitmap root for this vpath
57221167Sgnn * @vsport_choices: The mask of vsports that are available for this vpath
58221167Sgnn * @vsport_number: vsport attached to this vpath
59221167Sgnn * @sess_grp_start: Session oid start
60221167Sgnn * @sess_grp_end: session oid end
61221167Sgnn * @max_kdfc_db: Maximum kernel mode doorbells
62221167Sgnn * @max_nofl_db: Maximum non offload doorbells
63221167Sgnn * @max_ofl_db: Maximum offload doorbells
64221167Sgnn * @max_msg_db: Maximum message doorbells
65221167Sgnn * @rxd_mem_size: Maximum RxD memory size
66221167Sgnn * @tx_intr_num: Interrupt Number associated with the TX
67221167Sgnn * @rx_intr_num: Interrupt Number associated with the RX
68221167Sgnn * @einta_intr_num: Interrupt Number associated with Emulated MSIX DeAssert IntA
69221167Sgnn * @bmap_intr_num: Interrupt Number associated with the bitmap
70221167Sgnn * @nce_oid_db: NCE ID database
71221167Sgnn * @session_oid_db: Session Object Id database
72221167Sgnn * @active_lros: Active LRO session list
73221167Sgnn * @active_lro_count: Active LRO count
74221167Sgnn * @free_lros: Free LRO session list
75221167Sgnn * @free_lro_count: Free LRO count
76221167Sgnn * @lro_lock: LRO session lists' lock
77221167Sgnn * @sqs: List of send queues
78221167Sgnn * @sq_lock: Lock for operations on sqs
79221167Sgnn * @srqs: List of SRQs
80221167Sgnn * @srq_lock: Lock for operations on srqs
81221167Sgnn * @srq_oid_db: DRQ object id database
82221167Sgnn * @cqrqs: CQRQs
83221167Sgnn * @cqrq_lock: Lock for operations on cqrqs
84221167Sgnn * @cqrq_oid_db: CQRQ object id database
85221167Sgnn * @umqh: UP Message Queue
86221167Sgnn * @dmqh: Down Message Queue
87221167Sgnn * @umq_dmq_ir: The adapter will overwrite and update this location as Messages
88221167Sgnn *		are read from DMQ and written into UMQ.
89221167Sgnn * @umq_dmq_ir_reg_entry: Reg entry of umq_dmq_ir_t
90221167Sgnn * @ringh: Ring Queue
91221167Sgnn * @fifoh: FIFO Queue
92221167Sgnn * @vpath_handles: Virtual Path handles list
93221167Sgnn * @vpath_handles_lock: Lock for operations on Virtual Path handles list
94221167Sgnn * @stats_block: Memory for DMAing stats
95221167Sgnn * @stats: Vpath statistics
96221167Sgnn *
97221167Sgnn * Virtual path structure to encapsulate the data related to a virtual path.
98221167Sgnn * Virtual paths are allocated by the HAL upon getting configuration from the
99221167Sgnn * driver and inserted into the list of virtual paths.
100221167Sgnn */
101221167Sgnntypedef struct __hal_virtualpath_t {
102221167Sgnn	u32				vp_id;
103221167Sgnn
104221167Sgnn	u32				vp_open;
105221167Sgnn#define	VXGE_HAL_VP_NOT_OPEN		0
106221167Sgnn#define	VXGE_HAL_VP_OPEN		1
107221167Sgnn
108221167Sgnn	struct __hal_device_t		*hldev;
109221167Sgnn	vxge_hal_vp_config_t		*vp_config;
110221167Sgnn	vxge_hal_vpath_reg_t		*vp_reg;
111221167Sgnn	vxge_hal_vpmgmt_reg_t		*vpmgmt_reg;
112221167Sgnn	__hal_non_offload_db_wrapper_t	*nofl_db;
113221167Sgnn	__hal_messaging_db_wrapper_t	*msg_db;
114221167Sgnn	u32				is_first_vpath;
115221167Sgnn
116221167Sgnn	u32				promisc_en;
117221167Sgnn#define	VXGE_HAL_VP_PROMISC_ENABLE	1
118221167Sgnn#define	VXGE_HAL_VP_PROMISC_DISABLE	0
119221167Sgnn
120221167Sgnn	u32				min_bandwidth;
121221167Sgnn	u32				max_bandwidth;
122221167Sgnn
123221167Sgnn	u32				max_mtu;
124221167Sgnn	u64				sess_grps_available;
125221167Sgnn	u32				bmap_root_assigned;
126221167Sgnn	u32				vsport_choices;
127221167Sgnn	u32				vsport_number;
128221167Sgnn	u32				sess_grp_start;
129221167Sgnn	u32				sess_grp_end;
130221167Sgnn	u32				max_kdfc_db;
131221167Sgnn	u32				max_nofl_db;
132221167Sgnn	u32				max_ofl_db;
133221167Sgnn	u32				max_msg_db;
134221167Sgnn	u32				rxd_mem_size;
135221167Sgnn	u32				tx_intr_num;
136221167Sgnn	u32				rx_intr_num;
137221167Sgnn	u32				einta_intr_num;
138221167Sgnn	u32				bmap_intr_num;
139221167Sgnn
140221167Sgnn	u64				tim_tti_cfg1_saved;
141221167Sgnn	u64				tim_tti_cfg3_saved;
142221167Sgnn	u64				tim_rti_cfg1_saved;
143221167Sgnn	u64				tim_rti_cfg3_saved;
144221167Sgnn
145221167Sgnn
146221167Sgnn	vxge_hal_ring_h			ringh;
147221167Sgnn	vxge_hal_fifo_h			fifoh;
148221167Sgnn	vxge_list_t			vpath_handles;
149221167Sgnn	spinlock_t			vpath_handles_lock;
150221167Sgnn	__hal_blockpool_entry_t		*stats_block;
151221167Sgnn	vxge_hal_vpath_stats_hw_info_t	*hw_stats;
152221167Sgnn	vxge_hal_vpath_stats_hw_info_t	*hw_stats_sav;
153221167Sgnn	vxge_hal_vpath_stats_sw_info_t	*sw_stats;
154221167Sgnn} __hal_virtualpath_t;
155221167Sgnn
156221167Sgnn/*
157221167Sgnn * struct __hal_vpath_handle_t - List item to store callback information
158221167Sgnn * @item: List head to keep the item in linked list
159221167Sgnn * @vpath: Virtual path to which this item belongs
160221167Sgnn * @cb_fn: Callback function to be called
161221167Sgnn * @client_handle: Client handle to be returned with the callback
162221167Sgnn *
163221167Sgnn * This structure is used to store the callback information.
164221167Sgnn */
165221167Sgnntypedef struct __hal_vpath_handle_t {
166221167Sgnn	vxge_list_t			item;
167221167Sgnn	__hal_virtualpath_t		*vpath;
168221167Sgnn	vxge_hal_vpath_callback_f	cb_fn;
169221167Sgnn	vxge_hal_client_h		client_handle;
170221167Sgnn} __hal_vpath_handle_t;
171221167Sgnn
172221167Sgnn
173221167Sgnn#define	VXGE_HAL_VIRTUAL_PATH_HANDLE(vpath)				\
174221167Sgnn		((vxge_hal_vpath_h)(vpath)->vpath_handles.next)
175221167Sgnn
176221167Sgnn#define	VXGE_HAL_VPATH_STATS_PIO_READ(offset) {				\
177221167Sgnn	status = __hal_vpath_stats_access(vpath,			\
178221167Sgnn			VXGE_HAL_STATS_OP_READ,				\
179221167Sgnn			offset,						\
180221167Sgnn			&val64);					\
181221167Sgnn	if (status != VXGE_HAL_OK) {					\
182221167Sgnn		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",	\
183221167Sgnn		    __FILE__, __func__, __LINE__, status);		\
184221167Sgnn		return (status);					\
185221167Sgnn	}								\
186221167Sgnn}
187221167Sgnn
188221167Sgnnvxge_hal_status_e
189221167Sgnn__hal_vpath_size_quantum_set(
190221167Sgnn    vxge_hal_device_h devh,
191221167Sgnn    u32 vp_id);
192221167Sgnn
193221167Sgnnvxge_hal_status_e
194221167Sgnn__hal_vpath_mgmt_read(
195221167Sgnn    struct __hal_device_t *hldev,
196221167Sgnn    __hal_virtualpath_t *vpath);
197221167Sgnn
198221167Sgnnvxge_hal_status_e
199221167Sgnn__hal_vpath_pci_read(
200221167Sgnn    struct __hal_device_t *hldev,
201221167Sgnn    u32 vp_id,
202221167Sgnn    u32 offset,
203221167Sgnn    u32 length,
204221167Sgnn    void *val);
205221167Sgnn
206221167Sgnnvxge_hal_status_e
207221167Sgnn__hal_vpath_reset_check(
208221167Sgnn    __hal_virtualpath_t *vpath);
209221167Sgnn
210221167Sgnnvxge_hal_status_e
211221167Sgnn__hal_vpath_fw_memo_get(
212221167Sgnn    pci_dev_h pdev,
213221167Sgnn    pci_reg_h regh0,
214221167Sgnn    u32 vp_id,
215221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
216221167Sgnn    u32 action,
217221167Sgnn    u64 param_index,
218221167Sgnn    u64 *data0,
219221167Sgnn    u64 *data1);
220221167Sgnn
221221167Sgnnvxge_hal_status_e
222221167Sgnn__hal_vpath_fw_flash_ver_get(
223221167Sgnn    pci_dev_h pdev,
224221167Sgnn    pci_reg_h regh0,
225221167Sgnn    u32 vp_id,
226221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
227221167Sgnn    vxge_hal_device_version_t *fw_version,
228221167Sgnn    vxge_hal_device_date_t *fw_date,
229221167Sgnn    vxge_hal_device_version_t *flash_version,
230221167Sgnn    vxge_hal_device_date_t *flash_date);
231221167Sgnn
232221167Sgnnvxge_hal_status_e
233221167Sgnn__hal_vpath_card_info_get(
234221167Sgnn    pci_dev_h pdev,
235221167Sgnn    pci_reg_h regh0,
236221167Sgnn    u32 vp_id,
237221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
238221167Sgnn    u8 *serial_number,
239221167Sgnn    u8 *part_number,
240221167Sgnn    u8 *product_description);
241221167Sgnn
242221167Sgnnvxge_hal_status_e
243221167Sgnn__hal_vpath_pmd_info_get(
244221167Sgnn    pci_dev_h pdev,
245221167Sgnn    pci_reg_h regh0,
246221167Sgnn    u32 vp_id,
247221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
248221167Sgnn    u32 *ports,
249221167Sgnn    vxge_hal_device_pmd_info_t *pmd_port0,
250221167Sgnn    vxge_hal_device_pmd_info_t *pmd_port1);
251221167Sgnn
252221167Sgnnu64
253221167Sgnn__hal_vpath_pci_func_mode_get(
254221167Sgnn    pci_dev_h pdev,
255221167Sgnn    pci_reg_h regh0,
256221167Sgnn    u32 vp_id,
257221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg);
258221167Sgnn
259221167Sgnnvxge_hal_device_lag_mode_e
260221167Sgnn__hal_vpath_lag_mode_get(
261221167Sgnn    __hal_virtualpath_t *vpath);
262221167Sgnn
263221167Sgnnu64
264221167Sgnn__hal_vpath_vpath_map_get(
265221167Sgnn    pci_dev_h pdev,
266221167Sgnn    pci_reg_h regh0,
267221167Sgnn    u32 vp_id,
268221167Sgnn    u32 vh,
269221167Sgnn    u32 func,
270221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg);
271221167Sgnn
272221167Sgnnvxge_hal_status_e
273221167Sgnn__hal_vpath_fw_upgrade(
274221167Sgnn    pci_dev_h pdev,
275221167Sgnn    pci_reg_h regh0,
276221167Sgnn    u32 vp_id,
277221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
278221167Sgnn    u8 *buffer,
279221167Sgnn    u32 length);
280221167Sgnn
281221167Sgnnvxge_hal_status_e
282221167Sgnn__hal_vpath_pcie_func_mode_set(
283221167Sgnn    struct __hal_device_t *hldev,
284221167Sgnn    u32 vp_id,
285221167Sgnn    u32 func_mode);
286221167Sgnn
287221167Sgnnvxge_hal_status_e
288221167Sgnn__hal_vpath_flick_link_led(
289221167Sgnn    struct __hal_device_t *hldev,
290221167Sgnn    u32 vp_id,
291221167Sgnn    u32 port,
292221167Sgnn    u32 on_off);
293221167Sgnn
294221167Sgnnvxge_hal_status_e
295221167Sgnn__hal_vpath_udp_rth_set(
296221167Sgnn    struct __hal_device_t *hldev,
297221167Sgnn    u32 vp_id,
298221167Sgnn    u32 on_off);
299221167Sgnn
300221167Sgnnvxge_hal_status_e
301221167Sgnn__hal_vpath_rts_table_get(
302221167Sgnn    vxge_hal_vpath_h vpath_handle,
303221167Sgnn    u32 action,
304221167Sgnn    u32 rts_table,
305221167Sgnn    u32 offset,
306221167Sgnn    u64 *data1,
307221167Sgnn    u64 *data2);
308221167Sgnn
309221167Sgnnvxge_hal_status_e
310221167Sgnn__hal_vpath_rts_table_set(
311221167Sgnn    vxge_hal_vpath_h vpath_handle,
312221167Sgnn    u32 action,
313221167Sgnn    u32 rts_table,
314221167Sgnn    u32 offset,
315221167Sgnn    u64 data1,
316221167Sgnn    u64 data2);
317221167Sgnn
318221167Sgnn
319221167Sgnnvxge_hal_status_e
320221167Sgnn__hal_vpath_hw_reset(
321221167Sgnn    vxge_hal_device_h devh,
322221167Sgnn    u32 vp_id);
323221167Sgnn
324221167Sgnnvxge_hal_status_e
325221167Sgnn__hal_vpath_sw_reset(
326221167Sgnn    vxge_hal_device_h devh,
327221167Sgnn    u32 vp_id);
328221167Sgnn
329221167Sgnnvxge_hal_status_e
330221167Sgnn__hal_vpath_prc_configure(
331221167Sgnn    vxge_hal_device_h devh,
332221167Sgnn    u32 vp_id);
333221167Sgnn
334221167Sgnnvxge_hal_status_e
335221167Sgnn__hal_vpath_kdfc_configure(
336221167Sgnn    vxge_hal_device_h devh,
337221167Sgnn    u32 vp_id);
338221167Sgnn
339221167Sgnnvxge_hal_status_e
340221167Sgnn__hal_vpath_mac_configure(
341221167Sgnn    vxge_hal_device_h devh,
342221167Sgnn    u32 vp_id);
343221167Sgnn
344221167Sgnnvxge_hal_status_e
345221167Sgnn__hal_vpath_tim_configure(
346221167Sgnn    vxge_hal_device_h devh,
347221167Sgnn    u32 vp_id);
348221167Sgnn
349221167Sgnnvxge_hal_status_e
350221167Sgnn__hal_vpath_hw_initialize(
351221167Sgnn    vxge_hal_device_h devh,
352221167Sgnn    u32 vp_id);
353221167Sgnn
354221167Sgnnvxge_hal_status_e
355221167Sgnn__hal_vp_initialize(
356221167Sgnn    vxge_hal_device_h devh,
357221167Sgnn    u32 vp_id,
358221167Sgnn    vxge_hal_vp_config_t *config);
359221167Sgnn
360221167Sgnnvoid
361221167Sgnn__hal_vp_terminate(
362221167Sgnn    vxge_hal_device_h devh,
363221167Sgnn    u32 vp_id);
364221167Sgnn
365221167Sgnnvxge_hal_status_e
366221167Sgnn__hal_vpath_hw_addr_get(
367221167Sgnn    pci_dev_h pdev,
368221167Sgnn    pci_reg_h regh0,
369221167Sgnn    u32 vp_id,
370221167Sgnn    vxge_hal_vpath_reg_t *vpath_reg,
371221167Sgnn    macaddr_t macaddr,
372221167Sgnn    macaddr_t macaddr_mask);
373221167Sgnn
374221167Sgnn
375221167Sgnnvxge_hal_status_e
376221167Sgnn__hal_vpath_intr_enable(
377221167Sgnn    __hal_virtualpath_t *vpath);
378221167Sgnn
379221167Sgnnvxge_hal_status_e
380221167Sgnn__hal_vpath_intr_disable(
381221167Sgnn    __hal_virtualpath_t *vpath);
382221167Sgnn
383221167Sgnnvxge_hal_device_link_state_e
384221167Sgnn__hal_vpath_link_state_test(
385221167Sgnn    __hal_virtualpath_t *vpath);
386221167Sgnn
387221167Sgnnvxge_hal_device_link_state_e
388221167Sgnn__hal_vpath_link_state_poll(
389221167Sgnn    __hal_virtualpath_t *vpath);
390221167Sgnn
391221167Sgnnvxge_hal_device_data_rate_e
392221167Sgnn__hal_vpath_data_rate_poll(
393221167Sgnn    __hal_virtualpath_t *vpath);
394221167Sgnn
395221167Sgnnvxge_hal_status_e
396221167Sgnn__hal_vpath_alarm_process(
397221167Sgnn    __hal_virtualpath_t *vpath,
398221167Sgnn    u32 skip_alarms);
399221167Sgnn
400221167Sgnnvxge_hal_status_e
401221167Sgnn__hal_vpath_stats_access(
402221167Sgnn    __hal_virtualpath_t *vpath,
403221167Sgnn    u32 operation,
404221167Sgnn    u32 offset,
405221167Sgnn    u64 *stat);
406221167Sgnn
407221167Sgnnvxge_hal_status_e
408221167Sgnn__hal_vpath_xmac_tx_stats_get(
409221167Sgnn    __hal_virtualpath_t *vpath,
410221167Sgnn    vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats);
411221167Sgnn
412221167Sgnnvxge_hal_status_e
413221167Sgnn__hal_vpath_xmac_rx_stats_get(
414221167Sgnn    __hal_virtualpath_t *vpath,
415221167Sgnn    vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats);
416221167Sgnn
417221167Sgnn
418221167Sgnnvxge_hal_status_e
419221167Sgnn__hal_vpath_hw_stats_get(
420221167Sgnn    __hal_virtualpath_t *vpath,
421221167Sgnn    vxge_hal_vpath_stats_hw_info_t *hw_stats);
422221167Sgnn
423221167Sgnn__EXTERN_END_DECLS
424221167Sgnn
425221167Sgnn#endif	/* VXGE_HAL_VIRTUALPATH_H */
426