1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef VXGE_HAL_RING_H 34#define VXGE_HAL_RING_H 35 36__EXTERN_BEGIN_DECLS 37 38typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE]; 39 40#define VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8) 41#define VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET (VXGE_OS_HOST_PAGE_SIZE-16) 42 43/* 44 * struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 45 * @dma_addr: DMA (mapped) address of _this_ descriptor. 46 * @dma_handle: DMA handle used to map the descriptor onto device. 47 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 48 * descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE 49 * bytes. Each memblock is contiguous DMA-able memory. Each 50 * memblock contains 1 or more 4KB RxD blocks visible to the 51 * X3100 hardware. 52 * @dma_object: DMA address and handle of the memory block that contains 53 * the descriptor. This member is used only in the "checked" 54 * version of the HAL (to enforce certain assertions); 55 * otherwise it gets compiled out. 56 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 57 * @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes 58 * next RxD block pointers 59 * 60 * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 61 * information associated with the descriptor. Note that ULD can ask HAL 62 * to allocate additional per-descriptor space for its own (ULD-specific) 63 * purposes. 64 */ 65typedef struct __hal_ring_rxd_priv_t { 66 dma_addr_t dma_addr; 67 pci_dma_h dma_handle; 68 ptrdiff_t dma_offset; 69#if defined(VXGE_DEBUG_ASSERT) 70 vxge_hal_mempool_dma_t *dma_object; 71#endif 72#if defined(VXGE_OS_MEMORY_CHECK) 73 u32 allocated; 74#endif 75 u32 db_bytes; 76} __hal_ring_rxd_priv_t; 77 78 79/* 80 * struct __hal_ring_t - Ring channel. 81 * @channel: Channel "base" of this ring, the common part of all HAL 82 * channels. 83 * @mempool: Memory pool, the pool from which descriptors get allocated. 84 * (See vxge_hal_mm.h). 85 * @config: Ring configuration, part of device configuration 86 * (see vxge_hal_device_config_t {}). 87 * @ring_length: Length of the ring 88 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 89 * as per X3100 User Guide. 90 * @indicate_max_pkts: Maximum number of packets processed within a single 91 * interrupt. Can be used to limit the time spent inside hw interrupt. 92 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec, 93 * 1-buffer mode descriptor is 32 byte long, etc. 94 * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 95 * data (e.g., DMA handle for Solaris) 96 * @per_rxd_space: Per rxd space requested by ULD 97 * @rxds_per_block: Number of descriptors per hardware-defined RxD 98 * block. Depends on the (1-, 3-, 5-) buffer mode. 99 * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 100 * usage. Not to confuse with @rxd_priv_size. 101 * @rxd_mem_avail: Available RxD memory 102 * @db_byte_count: Number of doorbell bytes to be posted 103 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 104 * Used in conjunction with @indicate_max_pkts. 105 * @active_sw_lros: List of Software LRO sessions in progess 106 * @active_sw_lro_count: Number of Software LRO sessions in progess 107 * @free_sw_lros: List of Software LRO sessions free 108 * @free_sw_lro_count: Number of Software LRO sessions free 109 * @sw_lro_lock: LRO session lists' lock 110 * @callback: Channel completion callback. HAL invokes the callback when there 111 * are new completions on that channel. In many implementations 112 * the @callback executes in the hw interrupt context. 113 * @rxd_init: Channel's descriptor-initialize callback. 114 * See vxge_hal_ring_rxd_init_f {}. 115 * If not NULL, HAL invokes the callback when opening the ring. 116 * @rxd_term: Channel's descriptor-terminate callback. If not NULL, 117 * HAL invokes the callback when closing the corresponding channel. 118 * See also vxge_hal_channel_rxd_term_f {}. 119 * @stats: Statistics for ring 120 * Ring channel. 121 * 122 * Note: The structure is cache line aligned to better utilize 123 * CPU cache performance. 124 */ 125typedef struct __hal_ring_t { 126 __hal_channel_t channel; 127 vxge_hal_mempool_t *mempool; 128 vxge_hal_ring_config_t *config; 129 u32 ring_length; 130 u32 buffer_mode; 131 u32 indicate_max_pkts; 132 u32 rxd_size; 133 u32 rxd_priv_size; 134 u32 per_rxd_space; 135 u32 rxds_per_block; 136 u32 rxdblock_priv_size; 137 u32 rxd_mem_avail; 138 u32 db_byte_count; 139 u32 cmpl_cnt; 140 vxge_hal_ring_callback_f callback; 141 vxge_hal_ring_rxd_init_f rxd_init; 142 vxge_hal_ring_rxd_term_f rxd_term; 143 vxge_hal_vpath_stats_sw_ring_info_t *stats; 144} __vxge_os_attr_cacheline_aligned __hal_ring_t; 145 146#define VXGE_HAL_RING_ULD_PRIV(ring, rxdh) \ 147 ring->channel.dtr_arr[ \ 148 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv 149 150#define VXGE_HAL_RING_HAL_PRIV(ring, rxdh) \ 151 ((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[ \ 152 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv)) 153 154#define VXGE_HAL_RING_POST_DOORBELL(vph, ringh) \ 155{ \ 156 if (((__hal_ring_t *)(ringh))->config->post_mode == \ 157 VXGE_HAL_RING_POST_MODE_DOORBELL) { \ 158 vxge_hal_ring_rxd_post_post_db(vph); \ 159 } \ 160} 161 162#define VXGE_HAL_RING_RXD_INDEX(rxdp) \ 163 (u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control 164 165/* ========================== RING PRIVATE API ============================ */ 166 167u64 168__hal_ring_first_block_address_get( 169 vxge_hal_ring_h ringh); 170 171vxge_hal_status_e 172__hal_ring_create( 173 vxge_hal_vpath_h vpath_handle, 174 vxge_hal_ring_attr_t *attr); 175 176void 177__hal_ring_abort( 178 vxge_hal_ring_h ringh, 179 vxge_hal_reopen_e reopen); 180 181vxge_hal_status_e 182__hal_ring_reset( 183 vxge_hal_ring_h ringh); 184 185void 186__hal_ring_delete( 187 vxge_hal_vpath_h vpath_handle); 188 189vxge_hal_status_e 190vxge_hal_ring_initial_replenish( 191 __hal_ring_t *ring, 192 vxge_hal_reopen_e reopen); 193 194vxge_hal_status_e 195__hal_ring_frame_length_set( 196 __hal_virtualpath_t *vpath, 197 u32 new_frmlen); 198 199__EXTERN_END_DECLS 200 201#endif /* VXGE_HAL_RING_H */ 202