1221167Sgnn/*-
2221167Sgnn * Copyright(c) 2002-2011 Exar Corp.
3221167Sgnn * All rights reserved.
4221167Sgnn *
5221167Sgnn * Redistribution and use in source and binary forms, with or without
6221167Sgnn * modification are permitted provided the following conditions are met:
7221167Sgnn *
8221167Sgnn *    1. Redistributions of source code must retain the above copyright notice,
9221167Sgnn *       this list of conditions and the following disclaimer.
10221167Sgnn *
11221167Sgnn *    2. Redistributions in binary form must reproduce the above copyright
12221167Sgnn *       notice, this list of conditions and the following disclaimer in the
13221167Sgnn *       documentation and/or other materials provided with the distribution.
14221167Sgnn *
15221167Sgnn *    3. Neither the name of the Exar Corporation nor the names of its
16221167Sgnn *       contributors may be used to endorse or promote products derived from
17221167Sgnn *       this software without specific prior written permission.
18221167Sgnn *
19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29221167Sgnn * POSSIBILITY OF SUCH DAMAGE.
30221167Sgnn */
31221167Sgnn/*$FreeBSD$*/
32221167Sgnn
33221167Sgnn#ifndef	VXGE_HAL_FIFO_H
34221167Sgnn#define	VXGE_HAL_FIFO_H
35221167Sgnn
36221167Sgnn__EXTERN_BEGIN_DECLS
37221167Sgnn
38221167Sgnn/*
39221167Sgnn * struct __hal_fifo_t - Fifo.
40221167Sgnn * @channel: Channel "base" of this fifo, the common part of all HAL
41221167Sgnn *		channels.
42221167Sgnn * @mempool: Memory pool, from which descriptors get allocated.
43221167Sgnn * @config: Fifo configuration, part of device configuration
44221167Sgnn *		(see vxge_hal_device_config_t {}).
45221167Sgnn * @interrupt_type: Interrupt type to be used
46221167Sgnn * @no_snoop_bits: See vxge_hal_fifo_config_t {}.
47221167Sgnn * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
48221167Sgnn *		bytes. Setting @memblock_size to page size ensures
49221167Sgnn *		by-page allocation of descriptors. 128K bytes is the
50221167Sgnn *		maximum supported block size.
51221167Sgnn * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
52221167Sgnn *		on TxDL please refer to X3100 UG.
53221167Sgnn * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
54221167Sgnn *		per-TxDL HAL private space (__hal_fifo_txdl_priv_t).
55221167Sgnn * @txdl_priv_size: Per-TxDL space reserved for HAL and ULD
56221167Sgnn * @per_txdl_space: Per txdl private space for the ULD
57221167Sgnn * @txdlblock_priv_size: Total private space per TXDL memory block
58221167Sgnn * @align_size: Cache alignment size
59221167Sgnn * @callback: Fifo completion callback. HAL invokes the callback when there
60221167Sgnn *		are new completions on that fifo. In many implementations
61221167Sgnn *		the @callback executes in the hw interrupt context.
62221167Sgnn * @txdl_init: Fifo's descriptor-initialize callback.
63221167Sgnn *		See vxge_hal_fifo_txdl_init_f {}.
64221167Sgnn *		If not NULL, HAL invokes the callback when opening
65221167Sgnn *		the fifo via vxge_hal_vpath_open().
66221167Sgnn * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
67221167Sgnn *		HAL invokes the callback when closing the corresponding fifo.
68221167Sgnn *		See also vxge_hal_fifo_txdl_term_f {}.
69221167Sgnn * @stats: Statistics of this fifo
70221167Sgnn *
71221167Sgnn * Fifo channel.
72221167Sgnn * Note: The structure is cache line aligned.
73221167Sgnn */
74221167Sgnntypedef struct __hal_fifo_t {
75221167Sgnn	__hal_channel_t				channel;
76221167Sgnn	vxge_hal_mempool_t			*mempool;
77221167Sgnn	vxge_hal_fifo_config_t			*config;
78221167Sgnn	u64					interrupt_type;
79221167Sgnn	u32					no_snoop_bits;
80221167Sgnn	u32					memblock_size;
81221167Sgnn	u32					txdl_per_memblock;
82221167Sgnn	u32					txdl_size;
83221167Sgnn	u32					txdl_priv_size;
84221167Sgnn	u32					per_txdl_space;
85221167Sgnn	u32					txdlblock_priv_size;
86221167Sgnn	u32					align_size;
87221167Sgnn	vxge_hal_fifo_callback_f		callback;
88221167Sgnn	vxge_hal_fifo_txdl_init_f		txdl_init;
89221167Sgnn	vxge_hal_fifo_txdl_term_f		txdl_term;
90221167Sgnn	vxge_hal_vpath_stats_sw_fifo_info_t	*stats;
91221167Sgnn} __vxge_os_attr_cacheline_aligned __hal_fifo_t;
92221167Sgnn
93221167Sgnn/*
94221167Sgnn * struct __hal_fifo_txdl_priv_t - Transmit descriptor HAL-private data.
95221167Sgnn * @dma_addr: DMA (mapped) address of _this_ descriptor.
96221167Sgnn * @dma_handle: DMA handle used to map the descriptor onto device.
97221167Sgnn * @dma_offset: Descriptor's offset in the memory block. HAL allocates
98221167Sgnn *		  descriptors in memory blocks (see vxge_hal_fifo_config_t {})
99221167Sgnn *		Each memblock is a contiguous block of DMA-able memory.
100221167Sgnn * @frags: Total number of fragments (that is, contiguous data buffers)
101221167Sgnn * carried by this TxDL.
102221167Sgnn * @align_vaddr_start: Aligned virtual address start
103221167Sgnn * @align_vaddr: Virtual address of the per-TxDL area in memory used for
104221167Sgnn *		alignement. Used to place one or more mis-aligned fragments
105221167Sgnn *		(the maximum defined by configration variable
106221167Sgnn *		@max_aligned_frags).
107221167Sgnn * @align_dma_addr: DMA address translated from the @align_vaddr.
108221167Sgnn * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
109221167Sgnn * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
110221167Sgnn * @align_dma_offset: The current offset into the @align_vaddr area.
111221167Sgnn * Grows while filling the descriptor, gets reset.
112221167Sgnn * @align_used_frags: Number of fragments used.
113221167Sgnn * @alloc_frags: Total number of fragments allocated.
114221167Sgnn * @dang_frags: Number of fragments kept from release until this TxDL is freed.
115221167Sgnn * @bytes_sent:
116221167Sgnn * @unused:
117221167Sgnn * @dang_txdl:
118221167Sgnn * @next_txdl_priv:
119221167Sgnn * @first_txdp:
120221167Sgnn * @dang_txdlh: Pointer to TxDL (list) kept from release until this TxDL
121221167Sgnn *		is freed.
122221167Sgnn * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
123221167Sgnn *		TxDL list.
124221167Sgnn * @txdlh: Corresponding txdlh to this TxDL.
125221167Sgnn * @memblock: Pointer to the TxDL memory block or memory page.
126221167Sgnn *		on the next send operation.
127221167Sgnn * @dma_object: DMA address and handle of the memory block that contains
128221167Sgnn *		the descriptor. This member is used only in the "checked"
129221167Sgnn *		version of the HAL (to enforce certain assertions);
130221167Sgnn *		otherwise it gets compiled out.
131221167Sgnn * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
132221167Sgnn *
133221167Sgnn * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
134221167Sgnn * information associated with the descriptor. Note that ULD can ask HAL
135221167Sgnn * to allocate additional per-descriptor space for its own (ULD-specific)
136221167Sgnn * purposes.
137221167Sgnn *
138221167Sgnn * See also: vxge_hal_ring_rxd_priv_t {}.
139221167Sgnn */
140221167Sgnntypedef struct __hal_fifo_txdl_priv_t {
141221167Sgnn	dma_addr_t			dma_addr;
142221167Sgnn	pci_dma_h			dma_handle;
143221167Sgnn	ptrdiff_t			dma_offset;
144221167Sgnn	u32				frags;
145221167Sgnn	u8				*align_vaddr_start;
146221167Sgnn	u8				*align_vaddr;
147221167Sgnn	dma_addr_t			align_dma_addr;
148221167Sgnn	pci_dma_h			align_dma_handle;
149221167Sgnn	pci_dma_acc_h			align_dma_acch;
150221167Sgnn	ptrdiff_t			align_dma_offset;
151221167Sgnn	u32				align_used_frags;
152221167Sgnn	u32				alloc_frags;
153221167Sgnn	u32				dang_frags;
154221167Sgnn	u32				bytes_sent;
155221167Sgnn	u32				unused;
156221167Sgnn	vxge_hal_fifo_txd_t		*dang_txdl;
157221167Sgnn	struct __hal_fifo_txdl_priv_t	*next_txdl_priv;
158221167Sgnn	vxge_hal_fifo_txd_t		*first_txdp;
159221167Sgnn	void				*memblock;
160221167Sgnn#if defined(VXGE_DEBUG_ASSERT)
161221167Sgnn	vxge_hal_mempool_dma_t		*dma_object;
162221167Sgnn#endif
163221167Sgnn#if defined(VXGE_OS_MEMORY_CHECK)
164221167Sgnn	u32				allocated;
165221167Sgnn#endif
166221167Sgnn} __hal_fifo_txdl_priv_t;
167221167Sgnn
168221167Sgnn#define	VXGE_HAL_FIFO_ULD_PRIV(fifo, txdh)				\
169221167Sgnn	fifo->channel.dtr_arr[						\
170221167Sgnn		((vxge_hal_fifo_txd_t *)(txdh))->host_control].uld_priv
171221167Sgnn
172221167Sgnn#define	VXGE_HAL_FIFO_HAL_PRIV(fifo, txdh)				\
173221167Sgnn	((__hal_fifo_txdl_priv_t *)(fifo->channel.dtr_arr[		\
174221167Sgnn		((vxge_hal_fifo_txd_t *)(txdh))->host_control].hal_priv))
175221167Sgnn
176221167Sgnn#define	VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags
177221167Sgnn
178221167Sgnn#define	VXGE_HAL_FIFO_TXDL_INDEX(txdp)	\
179221167Sgnn	(u32)((vxge_hal_fifo_txd_t *)txdp)->host_control
180221167Sgnn
181221167Sgnn/* ========================= FIFO PRIVATE API ============================= */
182221167Sgnn
183221167Sgnnvxge_hal_status_e
184221167Sgnn__hal_fifo_create(
185221167Sgnn    vxge_hal_vpath_h vpath_handle,
186221167Sgnn    vxge_hal_fifo_attr_t *attr);
187221167Sgnn
188221167Sgnnvoid
189221167Sgnn__hal_fifo_abort(
190221167Sgnn    vxge_hal_fifo_h fifoh,
191221167Sgnn    vxge_hal_reopen_e reopen);
192221167Sgnn
193221167Sgnnvxge_hal_status_e
194221167Sgnn__hal_fifo_reset(
195221167Sgnn    vxge_hal_fifo_h ringh);
196221167Sgnn
197221167Sgnnvoid
198221167Sgnn__hal_fifo_delete(
199221167Sgnn    vxge_hal_vpath_h vpath_handle);
200221167Sgnn
201221167Sgnnvoid
202221167Sgnn__hal_fifo_txdl_free_many(
203221167Sgnn    __hal_fifo_t *fifo,
204221167Sgnn    vxge_hal_fifo_txd_t *txdp,
205221167Sgnn    u32 list_size,
206221167Sgnn    u32 frags);
207221167Sgnn
208221167Sgnn#if defined(VXGE_HAL_ALIGN_XMIT)
209221167Sgnnvoid
210221167Sgnn__hal_fifo_txdl_align_free_unmap(
211221167Sgnn    __hal_fifo_t *fifo,
212221167Sgnn    vxge_hal_fifo_txd_t *txdp);
213221167Sgnn
214221167Sgnnvxge_hal_status_e
215221167Sgnn__hal_fifo_txdl_align_alloc_map(
216221167Sgnn    __hal_fifo_t *fifo,
217221167Sgnn    vxge_hal_fifo_txd_t *txdp);
218221167Sgnn
219221167Sgnn#endif
220221167Sgnn
221221167Sgnn__EXTERN_END_DECLS
222221167Sgnn
223221167Sgnn#endif	/* VXGE_HAL_FIFO_H */
224