if_vte.c revision 257176
1/*- 2 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/vte/if_vte.c 257176 2013-10-26 17:58:36Z glebius $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_llc.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57#include <net/if_vlan_var.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <machine/bus.h> 69 70#include <dev/vte/if_vtereg.h> 71#include <dev/vte/if_vtevar.h> 72 73/* "device miibus" required. See GENERIC if you get errors here. */ 74#include "miibus_if.h" 75 76MODULE_DEPEND(vte, pci, 1, 1, 1); 77MODULE_DEPEND(vte, ether, 1, 1, 1); 78MODULE_DEPEND(vte, miibus, 1, 1, 1); 79 80/* Tunables. */ 81static int tx_deep_copy = 1; 82TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy); 83 84/* 85 * Devices supported by this driver. 86 */ 87static const struct vte_ident vte_ident_table[] = { 88 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"}, 89 { 0, 0, NULL} 90}; 91 92static int vte_attach(device_t); 93static int vte_detach(device_t); 94static int vte_dma_alloc(struct vte_softc *); 95static void vte_dma_free(struct vte_softc *); 96static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int); 97static struct vte_txdesc * 98 vte_encap(struct vte_softc *, struct mbuf **); 99static const struct vte_ident * 100 vte_find_ident(device_t); 101#ifndef __NO_STRICT_ALIGNMENT 102static struct mbuf * 103 vte_fixup_rx(struct ifnet *, struct mbuf *); 104#endif 105static void vte_get_macaddr(struct vte_softc *); 106static void vte_init(void *); 107static void vte_init_locked(struct vte_softc *); 108static int vte_init_rx_ring(struct vte_softc *); 109static int vte_init_tx_ring(struct vte_softc *); 110static void vte_intr(void *); 111static int vte_ioctl(struct ifnet *, u_long, caddr_t); 112static void vte_mac_config(struct vte_softc *); 113static int vte_miibus_readreg(device_t, int, int); 114static void vte_miibus_statchg(device_t); 115static int vte_miibus_writereg(device_t, int, int, int); 116static int vte_mediachange(struct ifnet *); 117static int vte_mediachange_locked(struct ifnet *); 118static void vte_mediastatus(struct ifnet *, struct ifmediareq *); 119static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 120static int vte_probe(device_t); 121static void vte_reset(struct vte_softc *); 122static int vte_resume(device_t); 123static void vte_rxeof(struct vte_softc *); 124static void vte_rxfilter(struct vte_softc *); 125static int vte_shutdown(device_t); 126static void vte_start(struct ifnet *); 127static void vte_start_locked(struct vte_softc *); 128static void vte_start_mac(struct vte_softc *); 129static void vte_stats_clear(struct vte_softc *); 130static void vte_stats_update(struct vte_softc *); 131static void vte_stop(struct vte_softc *); 132static void vte_stop_mac(struct vte_softc *); 133static int vte_suspend(device_t); 134static void vte_sysctl_node(struct vte_softc *); 135static void vte_tick(void *); 136static void vte_txeof(struct vte_softc *); 137static void vte_watchdog(struct vte_softc *); 138static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 139static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS); 140 141static device_method_t vte_methods[] = { 142 /* Device interface. */ 143 DEVMETHOD(device_probe, vte_probe), 144 DEVMETHOD(device_attach, vte_attach), 145 DEVMETHOD(device_detach, vte_detach), 146 DEVMETHOD(device_shutdown, vte_shutdown), 147 DEVMETHOD(device_suspend, vte_suspend), 148 DEVMETHOD(device_resume, vte_resume), 149 150 /* MII interface. */ 151 DEVMETHOD(miibus_readreg, vte_miibus_readreg), 152 DEVMETHOD(miibus_writereg, vte_miibus_writereg), 153 DEVMETHOD(miibus_statchg, vte_miibus_statchg), 154 155 DEVMETHOD_END 156}; 157 158static driver_t vte_driver = { 159 "vte", 160 vte_methods, 161 sizeof(struct vte_softc) 162}; 163 164static devclass_t vte_devclass; 165 166DRIVER_MODULE(vte, pci, vte_driver, vte_devclass, 0, 0); 167DRIVER_MODULE(miibus, vte, miibus_driver, miibus_devclass, 0, 0); 168 169static int 170vte_miibus_readreg(device_t dev, int phy, int reg) 171{ 172 struct vte_softc *sc; 173 int i; 174 175 sc = device_get_softc(dev); 176 177 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 178 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 179 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 180 DELAY(5); 181 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 182 break; 183 } 184 185 if (i == 0) { 186 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg); 187 return (0); 188 } 189 190 return (CSR_READ_2(sc, VTE_MMRD)); 191} 192 193static int 194vte_miibus_writereg(device_t dev, int phy, int reg, int val) 195{ 196 struct vte_softc *sc; 197 int i; 198 199 sc = device_get_softc(dev); 200 201 CSR_WRITE_2(sc, VTE_MMWD, val); 202 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 203 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 204 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 205 DELAY(5); 206 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 207 break; 208 } 209 210 if (i == 0) 211 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg); 212 213 return (0); 214} 215 216static void 217vte_miibus_statchg(device_t dev) 218{ 219 struct vte_softc *sc; 220 struct mii_data *mii; 221 struct ifnet *ifp; 222 uint16_t val; 223 224 sc = device_get_softc(dev); 225 226 mii = device_get_softc(sc->vte_miibus); 227 ifp = sc->vte_ifp; 228 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 229 return; 230 231 sc->vte_flags &= ~VTE_FLAG_LINK; 232 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 233 (IFM_ACTIVE | IFM_AVALID)) { 234 switch (IFM_SUBTYPE(mii->mii_media_active)) { 235 case IFM_10_T: 236 case IFM_100_TX: 237 sc->vte_flags |= VTE_FLAG_LINK; 238 break; 239 default: 240 break; 241 } 242 } 243 244 /* Stop RX/TX MACs. */ 245 vte_stop_mac(sc); 246 /* Program MACs with resolved duplex and flow control. */ 247 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 248 /* 249 * Timer waiting time : (63 + TIMER * 64) MII clock. 250 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 251 */ 252 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 253 val = 18 << VTE_IM_TIMER_SHIFT; 254 else 255 val = 1 << VTE_IM_TIMER_SHIFT; 256 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 257 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 258 CSR_WRITE_2(sc, VTE_MRICR, val); 259 260 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 261 val = 18 << VTE_IM_TIMER_SHIFT; 262 else 263 val = 1 << VTE_IM_TIMER_SHIFT; 264 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 265 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 266 CSR_WRITE_2(sc, VTE_MTICR, val); 267 268 vte_mac_config(sc); 269 vte_start_mac(sc); 270 } 271} 272 273static void 274vte_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 275{ 276 struct vte_softc *sc; 277 struct mii_data *mii; 278 279 sc = ifp->if_softc; 280 VTE_LOCK(sc); 281 if ((ifp->if_flags & IFF_UP) == 0) { 282 VTE_UNLOCK(sc); 283 return; 284 } 285 mii = device_get_softc(sc->vte_miibus); 286 287 mii_pollstat(mii); 288 ifmr->ifm_status = mii->mii_media_status; 289 ifmr->ifm_active = mii->mii_media_active; 290 VTE_UNLOCK(sc); 291} 292 293static int 294vte_mediachange(struct ifnet *ifp) 295{ 296 struct vte_softc *sc; 297 int error; 298 299 sc = ifp->if_softc; 300 VTE_LOCK(sc); 301 error = vte_mediachange_locked(ifp); 302 VTE_UNLOCK(sc); 303 return (error); 304} 305 306static int 307vte_mediachange_locked(struct ifnet *ifp) 308{ 309 struct vte_softc *sc; 310 struct mii_data *mii; 311 struct mii_softc *miisc; 312 int error; 313 314 sc = ifp->if_softc; 315 mii = device_get_softc(sc->vte_miibus); 316 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 317 PHY_RESET(miisc); 318 error = mii_mediachg(mii); 319 320 return (error); 321} 322 323static const struct vte_ident * 324vte_find_ident(device_t dev) 325{ 326 const struct vte_ident *ident; 327 uint16_t vendor, devid; 328 329 vendor = pci_get_vendor(dev); 330 devid = pci_get_device(dev); 331 for (ident = vte_ident_table; ident->name != NULL; ident++) { 332 if (vendor == ident->vendorid && devid == ident->deviceid) 333 return (ident); 334 } 335 336 return (NULL); 337} 338 339static int 340vte_probe(device_t dev) 341{ 342 const struct vte_ident *ident; 343 344 ident = vte_find_ident(dev); 345 if (ident != NULL) { 346 device_set_desc(dev, ident->name); 347 return (BUS_PROBE_DEFAULT); 348 } 349 350 return (ENXIO); 351} 352 353static void 354vte_get_macaddr(struct vte_softc *sc) 355{ 356 uint16_t mid; 357 358 /* 359 * It seems there is no way to reload station address and 360 * it is supposed to be set by BIOS. 361 */ 362 mid = CSR_READ_2(sc, VTE_MID0L); 363 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 364 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 365 mid = CSR_READ_2(sc, VTE_MID0M); 366 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 367 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 368 mid = CSR_READ_2(sc, VTE_MID0H); 369 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 370 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 371} 372 373static int 374vte_attach(device_t dev) 375{ 376 struct vte_softc *sc; 377 struct ifnet *ifp; 378 uint16_t macid; 379 int error, rid; 380 381 error = 0; 382 sc = device_get_softc(dev); 383 sc->vte_dev = dev; 384 385 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 386 MTX_DEF); 387 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0); 388 sc->vte_ident = vte_find_ident(dev); 389 390 /* Map the device. */ 391 pci_enable_busmaster(dev); 392 sc->vte_res_id = PCIR_BAR(1); 393 sc->vte_res_type = SYS_RES_MEMORY; 394 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 395 &sc->vte_res_id, RF_ACTIVE); 396 if (sc->vte_res == NULL) { 397 sc->vte_res_id = PCIR_BAR(0); 398 sc->vte_res_type = SYS_RES_IOPORT; 399 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 400 &sc->vte_res_id, RF_ACTIVE); 401 if (sc->vte_res == NULL) { 402 device_printf(dev, "cannot map memory/ports.\n"); 403 mtx_destroy(&sc->vte_mtx); 404 return (ENXIO); 405 } 406 } 407 if (bootverbose) { 408 device_printf(dev, "using %s space register mapping\n", 409 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 410 device_printf(dev, "MAC Identifier : 0x%04x\n", 411 CSR_READ_2(sc, VTE_MACID)); 412 macid = CSR_READ_2(sc, VTE_MACID_REV); 413 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n", 414 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT, 415 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT); 416 } 417 418 rid = 0; 419 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 420 RF_SHAREABLE | RF_ACTIVE); 421 if (sc->vte_irq == NULL) { 422 device_printf(dev, "cannot allocate IRQ resources.\n"); 423 error = ENXIO; 424 goto fail; 425 } 426 427 /* Reset the ethernet controller. */ 428 vte_reset(sc); 429 430 if ((error = vte_dma_alloc(sc) != 0)) 431 goto fail; 432 433 /* Create device sysctl node. */ 434 vte_sysctl_node(sc); 435 436 /* Load station address. */ 437 vte_get_macaddr(sc); 438 439 ifp = sc->vte_ifp = if_alloc(IFT_ETHER); 440 if (ifp == NULL) { 441 device_printf(dev, "cannot allocate ifnet structure.\n"); 442 error = ENXIO; 443 goto fail; 444 } 445 446 ifp->if_softc = sc; 447 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 448 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 449 ifp->if_ioctl = vte_ioctl; 450 ifp->if_start = vte_start; 451 ifp->if_init = vte_init; 452 ifp->if_snd.ifq_drv_maxlen = VTE_TX_RING_CNT - 1; 453 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 454 IFQ_SET_READY(&ifp->if_snd); 455 456 /* 457 * Set up MII bus. 458 * BIOS would have initialized VTE_MPSCCR to catch PHY 459 * status changes so driver may be able to extract 460 * configured PHY address. Since it's common to see BIOS 461 * fails to initialize the register(including the sample 462 * board I have), let mii(4) probe it. This is more 463 * reliable than relying on BIOS's initialization. 464 * 465 * Advertising flow control capability to mii(4) was 466 * intentionally disabled due to severe problems in TX 467 * pause frame generation. See vte_rxeof() for more 468 * details. 469 */ 470 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange, 471 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 472 if (error != 0) { 473 device_printf(dev, "attaching PHYs failed\n"); 474 goto fail; 475 } 476 477 ether_ifattach(ifp, sc->vte_eaddr); 478 479 /* VLAN capability setup. */ 480 ifp->if_capabilities |= IFCAP_VLAN_MTU; 481 ifp->if_capenable = ifp->if_capabilities; 482 /* Tell the upper layer we support VLAN over-sized frames. */ 483 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 484 485 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE, 486 NULL, vte_intr, sc, &sc->vte_intrhand); 487 if (error != 0) { 488 device_printf(dev, "could not set up interrupt handler.\n"); 489 ether_ifdetach(ifp); 490 goto fail; 491 } 492 493fail: 494 if (error != 0) 495 vte_detach(dev); 496 497 return (error); 498} 499 500static int 501vte_detach(device_t dev) 502{ 503 struct vte_softc *sc; 504 struct ifnet *ifp; 505 506 sc = device_get_softc(dev); 507 508 ifp = sc->vte_ifp; 509 if (device_is_attached(dev)) { 510 VTE_LOCK(sc); 511 vte_stop(sc); 512 VTE_UNLOCK(sc); 513 callout_drain(&sc->vte_tick_ch); 514 ether_ifdetach(ifp); 515 } 516 517 if (sc->vte_miibus != NULL) { 518 device_delete_child(dev, sc->vte_miibus); 519 sc->vte_miibus = NULL; 520 } 521 bus_generic_detach(dev); 522 523 if (sc->vte_intrhand != NULL) { 524 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand); 525 sc->vte_intrhand = NULL; 526 } 527 if (sc->vte_irq != NULL) { 528 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq); 529 sc->vte_irq = NULL; 530 } 531 if (sc->vte_res != NULL) { 532 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id, 533 sc->vte_res); 534 sc->vte_res = NULL; 535 } 536 if (ifp != NULL) { 537 if_free(ifp); 538 sc->vte_ifp = NULL; 539 } 540 vte_dma_free(sc); 541 mtx_destroy(&sc->vte_mtx); 542 543 return (0); 544} 545 546#define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 547 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 548 549static void 550vte_sysctl_node(struct vte_softc *sc) 551{ 552 struct sysctl_ctx_list *ctx; 553 struct sysctl_oid_list *child, *parent; 554 struct sysctl_oid *tree; 555 struct vte_hw_stats *stats; 556 int error; 557 558 stats = &sc->vte_stats; 559 ctx = device_get_sysctl_ctx(sc->vte_dev); 560 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev)); 561 562 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 563 CTLTYPE_INT | CTLFLAG_RW, &sc->vte_int_rx_mod, 0, 564 sysctl_hw_vte_int_mod, "I", "vte RX interrupt moderation"); 565 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 566 CTLTYPE_INT | CTLFLAG_RW, &sc->vte_int_tx_mod, 0, 567 sysctl_hw_vte_int_mod, "I", "vte TX interrupt moderation"); 568 /* Pull in device tunables. */ 569 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 570 error = resource_int_value(device_get_name(sc->vte_dev), 571 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod); 572 if (error == 0) { 573 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN || 574 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) { 575 device_printf(sc->vte_dev, "int_rx_mod value out of " 576 "range; using default: %d\n", 577 VTE_IM_RX_BUNDLE_DEFAULT); 578 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 579 } 580 } 581 582 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 583 error = resource_int_value(device_get_name(sc->vte_dev), 584 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod); 585 if (error == 0) { 586 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN || 587 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) { 588 device_printf(sc->vte_dev, "int_tx_mod value out of " 589 "range; using default: %d\n", 590 VTE_IM_TX_BUNDLE_DEFAULT); 591 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 592 } 593 } 594 595 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 596 NULL, "VTE statistics"); 597 parent = SYSCTL_CHILDREN(tree); 598 599 /* RX statistics. */ 600 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 601 NULL, "RX MAC statistics"); 602 child = SYSCTL_CHILDREN(tree); 603 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 604 &stats->rx_frames, "Good frames"); 605 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 606 &stats->rx_bcast_frames, "Good broadcast frames"); 607 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 608 &stats->rx_mcast_frames, "Good multicast frames"); 609 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt", 610 &stats->rx_runts, "Too short frames"); 611 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 612 &stats->rx_crcerrs, "CRC errors"); 613 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames", 614 &stats->rx_long_frames, 615 "Frames that have longer length than maximum packet length"); 616 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full", 617 &stats->rx_fifo_full, "FIFO full"); 618 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail", 619 &stats->rx_desc_unavail, "Descriptor unavailable frames"); 620 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 621 &stats->rx_pause_frames, "Pause control frames"); 622 623 /* TX statistics. */ 624 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 625 NULL, "TX MAC statistics"); 626 child = SYSCTL_CHILDREN(tree); 627 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 628 &stats->tx_frames, "Good frames"); 629 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 630 &stats->tx_underruns, "FIFO underruns"); 631 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 632 &stats->tx_late_colls, "Late collisions"); 633 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 634 &stats->tx_pause_frames, "Pause control frames"); 635} 636 637#undef VTE_SYSCTL_STAT_ADD32 638 639struct vte_dmamap_arg { 640 bus_addr_t vte_busaddr; 641}; 642 643static void 644vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 645{ 646 struct vte_dmamap_arg *ctx; 647 648 if (error != 0) 649 return; 650 651 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 652 653 ctx = (struct vte_dmamap_arg *)arg; 654 ctx->vte_busaddr = segs[0].ds_addr; 655} 656 657static int 658vte_dma_alloc(struct vte_softc *sc) 659{ 660 struct vte_txdesc *txd; 661 struct vte_rxdesc *rxd; 662 struct vte_dmamap_arg ctx; 663 int error, i; 664 665 /* Create parent DMA tag. */ 666 error = bus_dma_tag_create( 667 bus_get_dma_tag(sc->vte_dev), /* parent */ 668 1, 0, /* alignment, boundary */ 669 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 670 BUS_SPACE_MAXADDR, /* highaddr */ 671 NULL, NULL, /* filter, filterarg */ 672 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 673 0, /* nsegments */ 674 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 675 0, /* flags */ 676 NULL, NULL, /* lockfunc, lockarg */ 677 &sc->vte_cdata.vte_parent_tag); 678 if (error != 0) { 679 device_printf(sc->vte_dev, 680 "could not create parent DMA tag.\n"); 681 goto fail; 682 } 683 684 /* Create DMA tag for TX descriptor ring. */ 685 error = bus_dma_tag_create( 686 sc->vte_cdata.vte_parent_tag, /* parent */ 687 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */ 688 BUS_SPACE_MAXADDR, /* lowaddr */ 689 BUS_SPACE_MAXADDR, /* highaddr */ 690 NULL, NULL, /* filter, filterarg */ 691 VTE_TX_RING_SZ, /* maxsize */ 692 1, /* nsegments */ 693 VTE_TX_RING_SZ, /* maxsegsize */ 694 0, /* flags */ 695 NULL, NULL, /* lockfunc, lockarg */ 696 &sc->vte_cdata.vte_tx_ring_tag); 697 if (error != 0) { 698 device_printf(sc->vte_dev, 699 "could not create TX ring DMA tag.\n"); 700 goto fail; 701 } 702 703 /* Create DMA tag for RX free descriptor ring. */ 704 error = bus_dma_tag_create( 705 sc->vte_cdata.vte_parent_tag, /* parent */ 706 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */ 707 BUS_SPACE_MAXADDR, /* lowaddr */ 708 BUS_SPACE_MAXADDR, /* highaddr */ 709 NULL, NULL, /* filter, filterarg */ 710 VTE_RX_RING_SZ, /* maxsize */ 711 1, /* nsegments */ 712 VTE_RX_RING_SZ, /* maxsegsize */ 713 0, /* flags */ 714 NULL, NULL, /* lockfunc, lockarg */ 715 &sc->vte_cdata.vte_rx_ring_tag); 716 if (error != 0) { 717 device_printf(sc->vte_dev, 718 "could not create RX ring DMA tag.\n"); 719 goto fail; 720 } 721 722 /* Allocate DMA'able memory and load the DMA map for TX ring. */ 723 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag, 724 (void **)&sc->vte_cdata.vte_tx_ring, 725 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 726 &sc->vte_cdata.vte_tx_ring_map); 727 if (error != 0) { 728 device_printf(sc->vte_dev, 729 "could not allocate DMA'able memory for TX ring.\n"); 730 goto fail; 731 } 732 ctx.vte_busaddr = 0; 733 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag, 734 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 735 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0); 736 if (error != 0 || ctx.vte_busaddr == 0) { 737 device_printf(sc->vte_dev, 738 "could not load DMA'able memory for TX ring.\n"); 739 goto fail; 740 } 741 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr; 742 743 /* Allocate DMA'able memory and load the DMA map for RX ring. */ 744 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag, 745 (void **)&sc->vte_cdata.vte_rx_ring, 746 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 747 &sc->vte_cdata.vte_rx_ring_map); 748 if (error != 0) { 749 device_printf(sc->vte_dev, 750 "could not allocate DMA'able memory for RX ring.\n"); 751 goto fail; 752 } 753 ctx.vte_busaddr = 0; 754 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag, 755 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 756 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0); 757 if (error != 0 || ctx.vte_busaddr == 0) { 758 device_printf(sc->vte_dev, 759 "could not load DMA'able memory for RX ring.\n"); 760 goto fail; 761 } 762 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr; 763 764 /* Create TX buffer parent tag. */ 765 error = bus_dma_tag_create( 766 bus_get_dma_tag(sc->vte_dev), /* parent */ 767 1, 0, /* alignment, boundary */ 768 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 769 BUS_SPACE_MAXADDR, /* highaddr */ 770 NULL, NULL, /* filter, filterarg */ 771 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 772 0, /* nsegments */ 773 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 774 0, /* flags */ 775 NULL, NULL, /* lockfunc, lockarg */ 776 &sc->vte_cdata.vte_buffer_tag); 777 if (error != 0) { 778 device_printf(sc->vte_dev, 779 "could not create parent buffer DMA tag.\n"); 780 goto fail; 781 } 782 783 /* Create DMA tag for TX buffers. */ 784 error = bus_dma_tag_create( 785 sc->vte_cdata.vte_buffer_tag, /* parent */ 786 1, 0, /* alignment, boundary */ 787 BUS_SPACE_MAXADDR, /* lowaddr */ 788 BUS_SPACE_MAXADDR, /* highaddr */ 789 NULL, NULL, /* filter, filterarg */ 790 MCLBYTES, /* maxsize */ 791 1, /* nsegments */ 792 MCLBYTES, /* maxsegsize */ 793 0, /* flags */ 794 NULL, NULL, /* lockfunc, lockarg */ 795 &sc->vte_cdata.vte_tx_tag); 796 if (error != 0) { 797 device_printf(sc->vte_dev, "could not create TX DMA tag.\n"); 798 goto fail; 799 } 800 801 /* Create DMA tag for RX buffers. */ 802 error = bus_dma_tag_create( 803 sc->vte_cdata.vte_buffer_tag, /* parent */ 804 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 805 BUS_SPACE_MAXADDR, /* lowaddr */ 806 BUS_SPACE_MAXADDR, /* highaddr */ 807 NULL, NULL, /* filter, filterarg */ 808 MCLBYTES, /* maxsize */ 809 1, /* nsegments */ 810 MCLBYTES, /* maxsegsize */ 811 0, /* flags */ 812 NULL, NULL, /* lockfunc, lockarg */ 813 &sc->vte_cdata.vte_rx_tag); 814 if (error != 0) { 815 device_printf(sc->vte_dev, "could not create RX DMA tag.\n"); 816 goto fail; 817 } 818 /* Create DMA maps for TX buffers. */ 819 for (i = 0; i < VTE_TX_RING_CNT; i++) { 820 txd = &sc->vte_cdata.vte_txdesc[i]; 821 txd->tx_m = NULL; 822 txd->tx_dmamap = NULL; 823 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0, 824 &txd->tx_dmamap); 825 if (error != 0) { 826 device_printf(sc->vte_dev, 827 "could not create TX dmamap.\n"); 828 goto fail; 829 } 830 } 831 /* Create DMA maps for RX buffers. */ 832 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 833 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 834 device_printf(sc->vte_dev, 835 "could not create spare RX dmamap.\n"); 836 goto fail; 837 } 838 for (i = 0; i < VTE_RX_RING_CNT; i++) { 839 rxd = &sc->vte_cdata.vte_rxdesc[i]; 840 rxd->rx_m = NULL; 841 rxd->rx_dmamap = NULL; 842 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 843 &rxd->rx_dmamap); 844 if (error != 0) { 845 device_printf(sc->vte_dev, 846 "could not create RX dmamap.\n"); 847 goto fail; 848 } 849 } 850 851fail: 852 return (error); 853} 854 855static void 856vte_dma_free(struct vte_softc *sc) 857{ 858 struct vte_txdesc *txd; 859 struct vte_rxdesc *rxd; 860 int i; 861 862 /* TX buffers. */ 863 if (sc->vte_cdata.vte_tx_tag != NULL) { 864 for (i = 0; i < VTE_TX_RING_CNT; i++) { 865 txd = &sc->vte_cdata.vte_txdesc[i]; 866 if (txd->tx_dmamap != NULL) { 867 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag, 868 txd->tx_dmamap); 869 txd->tx_dmamap = NULL; 870 } 871 } 872 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag); 873 sc->vte_cdata.vte_tx_tag = NULL; 874 } 875 /* RX buffers */ 876 if (sc->vte_cdata.vte_rx_tag != NULL) { 877 for (i = 0; i < VTE_RX_RING_CNT; i++) { 878 rxd = &sc->vte_cdata.vte_rxdesc[i]; 879 if (rxd->rx_dmamap != NULL) { 880 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 881 rxd->rx_dmamap); 882 rxd->rx_dmamap = NULL; 883 } 884 } 885 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 886 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 887 sc->vte_cdata.vte_rx_sparemap); 888 sc->vte_cdata.vte_rx_sparemap = NULL; 889 } 890 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag); 891 sc->vte_cdata.vte_rx_tag = NULL; 892 } 893 /* TX descriptor ring. */ 894 if (sc->vte_cdata.vte_tx_ring_tag != NULL) { 895 if (sc->vte_cdata.vte_tx_ring_map != NULL) 896 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag, 897 sc->vte_cdata.vte_tx_ring_map); 898 if (sc->vte_cdata.vte_tx_ring_map != NULL && 899 sc->vte_cdata.vte_tx_ring != NULL) 900 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag, 901 sc->vte_cdata.vte_tx_ring, 902 sc->vte_cdata.vte_tx_ring_map); 903 sc->vte_cdata.vte_tx_ring = NULL; 904 sc->vte_cdata.vte_tx_ring_map = NULL; 905 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag); 906 sc->vte_cdata.vte_tx_ring_tag = NULL; 907 } 908 /* RX ring. */ 909 if (sc->vte_cdata.vte_rx_ring_tag != NULL) { 910 if (sc->vte_cdata.vte_rx_ring_map != NULL) 911 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag, 912 sc->vte_cdata.vte_rx_ring_map); 913 if (sc->vte_cdata.vte_rx_ring_map != NULL && 914 sc->vte_cdata.vte_rx_ring != NULL) 915 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag, 916 sc->vte_cdata.vte_rx_ring, 917 sc->vte_cdata.vte_rx_ring_map); 918 sc->vte_cdata.vte_rx_ring = NULL; 919 sc->vte_cdata.vte_rx_ring_map = NULL; 920 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag); 921 sc->vte_cdata.vte_rx_ring_tag = NULL; 922 } 923 if (sc->vte_cdata.vte_buffer_tag != NULL) { 924 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag); 925 sc->vte_cdata.vte_buffer_tag = NULL; 926 } 927 if (sc->vte_cdata.vte_parent_tag != NULL) { 928 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag); 929 sc->vte_cdata.vte_parent_tag = NULL; 930 } 931} 932 933static int 934vte_shutdown(device_t dev) 935{ 936 937 return (vte_suspend(dev)); 938} 939 940static int 941vte_suspend(device_t dev) 942{ 943 struct vte_softc *sc; 944 struct ifnet *ifp; 945 946 sc = device_get_softc(dev); 947 948 VTE_LOCK(sc); 949 ifp = sc->vte_ifp; 950 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 951 vte_stop(sc); 952 VTE_UNLOCK(sc); 953 954 return (0); 955} 956 957static int 958vte_resume(device_t dev) 959{ 960 struct vte_softc *sc; 961 struct ifnet *ifp; 962 963 sc = device_get_softc(dev); 964 965 VTE_LOCK(sc); 966 ifp = sc->vte_ifp; 967 if ((ifp->if_flags & IFF_UP) != 0) { 968 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 969 vte_init_locked(sc); 970 } 971 VTE_UNLOCK(sc); 972 973 return (0); 974} 975 976static struct vte_txdesc * 977vte_encap(struct vte_softc *sc, struct mbuf **m_head) 978{ 979 struct vte_txdesc *txd; 980 struct mbuf *m, *n; 981 bus_dma_segment_t txsegs[1]; 982 int copy, error, nsegs, padlen; 983 984 VTE_LOCK_ASSERT(sc); 985 986 M_ASSERTPKTHDR((*m_head)); 987 988 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 989 m = *m_head; 990 /* 991 * Controller doesn't auto-pad, so we have to make sure pad 992 * short frames out to the minimum frame length. 993 */ 994 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 995 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 996 else 997 padlen = 0; 998 999 /* 1000 * Controller does not support multi-fragmented TX buffers. 1001 * Controller spends most of its TX processing time in 1002 * de-fragmenting TX buffers. Either faster CPU or more 1003 * advanced controller DMA engine is required to speed up 1004 * TX path processing. 1005 * To mitigate the de-fragmenting issue, perform deep copy 1006 * from fragmented mbuf chains to a pre-allocated mbuf 1007 * cluster with extra cost of kernel memory. For frames 1008 * that is composed of single TX buffer, the deep copy is 1009 * bypassed. 1010 */ 1011 if (tx_deep_copy != 0) { 1012 copy = 0; 1013 if (m->m_next != NULL) 1014 copy++; 1015 if (padlen > 0 && (M_WRITABLE(m) == 0 || 1016 padlen > M_TRAILINGSPACE(m))) 1017 copy++; 1018 if (copy != 0) { 1019 /* Avoid expensive m_defrag(9) and do deep copy. */ 1020 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 1021 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 1022 n->m_pkthdr.len = m->m_pkthdr.len; 1023 n->m_len = m->m_pkthdr.len; 1024 m = n; 1025 txd->tx_flags |= VTE_TXMBUF; 1026 } 1027 1028 if (padlen > 0) { 1029 /* Zero out the bytes in the pad area. */ 1030 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1031 m->m_pkthdr.len += padlen; 1032 m->m_len = m->m_pkthdr.len; 1033 } 1034 } else { 1035 if (M_WRITABLE(m) == 0) { 1036 if (m->m_next != NULL || padlen > 0) { 1037 /* Get a writable copy. */ 1038 m = m_dup(*m_head, M_NOWAIT); 1039 /* Release original mbuf chains. */ 1040 m_freem(*m_head); 1041 if (m == NULL) { 1042 *m_head = NULL; 1043 return (NULL); 1044 } 1045 *m_head = m; 1046 } 1047 } 1048 1049 if (m->m_next != NULL) { 1050 m = m_defrag(*m_head, M_NOWAIT); 1051 if (m == NULL) { 1052 m_freem(*m_head); 1053 *m_head = NULL; 1054 return (NULL); 1055 } 1056 *m_head = m; 1057 } 1058 1059 if (padlen > 0) { 1060 if (M_TRAILINGSPACE(m) < padlen) { 1061 m = m_defrag(*m_head, M_NOWAIT); 1062 if (m == NULL) { 1063 m_freem(*m_head); 1064 *m_head = NULL; 1065 return (NULL); 1066 } 1067 *m_head = m; 1068 } 1069 /* Zero out the bytes in the pad area. */ 1070 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1071 m->m_pkthdr.len += padlen; 1072 m->m_len = m->m_pkthdr.len; 1073 } 1074 } 1075 1076 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag, 1077 txd->tx_dmamap, m, txsegs, &nsegs, 0); 1078 if (error != 0) { 1079 txd->tx_flags &= ~VTE_TXMBUF; 1080 return (NULL); 1081 } 1082 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1083 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1084 BUS_DMASYNC_PREWRITE); 1085 1086 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len)); 1087 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr); 1088 sc->vte_cdata.vte_tx_cnt++; 1089 /* Update producer index. */ 1090 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 1091 1092 /* Finally hand over ownership to controller. */ 1093 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 1094 txd->tx_m = m; 1095 1096 return (txd); 1097} 1098 1099static void 1100vte_start(struct ifnet *ifp) 1101{ 1102 struct vte_softc *sc; 1103 1104 sc = ifp->if_softc; 1105 VTE_LOCK(sc); 1106 vte_start_locked(sc); 1107 VTE_UNLOCK(sc); 1108} 1109 1110static void 1111vte_start_locked(struct vte_softc *sc) 1112{ 1113 struct ifnet *ifp; 1114 struct vte_txdesc *txd; 1115 struct mbuf *m_head; 1116 int enq; 1117 1118 ifp = sc->vte_ifp; 1119 1120 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1121 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 1122 return; 1123 1124 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1125 /* Reserve one free TX descriptor. */ 1126 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 1127 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1128 break; 1129 } 1130 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1131 if (m_head == NULL) 1132 break; 1133 /* 1134 * Pack the data into the transmit ring. If we 1135 * don't have room, set the OACTIVE flag and wait 1136 * for the NIC to drain the ring. 1137 */ 1138 if ((txd = vte_encap(sc, &m_head)) == NULL) { 1139 if (m_head != NULL) 1140 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1141 break; 1142 } 1143 1144 enq++; 1145 /* 1146 * If there's a BPF listener, bounce a copy of this frame 1147 * to him. 1148 */ 1149 ETHER_BPF_MTAP(ifp, m_head); 1150 /* Free consumed TX frame. */ 1151 if ((txd->tx_flags & VTE_TXMBUF) != 0) 1152 m_freem(m_head); 1153 } 1154 1155 if (enq > 0) { 1156 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1157 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1158 BUS_DMASYNC_PREWRITE); 1159 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 1160 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 1161 } 1162} 1163 1164static void 1165vte_watchdog(struct vte_softc *sc) 1166{ 1167 struct ifnet *ifp; 1168 1169 VTE_LOCK_ASSERT(sc); 1170 1171 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 1172 return; 1173 1174 ifp = sc->vte_ifp; 1175 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n"); 1176 ifp->if_oerrors++; 1177 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1178 vte_init_locked(sc); 1179 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1180 vte_start_locked(sc); 1181} 1182 1183static int 1184vte_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1185{ 1186 struct vte_softc *sc; 1187 struct ifreq *ifr; 1188 struct mii_data *mii; 1189 int error; 1190 1191 sc = ifp->if_softc; 1192 ifr = (struct ifreq *)data; 1193 error = 0; 1194 switch (cmd) { 1195 case SIOCSIFFLAGS: 1196 VTE_LOCK(sc); 1197 if ((ifp->if_flags & IFF_UP) != 0) { 1198 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1199 ((ifp->if_flags ^ sc->vte_if_flags) & 1200 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1201 vte_rxfilter(sc); 1202 else 1203 vte_init_locked(sc); 1204 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1205 vte_stop(sc); 1206 sc->vte_if_flags = ifp->if_flags; 1207 VTE_UNLOCK(sc); 1208 break; 1209 case SIOCADDMULTI: 1210 case SIOCDELMULTI: 1211 VTE_LOCK(sc); 1212 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1213 vte_rxfilter(sc); 1214 VTE_UNLOCK(sc); 1215 break; 1216 case SIOCSIFMEDIA: 1217 case SIOCGIFMEDIA: 1218 mii = device_get_softc(sc->vte_miibus); 1219 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1220 break; 1221 default: 1222 error = ether_ioctl(ifp, cmd, data); 1223 break; 1224 } 1225 1226 return (error); 1227} 1228 1229static void 1230vte_mac_config(struct vte_softc *sc) 1231{ 1232 struct mii_data *mii; 1233 uint16_t mcr; 1234 1235 VTE_LOCK_ASSERT(sc); 1236 1237 mii = device_get_softc(sc->vte_miibus); 1238 mcr = CSR_READ_2(sc, VTE_MCR0); 1239 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1240 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1241 mcr |= MCR0_FULL_DUPLEX; 1242#ifdef notyet 1243 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1244 mcr |= MCR0_FC_ENB; 1245 /* 1246 * The data sheet is not clear whether the controller 1247 * honors received pause frames or not. The is no 1248 * separate control bit for RX pause frame so just 1249 * enable MCR0_FC_ENB bit. 1250 */ 1251 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1252 mcr |= MCR0_FC_ENB; 1253#endif 1254 } 1255 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1256} 1257 1258static void 1259vte_stats_clear(struct vte_softc *sc) 1260{ 1261 1262 /* Reading counter registers clears its contents. */ 1263 CSR_READ_2(sc, VTE_CNT_RX_DONE); 1264 CSR_READ_2(sc, VTE_CNT_MECNT0); 1265 CSR_READ_2(sc, VTE_CNT_MECNT1); 1266 CSR_READ_2(sc, VTE_CNT_MECNT2); 1267 CSR_READ_2(sc, VTE_CNT_MECNT3); 1268 CSR_READ_2(sc, VTE_CNT_TX_DONE); 1269 CSR_READ_2(sc, VTE_CNT_MECNT4); 1270 CSR_READ_2(sc, VTE_CNT_PAUSE); 1271} 1272 1273static void 1274vte_stats_update(struct vte_softc *sc) 1275{ 1276 struct vte_hw_stats *stat; 1277 struct ifnet *ifp; 1278 uint16_t value; 1279 1280 VTE_LOCK_ASSERT(sc); 1281 1282 ifp = sc->vte_ifp; 1283 stat = &sc->vte_stats; 1284 1285 CSR_READ_2(sc, VTE_MECISR); 1286 /* RX stats. */ 1287 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 1288 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 1289 stat->rx_bcast_frames += (value >> 8); 1290 stat->rx_mcast_frames += (value & 0xFF); 1291 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 1292 stat->rx_runts += (value >> 8); 1293 stat->rx_crcerrs += (value & 0xFF); 1294 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 1295 stat->rx_long_frames += (value & 0xFF); 1296 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 1297 stat->rx_fifo_full += (value >> 8); 1298 stat->rx_desc_unavail += (value & 0xFF); 1299 1300 /* TX stats. */ 1301 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 1302 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 1303 stat->tx_underruns += (value >> 8); 1304 stat->tx_late_colls += (value & 0xFF); 1305 1306 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 1307 stat->tx_pause_frames += (value >> 8); 1308 stat->rx_pause_frames += (value & 0xFF); 1309 1310 /* Update ifp counters. */ 1311 ifp->if_opackets = stat->tx_frames; 1312 ifp->if_collisions = stat->tx_late_colls; 1313 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 1314 ifp->if_ipackets = stat->rx_frames; 1315 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 1316 stat->rx_long_frames + stat->rx_fifo_full; 1317} 1318 1319static void 1320vte_intr(void *arg) 1321{ 1322 struct vte_softc *sc; 1323 struct ifnet *ifp; 1324 uint16_t status; 1325 int n; 1326 1327 sc = (struct vte_softc *)arg; 1328 VTE_LOCK(sc); 1329 1330 ifp = sc->vte_ifp; 1331 /* Reading VTE_MISR acknowledges interrupts. */ 1332 status = CSR_READ_2(sc, VTE_MISR); 1333 if ((status & VTE_INTRS) == 0) { 1334 /* Not ours. */ 1335 VTE_UNLOCK(sc); 1336 return; 1337 } 1338 1339 /* Disable interrupts. */ 1340 CSR_WRITE_2(sc, VTE_MIER, 0); 1341 for (n = 8; (status & VTE_INTRS) != 0;) { 1342 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1343 break; 1344 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 1345 MISR_RX_FIFO_FULL)) != 0) 1346 vte_rxeof(sc); 1347 if ((status & MISR_TX_DONE) != 0) 1348 vte_txeof(sc); 1349 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 1350 vte_stats_update(sc); 1351 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1352 vte_start_locked(sc); 1353 if (--n > 0) 1354 status = CSR_READ_2(sc, VTE_MISR); 1355 else 1356 break; 1357 } 1358 1359 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1360 /* Re-enable interrupts. */ 1361 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1362 } 1363 VTE_UNLOCK(sc); 1364} 1365 1366static void 1367vte_txeof(struct vte_softc *sc) 1368{ 1369 struct ifnet *ifp; 1370 struct vte_txdesc *txd; 1371 uint16_t status; 1372 int cons, prog; 1373 1374 VTE_LOCK_ASSERT(sc); 1375 1376 ifp = sc->vte_ifp; 1377 1378 if (sc->vte_cdata.vte_tx_cnt == 0) 1379 return; 1380 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1381 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD | 1382 BUS_DMASYNC_POSTWRITE); 1383 cons = sc->vte_cdata.vte_tx_cons; 1384 /* 1385 * Go through our TX list and free mbufs for those 1386 * frames which have been transmitted. 1387 */ 1388 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1389 txd = &sc->vte_cdata.vte_txdesc[cons]; 1390 status = le16toh(txd->tx_desc->dtst); 1391 if ((status & VTE_DTST_TX_OWN) != 0) 1392 break; 1393 sc->vte_cdata.vte_tx_cnt--; 1394 /* Reclaim transmitted mbufs. */ 1395 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1396 BUS_DMASYNC_POSTWRITE); 1397 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap); 1398 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1399 m_freem(txd->tx_m); 1400 txd->tx_flags &= ~VTE_TXMBUF; 1401 txd->tx_m = NULL; 1402 prog++; 1403 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1404 } 1405 1406 if (prog > 0) { 1407 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1408 sc->vte_cdata.vte_tx_cons = cons; 1409 /* 1410 * Unarm watchdog timer only when there is no pending 1411 * frames in TX queue. 1412 */ 1413 if (sc->vte_cdata.vte_tx_cnt == 0) 1414 sc->vte_watchdog_timer = 0; 1415 } 1416} 1417 1418static int 1419vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1420{ 1421 struct mbuf *m; 1422 bus_dma_segment_t segs[1]; 1423 bus_dmamap_t map; 1424 int nsegs; 1425 1426 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1427 if (m == NULL) 1428 return (ENOBUFS); 1429 m->m_len = m->m_pkthdr.len = MCLBYTES; 1430 m_adj(m, sizeof(uint32_t)); 1431 1432 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag, 1433 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1434 m_freem(m); 1435 return (ENOBUFS); 1436 } 1437 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1438 1439 if (rxd->rx_m != NULL) { 1440 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1441 BUS_DMASYNC_POSTREAD); 1442 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap); 1443 } 1444 map = rxd->rx_dmamap; 1445 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1446 sc->vte_cdata.vte_rx_sparemap = map; 1447 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1448 BUS_DMASYNC_PREREAD); 1449 rxd->rx_m = m; 1450 rxd->rx_desc->drbp = htole32(segs[0].ds_addr); 1451 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len)); 1452 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1453 1454 return (0); 1455} 1456 1457/* 1458 * It's not supposed to see this controller on strict-alignment 1459 * architectures but make it work for completeness. 1460 */ 1461#ifndef __NO_STRICT_ALIGNMENT 1462static struct mbuf * 1463vte_fixup_rx(struct ifnet *ifp, struct mbuf *m) 1464{ 1465 uint16_t *src, *dst; 1466 int i; 1467 1468 src = mtod(m, uint16_t *); 1469 dst = src - 1; 1470 1471 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1472 *dst++ = *src++; 1473 m->m_data -= ETHER_ALIGN; 1474 return (m); 1475} 1476#endif 1477 1478static void 1479vte_rxeof(struct vte_softc *sc) 1480{ 1481 struct ifnet *ifp; 1482 struct vte_rxdesc *rxd; 1483 struct mbuf *m; 1484 uint16_t status, total_len; 1485 int cons, prog; 1486 1487 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1488 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD | 1489 BUS_DMASYNC_POSTWRITE); 1490 cons = sc->vte_cdata.vte_rx_cons; 1491 ifp = sc->vte_ifp; 1492 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; prog++, 1493 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1494 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1495 status = le16toh(rxd->rx_desc->drst); 1496 if ((status & VTE_DRST_RX_OWN) != 0) 1497 break; 1498 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1499 m = rxd->rx_m; 1500 if ((status & VTE_DRST_RX_OK) == 0) { 1501 /* Discard errored frame. */ 1502 rxd->rx_desc->drlen = 1503 htole16(MCLBYTES - sizeof(uint32_t)); 1504 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1505 continue; 1506 } 1507 if (vte_newbuf(sc, rxd) != 0) { 1508 ifp->if_iqdrops++; 1509 rxd->rx_desc->drlen = 1510 htole16(MCLBYTES - sizeof(uint32_t)); 1511 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1512 continue; 1513 } 1514 1515 /* 1516 * It seems there is no way to strip FCS bytes. 1517 */ 1518 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1519 m->m_pkthdr.rcvif = ifp; 1520#ifndef __NO_STRICT_ALIGNMENT 1521 vte_fixup_rx(ifp, m); 1522#endif 1523 VTE_UNLOCK(sc); 1524 (*ifp->if_input)(ifp, m); 1525 VTE_LOCK(sc); 1526 } 1527 1528 if (prog > 0) { 1529 /* Update the consumer index. */ 1530 sc->vte_cdata.vte_rx_cons = cons; 1531 /* 1532 * Sync updated RX descriptors such that controller see 1533 * modified RX buffer addresses. 1534 */ 1535 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1536 sc->vte_cdata.vte_rx_ring_map, 1537 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1538#ifdef notyet 1539 /* 1540 * Update residue counter. Controller does not 1541 * keep track of number of available RX descriptors 1542 * such that driver should have to update VTE_MRDCR 1543 * to make controller know how many free RX 1544 * descriptors were added to controller. This is 1545 * a similar mechanism used in VIA velocity 1546 * controllers and it indicates controller just 1547 * polls OWN bit of current RX descriptor pointer. 1548 * A couple of severe issues were seen on sample 1549 * board where the controller continuously emits TX 1550 * pause frames once RX pause threshold crossed. 1551 * Once triggered it never recovered form that 1552 * state, I couldn't find a way to make it back to 1553 * work at least. This issue effectively 1554 * disconnected the system from network. Also, the 1555 * controller used 00:00:00:00:00:00 as source 1556 * station address of TX pause frame. Probably this 1557 * is one of reason why vendor recommends not to 1558 * enable flow control on R6040 controller. 1559 */ 1560 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1561 (((VTE_RX_RING_CNT * 2) / 10) << 1562 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1563#endif 1564 } 1565} 1566 1567static void 1568vte_tick(void *arg) 1569{ 1570 struct vte_softc *sc; 1571 struct mii_data *mii; 1572 1573 sc = (struct vte_softc *)arg; 1574 1575 VTE_LOCK_ASSERT(sc); 1576 1577 mii = device_get_softc(sc->vte_miibus); 1578 mii_tick(mii); 1579 vte_stats_update(sc); 1580 vte_txeof(sc); 1581 vte_watchdog(sc); 1582 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1583} 1584 1585static void 1586vte_reset(struct vte_softc *sc) 1587{ 1588 uint16_t mcr; 1589 int i; 1590 1591 mcr = CSR_READ_2(sc, VTE_MCR1); 1592 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1593 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1594 DELAY(10); 1595 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1596 break; 1597 } 1598 if (i == 0) 1599 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1600 /* 1601 * Follow the guide of vendor recommended way to reset MAC. 1602 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1603 * not reliable so manually reset internal state machine. 1604 */ 1605 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1606 CSR_WRITE_2(sc, VTE_MACSM, 0); 1607 DELAY(5000); 1608} 1609 1610static void 1611vte_init(void *xsc) 1612{ 1613 struct vte_softc *sc; 1614 1615 sc = (struct vte_softc *)xsc; 1616 VTE_LOCK(sc); 1617 vte_init_locked(sc); 1618 VTE_UNLOCK(sc); 1619} 1620 1621static void 1622vte_init_locked(struct vte_softc *sc) 1623{ 1624 struct ifnet *ifp; 1625 bus_addr_t paddr; 1626 uint8_t *eaddr; 1627 1628 VTE_LOCK_ASSERT(sc); 1629 1630 ifp = sc->vte_ifp; 1631 1632 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1633 return; 1634 /* 1635 * Cancel any pending I/O. 1636 */ 1637 vte_stop(sc); 1638 /* 1639 * Reset the chip to a known state. 1640 */ 1641 vte_reset(sc); 1642 1643 /* Initialize RX descriptors. */ 1644 if (vte_init_rx_ring(sc) != 0) { 1645 device_printf(sc->vte_dev, "no memory for RX buffers.\n"); 1646 vte_stop(sc); 1647 return; 1648 } 1649 if (vte_init_tx_ring(sc) != 0) { 1650 device_printf(sc->vte_dev, "no memory for TX buffers.\n"); 1651 vte_stop(sc); 1652 return; 1653 } 1654 1655 /* 1656 * Reprogram the station address. Controller supports up 1657 * to 4 different station addresses so driver programs the 1658 * first station address as its own ethernet address and 1659 * configure the remaining three addresses as perfect 1660 * multicast addresses. 1661 */ 1662 eaddr = IF_LLADDR(sc->vte_ifp); 1663 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1664 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1665 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1666 1667 /* Set TX descriptor base addresses. */ 1668 paddr = sc->vte_cdata.vte_tx_ring_paddr; 1669 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1670 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1671 /* Set RX descriptor base addresses. */ 1672 paddr = sc->vte_cdata.vte_rx_ring_paddr; 1673 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1674 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1675 /* 1676 * Initialize RX descriptor residue counter and set RX 1677 * pause threshold to 20% of available RX descriptors. 1678 * See comments on vte_rxeof() for details on flow control 1679 * issues. 1680 */ 1681 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1682 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1683 1684 /* 1685 * Always use maximum frame size that controller can 1686 * support. Otherwise received frames that has longer 1687 * frame length than vte(4) MTU would be silently dropped 1688 * in controller. This would break path-MTU discovery as 1689 * sender wouldn't get any responses from receiver. The 1690 * RX buffer size should be multiple of 4. 1691 * Note, jumbo frames are silently ignored by controller 1692 * and even MAC counters do not detect them. 1693 */ 1694 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1695 1696 /* Configure FIFO. */ 1697 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1698 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1699 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1700 1701 /* 1702 * Configure TX/RX MACs. Actual resolved duplex and flow 1703 * control configuration is done after detecting a valid 1704 * link. Note, we don't generate early interrupt here 1705 * as well since FreeBSD does not have interrupt latency 1706 * problems like Windows. 1707 */ 1708 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1709 /* 1710 * We manually keep track of PHY status changes to 1711 * configure resolved duplex and flow control since only 1712 * duplex configuration can be automatically reflected to 1713 * MCR0. 1714 */ 1715 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1716 MCR1_EXCESS_COL_RETRY_16); 1717 1718 /* Initialize RX filter. */ 1719 vte_rxfilter(sc); 1720 1721 /* Disable TX/RX interrupt moderation control. */ 1722 CSR_WRITE_2(sc, VTE_MRICR, 0); 1723 CSR_WRITE_2(sc, VTE_MTICR, 0); 1724 1725 /* Enable MAC event counter interrupts. */ 1726 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1727 /* Clear MAC statistics. */ 1728 vte_stats_clear(sc); 1729 1730 /* Acknowledge all pending interrupts and clear it. */ 1731 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1732 CSR_WRITE_2(sc, VTE_MISR, 0); 1733 1734 sc->vte_flags &= ~VTE_FLAG_LINK; 1735 /* Switch to the current media. */ 1736 vte_mediachange_locked(ifp); 1737 1738 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1739 1740 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1741 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1742} 1743 1744static void 1745vte_stop(struct vte_softc *sc) 1746{ 1747 struct ifnet *ifp; 1748 struct vte_txdesc *txd; 1749 struct vte_rxdesc *rxd; 1750 int i; 1751 1752 VTE_LOCK_ASSERT(sc); 1753 /* 1754 * Mark the interface down and cancel the watchdog timer. 1755 */ 1756 ifp = sc->vte_ifp; 1757 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1758 sc->vte_flags &= ~VTE_FLAG_LINK; 1759 callout_stop(&sc->vte_tick_ch); 1760 sc->vte_watchdog_timer = 0; 1761 vte_stats_update(sc); 1762 /* Disable interrupts. */ 1763 CSR_WRITE_2(sc, VTE_MIER, 0); 1764 CSR_WRITE_2(sc, VTE_MECIER, 0); 1765 /* Stop RX/TX MACs. */ 1766 vte_stop_mac(sc); 1767 /* Clear interrupts. */ 1768 CSR_READ_2(sc, VTE_MISR); 1769 /* 1770 * Free TX/RX mbufs still in the queues. 1771 */ 1772 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1773 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1774 if (rxd->rx_m != NULL) { 1775 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, 1776 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1777 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, 1778 rxd->rx_dmamap); 1779 m_freem(rxd->rx_m); 1780 rxd->rx_m = NULL; 1781 } 1782 } 1783 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1784 txd = &sc->vte_cdata.vte_txdesc[i]; 1785 if (txd->tx_m != NULL) { 1786 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, 1787 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1788 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, 1789 txd->tx_dmamap); 1790 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1791 m_freem(txd->tx_m); 1792 txd->tx_m = NULL; 1793 txd->tx_flags &= ~VTE_TXMBUF; 1794 } 1795 } 1796 /* Free TX mbuf pools used for deep copy. */ 1797 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1798 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1799 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1800 sc->vte_cdata.vte_txmbufs[i] = NULL; 1801 } 1802 } 1803} 1804 1805static void 1806vte_start_mac(struct vte_softc *sc) 1807{ 1808 uint16_t mcr; 1809 int i; 1810 1811 VTE_LOCK_ASSERT(sc); 1812 1813 /* Enable RX/TX MACs. */ 1814 mcr = CSR_READ_2(sc, VTE_MCR0); 1815 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1816 (MCR0_RX_ENB | MCR0_TX_ENB)) { 1817 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1818 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1819 for (i = VTE_TIMEOUT; i > 0; i--) { 1820 mcr = CSR_READ_2(sc, VTE_MCR0); 1821 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1822 (MCR0_RX_ENB | MCR0_TX_ENB)) 1823 break; 1824 DELAY(10); 1825 } 1826 if (i == 0) 1827 device_printf(sc->vte_dev, 1828 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1829 } 1830} 1831 1832static void 1833vte_stop_mac(struct vte_softc *sc) 1834{ 1835 uint16_t mcr; 1836 int i; 1837 1838 VTE_LOCK_ASSERT(sc); 1839 1840 /* Disable RX/TX MACs. */ 1841 mcr = CSR_READ_2(sc, VTE_MCR0); 1842 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1843 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1844 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1845 for (i = VTE_TIMEOUT; i > 0; i--) { 1846 mcr = CSR_READ_2(sc, VTE_MCR0); 1847 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1848 break; 1849 DELAY(10); 1850 } 1851 if (i == 0) 1852 device_printf(sc->vte_dev, 1853 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1854 } 1855} 1856 1857static int 1858vte_init_tx_ring(struct vte_softc *sc) 1859{ 1860 struct vte_tx_desc *desc; 1861 struct vte_txdesc *txd; 1862 bus_addr_t addr; 1863 int i; 1864 1865 VTE_LOCK_ASSERT(sc); 1866 1867 sc->vte_cdata.vte_tx_prod = 0; 1868 sc->vte_cdata.vte_tx_cons = 0; 1869 sc->vte_cdata.vte_tx_cnt = 0; 1870 1871 /* Pre-allocate TX mbufs for deep copy. */ 1872 if (tx_deep_copy != 0) { 1873 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1874 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT, 1875 MT_DATA, M_PKTHDR); 1876 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1877 return (ENOBUFS); 1878 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1879 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1880 } 1881 } 1882 desc = sc->vte_cdata.vte_tx_ring; 1883 bzero(desc, VTE_TX_RING_SZ); 1884 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1885 txd = &sc->vte_cdata.vte_txdesc[i]; 1886 txd->tx_m = NULL; 1887 if (i != VTE_TX_RING_CNT - 1) 1888 addr = sc->vte_cdata.vte_tx_ring_paddr + 1889 sizeof(struct vte_tx_desc) * (i + 1); 1890 else 1891 addr = sc->vte_cdata.vte_tx_ring_paddr + 1892 sizeof(struct vte_tx_desc) * 0; 1893 desc = &sc->vte_cdata.vte_tx_ring[i]; 1894 desc->dtnp = htole32(addr); 1895 txd->tx_desc = desc; 1896 } 1897 1898 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1899 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1900 BUS_DMASYNC_PREWRITE); 1901 return (0); 1902} 1903 1904static int 1905vte_init_rx_ring(struct vte_softc *sc) 1906{ 1907 struct vte_rx_desc *desc; 1908 struct vte_rxdesc *rxd; 1909 bus_addr_t addr; 1910 int i; 1911 1912 VTE_LOCK_ASSERT(sc); 1913 1914 sc->vte_cdata.vte_rx_cons = 0; 1915 desc = sc->vte_cdata.vte_rx_ring; 1916 bzero(desc, VTE_RX_RING_SZ); 1917 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1918 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1919 rxd->rx_m = NULL; 1920 if (i != VTE_RX_RING_CNT - 1) 1921 addr = sc->vte_cdata.vte_rx_ring_paddr + 1922 sizeof(struct vte_rx_desc) * (i + 1); 1923 else 1924 addr = sc->vte_cdata.vte_rx_ring_paddr + 1925 sizeof(struct vte_rx_desc) * 0; 1926 desc = &sc->vte_cdata.vte_rx_ring[i]; 1927 desc->drnp = htole32(addr); 1928 rxd->rx_desc = desc; 1929 if (vte_newbuf(sc, rxd) != 0) 1930 return (ENOBUFS); 1931 } 1932 1933 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1934 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD | 1935 BUS_DMASYNC_PREWRITE); 1936 1937 return (0); 1938} 1939 1940static void 1941vte_rxfilter(struct vte_softc *sc) 1942{ 1943 struct ifnet *ifp; 1944 struct ifmultiaddr *ifma; 1945 uint8_t *eaddr; 1946 uint32_t crc; 1947 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1948 uint16_t mchash[4], mcr; 1949 int i, nperf; 1950 1951 VTE_LOCK_ASSERT(sc); 1952 1953 ifp = sc->vte_ifp; 1954 1955 bzero(mchash, sizeof(mchash)); 1956 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1957 rxfilt_perf[i][0] = 0xFFFF; 1958 rxfilt_perf[i][1] = 0xFFFF; 1959 rxfilt_perf[i][2] = 0xFFFF; 1960 } 1961 1962 mcr = CSR_READ_2(sc, VTE_MCR0); 1963 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST); 1964 mcr |= MCR0_BROADCAST_DIS; 1965 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1966 mcr &= ~MCR0_BROADCAST_DIS; 1967 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1968 if ((ifp->if_flags & IFF_PROMISC) != 0) 1969 mcr |= MCR0_PROMISC; 1970 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1971 mcr |= MCR0_MULTICAST; 1972 mchash[0] = 0xFFFF; 1973 mchash[1] = 0xFFFF; 1974 mchash[2] = 0xFFFF; 1975 mchash[3] = 0xFFFF; 1976 goto chipit; 1977 } 1978 1979 nperf = 0; 1980 if_maddr_rlock(ifp); 1981 TAILQ_FOREACH(ifma, &sc->vte_ifp->if_multiaddrs, ifma_link) { 1982 if (ifma->ifma_addr->sa_family != AF_LINK) 1983 continue; 1984 /* 1985 * Program the first 3 multicast groups into 1986 * the perfect filter. For all others, use the 1987 * hash table. 1988 */ 1989 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1990 eaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1991 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1992 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1993 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1994 nperf++; 1995 continue; 1996 } 1997 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1998 ifma->ifma_addr), ETHER_ADDR_LEN); 1999 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 2000 } 2001 if_maddr_runlock(ifp); 2002 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 2003 mchash[3] != 0) 2004 mcr |= MCR0_MULTICAST; 2005 2006chipit: 2007 /* Program multicast hash table. */ 2008 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 2009 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 2010 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 2011 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 2012 /* Program perfect filter table. */ 2013 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2014 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 2015 rxfilt_perf[i][0]); 2016 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 2017 rxfilt_perf[i][1]); 2018 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 2019 rxfilt_perf[i][2]); 2020 } 2021 CSR_WRITE_2(sc, VTE_MCR0, mcr); 2022 CSR_READ_2(sc, VTE_MCR0); 2023} 2024 2025static int 2026sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2027{ 2028 int error, value; 2029 2030 if (arg1 == NULL) 2031 return (EINVAL); 2032 value = *(int *)arg1; 2033 error = sysctl_handle_int(oidp, &value, 0, req); 2034 if (error || req->newptr == NULL) 2035 return (error); 2036 if (value < low || value > high) 2037 return (EINVAL); 2038 *(int *)arg1 = value; 2039 2040 return (0); 2041} 2042 2043static int 2044sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS) 2045{ 2046 2047 return (sysctl_int_range(oidp, arg1, arg2, req, 2048 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX)); 2049} 2050