if_vr.c revision 51446
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/vr/if_vr.c 51446 1999-09-20 06:50:52Z obrien $ 33 */ 34 35/* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include "bpf.h" 63 64#include <sys/param.h> 65#include <sys/systm.h> 66#include <sys/sockio.h> 67#include <sys/mbuf.h> 68#include <sys/malloc.h> 69#include <sys/kernel.h> 70#include <sys/socket.h> 71 72#include <net/if.h> 73#include <net/if_arp.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77 78#if NBPF > 0 79#include <net/bpf.h> 80#endif 81 82#include "opt_bdg.h" 83#ifdef BRIDGE 84#include <net/bridge.h> 85#endif /* BRIDGE */ 86 87#include <vm/vm.h> /* for vtophys */ 88#include <vm/pmap.h> /* for vtophys */ 89#include <machine/clock.h> /* for DELAY */ 90#include <machine/bus_pio.h> 91#include <machine/bus_memio.h> 92#include <machine/bus.h> 93#include <machine/resource.h> 94#include <sys/bus.h> 95#include <sys/rman.h> 96 97#include <dev/mii/mii.h> 98#include <dev/mii/miivar.h> 99 100#include <pci/pcireg.h> 101#include <pci/pcivar.h> 102 103#define VR_USEIOSPACE 104 105#include <pci/if_vrreg.h> 106 107/* "controller miibus0" required. See GENERIC if you get errors here. */ 108#include "miibus_if.h" 109 110#ifndef lint 111static const char rcsid[] = 112 "$FreeBSD: head/sys/dev/vr/if_vr.c 51446 1999-09-20 06:50:52Z obrien $"; 113#endif 114 115/* 116 * Various supported device vendors/types and their names. 117 */ 118static struct vr_type vr_devs[] = { 119 { VIA_VENDORID, VIA_DEVICEID_RHINE, 120 "VIA VT3043 Rhine I 10/100BaseTX" }, 121 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 122 "VIA VT86C100A Rhine II 10/100BaseTX" }, 123 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 124 "Delta Electronics Rhine II 10/100BaseTX" }, 125 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 126 "Addtron Technology Rhine II 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int vr_probe __P((device_t)); 131static int vr_attach __P((device_t)); 132static int vr_detach __P((device_t)); 133 134static int vr_newbuf __P((struct vr_softc *, 135 struct vr_chain_onefrag *, 136 struct mbuf *)); 137static int vr_encap __P((struct vr_softc *, struct vr_chain *, 138 struct mbuf * )); 139 140static void vr_rxeof __P((struct vr_softc *)); 141static void vr_rxeoc __P((struct vr_softc *)); 142static void vr_txeof __P((struct vr_softc *)); 143static void vr_txeoc __P((struct vr_softc *)); 144static void vr_tick __P((void *)); 145static void vr_intr __P((void *)); 146static void vr_start __P((struct ifnet *)); 147static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 148static void vr_init __P((void *)); 149static void vr_stop __P((struct vr_softc *)); 150static void vr_watchdog __P((struct ifnet *)); 151static void vr_shutdown __P((device_t)); 152static int vr_ifmedia_upd __P((struct ifnet *)); 153static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 154 155static void vr_mii_sync __P((struct vr_softc *)); 156static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 157static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 158static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 159static int vr_miibus_readreg __P((device_t, int, int)); 160static int vr_miibus_writereg __P((device_t, int, int, int)); 161static void vr_miibus_statchg __P((device_t)); 162 163static void vr_setcfg __P((struct vr_softc *, int)); 164static u_int8_t vr_calchash __P((u_int8_t *)); 165static void vr_setmulti __P((struct vr_softc *)); 166static void vr_reset __P((struct vr_softc *)); 167static int vr_list_rx_init __P((struct vr_softc *)); 168static int vr_list_tx_init __P((struct vr_softc *)); 169 170#ifdef VR_USEIOSPACE 171#define VR_RES SYS_RES_IOPORT 172#define VR_RID VR_PCI_LOIO 173#else 174#define VR_RES SYS_RES_MEMORY 175#define VR_RID VR_PCI_LOMEM 176#endif 177 178static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195}; 196 197static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201}; 202 203static devclass_t vr_devclass; 204 205DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 206DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 207 208#define VR_SETBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) | x) 211 212#define VR_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_1(sc, reg, \ 214 CSR_READ_1(sc, reg) & ~x) 215 216#define VR_SETBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) | x) 219 220#define VR_CLRBIT16(sc, reg, x) \ 221 CSR_WRITE_2(sc, reg, \ 222 CSR_READ_2(sc, reg) & ~x) 223 224#define VR_SETBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | x) 227 228#define VR_CLRBIT32(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~x) 231 232#define SIO_SET(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) | x) 235 236#define SIO_CLR(x) \ 237 CSR_WRITE_1(sc, VR_MIICMD, \ 238 CSR_READ_1(sc, VR_MIICMD) & ~x) 239 240/* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243static void vr_mii_sync(sc) 244 struct vr_softc *sc; 245{ 246 register int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 257 return; 258} 259 260/* 261 * Clock a series of bits through the MII. 262 */ 263static void vr_mii_send(sc, bits, cnt) 264 struct vr_softc *sc; 265 u_int32_t bits; 266 int cnt; 267{ 268 int i; 269 270 SIO_CLR(VR_MIICMD_CLK); 271 272 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 273 if (bits & i) { 274 SIO_SET(VR_MIICMD_DATAIN); 275 } else { 276 SIO_CLR(VR_MIICMD_DATAIN); 277 } 278 DELAY(1); 279 SIO_CLR(VR_MIICMD_CLK); 280 DELAY(1); 281 SIO_SET(VR_MIICMD_CLK); 282 } 283} 284 285/* 286 * Read an PHY register through the MII. 287 */ 288static int vr_mii_readreg(sc, frame) 289 struct vr_softc *sc; 290 struct vr_mii_frame *frame; 291 292{ 293 int i, ack, s; 294 295 s = splimp(); 296 297 /* 298 * Set up frame for RX. 299 */ 300 frame->mii_stdelim = VR_MII_STARTDELIM; 301 frame->mii_opcode = VR_MII_READOP; 302 frame->mii_turnaround = 0; 303 frame->mii_data = 0; 304 305 CSR_WRITE_1(sc, VR_MIICMD, 0); 306 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 307 308 /* 309 * Turn on data xmit. 310 */ 311 SIO_SET(VR_MIICMD_DIR); 312 313 vr_mii_sync(sc); 314 315 /* 316 * Send command/address info. 317 */ 318 vr_mii_send(sc, frame->mii_stdelim, 2); 319 vr_mii_send(sc, frame->mii_opcode, 2); 320 vr_mii_send(sc, frame->mii_phyaddr, 5); 321 vr_mii_send(sc, frame->mii_regaddr, 5); 322 323 /* Idle bit */ 324 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 325 DELAY(1); 326 SIO_SET(VR_MIICMD_CLK); 327 DELAY(1); 328 329 /* Turn off xmit. */ 330 SIO_CLR(VR_MIICMD_DIR); 331 332 /* Check for ack */ 333 SIO_CLR(VR_MIICMD_CLK); 334 DELAY(1); 335 SIO_SET(VR_MIICMD_CLK); 336 DELAY(1); 337 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 338 339 /* 340 * Now try reading data bits. If the ack failed, we still 341 * need to clock through 16 cycles to keep the PHY(s) in sync. 342 */ 343 if (ack) { 344 for(i = 0; i < 16; i++) { 345 SIO_CLR(VR_MIICMD_CLK); 346 DELAY(1); 347 SIO_SET(VR_MIICMD_CLK); 348 DELAY(1); 349 } 350 goto fail; 351 } 352 353 for (i = 0x8000; i; i >>= 1) { 354 SIO_CLR(VR_MIICMD_CLK); 355 DELAY(1); 356 if (!ack) { 357 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 358 frame->mii_data |= i; 359 DELAY(1); 360 } 361 SIO_SET(VR_MIICMD_CLK); 362 DELAY(1); 363 } 364 365fail: 366 367 SIO_CLR(VR_MIICMD_CLK); 368 DELAY(1); 369 SIO_SET(VR_MIICMD_CLK); 370 DELAY(1); 371 372 splx(s); 373 374 if (ack) 375 return(1); 376 return(0); 377} 378 379/* 380 * Write to a PHY register through the MII. 381 */ 382static int vr_mii_writereg(sc, frame) 383 struct vr_softc *sc; 384 struct vr_mii_frame *frame; 385 386{ 387 int s; 388 389 s = splimp(); 390 391 CSR_WRITE_1(sc, VR_MIICMD, 0); 392 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 393 394 /* 395 * Set up frame for TX. 396 */ 397 398 frame->mii_stdelim = VR_MII_STARTDELIM; 399 frame->mii_opcode = VR_MII_WRITEOP; 400 frame->mii_turnaround = VR_MII_TURNAROUND; 401 402 /* 403 * Turn on data output. 404 */ 405 SIO_SET(VR_MIICMD_DIR); 406 407 vr_mii_sync(sc); 408 409 vr_mii_send(sc, frame->mii_stdelim, 2); 410 vr_mii_send(sc, frame->mii_opcode, 2); 411 vr_mii_send(sc, frame->mii_phyaddr, 5); 412 vr_mii_send(sc, frame->mii_regaddr, 5); 413 vr_mii_send(sc, frame->mii_turnaround, 2); 414 vr_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 SIO_SET(VR_MIICMD_CLK); 418 DELAY(1); 419 SIO_CLR(VR_MIICMD_CLK); 420 DELAY(1); 421 422 /* 423 * Turn off xmit. 424 */ 425 SIO_CLR(VR_MIICMD_DIR); 426 427 splx(s); 428 429 return(0); 430} 431 432static int vr_miibus_readreg(dev, phy, reg) 433 device_t dev; 434 int phy, reg; 435{ 436 struct vr_softc *sc; 437 struct vr_mii_frame frame; 438 439 sc = device_get_softc(dev); 440 bzero((char *)&frame, sizeof(frame)); 441 442 frame.mii_phyaddr = phy; 443 frame.mii_regaddr = reg; 444 vr_mii_readreg(sc, &frame); 445 446 return(frame.mii_data); 447} 448 449static int vr_miibus_writereg(dev, phy, reg, data) 450 device_t dev; 451 u_int16_t phy, reg, data; 452{ 453 struct vr_softc *sc; 454 struct vr_mii_frame frame; 455 456 sc = device_get_softc(dev); 457 bzero((char *)&frame, sizeof(frame)); 458 459 frame.mii_phyaddr = phy; 460 frame.mii_regaddr = reg; 461 frame.mii_data = data; 462 463 vr_mii_writereg(sc, &frame); 464 465 return(0); 466} 467 468static void vr_miibus_statchg(dev) 469 device_t dev; 470{ 471 struct vr_softc *sc; 472 struct mii_data *mii; 473 474 sc = device_get_softc(dev); 475 mii = device_get_softc(sc->vr_miibus); 476 vr_setcfg(sc, mii->mii_media_active); 477 478 return; 479} 480 481/* 482 * Calculate CRC of a multicast group address, return the lower 6 bits. 483 */ 484static u_int8_t vr_calchash(addr) 485 u_int8_t *addr; 486{ 487 u_int32_t crc, carry; 488 int i, j; 489 u_int8_t c; 490 491 /* Compute CRC for the address value. */ 492 crc = 0xFFFFFFFF; /* initial value */ 493 494 for (i = 0; i < 6; i++) { 495 c = *(addr + i); 496 for (j = 0; j < 8; j++) { 497 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 498 crc <<= 1; 499 c >>= 1; 500 if (carry) 501 crc = (crc ^ 0x04c11db6) | carry; 502 } 503 } 504 505 /* return the filter bit position */ 506 return((crc >> 26) & 0x0000003F); 507} 508 509/* 510 * Program the 64-bit multicast hash filter. 511 */ 512static void vr_setmulti(sc) 513 struct vr_softc *sc; 514{ 515 struct ifnet *ifp; 516 int h = 0; 517 u_int32_t hashes[2] = { 0, 0 }; 518 struct ifmultiaddr *ifma; 519 u_int8_t rxfilt; 520 int mcnt = 0; 521 522 ifp = &sc->arpcom.ac_if; 523 524 rxfilt = CSR_READ_1(sc, VR_RXCFG); 525 526 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 527 rxfilt |= VR_RXCFG_RX_MULTI; 528 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 529 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 530 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 531 return; 532 } 533 534 /* first, zot all the existing hash bits */ 535 CSR_WRITE_4(sc, VR_MAR0, 0); 536 CSR_WRITE_4(sc, VR_MAR1, 0); 537 538 /* now program new ones */ 539 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 540 ifma = ifma->ifma_link.le_next) { 541 if (ifma->ifma_addr->sa_family != AF_LINK) 542 continue; 543 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 544 if (h < 32) 545 hashes[0] |= (1 << h); 546 else 547 hashes[1] |= (1 << (h - 32)); 548 mcnt++; 549 } 550 551 if (mcnt) 552 rxfilt |= VR_RXCFG_RX_MULTI; 553 else 554 rxfilt &= ~VR_RXCFG_RX_MULTI; 555 556 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 557 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 558 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 559 560 return; 561} 562 563/* 564 * In order to fiddle with the 565 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 566 * first have to put the transmit and/or receive logic in the idle state. 567 */ 568static void vr_setcfg(sc, media) 569 struct vr_softc *sc; 570 int media; 571{ 572 int restart = 0; 573 574 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 575 restart = 1; 576 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 577 } 578 579 if ((media & IFM_GMASK) == IFM_FDX) 580 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 581 else 582 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 583 584 if (restart) 585 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 586 587 return; 588} 589 590static void vr_reset(sc) 591 struct vr_softc *sc; 592{ 593 register int i; 594 595 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 596 597 for (i = 0; i < VR_TIMEOUT; i++) { 598 DELAY(10); 599 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 600 break; 601 } 602 if (i == VR_TIMEOUT) 603 printf("vr%d: reset never completed!\n", sc->vr_unit); 604 605 /* Wait a little while for the chip to get its brains in order. */ 606 DELAY(1000); 607 608 return; 609} 610 611/* 612 * Probe for a VIA Rhine chip. Check the PCI vendor and device 613 * IDs against our list and return a device name if we find a match. 614 */ 615static int vr_probe(dev) 616 device_t dev; 617{ 618 struct vr_type *t; 619 620 t = vr_devs; 621 622 while(t->vr_name != NULL) { 623 if ((pci_get_vendor(dev) == t->vr_vid) && 624 (pci_get_device(dev) == t->vr_did)) { 625 device_set_desc(dev, t->vr_name); 626 return(0); 627 } 628 t++; 629 } 630 631 return(ENXIO); 632} 633 634/* 635 * Attach the interface. Allocate softc structures, do ifmedia 636 * setup and ethernet/BPF attach. 637 */ 638static int vr_attach(dev) 639 device_t dev; 640{ 641 int i, s; 642 u_char eaddr[ETHER_ADDR_LEN]; 643 u_int32_t command; 644 struct vr_softc *sc; 645 struct ifnet *ifp; 646 int unit, error = 0, rid; 647 648 s = splimp(); 649 650 sc = device_get_softc(dev); 651 unit = device_get_unit(dev); 652 bzero(sc, sizeof(struct vr_softc *)); 653 654 /* 655 * Handle power management nonsense. 656 */ 657 658 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 659 if (command == 0x01) { 660 661 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 662 if (command & VR_PSTATE_MASK) { 663 u_int32_t iobase, membase, irq; 664 665 /* Save important PCI config data. */ 666 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 667 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 668 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 669 670 /* Reset the power state. */ 671 printf("vr%d: chip is in D%d power mode " 672 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 673 command &= 0xFFFFFFFC; 674 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 675 676 /* Restore PCI config data. */ 677 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 678 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 679 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 680 } 681 } 682 683 /* 684 * Map control/status registers. 685 */ 686 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 687 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 688 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 689 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 690 691#ifdef VR_USEIOSPACE 692 if (!(command & PCIM_CMD_PORTEN)) { 693 printf("vr%d: failed to enable I/O ports!\n", unit); 694 free(sc, M_DEVBUF); 695 goto fail; 696 } 697#else 698 if (!(command & PCIM_CMD_MEMEN)) { 699 printf("vr%d: failed to enable memory mapping!\n", unit); 700 goto fail; 701 } 702#endif 703 704 rid = VR_RID; 705 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 706 0, ~0, 1, RF_ACTIVE); 707 708 if (sc->vr_res == NULL) { 709 printf("vr%d: couldn't map ports/memory\n", unit); 710 error = ENXIO; 711 goto fail; 712 } 713 714 sc->vr_btag = rman_get_bustag(sc->vr_res); 715 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 716 717 /* Allocate interrupt */ 718 rid = 0; 719 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 720 RF_SHAREABLE | RF_ACTIVE); 721 722 if (sc->vr_irq == NULL) { 723 printf("vr%d: couldn't map interrupt\n", unit); 724 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 725 error = ENXIO; 726 goto fail; 727 } 728 729 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 730 vr_intr, sc, &sc->vr_intrhand); 731 732 if (error) { 733 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 734 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 735 printf("vr%d: couldn't set up irq\n", unit); 736 goto fail; 737 } 738 739 /* Reset the adapter. */ 740 vr_reset(sc); 741 742 /* 743 * Get station address. The way the Rhine chips work, 744 * you're not allowed to directly access the EEPROM once 745 * they've been programmed a special way. Consequently, 746 * we need to read the node address from the PAR0 and PAR1 747 * registers. 748 */ 749 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 750 DELAY(200); 751 for (i = 0; i < ETHER_ADDR_LEN; i++) 752 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 753 754 /* 755 * A Rhine chip was detected. Inform the world. 756 */ 757 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 758 759 sc->vr_unit = unit; 760 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 761 762 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 763 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 764 765 if (sc->vr_ldata == NULL) { 766 printf("vr%d: no memory for list buffers!\n", unit); 767 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 768 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 769 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 770 error = ENXIO; 771 goto fail; 772 } 773 774 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 775 776 ifp = &sc->arpcom.ac_if; 777 ifp->if_softc = sc; 778 ifp->if_unit = unit; 779 ifp->if_name = "vr"; 780 ifp->if_mtu = ETHERMTU; 781 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 782 ifp->if_ioctl = vr_ioctl; 783 ifp->if_output = ether_output; 784 ifp->if_start = vr_start; 785 ifp->if_watchdog = vr_watchdog; 786 ifp->if_init = vr_init; 787 ifp->if_baudrate = 10000000; 788 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 789 790 /* 791 * Do MII setup. 792 */ 793 if (mii_phy_probe(dev, &sc->vr_miibus, 794 vr_ifmedia_upd, vr_ifmedia_sts)) { 795 printf("vr%d: MII without any phy!\n", sc->vr_unit); 796 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 797 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 798 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 799 contigfree(sc->vr_ldata, 800 sizeof(struct vr_list_data), M_DEVBUF); 801 error = ENXIO; 802 goto fail; 803 } 804 805 callout_handle_init(&sc->vr_stat_ch); 806 807 /* 808 * Call MI attach routines. 809 */ 810 if_attach(ifp); 811 ether_ifattach(ifp); 812 813#if NBPF > 0 814 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 815#endif 816 817fail: 818 splx(s); 819 return(error); 820} 821 822static int vr_detach(dev) 823 device_t dev; 824{ 825 struct vr_softc *sc; 826 struct ifnet *ifp; 827 int s; 828 829 s = splimp(); 830 831 sc = device_get_softc(dev); 832 ifp = &sc->arpcom.ac_if; 833 834 vr_stop(sc); 835 if_detach(ifp); 836 837 bus_generic_detach(dev); 838 device_delete_child(dev, sc->vr_miibus); 839 840 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 842 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 843 844 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 845 846 splx(s); 847 848 return(0); 849} 850 851/* 852 * Initialize the transmit descriptors. 853 */ 854static int vr_list_tx_init(sc) 855 struct vr_softc *sc; 856{ 857 struct vr_chain_data *cd; 858 struct vr_list_data *ld; 859 int i; 860 861 cd = &sc->vr_cdata; 862 ld = sc->vr_ldata; 863 for (i = 0; i < VR_TX_LIST_CNT; i++) { 864 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 865 if (i == (VR_TX_LIST_CNT - 1)) 866 cd->vr_tx_chain[i].vr_nextdesc = 867 &cd->vr_tx_chain[0]; 868 else 869 cd->vr_tx_chain[i].vr_nextdesc = 870 &cd->vr_tx_chain[i + 1]; 871 } 872 873 cd->vr_tx_free = &cd->vr_tx_chain[0]; 874 cd->vr_tx_tail = cd->vr_tx_head = NULL; 875 876 return(0); 877} 878 879 880/* 881 * Initialize the RX descriptors and allocate mbufs for them. Note that 882 * we arrange the descriptors in a closed ring, so that the last descriptor 883 * points back to the first. 884 */ 885static int vr_list_rx_init(sc) 886 struct vr_softc *sc; 887{ 888 struct vr_chain_data *cd; 889 struct vr_list_data *ld; 890 int i; 891 892 cd = &sc->vr_cdata; 893 ld = sc->vr_ldata; 894 895 for (i = 0; i < VR_RX_LIST_CNT; i++) { 896 cd->vr_rx_chain[i].vr_ptr = 897 (struct vr_desc *)&ld->vr_rx_list[i]; 898 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 899 return(ENOBUFS); 900 if (i == (VR_RX_LIST_CNT - 1)) { 901 cd->vr_rx_chain[i].vr_nextdesc = 902 &cd->vr_rx_chain[0]; 903 ld->vr_rx_list[i].vr_next = 904 vtophys(&ld->vr_rx_list[0]); 905 } else { 906 cd->vr_rx_chain[i].vr_nextdesc = 907 &cd->vr_rx_chain[i + 1]; 908 ld->vr_rx_list[i].vr_next = 909 vtophys(&ld->vr_rx_list[i + 1]); 910 } 911 } 912 913 cd->vr_rx_head = &cd->vr_rx_chain[0]; 914 915 return(0); 916} 917 918/* 919 * Initialize an RX descriptor and attach an MBUF cluster. 920 * Note: the length fields are only 11 bits wide, which means the 921 * largest size we can specify is 2047. This is important because 922 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 923 * overflow the field and make a mess. 924 */ 925static int vr_newbuf(sc, c, m) 926 struct vr_softc *sc; 927 struct vr_chain_onefrag *c; 928 struct mbuf *m; 929{ 930 struct mbuf *m_new = NULL; 931 932 if (m == NULL) { 933 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 934 if (m_new == NULL) { 935 printf("vr%d: no memory for rx list " 936 "-- packet dropped!\n", sc->vr_unit); 937 return(ENOBUFS); 938 } 939 940 MCLGET(m_new, M_DONTWAIT); 941 if (!(m_new->m_flags & M_EXT)) { 942 printf("vr%d: no memory for rx list " 943 "-- packet dropped!\n", sc->vr_unit); 944 m_freem(m_new); 945 return(ENOBUFS); 946 } 947 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 948 } else { 949 m_new = m; 950 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 951 m_new->m_data = m_new->m_ext.ext_buf; 952 } 953 954 m_adj(m_new, sizeof(u_int64_t)); 955 956 c->vr_mbuf = m_new; 957 c->vr_ptr->vr_status = VR_RXSTAT; 958 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 959 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 960 961 return(0); 962} 963 964/* 965 * A frame has been uploaded: pass the resulting mbuf chain up to 966 * the higher level protocols. 967 */ 968static void vr_rxeof(sc) 969 struct vr_softc *sc; 970{ 971 struct ether_header *eh; 972 struct mbuf *m; 973 struct ifnet *ifp; 974 struct vr_chain_onefrag *cur_rx; 975 int total_len = 0; 976 u_int32_t rxstat; 977 978 ifp = &sc->arpcom.ac_if; 979 980 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 981 VR_RXSTAT_OWN)) { 982 struct mbuf *m0 = NULL; 983 984 cur_rx = sc->vr_cdata.vr_rx_head; 985 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 986 m = cur_rx->vr_mbuf; 987 988 /* 989 * If an error occurs, update stats, clear the 990 * status word and leave the mbuf cluster in place: 991 * it should simply get re-used next time this descriptor 992 * comes up in the ring. 993 */ 994 if (rxstat & VR_RXSTAT_RXERR) { 995 ifp->if_ierrors++; 996 printf("vr%d: rx error: ", sc->vr_unit); 997 switch(rxstat & 0x000000FF) { 998 case VR_RXSTAT_CRCERR: 999 printf("crc error\n"); 1000 break; 1001 case VR_RXSTAT_FRAMEALIGNERR: 1002 printf("frame alignment error\n"); 1003 break; 1004 case VR_RXSTAT_FIFOOFLOW: 1005 printf("FIFO overflow\n"); 1006 break; 1007 case VR_RXSTAT_GIANT: 1008 printf("received giant packet\n"); 1009 break; 1010 case VR_RXSTAT_RUNT: 1011 printf("received runt packet\n"); 1012 break; 1013 case VR_RXSTAT_BUSERR: 1014 printf("system bus error\n"); 1015 break; 1016 case VR_RXSTAT_BUFFERR: 1017 printf("rx buffer error\n"); 1018 break; 1019 default: 1020 printf("unknown rx error\n"); 1021 break; 1022 } 1023 vr_newbuf(sc, cur_rx, m); 1024 continue; 1025 } 1026 1027 /* No errors; receive the packet. */ 1028 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1029 1030 /* 1031 * XXX The VIA Rhine chip includes the CRC with every 1032 * received frame, and there's no way to turn this 1033 * behavior off (at least, I can't find anything in 1034 * the manual that explains how to do it) so we have 1035 * to trim off the CRC manually. 1036 */ 1037 total_len -= ETHER_CRC_LEN; 1038 1039 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1040 total_len + ETHER_ALIGN, 0, ifp, NULL); 1041 vr_newbuf(sc, cur_rx, m); 1042 if (m0 == NULL) { 1043 ifp->if_ierrors++; 1044 continue; 1045 } 1046 m_adj(m0, ETHER_ALIGN); 1047 m = m0; 1048 1049 ifp->if_ipackets++; 1050 eh = mtod(m, struct ether_header *); 1051 1052#if NBPF > 0 1053 /* 1054 * Handle BPF listeners. Let the BPF user see the packet, but 1055 * don't pass it up to the ether_input() layer unless it's 1056 * a broadcast packet, multicast packet, matches our ethernet 1057 * address or the interface is in promiscuous mode. 1058 */ 1059 if (ifp->if_bpf) { 1060 bpf_mtap(ifp, m); 1061 if (ifp->if_flags & IFF_PROMISC && 1062 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1063 ETHER_ADDR_LEN) && 1064 (eh->ether_dhost[0] & 1) == 0)) { 1065 m_freem(m); 1066 continue; 1067 } 1068 } 1069#endif /* NBPF>0 */ 1070#ifdef BRIDGE 1071 if (do_bridge) { 1072 struct ifnet *bdg_ifp; 1073 bdg_ifp = bridge_in(m); 1074 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1075 bdg_forward(&m, bdg_ifp); 1076 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1077 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1078 m_freem(m); 1079 continue; 1080 } 1081 } 1082#endif /* BRIDGE */ 1083 1084 /* Remove header from mbuf and pass it on. */ 1085 m_adj(m, sizeof(struct ether_header)); 1086 ether_input(ifp, eh, m); 1087 } 1088 1089 return; 1090} 1091 1092void vr_rxeoc(sc) 1093 struct vr_softc *sc; 1094{ 1095 1096 vr_rxeof(sc); 1097 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1098 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1099 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1100 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1101 1102 return; 1103} 1104 1105/* 1106 * A frame was downloaded to the chip. It's safe for us to clean up 1107 * the list buffers. 1108 */ 1109 1110static void vr_txeof(sc) 1111 struct vr_softc *sc; 1112{ 1113 struct vr_chain *cur_tx; 1114 struct ifnet *ifp; 1115 1116 ifp = &sc->arpcom.ac_if; 1117 1118 /* Clear the timeout timer. */ 1119 ifp->if_timer = 0; 1120 1121 /* Sanity check. */ 1122 if (sc->vr_cdata.vr_tx_head == NULL) 1123 return; 1124 1125 /* 1126 * Go through our tx list and free mbufs for those 1127 * frames that have been transmitted. 1128 */ 1129 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1130 u_int32_t txstat; 1131 1132 cur_tx = sc->vr_cdata.vr_tx_head; 1133 txstat = cur_tx->vr_ptr->vr_status; 1134 1135 if (txstat & VR_TXSTAT_OWN) 1136 break; 1137 1138 if (txstat & VR_TXSTAT_ERRSUM) { 1139 ifp->if_oerrors++; 1140 if (txstat & VR_TXSTAT_DEFER) 1141 ifp->if_collisions++; 1142 if (txstat & VR_TXSTAT_LATECOLL) 1143 ifp->if_collisions++; 1144 } 1145 1146 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1147 1148 ifp->if_opackets++; 1149 if (cur_tx->vr_mbuf != NULL) { 1150 m_freem(cur_tx->vr_mbuf); 1151 cur_tx->vr_mbuf = NULL; 1152 } 1153 1154 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1155 sc->vr_cdata.vr_tx_head = NULL; 1156 sc->vr_cdata.vr_tx_tail = NULL; 1157 break; 1158 } 1159 1160 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1161 } 1162 1163 return; 1164} 1165 1166/* 1167 * TX 'end of channel' interrupt handler. 1168 */ 1169static void vr_txeoc(sc) 1170 struct vr_softc *sc; 1171{ 1172 struct ifnet *ifp; 1173 1174 ifp = &sc->arpcom.ac_if; 1175 1176 ifp->if_timer = 0; 1177 1178 if (sc->vr_cdata.vr_tx_head == NULL) { 1179 ifp->if_flags &= ~IFF_OACTIVE; 1180 sc->vr_cdata.vr_tx_tail = NULL; 1181 } 1182 1183 return; 1184} 1185 1186static void vr_tick(xsc) 1187 void *xsc; 1188{ 1189 struct vr_softc *sc; 1190 struct mii_data *mii; 1191 int s; 1192 1193 s = splimp(); 1194 1195 sc = xsc; 1196 mii = device_get_softc(sc->vr_miibus); 1197 mii_tick(mii); 1198 1199 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1200 1201 splx(s); 1202 1203 return; 1204} 1205 1206static void vr_intr(arg) 1207 void *arg; 1208{ 1209 struct vr_softc *sc; 1210 struct ifnet *ifp; 1211 u_int16_t status; 1212 1213 sc = arg; 1214 ifp = &sc->arpcom.ac_if; 1215 1216 /* Supress unwanted interrupts. */ 1217 if (!(ifp->if_flags & IFF_UP)) { 1218 vr_stop(sc); 1219 return; 1220 } 1221 1222 /* Disable interrupts. */ 1223 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1224 1225 for (;;) { 1226 1227 status = CSR_READ_2(sc, VR_ISR); 1228 if (status) 1229 CSR_WRITE_2(sc, VR_ISR, status); 1230 1231 if ((status & VR_INTRS) == 0) 1232 break; 1233 1234 if (status & VR_ISR_RX_OK) 1235 vr_rxeof(sc); 1236 1237 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1238 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1239 (status & VR_ISR_RX_DROPPED)) { 1240 vr_rxeof(sc); 1241 vr_rxeoc(sc); 1242 } 1243 1244 if (status & VR_ISR_TX_OK) { 1245 vr_txeof(sc); 1246 vr_txeoc(sc); 1247 } 1248 1249 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1250 ifp->if_oerrors++; 1251 vr_txeof(sc); 1252 if (sc->vr_cdata.vr_tx_head != NULL) { 1253 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1254 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1255 } 1256 } 1257 1258 if (status & VR_ISR_BUSERR) { 1259 vr_reset(sc); 1260 vr_init(sc); 1261 } 1262 } 1263 1264 /* Re-enable interrupts. */ 1265 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1266 1267 if (ifp->if_snd.ifq_head != NULL) { 1268 vr_start(ifp); 1269 } 1270 1271 return; 1272} 1273 1274/* 1275 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1276 * pointers to the fragment pointers. 1277 */ 1278static int vr_encap(sc, c, m_head) 1279 struct vr_softc *sc; 1280 struct vr_chain *c; 1281 struct mbuf *m_head; 1282{ 1283 int frag = 0; 1284 struct vr_desc *f = NULL; 1285 int total_len; 1286 struct mbuf *m; 1287 1288 m = m_head; 1289 total_len = 0; 1290 1291 /* 1292 * The VIA Rhine wants packet buffers to be longword 1293 * aligned, but very often our mbufs aren't. Rather than 1294 * waste time trying to decide when to copy and when not 1295 * to copy, just do it all the time. 1296 */ 1297 if (m != NULL) { 1298 struct mbuf *m_new = NULL; 1299 1300 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1301 if (m_new == NULL) { 1302 printf("vr%d: no memory for tx list", sc->vr_unit); 1303 return(1); 1304 } 1305 if (m_head->m_pkthdr.len > MHLEN) { 1306 MCLGET(m_new, M_DONTWAIT); 1307 if (!(m_new->m_flags & M_EXT)) { 1308 m_freem(m_new); 1309 printf("vr%d: no memory for tx list", 1310 sc->vr_unit); 1311 return(1); 1312 } 1313 } 1314 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1315 mtod(m_new, caddr_t)); 1316 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1317 m_freem(m_head); 1318 m_head = m_new; 1319 /* 1320 * The Rhine chip doesn't auto-pad, so we have to make 1321 * sure to pad short frames out to the minimum frame length 1322 * ourselves. 1323 */ 1324 if (m_head->m_len < VR_MIN_FRAMELEN) { 1325 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1326 m_new->m_len = m_new->m_pkthdr.len; 1327 } 1328 f = c->vr_ptr; 1329 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1330 f->vr_ctl = total_len = m_new->m_len; 1331 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1332 f->vr_status = 0; 1333 frag = 1; 1334 } 1335 1336 c->vr_mbuf = m_head; 1337 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1338 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1339 1340 return(0); 1341} 1342 1343/* 1344 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1345 * to the mbuf data regions directly in the transmit lists. We also save a 1346 * copy of the pointers since the transmit list fragment pointers are 1347 * physical addresses. 1348 */ 1349 1350static void vr_start(ifp) 1351 struct ifnet *ifp; 1352{ 1353 struct vr_softc *sc; 1354 struct mbuf *m_head = NULL; 1355 struct vr_chain *cur_tx = NULL, *start_tx; 1356 1357 sc = ifp->if_softc; 1358 1359 if (ifp->if_flags & IFF_OACTIVE) 1360 return; 1361 1362 /* 1363 * Check for an available queue slot. If there are none, 1364 * punt. 1365 */ 1366 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1367 ifp->if_flags |= IFF_OACTIVE; 1368 return; 1369 } 1370 1371 start_tx = sc->vr_cdata.vr_tx_free; 1372 1373 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1374 IF_DEQUEUE(&ifp->if_snd, m_head); 1375 if (m_head == NULL) 1376 break; 1377 1378 /* Pick a descriptor off the free list. */ 1379 cur_tx = sc->vr_cdata.vr_tx_free; 1380 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1381 1382 /* Pack the data into the descriptor. */ 1383 vr_encap(sc, cur_tx, m_head); 1384 1385 if (cur_tx != start_tx) 1386 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1387 1388#if NBPF > 0 1389 /* 1390 * If there's a BPF listener, bounce a copy of this frame 1391 * to him. 1392 */ 1393 if (ifp->if_bpf) 1394 bpf_mtap(ifp, cur_tx->vr_mbuf); 1395#endif 1396 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1397 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1398 } 1399 1400 /* 1401 * If there are no frames queued, bail. 1402 */ 1403 if (cur_tx == NULL) 1404 return; 1405 1406 sc->vr_cdata.vr_tx_tail = cur_tx; 1407 1408 if (sc->vr_cdata.vr_tx_head == NULL) 1409 sc->vr_cdata.vr_tx_head = start_tx; 1410 1411 /* 1412 * Set a timeout in case the chip goes out to lunch. 1413 */ 1414 ifp->if_timer = 5; 1415 1416 return; 1417} 1418 1419static void vr_init(xsc) 1420 void *xsc; 1421{ 1422 struct vr_softc *sc = xsc; 1423 struct ifnet *ifp = &sc->arpcom.ac_if; 1424 struct mii_data *mii; 1425 int s; 1426 1427 s = splimp(); 1428 1429 mii = device_get_softc(sc->vr_miibus); 1430 1431 /* 1432 * Cancel pending I/O and free all RX/TX buffers. 1433 */ 1434 vr_stop(sc); 1435 vr_reset(sc); 1436 1437 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1438 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1439 1440 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1441 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1442 1443 /* Init circular RX list. */ 1444 if (vr_list_rx_init(sc) == ENOBUFS) { 1445 printf("vr%d: initialization failed: no " 1446 "memory for rx buffers\n", sc->vr_unit); 1447 vr_stop(sc); 1448 (void)splx(s); 1449 return; 1450 } 1451 1452 /* 1453 * Init tx descriptors. 1454 */ 1455 vr_list_tx_init(sc); 1456 1457 /* If we want promiscuous mode, set the allframes bit. */ 1458 if (ifp->if_flags & IFF_PROMISC) 1459 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1460 else 1461 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1462 1463 /* Set capture broadcast bit to capture broadcast frames. */ 1464 if (ifp->if_flags & IFF_BROADCAST) 1465 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1466 else 1467 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1468 1469 /* 1470 * Program the multicast filter, if necessary. 1471 */ 1472 vr_setmulti(sc); 1473 1474 /* 1475 * Load the address of the RX list. 1476 */ 1477 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1478 1479 /* Enable receiver and transmitter. */ 1480 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1481 VR_CMD_TX_ON|VR_CMD_RX_ON| 1482 VR_CMD_RX_GO); 1483 1484 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1485 1486 /* 1487 * Enable interrupts. 1488 */ 1489 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1490 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1491 1492 mii_mediachg(mii); 1493 1494 ifp->if_flags |= IFF_RUNNING; 1495 ifp->if_flags &= ~IFF_OACTIVE; 1496 1497 (void)splx(s); 1498 1499 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1500 1501 return; 1502} 1503 1504/* 1505 * Set media options. 1506 */ 1507static int vr_ifmedia_upd(ifp) 1508 struct ifnet *ifp; 1509{ 1510 struct vr_softc *sc; 1511 1512 sc = ifp->if_softc; 1513 1514 if (ifp->if_flags & IFF_UP) 1515 vr_init(sc); 1516 1517 return(0); 1518} 1519 1520/* 1521 * Report current media status. 1522 */ 1523static void vr_ifmedia_sts(ifp, ifmr) 1524 struct ifnet *ifp; 1525 struct ifmediareq *ifmr; 1526{ 1527 struct vr_softc *sc; 1528 struct mii_data *mii; 1529 1530 sc = ifp->if_softc; 1531 mii = device_get_softc(sc->vr_miibus); 1532 mii_pollstat(mii); 1533 ifmr->ifm_active = mii->mii_media_active; 1534 ifmr->ifm_status = mii->mii_media_status; 1535 1536 return; 1537} 1538 1539static int vr_ioctl(ifp, command, data) 1540 struct ifnet *ifp; 1541 u_long command; 1542 caddr_t data; 1543{ 1544 struct vr_softc *sc = ifp->if_softc; 1545 struct ifreq *ifr = (struct ifreq *) data; 1546 struct mii_data *mii; 1547 int s, error = 0; 1548 1549 s = splimp(); 1550 1551 switch(command) { 1552 case SIOCSIFADDR: 1553 case SIOCGIFADDR: 1554 case SIOCSIFMTU: 1555 error = ether_ioctl(ifp, command, data); 1556 break; 1557 case SIOCSIFFLAGS: 1558 if (ifp->if_flags & IFF_UP) { 1559 vr_init(sc); 1560 } else { 1561 if (ifp->if_flags & IFF_RUNNING) 1562 vr_stop(sc); 1563 } 1564 error = 0; 1565 break; 1566 case SIOCADDMULTI: 1567 case SIOCDELMULTI: 1568 vr_setmulti(sc); 1569 error = 0; 1570 break; 1571 case SIOCGIFMEDIA: 1572 case SIOCSIFMEDIA: 1573 mii = device_get_softc(sc->vr_miibus); 1574 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1575 break; 1576 default: 1577 error = EINVAL; 1578 break; 1579 } 1580 1581 (void)splx(s); 1582 1583 return(error); 1584} 1585 1586static void vr_watchdog(ifp) 1587 struct ifnet *ifp; 1588{ 1589 struct vr_softc *sc; 1590 1591 sc = ifp->if_softc; 1592 1593 ifp->if_oerrors++; 1594 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1595 1596 vr_stop(sc); 1597 vr_reset(sc); 1598 vr_init(sc); 1599 1600 if (ifp->if_snd.ifq_head != NULL) 1601 vr_start(ifp); 1602 1603 return; 1604} 1605 1606/* 1607 * Stop the adapter and free any mbufs allocated to the 1608 * RX and TX lists. 1609 */ 1610static void vr_stop(sc) 1611 struct vr_softc *sc; 1612{ 1613 register int i; 1614 struct ifnet *ifp; 1615 1616 ifp = &sc->arpcom.ac_if; 1617 ifp->if_timer = 0; 1618 1619 untimeout(vr_tick, sc, sc->vr_stat_ch); 1620 1621 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1622 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1623 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1624 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1625 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1626 1627 /* 1628 * Free data in the RX lists. 1629 */ 1630 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1631 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1632 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1633 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1634 } 1635 } 1636 bzero((char *)&sc->vr_ldata->vr_rx_list, 1637 sizeof(sc->vr_ldata->vr_rx_list)); 1638 1639 /* 1640 * Free the TX list buffers. 1641 */ 1642 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1643 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1644 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1645 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1646 } 1647 } 1648 1649 bzero((char *)&sc->vr_ldata->vr_tx_list, 1650 sizeof(sc->vr_ldata->vr_tx_list)); 1651 1652 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1653 1654 return; 1655} 1656 1657/* 1658 * Stop all chip I/O so that the kernel's probe routines don't 1659 * get confused by errant DMAs when rebooting. 1660 */ 1661static void vr_shutdown(dev) 1662 device_t dev; 1663{ 1664 struct vr_softc *sc; 1665 1666 sc = device_get_softc(dev); 1667 1668 vr_stop(sc); 1669 1670 return; 1671} 1672