if_vr.c revision 147256
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48/* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63#include <sys/param.h> 64#include <sys/systm.h> 65#include <sys/sockio.h> 66#include <sys/mbuf.h> 67#include <sys/malloc.h> 68#include <sys/kernel.h> 69#include <sys/module.h> 70#include <sys/socket.h> 71 72#include <net/if.h> 73#include <net/if_arp.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77#include <net/if_types.h> 78 79#include <net/bpf.h> 80 81#include <vm/vm.h> /* for vtophys */ 82#include <vm/pmap.h> /* for vtophys */ 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <dev/pci/pcireg.h> 92#include <dev/pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, pci, 1, 1, 1); 99MODULE_DEPEND(vr, ether, 1, 1, 1); 100MODULE_DEPEND(vr, miibus, 1, 1, 1); 101 102/* "controller miibus0" required. See GENERIC if you get errors here. */ 103#include "miibus_if.h" 104 105#undef VR_USESWSHIFT 106 107/* 108 * Various supported device vendors/types and their names. 109 */ 110static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 118 "VIA VT6105 Rhine III 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 120 "VIA VT6105M Rhine III 10/100BaseTX" }, 121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 122 "Delta Electronics Rhine II 10/100BaseTX" }, 123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 124 "Addtron Technology Rhine II 10/100BaseTX" }, 125 { 0, 0, NULL } 126}; 127 128static int vr_probe(device_t); 129static int vr_attach(device_t); 130static int vr_detach(device_t); 131 132static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 133 struct mbuf *); 134static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 135 136static void vr_rxeof(struct vr_softc *); 137static void vr_rxeoc(struct vr_softc *); 138static void vr_txeof(struct vr_softc *); 139static void vr_tick(void *); 140static void vr_intr(void *); 141static void vr_start(struct ifnet *); 142static void vr_start_locked(struct ifnet *); 143static int vr_ioctl(struct ifnet *, u_long, caddr_t); 144static void vr_init(void *); 145static void vr_init_locked(struct vr_softc *); 146static void vr_stop(struct vr_softc *); 147static void vr_watchdog(struct ifnet *); 148static void vr_shutdown(device_t); 149static int vr_ifmedia_upd(struct ifnet *); 150static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 151 152#ifdef VR_USESWSHIFT 153static void vr_mii_sync(struct vr_softc *); 154static void vr_mii_send(struct vr_softc *, uint32_t, int); 155#endif 156static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 157static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 158static int vr_miibus_readreg(device_t, uint16_t, uint16_t); 159static int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 160static void vr_miibus_statchg(device_t); 161 162static void vr_setcfg(struct vr_softc *, int); 163static void vr_setmulti(struct vr_softc *); 164static void vr_reset(struct vr_softc *); 165static int vr_list_rx_init(struct vr_softc *); 166static int vr_list_tx_init(struct vr_softc *); 167 168#ifdef VR_USEIOSPACE 169#define VR_RES SYS_RES_IOPORT 170#define VR_RID VR_PCI_LOIO 171#else 172#define VR_RES SYS_RES_MEMORY 173#define VR_RID VR_PCI_LOMEM 174#endif 175 176static device_method_t vr_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, vr_probe), 179 DEVMETHOD(device_attach, vr_attach), 180 DEVMETHOD(device_detach, vr_detach), 181 DEVMETHOD(device_shutdown, vr_shutdown), 182 183 /* bus interface */ 184 DEVMETHOD(bus_print_child, bus_generic_print_child), 185 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 186 187 /* MII interface */ 188 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 189 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 190 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 191 192 { 0, 0 } 193}; 194 195static driver_t vr_driver = { 196 "vr", 197 vr_methods, 198 sizeof(struct vr_softc) 199}; 200 201static devclass_t vr_devclass; 202 203DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 204DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 205 206#define VR_SETBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) | (x)) 209 210#define VR_CLRBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) & ~(x)) 213 214#define VR_SETBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) | (x)) 217 218#define VR_CLRBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) & ~(x)) 221 222#define VR_SETBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define VR_CLRBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 237 238#ifdef VR_USESWSHIFT 239/* 240 * Sync the PHYs by setting data bit and strobing the clock 32 times. 241 */ 242static void 243vr_mii_sync(struct vr_softc *sc) 244{ 245 register int i; 246 247 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 248 249 for (i = 0; i < 32; i++) { 250 SIO_SET(VR_MIICMD_CLK); 251 DELAY(1); 252 SIO_CLR(VR_MIICMD_CLK); 253 DELAY(1); 254 } 255} 256 257/* 258 * Clock a series of bits through the MII. 259 */ 260static void 261vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 262{ 263 int i; 264 265 SIO_CLR(VR_MIICMD_CLK); 266 267 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 268 if (bits & i) { 269 SIO_SET(VR_MIICMD_DATAIN); 270 } else { 271 SIO_CLR(VR_MIICMD_DATAIN); 272 } 273 DELAY(1); 274 SIO_CLR(VR_MIICMD_CLK); 275 DELAY(1); 276 SIO_SET(VR_MIICMD_CLK); 277 } 278} 279#endif 280 281/* 282 * Read an PHY register through the MII. 283 */ 284static int 285vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 286#ifdef VR_USESWSHIFT 287{ 288 int i, ack; 289 290 /* Set up frame for RX. */ 291 frame->mii_stdelim = VR_MII_STARTDELIM; 292 frame->mii_opcode = VR_MII_READOP; 293 frame->mii_turnaround = 0; 294 frame->mii_data = 0; 295 296 CSR_WRITE_1(sc, VR_MIICMD, 0); 297 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 298 299 /* Turn on data xmit. */ 300 SIO_SET(VR_MIICMD_DIR); 301 302 vr_mii_sync(sc); 303 304 /* Send command/address info. */ 305 vr_mii_send(sc, frame->mii_stdelim, 2); 306 vr_mii_send(sc, frame->mii_opcode, 2); 307 vr_mii_send(sc, frame->mii_phyaddr, 5); 308 vr_mii_send(sc, frame->mii_regaddr, 5); 309 310 /* Idle bit. */ 311 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 312 DELAY(1); 313 SIO_SET(VR_MIICMD_CLK); 314 DELAY(1); 315 316 /* Turn off xmit. */ 317 SIO_CLR(VR_MIICMD_DIR); 318 319 /* Check for ack */ 320 SIO_CLR(VR_MIICMD_CLK); 321 DELAY(1); 322 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 323 SIO_SET(VR_MIICMD_CLK); 324 DELAY(1); 325 326 /* 327 * Now try reading data bits. If the ack failed, we still 328 * need to clock through 16 cycles to keep the PHY(s) in sync. 329 */ 330 if (ack) { 331 for(i = 0; i < 16; i++) { 332 SIO_CLR(VR_MIICMD_CLK); 333 DELAY(1); 334 SIO_SET(VR_MIICMD_CLK); 335 DELAY(1); 336 } 337 goto fail; 338 } 339 340 for (i = 0x8000; i; i >>= 1) { 341 SIO_CLR(VR_MIICMD_CLK); 342 DELAY(1); 343 if (!ack) { 344 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 345 frame->mii_data |= i; 346 DELAY(1); 347 } 348 SIO_SET(VR_MIICMD_CLK); 349 DELAY(1); 350 } 351 352fail: 353 SIO_CLR(VR_MIICMD_CLK); 354 DELAY(1); 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 358 if (ack) 359 return (1); 360 return (0); 361} 362#else 363{ 364 int i; 365 366 /* Set the PHY address. */ 367 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 368 frame->mii_phyaddr); 369 370 /* Set the register address. */ 371 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 372 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 373 374 for (i = 0; i < 10000; i++) { 375 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 376 break; 377 DELAY(1); 378 } 379 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 380 381 return (0); 382} 383#endif 384 385 386/* 387 * Write to a PHY register through the MII. 388 */ 389static int 390vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 391#ifdef VR_USESWSHIFT 392{ 393 CSR_WRITE_1(sc, VR_MIICMD, 0); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 395 396 /* Set up frame for TX. */ 397 frame->mii_stdelim = VR_MII_STARTDELIM; 398 frame->mii_opcode = VR_MII_WRITEOP; 399 frame->mii_turnaround = VR_MII_TURNAROUND; 400 401 /* Turn on data output. */ 402 SIO_SET(VR_MIICMD_DIR); 403 404 vr_mii_sync(sc); 405 406 vr_mii_send(sc, frame->mii_stdelim, 2); 407 vr_mii_send(sc, frame->mii_opcode, 2); 408 vr_mii_send(sc, frame->mii_phyaddr, 5); 409 vr_mii_send(sc, frame->mii_regaddr, 5); 410 vr_mii_send(sc, frame->mii_turnaround, 2); 411 vr_mii_send(sc, frame->mii_data, 16); 412 413 /* Idle bit. */ 414 SIO_SET(VR_MIICMD_CLK); 415 DELAY(1); 416 SIO_CLR(VR_MIICMD_CLK); 417 DELAY(1); 418 419 /* Turn off xmit. */ 420 SIO_CLR(VR_MIICMD_DIR); 421 422 return (0); 423} 424#else 425{ 426 int i; 427 428 /* Set the PHY address. */ 429 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 430 frame->mii_phyaddr); 431 432 /* Set the register address and data to write. */ 433 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 434 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 435 436 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 437 438 for (i = 0; i < 10000; i++) { 439 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 440 break; 441 DELAY(1); 442 } 443 444 return (0); 445} 446#endif 447 448static int 449vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 450{ 451 struct vr_mii_frame frame; 452 struct vr_softc *sc = device_get_softc(dev); 453 454 switch (sc->vr_revid) { 455 case REV_ID_VT6102_APOLLO: 456 if (phy != 1) { 457 frame.mii_data = 0; 458 goto out; 459 } 460 default: 461 break; 462 } 463 464 bzero((char *)&frame, sizeof(frame)); 465 frame.mii_phyaddr = phy; 466 frame.mii_regaddr = reg; 467 vr_mii_readreg(sc, &frame); 468 469out: 470 return (frame.mii_data); 471} 472 473static int 474vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 475{ 476 struct vr_mii_frame frame; 477 struct vr_softc *sc = device_get_softc(dev); 478 479 switch (sc->vr_revid) { 480 case REV_ID_VT6102_APOLLO: 481 if (phy != 1) 482 return (0); 483 default: 484 break; 485 } 486 487 bzero((char *)&frame, sizeof(frame)); 488 frame.mii_phyaddr = phy; 489 frame.mii_regaddr = reg; 490 frame.mii_data = data; 491 vr_mii_writereg(sc, &frame); 492 493 return (0); 494} 495 496static void 497vr_miibus_statchg(device_t dev) 498{ 499 struct mii_data *mii; 500 struct vr_softc *sc = device_get_softc(dev); 501 502 mii = device_get_softc(sc->vr_miibus); 503 vr_setcfg(sc, mii->mii_media_active); 504} 505 506/* 507 * Program the 64-bit multicast hash filter. 508 */ 509static void 510vr_setmulti(struct vr_softc *sc) 511{ 512 struct ifnet *ifp = sc->vr_ifp; 513 int h = 0; 514 uint32_t hashes[2] = { 0, 0 }; 515 struct ifmultiaddr *ifma; 516 uint8_t rxfilt; 517 int mcnt = 0; 518 519 VR_LOCK_ASSERT(sc); 520 521 rxfilt = CSR_READ_1(sc, VR_RXCFG); 522 523 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 524 rxfilt |= VR_RXCFG_RX_MULTI; 525 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 526 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 527 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 528 return; 529 } 530 531 /* First, zero out all the existing hash bits. */ 532 CSR_WRITE_4(sc, VR_MAR0, 0); 533 CSR_WRITE_4(sc, VR_MAR1, 0); 534 535 /* Now program new ones. */ 536 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 537 if (ifma->ifma_addr->sa_family != AF_LINK) 538 continue; 539 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 540 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 541 if (h < 32) 542 hashes[0] |= (1 << h); 543 else 544 hashes[1] |= (1 << (h - 32)); 545 mcnt++; 546 } 547 548 if (mcnt) 549 rxfilt |= VR_RXCFG_RX_MULTI; 550 else 551 rxfilt &= ~VR_RXCFG_RX_MULTI; 552 553 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 554 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 555 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 556} 557 558/* 559 * In order to fiddle with the 560 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 561 * first have to put the transmit and/or receive logic in the idle state. 562 */ 563static void 564vr_setcfg(struct vr_softc *sc, int media) 565{ 566 int restart = 0; 567 568 VR_LOCK_ASSERT(sc); 569 570 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 571 restart = 1; 572 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 573 } 574 575 if ((media & IFM_GMASK) == IFM_FDX) 576 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 577 else 578 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 579 580 if (restart) 581 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 582} 583 584static void 585vr_reset(struct vr_softc *sc) 586{ 587 register int i; 588 589 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during detach w/o lock. */ 590 591 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 592 593 for (i = 0; i < VR_TIMEOUT; i++) { 594 DELAY(10); 595 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 596 break; 597 } 598 if (i == VR_TIMEOUT) { 599 if (sc->vr_revid < REV_ID_VT3065_A) 600 printf("vr%d: reset never completed!\n", sc->vr_unit); 601 else { 602 /* Use newer force reset command */ 603 printf("vr%d: Using force reset command.\n", 604 sc->vr_unit); 605 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 606 } 607 } 608 609 /* Wait a little while for the chip to get its brains in order. */ 610 DELAY(1000); 611} 612 613/* 614 * Probe for a VIA Rhine chip. Check the PCI vendor and device 615 * IDs against our list and return a device name if we find a match. 616 */ 617static int 618vr_probe(device_t dev) 619{ 620 struct vr_type *t = vr_devs; 621 622 while (t->vr_name != NULL) { 623 if ((pci_get_vendor(dev) == t->vr_vid) && 624 (pci_get_device(dev) == t->vr_did)) { 625 device_set_desc(dev, t->vr_name); 626 return (BUS_PROBE_DEFAULT); 627 } 628 t++; 629 } 630 631 return (ENXIO); 632} 633 634/* 635 * Attach the interface. Allocate softc structures, do ifmedia 636 * setup and ethernet/BPF attach. 637 */ 638static int 639vr_attach(dev) 640 device_t dev; 641{ 642 int i; 643 u_char eaddr[ETHER_ADDR_LEN]; 644 struct vr_softc *sc; 645 struct ifnet *ifp; 646 int unit, error = 0, rid; 647 648 sc = device_get_softc(dev); 649 unit = device_get_unit(dev); 650 651 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 652 MTX_DEF); 653 /* 654 * Map control/status registers. 655 */ 656 pci_enable_busmaster(dev); 657 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 658 659 rid = VR_RID; 660 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 661 662 if (sc->vr_res == NULL) { 663 printf("vr%d: couldn't map ports/memory\n", unit); 664 error = ENXIO; 665 goto fail; 666 } 667 668 sc->vr_btag = rman_get_bustag(sc->vr_res); 669 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 670 671 /* Allocate interrupt */ 672 rid = 0; 673 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 674 RF_SHAREABLE | RF_ACTIVE); 675 676 if (sc->vr_irq == NULL) { 677 printf("vr%d: couldn't map interrupt\n", unit); 678 error = ENXIO; 679 goto fail; 680 } 681 682 /* 683 * Windows may put the chip in suspend mode when it 684 * shuts down. Be sure to kick it in the head to wake it 685 * up again. 686 */ 687 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 688 689 /* Reset the adapter. */ 690 vr_reset(sc); 691 692 /* 693 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 694 * initialization and disable AUTOPOLL. 695 */ 696 pci_write_config(dev, VR_PCI_MODE, 697 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 698 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 699 700 /* 701 * Get station address. The way the Rhine chips work, 702 * you're not allowed to directly access the EEPROM once 703 * they've been programmed a special way. Consequently, 704 * we need to read the node address from the PAR0 and PAR1 705 * registers. 706 */ 707 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 708 DELAY(200); 709 for (i = 0; i < ETHER_ADDR_LEN; i++) 710 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 711 712 sc->vr_unit = unit; 713 714 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 715 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 716 717 if (sc->vr_ldata == NULL) { 718 printf("vr%d: no memory for list buffers!\n", unit); 719 error = ENXIO; 720 goto fail; 721 } 722 723 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 724 725 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 726 if (ifp == NULL) { 727 printf("vr%d: can not if_alloc()\n", unit); 728 error = ENOSPC; 729 goto fail; 730 } 731 ifp->if_softc = sc; 732 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 733 ifp->if_mtu = ETHERMTU; 734 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 735 ifp->if_ioctl = vr_ioctl; 736 ifp->if_start = vr_start; 737 ifp->if_watchdog = vr_watchdog; 738 ifp->if_init = vr_init; 739 ifp->if_baudrate = 10000000; 740 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 741 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 742 IFQ_SET_READY(&ifp->if_snd); 743#ifdef DEVICE_POLLING 744 ifp->if_capabilities |= IFCAP_POLLING; 745#endif 746 ifp->if_capenable = ifp->if_capabilities; 747 748 /* Do MII setup. */ 749 if (mii_phy_probe(dev, &sc->vr_miibus, 750 vr_ifmedia_upd, vr_ifmedia_sts)) { 751 printf("vr%d: MII without any phy!\n", sc->vr_unit); 752 error = ENXIO; 753 goto fail; 754 } 755 756 callout_handle_init(&sc->vr_stat_ch); 757 758 /* Call MI attach routine. */ 759 ether_ifattach(ifp, eaddr); 760 761 sc->suspended = 0; 762 763 /* Hook interrupt last to avoid having to lock softc */ 764 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 765 vr_intr, sc, &sc->vr_intrhand); 766 767 if (error) { 768 printf("vr%d: couldn't set up irq\n", unit); 769 ether_ifdetach(ifp); 770 if_free(ifp); 771 goto fail; 772 } 773 774fail: 775 if (error) 776 vr_detach(dev); 777 778 return (error); 779} 780 781/* 782 * Shutdown hardware and free up resources. This can be called any 783 * time after the mutex has been initialized. It is called in both 784 * the error case in attach and the normal detach case so it needs 785 * to be careful about only freeing resources that have actually been 786 * allocated. 787 */ 788static int 789vr_detach(device_t dev) 790{ 791 struct vr_softc *sc = device_get_softc(dev); 792 struct ifnet *ifp = sc->vr_ifp; 793 794 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 795 796 VR_LOCK(sc); 797 798 sc->suspended = 1; 799 800 /* These should only be active if attach succeeded */ 801 if (device_is_attached(dev)) { 802 vr_stop(sc); 803 VR_UNLOCK(sc); /* XXX: Avoid recursive acquire. */ 804 ether_ifdetach(ifp); 805 if_free(ifp); 806 VR_LOCK(sc); 807 } 808 if (sc->vr_miibus) 809 device_delete_child(dev, sc->vr_miibus); 810 bus_generic_detach(dev); 811 812 if (sc->vr_intrhand) 813 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 814 if (sc->vr_irq) 815 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 816 if (sc->vr_res) 817 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 818 819 if (sc->vr_ldata) 820 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 821 822 VR_UNLOCK(sc); 823 mtx_destroy(&sc->vr_mtx); 824 825 return (0); 826} 827 828/* 829 * Initialize the transmit descriptors. 830 */ 831static int 832vr_list_tx_init(struct vr_softc *sc) 833{ 834 struct vr_chain_data *cd; 835 struct vr_list_data *ld; 836 int i; 837 838 cd = &sc->vr_cdata; 839 ld = sc->vr_ldata; 840 for (i = 0; i < VR_TX_LIST_CNT; i++) { 841 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 842 if (i == (VR_TX_LIST_CNT - 1)) 843 cd->vr_tx_chain[i].vr_nextdesc = 844 &cd->vr_tx_chain[0]; 845 else 846 cd->vr_tx_chain[i].vr_nextdesc = 847 &cd->vr_tx_chain[i + 1]; 848 } 849 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 850 851 return (0); 852} 853 854 855/* 856 * Initialize the RX descriptors and allocate mbufs for them. Note that 857 * we arrange the descriptors in a closed ring, so that the last descriptor 858 * points back to the first. 859 */ 860static int 861vr_list_rx_init(struct vr_softc *sc) 862{ 863 struct vr_chain_data *cd; 864 struct vr_list_data *ld; 865 int i; 866 867 VR_LOCK_ASSERT(sc); 868 869 cd = &sc->vr_cdata; 870 ld = sc->vr_ldata; 871 872 for (i = 0; i < VR_RX_LIST_CNT; i++) { 873 cd->vr_rx_chain[i].vr_ptr = 874 (struct vr_desc *)&ld->vr_rx_list[i]; 875 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 876 return (ENOBUFS); 877 if (i == (VR_RX_LIST_CNT - 1)) { 878 cd->vr_rx_chain[i].vr_nextdesc = 879 &cd->vr_rx_chain[0]; 880 ld->vr_rx_list[i].vr_next = 881 vtophys(&ld->vr_rx_list[0]); 882 } else { 883 cd->vr_rx_chain[i].vr_nextdesc = 884 &cd->vr_rx_chain[i + 1]; 885 ld->vr_rx_list[i].vr_next = 886 vtophys(&ld->vr_rx_list[i + 1]); 887 } 888 } 889 890 cd->vr_rx_head = &cd->vr_rx_chain[0]; 891 892 return (0); 893} 894 895/* 896 * Initialize an RX descriptor and attach an MBUF cluster. 897 * Note: the length fields are only 11 bits wide, which means the 898 * largest size we can specify is 2047. This is important because 899 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 900 * overflow the field and make a mess. 901 */ 902static int 903vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 904{ 905 struct mbuf *m_new = NULL; 906 907 if (m == NULL) { 908 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 909 if (m_new == NULL) 910 return (ENOBUFS); 911 912 MCLGET(m_new, M_DONTWAIT); 913 if (!(m_new->m_flags & M_EXT)) { 914 m_freem(m_new); 915 return (ENOBUFS); 916 } 917 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 918 } else { 919 m_new = m; 920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 921 m_new->m_data = m_new->m_ext.ext_buf; 922 } 923 924 m_adj(m_new, sizeof(uint64_t)); 925 926 c->vr_mbuf = m_new; 927 c->vr_ptr->vr_status = VR_RXSTAT; 928 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 929 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 930 931 return (0); 932} 933 934/* 935 * A frame has been uploaded: pass the resulting mbuf chain up to 936 * the higher level protocols. 937 */ 938static void 939vr_rxeof(struct vr_softc *sc) 940{ 941 struct mbuf *m, *m0; 942 struct ifnet *ifp; 943 struct vr_chain_onefrag *cur_rx; 944 int total_len = 0; 945 uint32_t rxstat; 946 947 VR_LOCK_ASSERT(sc); 948 ifp = sc->vr_ifp; 949 950 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 951 VR_RXSTAT_OWN)) { 952#ifdef DEVICE_POLLING 953 if (ifp->if_flags & IFF_POLLING) { 954 if (sc->rxcycles <= 0) 955 break; 956 sc->rxcycles--; 957 } 958#endif /* DEVICE_POLLING */ 959 m0 = NULL; 960 cur_rx = sc->vr_cdata.vr_rx_head; 961 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 962 m = cur_rx->vr_mbuf; 963 964 /* 965 * If an error occurs, update stats, clear the 966 * status word and leave the mbuf cluster in place: 967 * it should simply get re-used next time this descriptor 968 * comes up in the ring. 969 */ 970 if (rxstat & VR_RXSTAT_RXERR) { 971 ifp->if_ierrors++; 972 printf("vr%d: rx error (%02x):", sc->vr_unit, 973 rxstat & 0x000000ff); 974 if (rxstat & VR_RXSTAT_CRCERR) 975 printf(" crc error"); 976 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 977 printf(" frame alignment error\n"); 978 if (rxstat & VR_RXSTAT_FIFOOFLOW) 979 printf(" FIFO overflow"); 980 if (rxstat & VR_RXSTAT_GIANT) 981 printf(" received giant packet"); 982 if (rxstat & VR_RXSTAT_RUNT) 983 printf(" received runt packet"); 984 if (rxstat & VR_RXSTAT_BUSERR) 985 printf(" system bus error"); 986 if (rxstat & VR_RXSTAT_BUFFERR) 987 printf("rx buffer error"); 988 printf("\n"); 989 vr_newbuf(sc, cur_rx, m); 990 continue; 991 } 992 993 /* No errors; receive the packet. */ 994 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 995 996 /* 997 * XXX The VIA Rhine chip includes the CRC with every 998 * received frame, and there's no way to turn this 999 * behavior off (at least, I can't find anything in 1000 * the manual that explains how to do it) so we have 1001 * to trim off the CRC manually. 1002 */ 1003 total_len -= ETHER_CRC_LEN; 1004 1005 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1006 NULL); 1007 vr_newbuf(sc, cur_rx, m); 1008 if (m0 == NULL) { 1009 ifp->if_ierrors++; 1010 continue; 1011 } 1012 m = m0; 1013 1014 ifp->if_ipackets++; 1015 VR_UNLOCK(sc); 1016 (*ifp->if_input)(ifp, m); 1017 VR_LOCK(sc); 1018 } 1019} 1020 1021static void 1022vr_rxeoc(struct vr_softc *sc) 1023{ 1024 struct ifnet *ifp = sc->vr_ifp; 1025 int i; 1026 1027 VR_LOCK_ASSERT(sc); 1028 1029 ifp->if_ierrors++; 1030 1031 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1032 DELAY(10000); 1033 1034 /* Wait for receiver to stop */ 1035 for (i = 0x400; 1036 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1037 i--) { 1038 ; 1039 } 1040 1041 if (!i) { 1042 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1043 sc->vr_flags |= VR_F_RESTART; 1044 return; 1045 } 1046 1047 vr_rxeof(sc); 1048 1049 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1050 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1051 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1052} 1053 1054/* 1055 * A frame was downloaded to the chip. It's safe for us to clean up 1056 * the list buffers. 1057 */ 1058static void 1059vr_txeof(struct vr_softc *sc) 1060{ 1061 struct vr_chain *cur_tx; 1062 struct ifnet *ifp = sc->vr_ifp; 1063 1064 VR_LOCK_ASSERT(sc); 1065 1066 /* 1067 * Go through our tx list and free mbufs for those 1068 * frames that have been transmitted. 1069 */ 1070 cur_tx = sc->vr_cdata.vr_tx_cons; 1071 while (cur_tx->vr_mbuf != NULL) { 1072 uint32_t txstat; 1073 int i; 1074 1075 txstat = cur_tx->vr_ptr->vr_status; 1076 1077 if ((txstat & VR_TXSTAT_ABRT) || 1078 (txstat & VR_TXSTAT_UDF)) { 1079 for (i = 0x400; 1080 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1081 i--) 1082 ; /* Wait for chip to shutdown */ 1083 if (!i) { 1084 printf("vr%d: tx shutdown timeout\n", 1085 sc->vr_unit); 1086 sc->vr_flags |= VR_F_RESTART; 1087 break; 1088 } 1089 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1090 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1091 break; 1092 } 1093 1094 if (txstat & VR_TXSTAT_OWN) 1095 break; 1096 1097 if (txstat & VR_TXSTAT_ERRSUM) { 1098 ifp->if_oerrors++; 1099 if (txstat & VR_TXSTAT_DEFER) 1100 ifp->if_collisions++; 1101 if (txstat & VR_TXSTAT_LATECOLL) 1102 ifp->if_collisions++; 1103 } 1104 1105 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1106 1107 ifp->if_opackets++; 1108 m_freem(cur_tx->vr_mbuf); 1109 cur_tx->vr_mbuf = NULL; 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 1112 cur_tx = cur_tx->vr_nextdesc; 1113 } 1114 sc->vr_cdata.vr_tx_cons = cur_tx; 1115 if (cur_tx->vr_mbuf == NULL) 1116 ifp->if_timer = 0; 1117} 1118 1119static void 1120vr_tick(void *xsc) 1121{ 1122 struct vr_softc *sc = xsc; 1123 struct mii_data *mii; 1124 1125 VR_LOCK(sc); 1126 1127 if (sc->vr_flags & VR_F_RESTART) { 1128 printf("vr%d: restarting\n", sc->vr_unit); 1129 vr_stop(sc); 1130 vr_reset(sc); 1131 vr_init_locked(sc); 1132 sc->vr_flags &= ~VR_F_RESTART; 1133 } 1134 1135 mii = device_get_softc(sc->vr_miibus); 1136 mii_tick(mii); 1137 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1138 1139 VR_UNLOCK(sc); 1140} 1141 1142#ifdef DEVICE_POLLING 1143static poll_handler_t vr_poll; 1144static poll_handler_t vr_poll_locked; 1145 1146static void 1147vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1148{ 1149 struct vr_softc *sc = ifp->if_softc; 1150 1151 VR_LOCK(sc); 1152 vr_poll_locked(ifp, cmd, count); 1153 VR_UNLOCK(sc); 1154} 1155 1156static void 1157vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1158{ 1159 struct vr_softc *sc = ifp->if_softc; 1160 1161 VR_LOCK_ASSERT(sc); 1162 1163 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1164 ether_poll_deregister(ifp); 1165 cmd = POLL_DEREGISTER; 1166 } 1167 1168 if (cmd == POLL_DEREGISTER) { 1169 /* Final call, enable interrupts. */ 1170 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1171 return; 1172 } 1173 1174 sc->rxcycles = count; 1175 vr_rxeof(sc); 1176 vr_txeof(sc); 1177 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1178 vr_start_locked(ifp); 1179 1180 if (cmd == POLL_AND_CHECK_STATUS) { 1181 uint16_t status; 1182 1183 /* Also check status register. */ 1184 status = CSR_READ_2(sc, VR_ISR); 1185 if (status) 1186 CSR_WRITE_2(sc, VR_ISR, status); 1187 1188 if ((status & VR_INTRS) == 0) 1189 return; 1190 1191 if (status & VR_ISR_RX_DROPPED) { 1192 printf("vr%d: rx packet lost\n", sc->vr_unit); 1193 ifp->if_ierrors++; 1194 } 1195 1196 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1197 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1198 printf("vr%d: receive error (%04x)", 1199 sc->vr_unit, status); 1200 if (status & VR_ISR_RX_NOBUF) 1201 printf(" no buffers"); 1202 if (status & VR_ISR_RX_OFLOW) 1203 printf(" overflow"); 1204 if (status & VR_ISR_RX_DROPPED) 1205 printf(" packet lost"); 1206 printf("\n"); 1207 vr_rxeoc(sc); 1208 } 1209 1210 if ((status & VR_ISR_BUSERR) || 1211 (status & VR_ISR_TX_UNDERRUN)) { 1212 vr_reset(sc); 1213 vr_init_locked(sc); 1214 return; 1215 } 1216 1217 if ((status & VR_ISR_UDFI) || 1218 (status & VR_ISR_TX_ABRT2) || 1219 (status & VR_ISR_TX_ABRT)) { 1220 ifp->if_oerrors++; 1221 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1222 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1223 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1224 } 1225 } 1226 } 1227} 1228#endif /* DEVICE_POLLING */ 1229 1230static void 1231vr_intr(void *arg) 1232{ 1233 struct vr_softc *sc = arg; 1234 struct ifnet *ifp = sc->vr_ifp; 1235 uint16_t status; 1236 1237 VR_LOCK(sc); 1238 1239 if (sc->suspended) { 1240 /* 1241 * Forcibly disable interrupts. 1242 * XXX: Mobile VIA based platforms may need 1243 * interrupt re-enable on resume. 1244 */ 1245 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1246 goto done_locked; 1247 } 1248 1249#ifdef DEVICE_POLLING 1250 if (ifp->if_flags & IFF_POLLING) 1251 goto done_locked; 1252 1253 if ((ifp->if_capenable & IFCAP_POLLING) && 1254 ether_poll_register(vr_poll, ifp)) { 1255 /* OK, disable interrupts. */ 1256 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1257 vr_poll_locked(ifp, 0, 1); 1258 goto done_locked; 1259 } 1260#endif /* DEVICE_POLLING */ 1261 1262 /* Suppress unwanted interrupts. */ 1263 if (!(ifp->if_flags & IFF_UP)) { 1264 vr_stop(sc); 1265 goto done_locked; 1266 } 1267 1268 /* Disable interrupts. */ 1269 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1270 1271 for (;;) { 1272 status = CSR_READ_2(sc, VR_ISR); 1273 if (status) 1274 CSR_WRITE_2(sc, VR_ISR, status); 1275 1276 if ((status & VR_INTRS) == 0) 1277 break; 1278 1279 if (status & VR_ISR_RX_OK) 1280 vr_rxeof(sc); 1281 1282 if (status & VR_ISR_RX_DROPPED) { 1283 printf("vr%d: rx packet lost\n", sc->vr_unit); 1284 ifp->if_ierrors++; 1285 } 1286 1287 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1288 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1289 printf("vr%d: receive error (%04x)", 1290 sc->vr_unit, status); 1291 if (status & VR_ISR_RX_NOBUF) 1292 printf(" no buffers"); 1293 if (status & VR_ISR_RX_OFLOW) 1294 printf(" overflow"); 1295 if (status & VR_ISR_RX_DROPPED) 1296 printf(" packet lost"); 1297 printf("\n"); 1298 vr_rxeoc(sc); 1299 } 1300 1301 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1302 vr_reset(sc); 1303 vr_init_locked(sc); 1304 break; 1305 } 1306 1307 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1308 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1309 vr_txeof(sc); 1310 if ((status & VR_ISR_UDFI) || 1311 (status & VR_ISR_TX_ABRT2) || 1312 (status & VR_ISR_TX_ABRT)) { 1313 ifp->if_oerrors++; 1314 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1315 VR_SETBIT16(sc, VR_COMMAND, 1316 VR_CMD_TX_ON); 1317 VR_SETBIT16(sc, VR_COMMAND, 1318 VR_CMD_TX_GO); 1319 } 1320 } 1321 } 1322 } 1323 1324 /* Re-enable interrupts. */ 1325 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1326 1327 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1328 vr_start_locked(ifp); 1329 1330done_locked: 1331 VR_UNLOCK(sc); 1332} 1333 1334/* 1335 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1336 * pointers to the fragment pointers. 1337 */ 1338static int 1339vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1340{ 1341 struct vr_desc *f = NULL; 1342 struct mbuf *m; 1343 1344 VR_LOCK_ASSERT(sc); 1345 /* 1346 * The VIA Rhine wants packet buffers to be longword 1347 * aligned, but very often our mbufs aren't. Rather than 1348 * waste time trying to decide when to copy and when not 1349 * to copy, just do it all the time. 1350 */ 1351 m = m_defrag(m_head, M_DONTWAIT); 1352 if (m == NULL) 1353 return (1); 1354 1355 /* 1356 * The Rhine chip doesn't auto-pad, so we have to make 1357 * sure to pad short frames out to the minimum frame length 1358 * ourselves. 1359 */ 1360 if (m->m_len < VR_MIN_FRAMELEN) { 1361 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1362 m->m_len = m->m_pkthdr.len; 1363 } 1364 1365 c->vr_mbuf = m; 1366 f = c->vr_ptr; 1367 f->vr_data = vtophys(mtod(m, caddr_t)); 1368 f->vr_ctl = m->m_len; 1369 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1370 f->vr_status = 0; 1371 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1372 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1373 1374 return (0); 1375} 1376 1377/* 1378 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1379 * to the mbuf data regions directly in the transmit lists. We also save a 1380 * copy of the pointers since the transmit list fragment pointers are 1381 * physical addresses. 1382 */ 1383 1384static void 1385vr_start(struct ifnet *ifp) 1386{ 1387 struct vr_softc *sc = ifp->if_softc; 1388 1389 VR_LOCK(sc); 1390 vr_start_locked(ifp); 1391 VR_UNLOCK(sc); 1392} 1393 1394static void 1395vr_start_locked(struct ifnet *ifp) 1396{ 1397 struct vr_softc *sc = ifp->if_softc; 1398 struct mbuf *m_head; 1399 struct vr_chain *cur_tx; 1400 1401 if (ifp->if_flags & IFF_OACTIVE) 1402 return; 1403 1404 cur_tx = sc->vr_cdata.vr_tx_prod; 1405 while (cur_tx->vr_mbuf == NULL) { 1406 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1407 if (m_head == NULL) 1408 break; 1409 1410 /* Pack the data into the descriptor. */ 1411 if (vr_encap(sc, cur_tx, m_head)) { 1412 /* Rollback, send what we were able to encap. */ 1413 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1414 break; 1415 } 1416 1417 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1418 1419 /* 1420 * If there's a BPF listener, bounce a copy of this frame 1421 * to him. 1422 */ 1423 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1424 1425 cur_tx = cur_tx->vr_nextdesc; 1426 } 1427 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1428 sc->vr_cdata.vr_tx_prod = cur_tx; 1429 1430 /* Tell the chip to start transmitting. */ 1431 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1432 1433 /* Set a timeout in case the chip goes out to lunch. */ 1434 ifp->if_timer = 5; 1435 1436 if (cur_tx->vr_mbuf != NULL) 1437 ifp->if_flags |= IFF_OACTIVE; 1438 } 1439} 1440 1441static void 1442vr_init(void *xsc) 1443{ 1444 struct vr_softc *sc = xsc; 1445 1446 VR_LOCK(sc); 1447 vr_init_locked(sc); 1448 VR_UNLOCK(sc); 1449} 1450 1451static void 1452vr_init_locked(struct vr_softc *sc) 1453{ 1454 struct ifnet *ifp = sc->vr_ifp; 1455 struct mii_data *mii; 1456 int i; 1457 1458 VR_LOCK_ASSERT(sc); 1459 1460 mii = device_get_softc(sc->vr_miibus); 1461 1462 /* Cancel pending I/O and free all RX/TX buffers. */ 1463 vr_stop(sc); 1464 vr_reset(sc); 1465 1466 /* Set our station address. */ 1467 for (i = 0; i < ETHER_ADDR_LEN; i++) 1468 CSR_WRITE_1(sc, VR_PAR0 + i, IFP2ENADDR(sc->vr_ifp)[i]); 1469 1470 /* Set DMA size. */ 1471 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1472 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1473 1474 /* 1475 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1476 * so we must set both. 1477 */ 1478 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1479 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1480 1481 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1482 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1483 1484 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1485 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1486 1487 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1488 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1489 1490 /* Init circular RX list. */ 1491 if (vr_list_rx_init(sc) == ENOBUFS) { 1492 printf( 1493"vr%d: initialization failed: no memory for rx buffers\n", sc->vr_unit); 1494 vr_stop(sc); 1495 return; 1496 } 1497 1498 /* Init tx descriptors. */ 1499 vr_list_tx_init(sc); 1500 1501 /* If we want promiscuous mode, set the allframes bit. */ 1502 if (ifp->if_flags & IFF_PROMISC) 1503 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1504 else 1505 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1506 1507 /* Set capture broadcast bit to capture broadcast frames. */ 1508 if (ifp->if_flags & IFF_BROADCAST) 1509 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1510 else 1511 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1512 1513 /* 1514 * Program the multicast filter, if necessary. 1515 */ 1516 vr_setmulti(sc); 1517 1518 /* 1519 * Load the address of the RX list. 1520 */ 1521 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1522 1523 /* Enable receiver and transmitter. */ 1524 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1525 VR_CMD_TX_ON|VR_CMD_RX_ON| 1526 VR_CMD_RX_GO); 1527 1528 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1529 1530 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1531#ifdef DEVICE_POLLING 1532 /* 1533 * Disable interrupts if we are polling. 1534 */ 1535 if (ifp->if_flags & IFF_POLLING) 1536 CSR_WRITE_2(sc, VR_IMR, 0); 1537 else 1538#endif /* DEVICE_POLLING */ 1539 /* 1540 * Enable interrupts. 1541 */ 1542 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1543 1544 mii_mediachg(mii); 1545 1546 ifp->if_flags |= IFF_RUNNING; 1547 ifp->if_flags &= ~IFF_OACTIVE; 1548 1549 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1550} 1551 1552/* 1553 * Set media options. 1554 */ 1555static int 1556vr_ifmedia_upd(struct ifnet *ifp) 1557{ 1558 struct vr_softc *sc = ifp->if_softc; 1559 1560 if (ifp->if_flags & IFF_UP) 1561 vr_init(sc); 1562 1563 return (0); 1564} 1565 1566/* 1567 * Report current media status. 1568 */ 1569static void 1570vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1571{ 1572 struct vr_softc *sc = ifp->if_softc; 1573 struct mii_data *mii; 1574 1575 mii = device_get_softc(sc->vr_miibus); 1576 VR_LOCK(sc); 1577 mii_pollstat(mii); 1578 VR_UNLOCK(sc); 1579 ifmr->ifm_active = mii->mii_media_active; 1580 ifmr->ifm_status = mii->mii_media_status; 1581} 1582 1583static int 1584vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1585{ 1586 struct vr_softc *sc = ifp->if_softc; 1587 struct ifreq *ifr = (struct ifreq *) data; 1588 struct mii_data *mii; 1589 int error = 0; 1590 1591 switch (command) { 1592 case SIOCSIFFLAGS: 1593 VR_LOCK(sc); 1594 if (ifp->if_flags & IFF_UP) { 1595 vr_init_locked(sc); 1596 } else { 1597 if (ifp->if_flags & IFF_RUNNING) 1598 vr_stop(sc); 1599 } 1600 VR_UNLOCK(sc); 1601 error = 0; 1602 break; 1603 case SIOCADDMULTI: 1604 case SIOCDELMULTI: 1605 VR_LOCK(sc); 1606 vr_setmulti(sc); 1607 VR_UNLOCK(sc); 1608 error = 0; 1609 break; 1610 case SIOCGIFMEDIA: 1611 case SIOCSIFMEDIA: 1612 mii = device_get_softc(sc->vr_miibus); 1613 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1614 break; 1615 case SIOCSIFCAP: 1616 ifp->if_capenable = ifr->ifr_reqcap; 1617 break; 1618 default: 1619 error = ether_ioctl(ifp, command, data); 1620 break; 1621 } 1622 1623 return (error); 1624} 1625 1626static void 1627vr_watchdog(struct ifnet *ifp) 1628{ 1629 struct vr_softc *sc = ifp->if_softc; 1630 1631 VR_LOCK(sc); 1632 1633 ifp->if_oerrors++; 1634 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1635 1636 vr_stop(sc); 1637 vr_reset(sc); 1638 vr_init_locked(sc); 1639 1640 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1641 vr_start_locked(ifp); 1642 1643 VR_UNLOCK(sc); 1644} 1645 1646/* 1647 * Stop the adapter and free any mbufs allocated to the 1648 * RX and TX lists. 1649 */ 1650static void 1651vr_stop(struct vr_softc *sc) 1652{ 1653 register int i; 1654 struct ifnet *ifp; 1655 1656 VR_LOCK_ASSERT(sc); 1657 1658 ifp = sc->vr_ifp; 1659 ifp->if_timer = 0; 1660 1661 untimeout(vr_tick, sc, sc->vr_stat_ch); 1662 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1663#ifdef DEVICE_POLLING 1664 ether_poll_deregister(ifp); 1665#endif /* DEVICE_POLLING */ 1666 1667 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1668 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1669 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1670 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1671 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1672 1673 /* 1674 * Free data in the RX lists. 1675 */ 1676 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1677 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1678 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1679 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1680 } 1681 } 1682 bzero((char *)&sc->vr_ldata->vr_rx_list, 1683 sizeof(sc->vr_ldata->vr_rx_list)); 1684 1685 /* 1686 * Free the TX list buffers. 1687 */ 1688 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1689 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1690 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1691 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1692 } 1693 } 1694 bzero((char *)&sc->vr_ldata->vr_tx_list, 1695 sizeof(sc->vr_ldata->vr_tx_list)); 1696} 1697 1698/* 1699 * Stop all chip I/O so that the kernel's probe routines don't 1700 * get confused by errant DMAs when rebooting. 1701 */ 1702static void 1703vr_shutdown(device_t dev) 1704{ 1705 1706 vr_detach(dev); 1707} 1708