if_vr.c revision 133006
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 133006 2004-08-02 10:08:28Z mlaier $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48/* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63#include <sys/param.h> 64#include <sys/systm.h> 65#include <sys/sockio.h> 66#include <sys/mbuf.h> 67#include <sys/malloc.h> 68#include <sys/kernel.h> 69#include <sys/module.h> 70#include <sys/socket.h> 71 72#include <net/if.h> 73#include <net/if_arp.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77 78#include <net/bpf.h> 79 80#include <vm/vm.h> /* for vtophys */ 81#include <vm/pmap.h> /* for vtophys */ 82#include <machine/bus_pio.h> 83#include <machine/bus_memio.h> 84#include <machine/bus.h> 85#include <machine/resource.h> 86#include <sys/bus.h> 87#include <sys/rman.h> 88 89#include <dev/mii/mii.h> 90#include <dev/mii/miivar.h> 91 92#include <dev/pci/pcireg.h> 93#include <dev/pci/pcivar.h> 94 95#define VR_USEIOSPACE 96 97#include <pci/if_vrreg.h> 98 99MODULE_DEPEND(vr, pci, 1, 1, 1); 100MODULE_DEPEND(vr, ether, 1, 1, 1); 101MODULE_DEPEND(vr, miibus, 1, 1, 1); 102 103/* "controller miibus0" required. See GENERIC if you get errors here. */ 104#include "miibus_if.h" 105 106#undef VR_USESWSHIFT 107 108/* 109 * Various supported device vendors/types and their names. 110 */ 111static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117 "VIA VT6102 Rhine II 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 119 "VIA VT6105 Rhine III 10/100BaseTX" }, 120 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 121 "VIA VT6105M Rhine III 10/100BaseTX" }, 122 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 123 "Delta Electronics Rhine II 10/100BaseTX" }, 124 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 125 "Addtron Technology Rhine II 10/100BaseTX" }, 126 { 0, 0, NULL } 127}; 128 129static int vr_probe (device_t); 130static int vr_attach (device_t); 131static int vr_detach (device_t); 132 133static int vr_newbuf (struct vr_softc *, 134 struct vr_chain_onefrag *, 135 struct mbuf *); 136static int vr_encap (struct vr_softc *, struct vr_chain *, 137 struct mbuf * ); 138 139static void vr_rxeof (struct vr_softc *); 140static void vr_rxeoc (struct vr_softc *); 141static void vr_txeof (struct vr_softc *); 142static void vr_tick (void *); 143static void vr_intr (void *); 144static void vr_start (struct ifnet *); 145static void vr_start_locked (struct ifnet *); 146static int vr_ioctl (struct ifnet *, u_long, caddr_t); 147static void vr_init (void *); 148static void vr_init_locked (struct vr_softc *); 149static void vr_stop (struct vr_softc *); 150static void vr_watchdog (struct ifnet *); 151static void vr_shutdown (device_t); 152static int vr_ifmedia_upd (struct ifnet *); 153static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 154 155#ifdef VR_USESWSHIFT 156static void vr_mii_sync (struct vr_softc *); 157static void vr_mii_send (struct vr_softc *, uint32_t, int); 158#endif 159static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 160static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 161static int vr_miibus_readreg (device_t, uint16_t, uint16_t); 162static int vr_miibus_writereg (device_t, uint16_t, uint16_t, uint16_t); 163static void vr_miibus_statchg (device_t); 164 165static void vr_setcfg (struct vr_softc *, int); 166static void vr_setmulti (struct vr_softc *); 167static void vr_reset (struct vr_softc *); 168static int vr_list_rx_init (struct vr_softc *); 169static int vr_list_tx_init (struct vr_softc *); 170 171#ifdef VR_USEIOSPACE 172#define VR_RES SYS_RES_IOPORT 173#define VR_RID VR_PCI_LOIO 174#else 175#define VR_RES SYS_RES_MEMORY 176#define VR_RID VR_PCI_LOMEM 177#endif 178 179static device_method_t vr_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, vr_probe), 182 DEVMETHOD(device_attach, vr_attach), 183 DEVMETHOD(device_detach, vr_detach), 184 DEVMETHOD(device_shutdown, vr_shutdown), 185 186 /* bus interface */ 187 DEVMETHOD(bus_print_child, bus_generic_print_child), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 192 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 193 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 194 195 { 0, 0 } 196}; 197 198static driver_t vr_driver = { 199 "vr", 200 vr_methods, 201 sizeof(struct vr_softc) 202}; 203 204static devclass_t vr_devclass; 205 206DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 207DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 208 209#define VR_SETBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) | (x)) 212 213#define VR_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_1(sc, reg, \ 215 CSR_READ_1(sc, reg) & ~(x)) 216 217#define VR_SETBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) | (x)) 220 221#define VR_CLRBIT16(sc, reg, x) \ 222 CSR_WRITE_2(sc, reg, \ 223 CSR_READ_2(sc, reg) & ~(x)) 224 225#define VR_SETBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229#define VR_CLRBIT32(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233#define SIO_SET(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) | (x)) 236 237#define SIO_CLR(x) \ 238 CSR_WRITE_1(sc, VR_MIICMD, \ 239 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 240 241#ifdef VR_USESWSHIFT 242/* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245static void 246vr_mii_sync(struct vr_softc *sc) 247{ 248 register int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258} 259 260/* 261 * Clock a series of bits through the MII. 262 */ 263static void 264vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 265{ 266 int i; 267 268 SIO_CLR(VR_MIICMD_CLK); 269 270 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 271 if (bits & i) { 272 SIO_SET(VR_MIICMD_DATAIN); 273 } else { 274 SIO_CLR(VR_MIICMD_DATAIN); 275 } 276 DELAY(1); 277 SIO_CLR(VR_MIICMD_CLK); 278 DELAY(1); 279 SIO_SET(VR_MIICMD_CLK); 280 } 281} 282#endif 283 284/* 285 * Read an PHY register through the MII. 286 */ 287static int 288vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 289#ifdef VR_USESWSHIFT 290{ 291 int i, ack; 292 293 /* Set up frame for RX. */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* Turn on data xmit. */ 303 SIO_SET(VR_MIICMD_DIR); 304 305 vr_mii_sync(sc); 306 307 /* Send command/address info. */ 308 vr_mii_send(sc, frame->mii_stdelim, 2); 309 vr_mii_send(sc, frame->mii_opcode, 2); 310 vr_mii_send(sc, frame->mii_phyaddr, 5); 311 vr_mii_send(sc, frame->mii_regaddr, 5); 312 313 /* Idle bit. */ 314 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 315 DELAY(1); 316 SIO_SET(VR_MIICMD_CLK); 317 DELAY(1); 318 319 /* Turn off xmit. */ 320 SIO_CLR(VR_MIICMD_DIR); 321 322 /* Check for ack */ 323 SIO_CLR(VR_MIICMD_CLK); 324 DELAY(1); 325 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 326 SIO_SET(VR_MIICMD_CLK); 327 DELAY(1); 328 329 /* 330 * Now try reading data bits. If the ack failed, we still 331 * need to clock through 16 cycles to keep the PHY(s) in sync. 332 */ 333 if (ack) { 334 for(i = 0; i < 16; i++) { 335 SIO_CLR(VR_MIICMD_CLK); 336 DELAY(1); 337 SIO_SET(VR_MIICMD_CLK); 338 DELAY(1); 339 } 340 goto fail; 341 } 342 343 for (i = 0x8000; i; i >>= 1) { 344 SIO_CLR(VR_MIICMD_CLK); 345 DELAY(1); 346 if (!ack) { 347 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 348 frame->mii_data |= i; 349 DELAY(1); 350 } 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 355fail: 356 SIO_CLR(VR_MIICMD_CLK); 357 DELAY(1); 358 SIO_SET(VR_MIICMD_CLK); 359 DELAY(1); 360 361 if (ack) 362 return (1); 363 return (0); 364} 365#else 366{ 367 int i; 368 369 /* Set the PHY address. */ 370 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 371 frame->mii_phyaddr); 372 373 /* Set the register address. */ 374 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 375 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 376 377 for (i = 0; i < 10000; i++) { 378 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 379 break; 380 DELAY(1); 381 } 382 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 383 384 return (0); 385} 386#endif 387 388 389/* 390 * Write to a PHY register through the MII. 391 */ 392static int 393vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 394#ifdef VR_USESWSHIFT 395{ 396 CSR_WRITE_1(sc, VR_MIICMD, 0); 397 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 398 399 /* Set up frame for TX. */ 400 frame->mii_stdelim = VR_MII_STARTDELIM; 401 frame->mii_opcode = VR_MII_WRITEOP; 402 frame->mii_turnaround = VR_MII_TURNAROUND; 403 404 /* Turn on data output. */ 405 SIO_SET(VR_MIICMD_DIR); 406 407 vr_mii_sync(sc); 408 409 vr_mii_send(sc, frame->mii_stdelim, 2); 410 vr_mii_send(sc, frame->mii_opcode, 2); 411 vr_mii_send(sc, frame->mii_phyaddr, 5); 412 vr_mii_send(sc, frame->mii_regaddr, 5); 413 vr_mii_send(sc, frame->mii_turnaround, 2); 414 vr_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 SIO_SET(VR_MIICMD_CLK); 418 DELAY(1); 419 SIO_CLR(VR_MIICMD_CLK); 420 DELAY(1); 421 422 /* Turn off xmit. */ 423 SIO_CLR(VR_MIICMD_DIR); 424 425 return (0); 426} 427#else 428{ 429 int i; 430 431 /* Set the PHY address. */ 432 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 433 frame->mii_phyaddr); 434 435 /* Set the register address and data to write. */ 436 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 437 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 438 439 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 440 441 for (i = 0; i < 10000; i++) { 442 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 443 break; 444 DELAY(1); 445 } 446 447 return (0); 448} 449#endif 450 451static int 452vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 453{ 454 struct vr_mii_frame frame; 455 struct vr_softc *sc = device_get_softc(dev); 456 457 switch (sc->vr_revid) { 458 case REV_ID_VT6102_APOLLO: 459 if (phy != 1) { 460 frame.mii_data = 0; 461 goto out; 462 } 463 default: 464 break; 465 } 466 467 bzero((char *)&frame, sizeof(frame)); 468 frame.mii_phyaddr = phy; 469 frame.mii_regaddr = reg; 470 vr_mii_readreg(sc, &frame); 471 472out: 473 return (frame.mii_data); 474} 475 476static int 477vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 478{ 479 struct vr_mii_frame frame; 480 struct vr_softc *sc = device_get_softc(dev); 481 482 switch (sc->vr_revid) { 483 case REV_ID_VT6102_APOLLO: 484 if (phy != 1) 485 return (0); 486 default: 487 break; 488 } 489 490 bzero((char *)&frame, sizeof(frame)); 491 frame.mii_phyaddr = phy; 492 frame.mii_regaddr = reg; 493 frame.mii_data = data; 494 vr_mii_writereg(sc, &frame); 495 496 return (0); 497} 498 499static void 500vr_miibus_statchg(device_t dev) 501{ 502 struct mii_data *mii; 503 struct vr_softc *sc = device_get_softc(dev); 504 505 mii = device_get_softc(sc->vr_miibus); 506 vr_setcfg(sc, mii->mii_media_active); 507} 508 509/* 510 * Program the 64-bit multicast hash filter. 511 */ 512static void 513vr_setmulti(struct vr_softc *sc) 514{ 515 struct ifnet *ifp = &sc->arpcom.ac_if; 516 int h = 0; 517 uint32_t hashes[2] = { 0, 0 }; 518 struct ifmultiaddr *ifma; 519 uint8_t rxfilt; 520 int mcnt = 0; 521 522 VR_LOCK_ASSERT(sc); 523 524 rxfilt = CSR_READ_1(sc, VR_RXCFG); 525 526 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 527 rxfilt |= VR_RXCFG_RX_MULTI; 528 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 529 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 530 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 531 return; 532 } 533 534 /* First, zero out all the existing hash bits. */ 535 CSR_WRITE_4(sc, VR_MAR0, 0); 536 CSR_WRITE_4(sc, VR_MAR1, 0); 537 538 /* Now program new ones. */ 539 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 540 if (ifma->ifma_addr->sa_family != AF_LINK) 541 continue; 542 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 543 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 544 if (h < 32) 545 hashes[0] |= (1 << h); 546 else 547 hashes[1] |= (1 << (h - 32)); 548 mcnt++; 549 } 550 551 if (mcnt) 552 rxfilt |= VR_RXCFG_RX_MULTI; 553 else 554 rxfilt &= ~VR_RXCFG_RX_MULTI; 555 556 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 557 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 558 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 559} 560 561/* 562 * In order to fiddle with the 563 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 564 * first have to put the transmit and/or receive logic in the idle state. 565 */ 566static void 567vr_setcfg(struct vr_softc *sc, int media) 568{ 569 int restart = 0; 570 571 VR_LOCK_ASSERT(sc); 572 573 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 574 restart = 1; 575 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 576 } 577 578 if ((media & IFM_GMASK) == IFM_FDX) 579 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 580 else 581 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 582 583 if (restart) 584 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 585} 586 587static void 588vr_reset(struct vr_softc *sc) 589{ 590 register int i; 591 592 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during detach w/o lock. */ 593 594 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 595 596 for (i = 0; i < VR_TIMEOUT; i++) { 597 DELAY(10); 598 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 599 break; 600 } 601 if (i == VR_TIMEOUT) { 602 if (sc->vr_revid < REV_ID_VT3065_A) 603 printf("vr%d: reset never completed!\n", sc->vr_unit); 604 else { 605 /* Use newer force reset command */ 606 printf("vr%d: Using force reset command.\n", 607 sc->vr_unit); 608 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 609 } 610 } 611 612 /* Wait a little while for the chip to get its brains in order. */ 613 DELAY(1000); 614} 615 616/* 617 * Probe for a VIA Rhine chip. Check the PCI vendor and device 618 * IDs against our list and return a device name if we find a match. 619 */ 620static int 621vr_probe(device_t dev) 622{ 623 struct vr_type *t = vr_devs; 624 625 while (t->vr_name != NULL) { 626 if ((pci_get_vendor(dev) == t->vr_vid) && 627 (pci_get_device(dev) == t->vr_did)) { 628 device_set_desc(dev, t->vr_name); 629 return (0); 630 } 631 t++; 632 } 633 634 return (ENXIO); 635} 636 637/* 638 * Attach the interface. Allocate softc structures, do ifmedia 639 * setup and ethernet/BPF attach. 640 */ 641static int 642vr_attach(dev) 643 device_t dev; 644{ 645 int i; 646 u_char eaddr[ETHER_ADDR_LEN]; 647 struct vr_softc *sc; 648 struct ifnet *ifp; 649 int unit, error = 0, rid; 650 651 sc = device_get_softc(dev); 652 unit = device_get_unit(dev); 653 654 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 655 MTX_DEF); 656 /* 657 * Map control/status registers. 658 */ 659 pci_enable_busmaster(dev); 660 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 661 662 rid = VR_RID; 663 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 664 665 if (sc->vr_res == NULL) { 666 printf("vr%d: couldn't map ports/memory\n", unit); 667 error = ENXIO; 668 goto fail; 669 } 670 671 sc->vr_btag = rman_get_bustag(sc->vr_res); 672 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 673 674 /* Allocate interrupt */ 675 rid = 0; 676 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 677 RF_SHAREABLE | RF_ACTIVE); 678 679 if (sc->vr_irq == NULL) { 680 printf("vr%d: couldn't map interrupt\n", unit); 681 error = ENXIO; 682 goto fail; 683 } 684 685 /* 686 * Windows may put the chip in suspend mode when it 687 * shuts down. Be sure to kick it in the head to wake it 688 * up again. 689 */ 690 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 691 692 /* Reset the adapter. */ 693 vr_reset(sc); 694 695 /* 696 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 697 * initialization and disable AUTOPOLL. 698 */ 699 pci_write_config(dev, VR_PCI_MODE, 700 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 701 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 702 703 /* 704 * Get station address. The way the Rhine chips work, 705 * you're not allowed to directly access the EEPROM once 706 * they've been programmed a special way. Consequently, 707 * we need to read the node address from the PAR0 and PAR1 708 * registers. 709 */ 710 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 711 DELAY(200); 712 for (i = 0; i < ETHER_ADDR_LEN; i++) 713 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 714 715 sc->vr_unit = unit; 716 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 717 718 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 719 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 720 721 if (sc->vr_ldata == NULL) { 722 printf("vr%d: no memory for list buffers!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 727 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 728 729 ifp = &sc->arpcom.ac_if; 730 ifp->if_softc = sc; 731 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 732 ifp->if_mtu = ETHERMTU; 733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 734 ifp->if_ioctl = vr_ioctl; 735 ifp->if_start = vr_start; 736 ifp->if_watchdog = vr_watchdog; 737 ifp->if_init = vr_init; 738 ifp->if_baudrate = 10000000; 739 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 740 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 741 IFQ_SET_READY(&ifp->if_snd); 742#ifdef DEVICE_POLLING 743 ifp->if_capabilities |= IFCAP_POLLING; 744#endif 745 ifp->if_capenable = ifp->if_capabilities; 746 747 /* Do MII setup. */ 748 if (mii_phy_probe(dev, &sc->vr_miibus, 749 vr_ifmedia_upd, vr_ifmedia_sts)) { 750 printf("vr%d: MII without any phy!\n", sc->vr_unit); 751 error = ENXIO; 752 goto fail; 753 } 754 755 callout_handle_init(&sc->vr_stat_ch); 756 757 /* Call MI attach routine. */ 758 ether_ifattach(ifp, eaddr); 759 760 sc->suspended = 0; 761 762 /* Hook interrupt last to avoid having to lock softc */ 763 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 764 vr_intr, sc, &sc->vr_intrhand); 765 766 if (error) { 767 printf("vr%d: couldn't set up irq\n", unit); 768 ether_ifdetach(ifp); 769 goto fail; 770 } 771 772fail: 773 if (error) 774 vr_detach(dev); 775 776 return (error); 777} 778 779/* 780 * Shutdown hardware and free up resources. This can be called any 781 * time after the mutex has been initialized. It is called in both 782 * the error case in attach and the normal detach case so it needs 783 * to be careful about only freeing resources that have actually been 784 * allocated. 785 */ 786static int 787vr_detach(device_t dev) 788{ 789 struct vr_softc *sc = device_get_softc(dev); 790 struct ifnet *ifp = &sc->arpcom.ac_if; 791 792 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 793 794 VR_LOCK(sc); 795 796 sc->suspended = 1; 797 798 /* These should only be active if attach succeeded */ 799 if (device_is_attached(dev)) { 800 vr_stop(sc); 801 ether_ifdetach(ifp); 802 } 803 if (sc->vr_miibus) 804 device_delete_child(dev, sc->vr_miibus); 805 bus_generic_detach(dev); 806 807 if (sc->vr_intrhand) 808 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 809 if (sc->vr_irq) 810 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 811 if (sc->vr_res) 812 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 813 814 if (sc->vr_ldata) 815 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 816 817 VR_UNLOCK(sc); 818 mtx_destroy(&sc->vr_mtx); 819 820 return (0); 821} 822 823/* 824 * Initialize the transmit descriptors. 825 */ 826static int 827vr_list_tx_init(struct vr_softc *sc) 828{ 829 struct vr_chain_data *cd; 830 struct vr_list_data *ld; 831 int i; 832 833 cd = &sc->vr_cdata; 834 ld = sc->vr_ldata; 835 for (i = 0; i < VR_TX_LIST_CNT; i++) { 836 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 837 if (i == (VR_TX_LIST_CNT - 1)) 838 cd->vr_tx_chain[i].vr_nextdesc = 839 &cd->vr_tx_chain[0]; 840 else 841 cd->vr_tx_chain[i].vr_nextdesc = 842 &cd->vr_tx_chain[i + 1]; 843 } 844 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 845 846 return (0); 847} 848 849 850/* 851 * Initialize the RX descriptors and allocate mbufs for them. Note that 852 * we arrange the descriptors in a closed ring, so that the last descriptor 853 * points back to the first. 854 */ 855static int 856vr_list_rx_init(struct vr_softc *sc) 857{ 858 struct vr_chain_data *cd; 859 struct vr_list_data *ld; 860 int i; 861 862 VR_LOCK_ASSERT(sc); 863 864 cd = &sc->vr_cdata; 865 ld = sc->vr_ldata; 866 867 for (i = 0; i < VR_RX_LIST_CNT; i++) { 868 cd->vr_rx_chain[i].vr_ptr = 869 (struct vr_desc *)&ld->vr_rx_list[i]; 870 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 871 return (ENOBUFS); 872 if (i == (VR_RX_LIST_CNT - 1)) { 873 cd->vr_rx_chain[i].vr_nextdesc = 874 &cd->vr_rx_chain[0]; 875 ld->vr_rx_list[i].vr_next = 876 vtophys(&ld->vr_rx_list[0]); 877 } else { 878 cd->vr_rx_chain[i].vr_nextdesc = 879 &cd->vr_rx_chain[i + 1]; 880 ld->vr_rx_list[i].vr_next = 881 vtophys(&ld->vr_rx_list[i + 1]); 882 } 883 } 884 885 cd->vr_rx_head = &cd->vr_rx_chain[0]; 886 887 return (0); 888} 889 890/* 891 * Initialize an RX descriptor and attach an MBUF cluster. 892 * Note: the length fields are only 11 bits wide, which means the 893 * largest size we can specify is 2047. This is important because 894 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 895 * overflow the field and make a mess. 896 */ 897static int 898vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 899{ 900 struct mbuf *m_new = NULL; 901 902 if (m == NULL) { 903 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 904 if (m_new == NULL) 905 return (ENOBUFS); 906 907 MCLGET(m_new, M_DONTWAIT); 908 if (!(m_new->m_flags & M_EXT)) { 909 m_freem(m_new); 910 return (ENOBUFS); 911 } 912 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 913 } else { 914 m_new = m; 915 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 916 m_new->m_data = m_new->m_ext.ext_buf; 917 } 918 919 m_adj(m_new, sizeof(uint64_t)); 920 921 c->vr_mbuf = m_new; 922 c->vr_ptr->vr_status = VR_RXSTAT; 923 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 924 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 925 926 return (0); 927} 928 929/* 930 * A frame has been uploaded: pass the resulting mbuf chain up to 931 * the higher level protocols. 932 */ 933static void 934vr_rxeof(struct vr_softc *sc) 935{ 936 struct mbuf *m, *m0; 937 struct ifnet *ifp; 938 struct vr_chain_onefrag *cur_rx; 939 int total_len = 0; 940 uint32_t rxstat; 941 942 VR_LOCK_ASSERT(sc); 943 ifp = &sc->arpcom.ac_if; 944 945 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 946 VR_RXSTAT_OWN)) { 947#ifdef DEVICE_POLLING 948 if (ifp->if_flags & IFF_POLLING) { 949 if (sc->rxcycles <= 0) 950 break; 951 sc->rxcycles--; 952 } 953#endif /* DEVICE_POLLING */ 954 m0 = NULL; 955 cur_rx = sc->vr_cdata.vr_rx_head; 956 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 957 m = cur_rx->vr_mbuf; 958 959 /* 960 * If an error occurs, update stats, clear the 961 * status word and leave the mbuf cluster in place: 962 * it should simply get re-used next time this descriptor 963 * comes up in the ring. 964 */ 965 if (rxstat & VR_RXSTAT_RXERR) { 966 ifp->if_ierrors++; 967 printf("vr%d: rx error (%02x):", sc->vr_unit, 968 rxstat & 0x000000ff); 969 if (rxstat & VR_RXSTAT_CRCERR) 970 printf(" crc error"); 971 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 972 printf(" frame alignment error\n"); 973 if (rxstat & VR_RXSTAT_FIFOOFLOW) 974 printf(" FIFO overflow"); 975 if (rxstat & VR_RXSTAT_GIANT) 976 printf(" received giant packet"); 977 if (rxstat & VR_RXSTAT_RUNT) 978 printf(" received runt packet"); 979 if (rxstat & VR_RXSTAT_BUSERR) 980 printf(" system bus error"); 981 if (rxstat & VR_RXSTAT_BUFFERR) 982 printf("rx buffer error"); 983 printf("\n"); 984 vr_newbuf(sc, cur_rx, m); 985 continue; 986 } 987 988 /* No errors; receive the packet. */ 989 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 990 991 /* 992 * XXX The VIA Rhine chip includes the CRC with every 993 * received frame, and there's no way to turn this 994 * behavior off (at least, I can't find anything in 995 * the manual that explains how to do it) so we have 996 * to trim off the CRC manually. 997 */ 998 total_len -= ETHER_CRC_LEN; 999 1000 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1001 NULL); 1002 vr_newbuf(sc, cur_rx, m); 1003 if (m0 == NULL) { 1004 ifp->if_ierrors++; 1005 continue; 1006 } 1007 m = m0; 1008 1009 ifp->if_ipackets++; 1010 VR_UNLOCK(sc); 1011 (*ifp->if_input)(ifp, m); 1012 VR_LOCK(sc); 1013 } 1014} 1015 1016static void 1017vr_rxeoc(struct vr_softc *sc) 1018{ 1019 struct ifnet *ifp = &sc->arpcom.ac_if; 1020 int i; 1021 1022 VR_LOCK_ASSERT(sc); 1023 1024 ifp->if_ierrors++; 1025 1026 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1027 DELAY(10000); 1028 1029 /* Wait for receiver to stop */ 1030 for (i = 0x400; 1031 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1032 i--) { 1033 ; 1034 } 1035 1036 if (!i) { 1037 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1038 sc->vr_flags |= VR_F_RESTART; 1039 return; 1040 } 1041 1042 vr_rxeof(sc); 1043 1044 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1045 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1046 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1047} 1048 1049/* 1050 * A frame was downloaded to the chip. It's safe for us to clean up 1051 * the list buffers. 1052 */ 1053static void 1054vr_txeof(struct vr_softc *sc) 1055{ 1056 struct vr_chain *cur_tx; 1057 struct ifnet *ifp = &sc->arpcom.ac_if; 1058 1059 VR_LOCK_ASSERT(sc); 1060 1061 /* 1062 * Go through our tx list and free mbufs for those 1063 * frames that have been transmitted. 1064 */ 1065 cur_tx = sc->vr_cdata.vr_tx_cons; 1066 while (cur_tx->vr_mbuf != NULL) { 1067 uint32_t txstat; 1068 int i; 1069 1070 txstat = cur_tx->vr_ptr->vr_status; 1071 1072 if ((txstat & VR_TXSTAT_ABRT) || 1073 (txstat & VR_TXSTAT_UDF)) { 1074 for (i = 0x400; 1075 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1076 i--) 1077 ; /* Wait for chip to shutdown */ 1078 if (!i) { 1079 printf("vr%d: tx shutdown timeout\n", 1080 sc->vr_unit); 1081 sc->vr_flags |= VR_F_RESTART; 1082 break; 1083 } 1084 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1085 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1086 break; 1087 } 1088 1089 if (txstat & VR_TXSTAT_OWN) 1090 break; 1091 1092 if (txstat & VR_TXSTAT_ERRSUM) { 1093 ifp->if_oerrors++; 1094 if (txstat & VR_TXSTAT_DEFER) 1095 ifp->if_collisions++; 1096 if (txstat & VR_TXSTAT_LATECOLL) 1097 ifp->if_collisions++; 1098 } 1099 1100 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1101 1102 ifp->if_opackets++; 1103 m_freem(cur_tx->vr_mbuf); 1104 cur_tx->vr_mbuf = NULL; 1105 ifp->if_flags &= ~IFF_OACTIVE; 1106 1107 cur_tx = cur_tx->vr_nextdesc; 1108 } 1109 sc->vr_cdata.vr_tx_cons = cur_tx; 1110 if (cur_tx->vr_mbuf == NULL) 1111 ifp->if_timer = 0; 1112} 1113 1114static void 1115vr_tick(void *xsc) 1116{ 1117 struct vr_softc *sc = xsc; 1118 struct mii_data *mii; 1119 1120 VR_LOCK(sc); 1121 1122 if (sc->vr_flags & VR_F_RESTART) { 1123 printf("vr%d: restarting\n", sc->vr_unit); 1124 vr_stop(sc); 1125 vr_reset(sc); 1126 vr_init_locked(sc); 1127 sc->vr_flags &= ~VR_F_RESTART; 1128 } 1129 1130 mii = device_get_softc(sc->vr_miibus); 1131 mii_tick(mii); 1132 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1133 1134 VR_UNLOCK(sc); 1135} 1136 1137#ifdef DEVICE_POLLING 1138static poll_handler_t vr_poll; 1139static poll_handler_t vr_poll_locked; 1140 1141static void 1142vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1143{ 1144 struct vr_softc *sc = ifp->if_softc; 1145 1146 VR_LOCK(sc); 1147 vr_poll_locked(ifp, cmd, count); 1148 VR_UNLOCK(sc); 1149} 1150 1151static void 1152vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1153{ 1154 struct vr_softc *sc = ifp->if_softc; 1155 1156 VR_LOCK_ASSERT(sc); 1157 1158 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1159 ether_poll_deregister(ifp); 1160 cmd = POLL_DEREGISTER; 1161 } 1162 1163 if (cmd == POLL_DEREGISTER) { 1164 /* Final call, enable interrupts. */ 1165 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1166 return; 1167 } 1168 1169 sc->rxcycles = count; 1170 vr_rxeof(sc); 1171 vr_txeof(sc); 1172 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1173 vr_start_locked(ifp); 1174 1175 if (cmd == POLL_AND_CHECK_STATUS) { 1176 uint16_t status; 1177 1178 /* Also check status register. */ 1179 status = CSR_READ_2(sc, VR_ISR); 1180 if (status) 1181 CSR_WRITE_2(sc, VR_ISR, status); 1182 1183 if ((status & VR_INTRS) == 0) 1184 return; 1185 1186 if (status & VR_ISR_RX_DROPPED) { 1187 printf("vr%d: rx packet lost\n", sc->vr_unit); 1188 ifp->if_ierrors++; 1189 } 1190 1191 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1192 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1193 printf("vr%d: receive error (%04x)", 1194 sc->vr_unit, status); 1195 if (status & VR_ISR_RX_NOBUF) 1196 printf(" no buffers"); 1197 if (status & VR_ISR_RX_OFLOW) 1198 printf(" overflow"); 1199 if (status & VR_ISR_RX_DROPPED) 1200 printf(" packet lost"); 1201 printf("\n"); 1202 vr_rxeoc(sc); 1203 } 1204 1205 if ((status & VR_ISR_BUSERR) || 1206 (status & VR_ISR_TX_UNDERRUN)) { 1207 vr_reset(sc); 1208 vr_init_locked(sc); 1209 return; 1210 } 1211 1212 if ((status & VR_ISR_UDFI) || 1213 (status & VR_ISR_TX_ABRT2) || 1214 (status & VR_ISR_TX_ABRT)) { 1215 ifp->if_oerrors++; 1216 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1217 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1218 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1219 } 1220 } 1221 } 1222} 1223#endif /* DEVICE_POLLING */ 1224 1225static void 1226vr_intr(void *arg) 1227{ 1228 struct vr_softc *sc = arg; 1229 struct ifnet *ifp = &sc->arpcom.ac_if; 1230 uint16_t status; 1231 1232 VR_LOCK(sc); 1233 1234 if (sc->suspended) 1235 goto done_locked; 1236 1237#ifdef DEVICE_POLLING 1238 if (ifp->if_flags & IFF_POLLING) 1239 goto done_locked; 1240 1241 if ((ifp->if_capenable & IFCAP_POLLING) && 1242 ether_poll_register(vr_poll, ifp)) { 1243 /* OK, disable interrupts. */ 1244 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1245 vr_poll_locked(ifp, 0, 1); 1246 goto done_locked; 1247 } 1248#endif /* DEVICE_POLLING */ 1249 1250 /* Suppress unwanted interrupts. */ 1251 if (!(ifp->if_flags & IFF_UP)) { 1252 vr_stop(sc); 1253 goto done_locked; 1254 } 1255 1256 /* Disable interrupts. */ 1257 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1258 1259 for (;;) { 1260 status = CSR_READ_2(sc, VR_ISR); 1261 if (status) 1262 CSR_WRITE_2(sc, VR_ISR, status); 1263 1264 if ((status & VR_INTRS) == 0) 1265 break; 1266 1267 if (status & VR_ISR_RX_OK) 1268 vr_rxeof(sc); 1269 1270 if (status & VR_ISR_RX_DROPPED) { 1271 printf("vr%d: rx packet lost\n", sc->vr_unit); 1272 ifp->if_ierrors++; 1273 } 1274 1275 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1276 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1277 printf("vr%d: receive error (%04x)", 1278 sc->vr_unit, status); 1279 if (status & VR_ISR_RX_NOBUF) 1280 printf(" no buffers"); 1281 if (status & VR_ISR_RX_OFLOW) 1282 printf(" overflow"); 1283 if (status & VR_ISR_RX_DROPPED) 1284 printf(" packet lost"); 1285 printf("\n"); 1286 vr_rxeoc(sc); 1287 } 1288 1289 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1290 vr_reset(sc); 1291 vr_init_locked(sc); 1292 break; 1293 } 1294 1295 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1296 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1297 vr_txeof(sc); 1298 if ((status & VR_ISR_UDFI) || 1299 (status & VR_ISR_TX_ABRT2) || 1300 (status & VR_ISR_TX_ABRT)) { 1301 ifp->if_oerrors++; 1302 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1303 VR_SETBIT16(sc, VR_COMMAND, 1304 VR_CMD_TX_ON); 1305 VR_SETBIT16(sc, VR_COMMAND, 1306 VR_CMD_TX_GO); 1307 } 1308 } 1309 } 1310 } 1311 1312 /* Re-enable interrupts. */ 1313 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1314 1315 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1316 vr_start_locked(ifp); 1317 1318done_locked: 1319 VR_UNLOCK(sc); 1320} 1321 1322/* 1323 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1324 * pointers to the fragment pointers. 1325 */ 1326static int 1327vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1328{ 1329 struct vr_desc *f = NULL; 1330 struct mbuf *m; 1331 1332 VR_LOCK_ASSERT(sc); 1333 /* 1334 * The VIA Rhine wants packet buffers to be longword 1335 * aligned, but very often our mbufs aren't. Rather than 1336 * waste time trying to decide when to copy and when not 1337 * to copy, just do it all the time. 1338 */ 1339 m = m_defrag(m_head, M_DONTWAIT); 1340 if (m == NULL) 1341 return (1); 1342 1343 /* 1344 * The Rhine chip doesn't auto-pad, so we have to make 1345 * sure to pad short frames out to the minimum frame length 1346 * ourselves. 1347 */ 1348 if (m->m_len < VR_MIN_FRAMELEN) { 1349 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1350 m->m_len = m->m_pkthdr.len; 1351 } 1352 1353 c->vr_mbuf = m; 1354 f = c->vr_ptr; 1355 f->vr_data = vtophys(mtod(m, caddr_t)); 1356 f->vr_ctl = m->m_len; 1357 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1358 f->vr_status = 0; 1359 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1360 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1361 1362 return (0); 1363} 1364 1365/* 1366 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1367 * to the mbuf data regions directly in the transmit lists. We also save a 1368 * copy of the pointers since the transmit list fragment pointers are 1369 * physical addresses. 1370 */ 1371 1372static void 1373vr_start(struct ifnet *ifp) 1374{ 1375 struct vr_softc *sc = ifp->if_softc; 1376 1377 VR_LOCK(sc); 1378 vr_start_locked(ifp); 1379 VR_UNLOCK(sc); 1380} 1381 1382static void 1383vr_start_locked(struct ifnet *ifp) 1384{ 1385 struct vr_softc *sc = ifp->if_softc; 1386 struct mbuf *m_head; 1387 struct vr_chain *cur_tx; 1388 1389 if (ifp->if_flags & IFF_OACTIVE) 1390 return; 1391 1392 cur_tx = sc->vr_cdata.vr_tx_prod; 1393 while (cur_tx->vr_mbuf == NULL) { 1394 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1395 if (m_head == NULL) 1396 break; 1397 1398 /* Pack the data into the descriptor. */ 1399 if (vr_encap(sc, cur_tx, m_head)) { 1400 /* Rollback, send what we were able to encap. */ 1401 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1402 break; 1403 } 1404 1405 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1406 1407 /* 1408 * If there's a BPF listener, bounce a copy of this frame 1409 * to him. 1410 */ 1411 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1412 1413 cur_tx = cur_tx->vr_nextdesc; 1414 } 1415 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1416 sc->vr_cdata.vr_tx_prod = cur_tx; 1417 1418 /* Tell the chip to start transmitting. */ 1419 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1420 1421 /* Set a timeout in case the chip goes out to lunch. */ 1422 ifp->if_timer = 5; 1423 1424 if (cur_tx->vr_mbuf != NULL) 1425 ifp->if_flags |= IFF_OACTIVE; 1426 } 1427} 1428 1429static void 1430vr_init(void *xsc) 1431{ 1432 struct vr_softc *sc = xsc; 1433 1434 VR_LOCK(sc); 1435 vr_init_locked(sc); 1436 VR_UNLOCK(sc); 1437} 1438 1439static void 1440vr_init_locked(struct vr_softc *sc) 1441{ 1442 struct ifnet *ifp = &sc->arpcom.ac_if; 1443 struct mii_data *mii; 1444 int i; 1445 1446 VR_LOCK_ASSERT(sc); 1447 1448 mii = device_get_softc(sc->vr_miibus); 1449 1450 /* Cancel pending I/O and free all RX/TX buffers. */ 1451 vr_stop(sc); 1452 vr_reset(sc); 1453 1454 /* Set our station address. */ 1455 for (i = 0; i < ETHER_ADDR_LEN; i++) 1456 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1457 1458 /* Set DMA size. */ 1459 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1460 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1461 1462 /* 1463 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1464 * so we must set both. 1465 */ 1466 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1467 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1468 1469 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1470 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1471 1472 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1473 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1474 1475 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1476 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1477 1478 /* Init circular RX list. */ 1479 if (vr_list_rx_init(sc) == ENOBUFS) { 1480 printf( 1481"vr%d: initialization failed: no memory for rx buffers\n", sc->vr_unit); 1482 vr_stop(sc); 1483 return; 1484 } 1485 1486 /* Init tx descriptors. */ 1487 vr_list_tx_init(sc); 1488 1489 /* If we want promiscuous mode, set the allframes bit. */ 1490 if (ifp->if_flags & IFF_PROMISC) 1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1492 else 1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1494 1495 /* Set capture broadcast bit to capture broadcast frames. */ 1496 if (ifp->if_flags & IFF_BROADCAST) 1497 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1498 else 1499 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1500 1501 /* 1502 * Program the multicast filter, if necessary. 1503 */ 1504 vr_setmulti(sc); 1505 1506 /* 1507 * Load the address of the RX list. 1508 */ 1509 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1510 1511 /* Enable receiver and transmitter. */ 1512 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1513 VR_CMD_TX_ON|VR_CMD_RX_ON| 1514 VR_CMD_RX_GO); 1515 1516 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1517 1518 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1519#ifdef DEVICE_POLLING 1520 /* 1521 * Disable interrupts if we are polling. 1522 */ 1523 if (ifp->if_flags & IFF_POLLING) 1524 CSR_WRITE_2(sc, VR_IMR, 0); 1525 else 1526#endif /* DEVICE_POLLING */ 1527 /* 1528 * Enable interrupts. 1529 */ 1530 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1531 1532 mii_mediachg(mii); 1533 1534 ifp->if_flags |= IFF_RUNNING; 1535 ifp->if_flags &= ~IFF_OACTIVE; 1536 1537 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1538} 1539 1540/* 1541 * Set media options. 1542 */ 1543static int 1544vr_ifmedia_upd(struct ifnet *ifp) 1545{ 1546 struct vr_softc *sc = ifp->if_softc; 1547 1548 if (ifp->if_flags & IFF_UP) 1549 vr_init(sc); 1550 1551 return (0); 1552} 1553 1554/* 1555 * Report current media status. 1556 */ 1557static void 1558vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1559{ 1560 struct vr_softc *sc = ifp->if_softc; 1561 struct mii_data *mii; 1562 1563 mii = device_get_softc(sc->vr_miibus); 1564 mii_pollstat(mii); 1565 ifmr->ifm_active = mii->mii_media_active; 1566 ifmr->ifm_status = mii->mii_media_status; 1567} 1568 1569static int 1570vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1571{ 1572 struct vr_softc *sc = ifp->if_softc; 1573 struct ifreq *ifr = (struct ifreq *) data; 1574 struct mii_data *mii; 1575 int error = 0; 1576 1577 switch (command) { 1578 case SIOCSIFFLAGS: 1579 VR_LOCK(sc); 1580 if (ifp->if_flags & IFF_UP) { 1581 vr_init_locked(sc); 1582 } else { 1583 if (ifp->if_flags & IFF_RUNNING) 1584 vr_stop(sc); 1585 } 1586 VR_UNLOCK(sc); 1587 error = 0; 1588 break; 1589 case SIOCADDMULTI: 1590 case SIOCDELMULTI: 1591 VR_LOCK(sc); 1592 vr_setmulti(sc); 1593 VR_UNLOCK(sc); 1594 error = 0; 1595 break; 1596 case SIOCGIFMEDIA: 1597 case SIOCSIFMEDIA: 1598 mii = device_get_softc(sc->vr_miibus); 1599 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1600 break; 1601 case SIOCSIFCAP: 1602 ifp->if_capenable = ifr->ifr_reqcap; 1603 break; 1604 default: 1605 error = ether_ioctl(ifp, command, data); 1606 break; 1607 } 1608 1609 return (error); 1610} 1611 1612static void 1613vr_watchdog(struct ifnet *ifp) 1614{ 1615 struct vr_softc *sc = ifp->if_softc; 1616 1617 VR_LOCK(sc); 1618 1619 ifp->if_oerrors++; 1620 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1621 1622 vr_stop(sc); 1623 vr_reset(sc); 1624 vr_init_locked(sc); 1625 1626 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1627 vr_start_locked(ifp); 1628 1629 VR_UNLOCK(sc); 1630} 1631 1632/* 1633 * Stop the adapter and free any mbufs allocated to the 1634 * RX and TX lists. 1635 */ 1636static void 1637vr_stop(struct vr_softc *sc) 1638{ 1639 register int i; 1640 struct ifnet *ifp; 1641 1642 VR_LOCK_ASSERT(sc); 1643 1644 ifp = &sc->arpcom.ac_if; 1645 ifp->if_timer = 0; 1646 1647 untimeout(vr_tick, sc, sc->vr_stat_ch); 1648 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1649#ifdef DEVICE_POLLING 1650 ether_poll_deregister(ifp); 1651#endif /* DEVICE_POLLING */ 1652 1653 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1654 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1655 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1656 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1657 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1658 1659 /* 1660 * Free data in the RX lists. 1661 */ 1662 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1663 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1664 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1665 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1666 } 1667 } 1668 bzero((char *)&sc->vr_ldata->vr_rx_list, 1669 sizeof(sc->vr_ldata->vr_rx_list)); 1670 1671 /* 1672 * Free the TX list buffers. 1673 */ 1674 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1675 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1676 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1677 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1678 } 1679 } 1680 bzero((char *)&sc->vr_ldata->vr_tx_list, 1681 sizeof(sc->vr_ldata->vr_tx_list)); 1682} 1683 1684/* 1685 * Stop all chip I/O so that the kernel's probe routines don't 1686 * get confused by errant DMAs when rebooting. 1687 */ 1688static void 1689vr_shutdown(device_t dev) 1690{ 1691 struct vr_softc *sc = device_get_softc(dev); 1692 1693 VR_LOCK(sc); 1694 vr_stop(sc); 1695 VR_UNLOCK(sc); 1696} 1697