if_vr.c revision 128118
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 128118 2004-04-11 15:18:09Z ru $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include <sys/param.h> 63#include <sys/systm.h> 64#include <sys/sockio.h> 65#include <sys/mbuf.h> 66#include <sys/malloc.h> 67#include <sys/kernel.h> 68#include <sys/socket.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75 76#include <net/bpf.h> 77 78#include <vm/vm.h> /* for vtophys */ 79#include <vm/pmap.h> /* for vtophys */ 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#define VR_USEIOSPACE 94 95#include <pci/if_vrreg.h> 96 97MODULE_DEPEND(vr, pci, 1, 1, 1); 98MODULE_DEPEND(vr, ether, 1, 1, 1); 99MODULE_DEPEND(vr, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104#undef VR_USESWSHIFT 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125}; 126 127static int vr_probe (device_t); 128static int vr_attach (device_t); 129static int vr_detach (device_t); 130 131static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137static void vr_rxeof (struct vr_softc *); 138static void vr_rxeoc (struct vr_softc *); 139static void vr_txeof (struct vr_softc *); 140static void vr_tick (void *); 141static void vr_intr (void *); 142static void vr_start (struct ifnet *); 143static int vr_ioctl (struct ifnet *, u_long, caddr_t); 144static void vr_init (void *); 145static void vr_stop (struct vr_softc *); 146static void vr_watchdog (struct ifnet *); 147static void vr_shutdown (device_t); 148static int vr_ifmedia_upd (struct ifnet *); 149static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 150 151#ifdef VR_USESWSHIFT 152static void vr_mii_sync (struct vr_softc *); 153static void vr_mii_send (struct vr_softc *, u_int32_t, int); 154#endif 155static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 156static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 157static int vr_miibus_readreg (device_t, int, int); 158static int vr_miibus_writereg (device_t, int, int, int); 159static void vr_miibus_statchg (device_t); 160 161static void vr_setcfg (struct vr_softc *, int); 162static uint32_t vr_mchash (const uint8_t *); 163static void vr_setmulti (struct vr_softc *); 164static void vr_reset (struct vr_softc *); 165static int vr_list_rx_init (struct vr_softc *); 166static int vr_list_tx_init (struct vr_softc *); 167 168#ifdef VR_USEIOSPACE 169#define VR_RES SYS_RES_IOPORT 170#define VR_RID VR_PCI_LOIO 171#else 172#define VR_RES SYS_RES_MEMORY 173#define VR_RID VR_PCI_LOMEM 174#endif 175 176static device_method_t vr_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, vr_probe), 179 DEVMETHOD(device_attach, vr_attach), 180 DEVMETHOD(device_detach, vr_detach), 181 DEVMETHOD(device_shutdown, vr_shutdown), 182 183 /* bus interface */ 184 DEVMETHOD(bus_print_child, bus_generic_print_child), 185 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 186 187 /* MII interface */ 188 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 189 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 190 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 191 192 { 0, 0 } 193}; 194 195static driver_t vr_driver = { 196 "vr", 197 vr_methods, 198 sizeof(struct vr_softc) 199}; 200 201static devclass_t vr_devclass; 202 203DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 204DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 205 206#define VR_SETBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) | (x)) 209 210#define VR_CLRBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) & ~(x)) 213 214#define VR_SETBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) | (x)) 217 218#define VR_CLRBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) & ~(x)) 221 222#define VR_SETBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define VR_CLRBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 237 238#ifdef VR_USESWSHIFT 239/* 240 * Sync the PHYs by setting data bit and strobing the clock 32 times. 241 */ 242static void 243vr_mii_sync(sc) 244 struct vr_softc *sc; 245{ 246 register int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 257 return; 258} 259 260/* 261 * Clock a series of bits through the MII. 262 */ 263static void 264vr_mii_send(sc, bits, cnt) 265 struct vr_softc *sc; 266 u_int32_t bits; 267 int cnt; 268{ 269 int i; 270 271 SIO_CLR(VR_MIICMD_CLK); 272 273 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 274 if (bits & i) { 275 SIO_SET(VR_MIICMD_DATAIN); 276 } else { 277 SIO_CLR(VR_MIICMD_DATAIN); 278 } 279 DELAY(1); 280 SIO_CLR(VR_MIICMD_CLK); 281 DELAY(1); 282 SIO_SET(VR_MIICMD_CLK); 283 } 284} 285#endif 286 287/* 288 * Read an PHY register through the MII. 289 */ 290static int 291vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295#ifdef VR_USESWSHIFT 296{ 297 int i, ack; 298 299 VR_LOCK(sc); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 VR_UNLOCK(sc); 377 378 if (ack) 379 return(1); 380 return(0); 381} 382#else 383{ 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407} 408#endif 409 410 411/* 412 * Write to a PHY register through the MII. 413 */ 414static int 415vr_mii_writereg(sc, frame) 416 struct vr_softc *sc; 417 struct vr_mii_frame *frame; 418 419#ifdef VR_USESWSHIFT 420{ 421 VR_LOCK(sc); 422 423 CSR_WRITE_1(sc, VR_MIICMD, 0); 424 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 425 426 /* 427 * Set up frame for TX. 428 */ 429 430 frame->mii_stdelim = VR_MII_STARTDELIM; 431 frame->mii_opcode = VR_MII_WRITEOP; 432 frame->mii_turnaround = VR_MII_TURNAROUND; 433 434 /* 435 * Turn on data output. 436 */ 437 SIO_SET(VR_MIICMD_DIR); 438 439 vr_mii_sync(sc); 440 441 vr_mii_send(sc, frame->mii_stdelim, 2); 442 vr_mii_send(sc, frame->mii_opcode, 2); 443 vr_mii_send(sc, frame->mii_phyaddr, 5); 444 vr_mii_send(sc, frame->mii_regaddr, 5); 445 vr_mii_send(sc, frame->mii_turnaround, 2); 446 vr_mii_send(sc, frame->mii_data, 16); 447 448 /* Idle bit. */ 449 SIO_SET(VR_MIICMD_CLK); 450 DELAY(1); 451 SIO_CLR(VR_MIICMD_CLK); 452 DELAY(1); 453 454 /* 455 * Turn off xmit. 456 */ 457 SIO_CLR(VR_MIICMD_DIR); 458 459 VR_UNLOCK(sc); 460 461 return(0); 462} 463#else 464{ 465 int s, i; 466 467 s = splimp(); 468 469 /* Set the PHY-adress */ 470 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 471 frame->mii_phyaddr); 472 473 /* Set the register-adress and data to write */ 474 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 475 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 476 477 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 478 479 for (i = 0; i < 10000; i++) { 480 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 481 break; 482 DELAY(1); 483 } 484 485 (void)splx(s); 486 487 return(0); 488} 489#endif 490 491static int 492vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516} 517 518static int 519vr_miibus_writereg(dev, phy, reg, data) 520 device_t dev; 521 u_int16_t phy, reg, data; 522{ 523 struct vr_softc *sc; 524 struct vr_mii_frame frame; 525 526 sc = device_get_softc(dev); 527 528 switch (sc->vr_revid) { 529 case REV_ID_VT6102_APOLLO: 530 if (phy != 1) 531 return 0; 532 default: 533 break; 534 } 535 536 bzero((char *)&frame, sizeof(frame)); 537 538 frame.mii_phyaddr = phy; 539 frame.mii_regaddr = reg; 540 frame.mii_data = data; 541 542 vr_mii_writereg(sc, &frame); 543 544 return(0); 545} 546 547static void 548vr_miibus_statchg(dev) 549 device_t dev; 550{ 551 struct vr_softc *sc; 552 struct mii_data *mii; 553 554 sc = device_get_softc(dev); 555 VR_LOCK(sc); 556 mii = device_get_softc(sc->vr_miibus); 557 vr_setcfg(sc, mii->mii_media_active); 558 VR_UNLOCK(sc); 559 560 return; 561} 562 563/* 564 * Calculate CRC of a multicast group address, return the lower 6 bits. 565 */ 566static u_int32_t 567vr_mchash(addr) 568 const uint8_t *addr; 569{ 570 uint32_t crc, carry; 571 int idx, bit; 572 uint8_t data; 573 574 /* Compute CRC for the address value. */ 575 crc = 0xFFFFFFFF; /* initial value */ 576 577 for (idx = 0; idx < 6; idx++) { 578 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 579 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 580 crc <<= 1; 581 if (carry) 582 crc = (crc ^ 0x04c11db6) | carry; 583 } 584 } 585 586 /* return the filter bit position */ 587 return((crc >> 26) & 0x0000003F); 588} 589 590/* 591 * Program the 64-bit multicast hash filter. 592 */ 593static void 594vr_setmulti(sc) 595 struct vr_softc *sc; 596{ 597 struct ifnet *ifp; 598 int h = 0; 599 u_int32_t hashes[2] = { 0, 0 }; 600 struct ifmultiaddr *ifma; 601 u_int8_t rxfilt; 602 int mcnt = 0; 603 604 ifp = &sc->arpcom.ac_if; 605 606 rxfilt = CSR_READ_1(sc, VR_RXCFG); 607 608 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 609 rxfilt |= VR_RXCFG_RX_MULTI; 610 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 611 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 612 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 613 return; 614 } 615 616 /* first, zot all the existing hash bits */ 617 CSR_WRITE_4(sc, VR_MAR0, 0); 618 CSR_WRITE_4(sc, VR_MAR1, 0); 619 620 /* now program new ones */ 621 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 622 if (ifma->ifma_addr->sa_family != AF_LINK) 623 continue; 624 h = vr_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 625 if (h < 32) 626 hashes[0] |= (1 << h); 627 else 628 hashes[1] |= (1 << (h - 32)); 629 mcnt++; 630 } 631 632 if (mcnt) 633 rxfilt |= VR_RXCFG_RX_MULTI; 634 else 635 rxfilt &= ~VR_RXCFG_RX_MULTI; 636 637 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 638 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 639 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 640 641 return; 642} 643 644/* 645 * In order to fiddle with the 646 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 647 * first have to put the transmit and/or receive logic in the idle state. 648 */ 649static void 650vr_setcfg(sc, media) 651 struct vr_softc *sc; 652 int media; 653{ 654 int restart = 0; 655 656 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 657 restart = 1; 658 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 659 } 660 661 if ((media & IFM_GMASK) == IFM_FDX) 662 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 663 else 664 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 665 666 if (restart) 667 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 668 669 return; 670} 671 672static void 673vr_reset(sc) 674 struct vr_softc *sc; 675{ 676 register int i; 677 678 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 679 680 for (i = 0; i < VR_TIMEOUT; i++) { 681 DELAY(10); 682 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 683 break; 684 } 685 if (i == VR_TIMEOUT) { 686 if (sc->vr_revid < REV_ID_VT3065_A) 687 printf("vr%d: reset never completed!\n", sc->vr_unit); 688 else { 689 /* Use newer force reset command */ 690 printf("vr%d: Using force reset command.\n", sc->vr_unit); 691 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 692 } 693 } 694 695 /* Wait a little while for the chip to get its brains in order. */ 696 DELAY(1000); 697 698 return; 699} 700 701/* 702 * Probe for a VIA Rhine chip. Check the PCI vendor and device 703 * IDs against our list and return a device name if we find a match. 704 */ 705static int 706vr_probe(dev) 707 device_t dev; 708{ 709 struct vr_type *t; 710 711 t = vr_devs; 712 713 while(t->vr_name != NULL) { 714 if ((pci_get_vendor(dev) == t->vr_vid) && 715 (pci_get_device(dev) == t->vr_did)) { 716 device_set_desc(dev, t->vr_name); 717 return(0); 718 } 719 t++; 720 } 721 722 return(ENXIO); 723} 724 725/* 726 * Attach the interface. Allocate softc structures, do ifmedia 727 * setup and ethernet/BPF attach. 728 */ 729static int 730vr_attach(dev) 731 device_t dev; 732{ 733 int i; 734 u_char eaddr[ETHER_ADDR_LEN]; 735 struct vr_softc *sc; 736 struct ifnet *ifp; 737 int unit, error = 0, rid; 738 739 sc = device_get_softc(dev); 740 unit = device_get_unit(dev); 741 742 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 743 MTX_DEF | MTX_RECURSE); 744#ifndef BURN_BRIDGES 745 /* 746 * Handle power management nonsense. 747 */ 748 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 749 u_int32_t iobase, membase, irq; 750 751 /* Save important PCI config data. */ 752 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 753 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 754 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 755 756 /* Reset the power state. */ 757 printf("vr%d: chip is in D%d power mode " 758 "-- setting to D0\n", unit, 759 pci_get_powerstate(dev)); 760 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 761 762 /* Restore PCI config data. */ 763 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 764 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 765 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 766 } 767#endif 768 /* 769 * Map control/status registers. 770 */ 771 pci_enable_busmaster(dev); 772 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 773 774 rid = VR_RID; 775 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 776 777 if (sc->vr_res == NULL) { 778 printf("vr%d: couldn't map ports/memory\n", unit); 779 error = ENXIO; 780 goto fail; 781 } 782 783 sc->vr_btag = rman_get_bustag(sc->vr_res); 784 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 785 786 /* Allocate interrupt */ 787 rid = 0; 788 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 789 RF_SHAREABLE | RF_ACTIVE); 790 791 if (sc->vr_irq == NULL) { 792 printf("vr%d: couldn't map interrupt\n", unit); 793 error = ENXIO; 794 goto fail; 795 } 796 797 /* 798 * Windows may put the chip in suspend mode when it 799 * shuts down. Be sure to kick it in the head to wake it 800 * up again. 801 */ 802 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 803 804 /* Reset the adapter. */ 805 vr_reset(sc); 806 807 /* 808 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 809 * initialization and disable AUTOPOLL. 810 */ 811 pci_write_config(dev, VR_PCI_MODE, 812 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 813 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 814 815 /* 816 * Get station address. The way the Rhine chips work, 817 * you're not allowed to directly access the EEPROM once 818 * they've been programmed a special way. Consequently, 819 * we need to read the node address from the PAR0 and PAR1 820 * registers. 821 */ 822 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 823 DELAY(200); 824 for (i = 0; i < ETHER_ADDR_LEN; i++) 825 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 826 827 sc->vr_unit = unit; 828 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 829 830 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 831 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 832 833 if (sc->vr_ldata == NULL) { 834 printf("vr%d: no memory for list buffers!\n", unit); 835 error = ENXIO; 836 goto fail; 837 } 838 839 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 840 841 ifp = &sc->arpcom.ac_if; 842 ifp->if_softc = sc; 843 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 844 ifp->if_mtu = ETHERMTU; 845 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 846 ifp->if_ioctl = vr_ioctl; 847 ifp->if_start = vr_start; 848 ifp->if_watchdog = vr_watchdog; 849 ifp->if_init = vr_init; 850 ifp->if_baudrate = 10000000; 851 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 852#ifdef DEVICE_POLLING 853 ifp->if_capabilities |= IFCAP_POLLING; 854#endif 855 ifp->if_capenable = ifp->if_capabilities; 856 857 /* 858 * Do MII setup. 859 */ 860 if (mii_phy_probe(dev, &sc->vr_miibus, 861 vr_ifmedia_upd, vr_ifmedia_sts)) { 862 printf("vr%d: MII without any phy!\n", sc->vr_unit); 863 error = ENXIO; 864 goto fail; 865 } 866 867 callout_handle_init(&sc->vr_stat_ch); 868 869 /* 870 * Call MI attach routine. 871 */ 872 ether_ifattach(ifp, eaddr); 873 874 /* Hook interrupt last to avoid having to lock softc */ 875 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 876 vr_intr, sc, &sc->vr_intrhand); 877 878 if (error) { 879 printf("vr%d: couldn't set up irq\n", unit); 880 ether_ifdetach(ifp); 881 goto fail; 882 } 883 884fail: 885 if (error) 886 vr_detach(dev); 887 888 return(error); 889} 890 891/* 892 * Shutdown hardware and free up resources. This can be called any 893 * time after the mutex has been initialized. It is called in both 894 * the error case in attach and the normal detach case so it needs 895 * to be careful about only freeing resources that have actually been 896 * allocated. 897 */ 898static int 899vr_detach(dev) 900 device_t dev; 901{ 902 struct vr_softc *sc; 903 struct ifnet *ifp; 904 905 sc = device_get_softc(dev); 906 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 907 VR_LOCK(sc); 908 ifp = &sc->arpcom.ac_if; 909 910 /* These should only be active if attach succeeded */ 911 if (device_is_attached(dev)) { 912 vr_stop(sc); 913 ether_ifdetach(ifp); 914 } 915 if (sc->vr_miibus) 916 device_delete_child(dev, sc->vr_miibus); 917 bus_generic_detach(dev); 918 919 if (sc->vr_intrhand) 920 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 921 if (sc->vr_irq) 922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 923 if (sc->vr_res) 924 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 925 926 if (sc->vr_ldata) 927 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 928 929 VR_UNLOCK(sc); 930 mtx_destroy(&sc->vr_mtx); 931 932 return(0); 933} 934 935/* 936 * Initialize the transmit descriptors. 937 */ 938static int 939vr_list_tx_init(sc) 940 struct vr_softc *sc; 941{ 942 struct vr_chain_data *cd; 943 struct vr_list_data *ld; 944 int i; 945 946 cd = &sc->vr_cdata; 947 ld = sc->vr_ldata; 948 for (i = 0; i < VR_TX_LIST_CNT; i++) { 949 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 950 if (i == (VR_TX_LIST_CNT - 1)) 951 cd->vr_tx_chain[i].vr_nextdesc = 952 &cd->vr_tx_chain[0]; 953 else 954 cd->vr_tx_chain[i].vr_nextdesc = 955 &cd->vr_tx_chain[i + 1]; 956 } 957 958 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 959 960 return(0); 961} 962 963 964/* 965 * Initialize the RX descriptors and allocate mbufs for them. Note that 966 * we arrange the descriptors in a closed ring, so that the last descriptor 967 * points back to the first. 968 */ 969static int 970vr_list_rx_init(sc) 971 struct vr_softc *sc; 972{ 973 struct vr_chain_data *cd; 974 struct vr_list_data *ld; 975 int i; 976 977 cd = &sc->vr_cdata; 978 ld = sc->vr_ldata; 979 980 for (i = 0; i < VR_RX_LIST_CNT; i++) { 981 cd->vr_rx_chain[i].vr_ptr = 982 (struct vr_desc *)&ld->vr_rx_list[i]; 983 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 984 return(ENOBUFS); 985 if (i == (VR_RX_LIST_CNT - 1)) { 986 cd->vr_rx_chain[i].vr_nextdesc = 987 &cd->vr_rx_chain[0]; 988 ld->vr_rx_list[i].vr_next = 989 vtophys(&ld->vr_rx_list[0]); 990 } else { 991 cd->vr_rx_chain[i].vr_nextdesc = 992 &cd->vr_rx_chain[i + 1]; 993 ld->vr_rx_list[i].vr_next = 994 vtophys(&ld->vr_rx_list[i + 1]); 995 } 996 } 997 998 cd->vr_rx_head = &cd->vr_rx_chain[0]; 999 1000 return(0); 1001} 1002 1003/* 1004 * Initialize an RX descriptor and attach an MBUF cluster. 1005 * Note: the length fields are only 11 bits wide, which means the 1006 * largest size we can specify is 2047. This is important because 1007 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1008 * overflow the field and make a mess. 1009 */ 1010static int 1011vr_newbuf(sc, c, m) 1012 struct vr_softc *sc; 1013 struct vr_chain_onefrag *c; 1014 struct mbuf *m; 1015{ 1016 struct mbuf *m_new = NULL; 1017 1018 if (m == NULL) { 1019 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1020 if (m_new == NULL) 1021 return(ENOBUFS); 1022 1023 MCLGET(m_new, M_DONTWAIT); 1024 if (!(m_new->m_flags & M_EXT)) { 1025 m_freem(m_new); 1026 return(ENOBUFS); 1027 } 1028 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1029 } else { 1030 m_new = m; 1031 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1032 m_new->m_data = m_new->m_ext.ext_buf; 1033 } 1034 1035 m_adj(m_new, sizeof(u_int64_t)); 1036 1037 c->vr_mbuf = m_new; 1038 c->vr_ptr->vr_status = VR_RXSTAT; 1039 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1040 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1041 1042 return(0); 1043} 1044 1045/* 1046 * A frame has been uploaded: pass the resulting mbuf chain up to 1047 * the higher level protocols. 1048 */ 1049static void 1050vr_rxeof(sc) 1051 struct vr_softc *sc; 1052{ 1053 struct mbuf *m, *m0; 1054 struct ifnet *ifp; 1055 struct vr_chain_onefrag *cur_rx; 1056 int total_len = 0; 1057 u_int32_t rxstat; 1058 1059 VR_LOCK_ASSERT(sc); 1060 1061 ifp = &sc->arpcom.ac_if; 1062 1063 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1064 VR_RXSTAT_OWN)) { 1065#ifdef DEVICE_POLLING 1066 if (ifp->if_flags & IFF_POLLING) { 1067 if (sc->rxcycles <= 0) 1068 break; 1069 sc->rxcycles--; 1070 } 1071#endif /* DEVICE_POLLING */ 1072 m0 = NULL; 1073 cur_rx = sc->vr_cdata.vr_rx_head; 1074 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1075 m = cur_rx->vr_mbuf; 1076 1077 /* 1078 * If an error occurs, update stats, clear the 1079 * status word and leave the mbuf cluster in place: 1080 * it should simply get re-used next time this descriptor 1081 * comes up in the ring. 1082 */ 1083 if (rxstat & VR_RXSTAT_RXERR) { 1084 ifp->if_ierrors++; 1085 printf("vr%d: rx error (%02x):", 1086 sc->vr_unit, rxstat & 0x000000ff); 1087 if (rxstat & VR_RXSTAT_CRCERR) 1088 printf(" crc error"); 1089 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1090 printf(" frame alignment error\n"); 1091 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1092 printf(" FIFO overflow"); 1093 if (rxstat & VR_RXSTAT_GIANT) 1094 printf(" received giant packet"); 1095 if (rxstat & VR_RXSTAT_RUNT) 1096 printf(" received runt packet"); 1097 if (rxstat & VR_RXSTAT_BUSERR) 1098 printf(" system bus error"); 1099 if (rxstat & VR_RXSTAT_BUFFERR) 1100 printf("rx buffer error"); 1101 printf("\n"); 1102 vr_newbuf(sc, cur_rx, m); 1103 continue; 1104 } 1105 1106 /* No errors; receive the packet. */ 1107 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1108 1109 /* 1110 * XXX The VIA Rhine chip includes the CRC with every 1111 * received frame, and there's no way to turn this 1112 * behavior off (at least, I can't find anything in 1113 * the manual that explains how to do it) so we have 1114 * to trim off the CRC manually. 1115 */ 1116 total_len -= ETHER_CRC_LEN; 1117 1118 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1119 NULL); 1120 vr_newbuf(sc, cur_rx, m); 1121 if (m0 == NULL) { 1122 ifp->if_ierrors++; 1123 continue; 1124 } 1125 m = m0; 1126 1127 ifp->if_ipackets++; 1128 VR_UNLOCK(sc); 1129 (*ifp->if_input)(ifp, m); 1130 VR_LOCK(sc); 1131 } 1132 1133 return; 1134} 1135 1136static void 1137vr_rxeoc(sc) 1138 struct vr_softc *sc; 1139{ 1140 struct ifnet *ifp; 1141 int i; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 ifp->if_ierrors++; 1146 1147 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1148 DELAY(10000); 1149 1150 for (i = 0x400; 1151 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1152 i--) 1153 ; /* Wait for receiver to stop */ 1154 1155 if (!i) { 1156 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1157 sc->vr_flags |= VR_F_RESTART; 1158 return; 1159 } 1160 1161 vr_rxeof(sc); 1162 1163 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1164 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1165 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1166 1167 return; 1168} 1169 1170/* 1171 * A frame was downloaded to the chip. It's safe for us to clean up 1172 * the list buffers. 1173 */ 1174 1175static void 1176vr_txeof(sc) 1177 struct vr_softc *sc; 1178{ 1179 struct vr_chain *cur_tx; 1180 struct ifnet *ifp; 1181 1182 ifp = &sc->arpcom.ac_if; 1183 1184 /* 1185 * Go through our tx list and free mbufs for those 1186 * frames that have been transmitted. 1187 */ 1188 cur_tx = sc->vr_cdata.vr_tx_cons; 1189 while (cur_tx->vr_mbuf != NULL) { 1190 u_int32_t txstat; 1191 int i; 1192 1193 txstat = cur_tx->vr_ptr->vr_status; 1194 1195 if ((txstat & VR_TXSTAT_ABRT) || 1196 (txstat & VR_TXSTAT_UDF)) { 1197 for (i = 0x400; 1198 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1199 i--) 1200 ; /* Wait for chip to shutdown */ 1201 if (!i) { 1202 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1203 sc->vr_flags |= VR_F_RESTART; 1204 break; 1205 } 1206 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1207 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1208 break; 1209 } 1210 1211 if (txstat & VR_TXSTAT_OWN) 1212 break; 1213 1214 if (txstat & VR_TXSTAT_ERRSUM) { 1215 ifp->if_oerrors++; 1216 if (txstat & VR_TXSTAT_DEFER) 1217 ifp->if_collisions++; 1218 if (txstat & VR_TXSTAT_LATECOLL) 1219 ifp->if_collisions++; 1220 } 1221 1222 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1223 1224 ifp->if_opackets++; 1225 m_freem(cur_tx->vr_mbuf); 1226 cur_tx->vr_mbuf = NULL; 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 1229 cur_tx = cur_tx->vr_nextdesc; 1230 } 1231 sc->vr_cdata.vr_tx_cons = cur_tx; 1232 if (cur_tx->vr_mbuf == NULL) 1233 ifp->if_timer = 0; 1234} 1235 1236static void 1237vr_tick(xsc) 1238 void *xsc; 1239{ 1240 struct vr_softc *sc; 1241 struct mii_data *mii; 1242 1243 sc = xsc; 1244 VR_LOCK(sc); 1245 if (sc->vr_flags & VR_F_RESTART) { 1246 printf("vr%d: restarting\n", sc->vr_unit); 1247 vr_stop(sc); 1248 vr_reset(sc); 1249 vr_init(sc); 1250 sc->vr_flags &= ~VR_F_RESTART; 1251 } 1252 1253 mii = device_get_softc(sc->vr_miibus); 1254 mii_tick(mii); 1255 1256 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1257 1258 VR_UNLOCK(sc); 1259 1260 return; 1261} 1262 1263#ifdef DEVICE_POLLING 1264static poll_handler_t vr_poll; 1265 1266static void 1267vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1268{ 1269 struct vr_softc *sc = ifp->if_softc; 1270 1271 VR_LOCK(sc); 1272 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1273 ether_poll_deregister(ifp); 1274 cmd = POLL_DEREGISTER; 1275 } 1276 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1277 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1278 goto done; 1279 } 1280 1281 sc->rxcycles = count; 1282 vr_rxeof(sc); 1283 vr_txeof(sc); 1284 if (ifp->if_snd.ifq_head != NULL) 1285 vr_start(ifp); 1286 1287 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1288 u_int16_t status; 1289 1290 status = CSR_READ_2(sc, VR_ISR); 1291 if (status) 1292 CSR_WRITE_2(sc, VR_ISR, status); 1293 1294 if ((status & VR_INTRS) == 0) 1295 goto done; 1296 1297 if (status & VR_ISR_RX_DROPPED) { 1298 printf("vr%d: rx packet lost\n", sc->vr_unit); 1299 ifp->if_ierrors++; 1300 } 1301 1302 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1303 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1304 printf("vr%d: receive error (%04x)", 1305 sc->vr_unit, status); 1306 if (status & VR_ISR_RX_NOBUF) 1307 printf(" no buffers"); 1308 if (status & VR_ISR_RX_OFLOW) 1309 printf(" overflow"); 1310 if (status & VR_ISR_RX_DROPPED) 1311 printf(" packet lost"); 1312 printf("\n"); 1313 vr_rxeoc(sc); 1314 } 1315 1316 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1317 vr_reset(sc); 1318 vr_init(sc); 1319 goto done; 1320 } 1321 1322 if ((status & VR_ISR_UDFI) || 1323 (status & VR_ISR_TX_ABRT2) || 1324 (status & VR_ISR_TX_ABRT)) { 1325 ifp->if_oerrors++; 1326 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1327 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1328 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1329 } 1330 } 1331 } 1332 1333done: 1334 VR_UNLOCK(sc); 1335 1336} 1337#endif /* DEVICE_POLLING */ 1338 1339static void 1340vr_intr(arg) 1341 void *arg; 1342{ 1343 struct vr_softc *sc; 1344 struct ifnet *ifp; 1345 u_int16_t status; 1346 1347 sc = arg; 1348 VR_LOCK(sc); 1349 ifp = &sc->arpcom.ac_if; 1350 1351#ifdef DEVICE_POLLING 1352 if (ifp->if_flags & IFF_POLLING) 1353 goto done; 1354 if ((ifp->if_capenable & IFCAP_POLLING) && 1355 ether_poll_register(vr_poll, ifp)) { /* ok, disable interrupts */ 1356 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1357 vr_poll(ifp, 0, 1); 1358 goto done; 1359 } 1360#endif /* DEVICE_POLLING */ 1361 1362 /* Supress unwanted interrupts. */ 1363 if (!(ifp->if_flags & IFF_UP)) { 1364 vr_stop(sc); 1365 VR_UNLOCK(sc); 1366 return; 1367 } 1368 1369 /* Disable interrupts. */ 1370 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1371 1372 for (;;) { 1373 1374 status = CSR_READ_2(sc, VR_ISR); 1375 if (status) 1376 CSR_WRITE_2(sc, VR_ISR, status); 1377 1378 if ((status & VR_INTRS) == 0) 1379 break; 1380 1381 if (status & VR_ISR_RX_OK) 1382 vr_rxeof(sc); 1383 1384 if (status & VR_ISR_RX_DROPPED) { 1385 printf("vr%d: rx packet lost\n", sc->vr_unit); 1386 ifp->if_ierrors++; 1387 } 1388 1389 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1390 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1391 printf("vr%d: receive error (%04x)", 1392 sc->vr_unit, status); 1393 if (status & VR_ISR_RX_NOBUF) 1394 printf(" no buffers"); 1395 if (status & VR_ISR_RX_OFLOW) 1396 printf(" overflow"); 1397 if (status & VR_ISR_RX_DROPPED) 1398 printf(" packet lost"); 1399 printf("\n"); 1400 vr_rxeoc(sc); 1401 } 1402 1403 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1404 vr_reset(sc); 1405 vr_init(sc); 1406 break; 1407 } 1408 1409 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1410 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1411 vr_txeof(sc); 1412 if ((status & VR_ISR_UDFI) || 1413 (status & VR_ISR_TX_ABRT2) || 1414 (status & VR_ISR_TX_ABRT)) { 1415 ifp->if_oerrors++; 1416 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1417 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1418 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1419 } 1420 } 1421 } 1422 1423 } 1424 1425 /* Re-enable interrupts. */ 1426 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1427 1428 if (ifp->if_snd.ifq_head != NULL) { 1429 vr_start(ifp); 1430 } 1431 1432#ifdef DEVICE_POLLING 1433done: 1434#endif /* DEVICE_POLLING */ 1435 VR_UNLOCK(sc); 1436 1437 return; 1438} 1439 1440/* 1441 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1442 * pointers to the fragment pointers. 1443 */ 1444static int 1445vr_encap(sc, c, m_head) 1446 struct vr_softc *sc; 1447 struct vr_chain *c; 1448 struct mbuf *m_head; 1449{ 1450 struct vr_desc *f = NULL; 1451 struct mbuf *m; 1452 1453 /* 1454 * The VIA Rhine wants packet buffers to be longword 1455 * aligned, but very often our mbufs aren't. Rather than 1456 * waste time trying to decide when to copy and when not 1457 * to copy, just do it all the time. 1458 */ 1459 m = m_defrag(m_head, M_DONTWAIT); 1460 if (m == NULL) { 1461 return(1); 1462 } 1463 1464 /* 1465 * The Rhine chip doesn't auto-pad, so we have to make 1466 * sure to pad short frames out to the minimum frame length 1467 * ourselves. 1468 */ 1469 if (m->m_len < VR_MIN_FRAMELEN) { 1470 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1471 m->m_len = m->m_pkthdr.len; 1472 } 1473 1474 c->vr_mbuf = m; 1475 f = c->vr_ptr; 1476 f->vr_data = vtophys(mtod(m, caddr_t)); 1477 f->vr_ctl = m->m_len; 1478 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1479 f->vr_status = 0; 1480 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1481 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1482 1483 return(0); 1484} 1485 1486/* 1487 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1488 * to the mbuf data regions directly in the transmit lists. We also save a 1489 * copy of the pointers since the transmit list fragment pointers are 1490 * physical addresses. 1491 */ 1492 1493static void 1494vr_start(ifp) 1495 struct ifnet *ifp; 1496{ 1497 struct vr_softc *sc; 1498 struct mbuf *m_head; 1499 struct vr_chain *cur_tx; 1500 1501 if (ifp->if_flags & IFF_OACTIVE) 1502 return; 1503 1504 sc = ifp->if_softc; 1505 1506 VR_LOCK(sc); 1507 1508 cur_tx = sc->vr_cdata.vr_tx_prod; 1509 while (cur_tx->vr_mbuf == NULL) { 1510 IF_DEQUEUE(&ifp->if_snd, m_head); 1511 if (m_head == NULL) 1512 break; 1513 1514 /* Pack the data into the descriptor. */ 1515 if (vr_encap(sc, cur_tx, m_head)) { 1516 /* Rollback, send what we were able to encap. */ 1517 IF_PREPEND(&ifp->if_snd, m_head); 1518 break; 1519 } 1520 1521 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1522 1523 /* 1524 * If there's a BPF listener, bounce a copy of this frame 1525 * to him. 1526 */ 1527 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1528 1529 cur_tx = cur_tx->vr_nextdesc; 1530 } 1531 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1532 sc->vr_cdata.vr_tx_prod = cur_tx; 1533 1534 /* Tell the chip to start transmitting. */ 1535 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1536 1537 /* Set a timeout in case the chip goes out to lunch. */ 1538 ifp->if_timer = 5; 1539 1540 if (cur_tx->vr_mbuf != NULL) 1541 ifp->if_flags |= IFF_OACTIVE; 1542 } 1543 1544 VR_UNLOCK(sc); 1545 1546 return; 1547} 1548 1549static void 1550vr_init(xsc) 1551 void *xsc; 1552{ 1553 struct vr_softc *sc = xsc; 1554 struct ifnet *ifp = &sc->arpcom.ac_if; 1555 struct mii_data *mii; 1556 int i; 1557 1558 VR_LOCK(sc); 1559 1560 mii = device_get_softc(sc->vr_miibus); 1561 1562 /* 1563 * Cancel pending I/O and free all RX/TX buffers. 1564 */ 1565 vr_stop(sc); 1566 vr_reset(sc); 1567 1568 /* 1569 * Set our station address. 1570 */ 1571 for (i = 0; i < ETHER_ADDR_LEN; i++) 1572 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1573 1574 /* Set DMA size */ 1575 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1576 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1577 1578 /* 1579 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1580 * so we must set both. 1581 */ 1582 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1583 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1584 1585 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1586 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1587 1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1589 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1590 1591 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1592 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1593 1594 /* Init circular RX list. */ 1595 if (vr_list_rx_init(sc) == ENOBUFS) { 1596 printf("vr%d: initialization failed: no " 1597 "memory for rx buffers\n", sc->vr_unit); 1598 vr_stop(sc); 1599 VR_UNLOCK(sc); 1600 return; 1601 } 1602 1603 /* 1604 * Init tx descriptors. 1605 */ 1606 vr_list_tx_init(sc); 1607 1608 /* If we want promiscuous mode, set the allframes bit. */ 1609 if (ifp->if_flags & IFF_PROMISC) 1610 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1611 else 1612 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1613 1614 /* Set capture broadcast bit to capture broadcast frames. */ 1615 if (ifp->if_flags & IFF_BROADCAST) 1616 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1617 else 1618 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1619 1620 /* 1621 * Program the multicast filter, if necessary. 1622 */ 1623 vr_setmulti(sc); 1624 1625 /* 1626 * Load the address of the RX list. 1627 */ 1628 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1629 1630 /* Enable receiver and transmitter. */ 1631 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1632 VR_CMD_TX_ON|VR_CMD_RX_ON| 1633 VR_CMD_RX_GO); 1634 1635 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1636 1637 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1638#ifdef DEVICE_POLLING 1639 /* 1640 * Disable interrupts if we are polling. 1641 */ 1642 if (ifp->if_flags & IFF_POLLING) 1643 CSR_WRITE_2(sc, VR_IMR, 0); 1644 else 1645#endif /* DEVICE_POLLING */ 1646 /* 1647 * Enable interrupts. 1648 */ 1649 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1650 1651 mii_mediachg(mii); 1652 1653 ifp->if_flags |= IFF_RUNNING; 1654 ifp->if_flags &= ~IFF_OACTIVE; 1655 1656 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1657 1658 VR_UNLOCK(sc); 1659 1660 return; 1661} 1662 1663/* 1664 * Set media options. 1665 */ 1666static int 1667vr_ifmedia_upd(ifp) 1668 struct ifnet *ifp; 1669{ 1670 struct vr_softc *sc; 1671 1672 sc = ifp->if_softc; 1673 1674 if (ifp->if_flags & IFF_UP) 1675 vr_init(sc); 1676 1677 return(0); 1678} 1679 1680/* 1681 * Report current media status. 1682 */ 1683static void 1684vr_ifmedia_sts(ifp, ifmr) 1685 struct ifnet *ifp; 1686 struct ifmediareq *ifmr; 1687{ 1688 struct vr_softc *sc; 1689 struct mii_data *mii; 1690 1691 sc = ifp->if_softc; 1692 mii = device_get_softc(sc->vr_miibus); 1693 mii_pollstat(mii); 1694 ifmr->ifm_active = mii->mii_media_active; 1695 ifmr->ifm_status = mii->mii_media_status; 1696 1697 return; 1698} 1699 1700static int 1701vr_ioctl(ifp, command, data) 1702 struct ifnet *ifp; 1703 u_long command; 1704 caddr_t data; 1705{ 1706 struct vr_softc *sc = ifp->if_softc; 1707 struct ifreq *ifr = (struct ifreq *) data; 1708 struct mii_data *mii; 1709 int error = 0; 1710 1711 VR_LOCK(sc); 1712 1713 switch(command) { 1714 case SIOCSIFFLAGS: 1715 if (ifp->if_flags & IFF_UP) { 1716 vr_init(sc); 1717 } else { 1718 if (ifp->if_flags & IFF_RUNNING) 1719 vr_stop(sc); 1720 } 1721 error = 0; 1722 break; 1723 case SIOCADDMULTI: 1724 case SIOCDELMULTI: 1725 vr_setmulti(sc); 1726 error = 0; 1727 break; 1728 case SIOCGIFMEDIA: 1729 case SIOCSIFMEDIA: 1730 mii = device_get_softc(sc->vr_miibus); 1731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1732 break; 1733 case SIOCSIFCAP: 1734 ifp->if_capenable = ifr->ifr_reqcap; 1735 break; 1736 default: 1737 error = ether_ioctl(ifp, command, data); 1738 break; 1739 } 1740 1741 VR_UNLOCK(sc); 1742 1743 return(error); 1744} 1745 1746static void 1747vr_watchdog(ifp) 1748 struct ifnet *ifp; 1749{ 1750 struct vr_softc *sc; 1751 1752 sc = ifp->if_softc; 1753 1754 VR_LOCK(sc); 1755 ifp->if_oerrors++; 1756 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1757 1758 vr_stop(sc); 1759 vr_reset(sc); 1760 vr_init(sc); 1761 1762 if (ifp->if_snd.ifq_head != NULL) 1763 vr_start(ifp); 1764 1765 VR_UNLOCK(sc); 1766 1767 return; 1768} 1769 1770/* 1771 * Stop the adapter and free any mbufs allocated to the 1772 * RX and TX lists. 1773 */ 1774static void 1775vr_stop(sc) 1776 struct vr_softc *sc; 1777{ 1778 register int i; 1779 struct ifnet *ifp; 1780 1781 VR_LOCK(sc); 1782 1783 ifp = &sc->arpcom.ac_if; 1784 ifp->if_timer = 0; 1785 1786 untimeout(vr_tick, sc, sc->vr_stat_ch); 1787 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1788#ifdef DEVICE_POLLING 1789 ether_poll_deregister(ifp); 1790#endif /* DEVICE_POLLING */ 1791 1792 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1793 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1794 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1795 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1796 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1797 1798 /* 1799 * Free data in the RX lists. 1800 */ 1801 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1802 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1803 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1804 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1805 } 1806 } 1807 bzero((char *)&sc->vr_ldata->vr_rx_list, 1808 sizeof(sc->vr_ldata->vr_rx_list)); 1809 1810 /* 1811 * Free the TX list buffers. 1812 */ 1813 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1814 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1815 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1816 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1817 } 1818 } 1819 1820 bzero((char *)&sc->vr_ldata->vr_tx_list, 1821 sizeof(sc->vr_ldata->vr_tx_list)); 1822 1823 VR_UNLOCK(sc); 1824 1825 return; 1826} 1827 1828/* 1829 * Stop all chip I/O so that the kernel's probe routines don't 1830 * get confused by errant DMAs when rebooting. 1831 */ 1832static void 1833vr_shutdown(dev) 1834 device_t dev; 1835{ 1836 struct vr_softc *sc; 1837 1838 sc = device_get_softc(dev); 1839 1840 vr_stop(sc); 1841 1842 return; 1843} 1844