if_vr.c revision 126847
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 126847 2004-03-11 14:04:59Z mux $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include <sys/param.h> 63#include <sys/systm.h> 64#include <sys/sockio.h> 65#include <sys/mbuf.h> 66#include <sys/malloc.h> 67#include <sys/kernel.h> 68#include <sys/socket.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75 76#include <net/bpf.h> 77 78#include <vm/vm.h> /* for vtophys */ 79#include <vm/pmap.h> /* for vtophys */ 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#define VR_USEIOSPACE 94 95#include <pci/if_vrreg.h> 96 97MODULE_DEPEND(vr, pci, 1, 1, 1); 98MODULE_DEPEND(vr, ether, 1, 1, 1); 99MODULE_DEPEND(vr, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104#undef VR_USESWSHIFT 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125}; 126 127static int vr_probe (device_t); 128static int vr_attach (device_t); 129static int vr_detach (device_t); 130 131static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137static void vr_rxeof (struct vr_softc *); 138static void vr_rxeoc (struct vr_softc *); 139static void vr_txeof (struct vr_softc *); 140static void vr_txeoc (struct vr_softc *); 141static void vr_tick (void *); 142static void vr_intr (void *); 143static void vr_start (struct ifnet *); 144static int vr_ioctl (struct ifnet *, u_long, caddr_t); 145static void vr_init (void *); 146static void vr_stop (struct vr_softc *); 147static void vr_watchdog (struct ifnet *); 148static void vr_shutdown (device_t); 149static int vr_ifmedia_upd (struct ifnet *); 150static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152#ifdef VR_USESWSHIFT 153static void vr_mii_sync (struct vr_softc *); 154static void vr_mii_send (struct vr_softc *, u_int32_t, int); 155#endif 156static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 157static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 158static int vr_miibus_readreg (device_t, int, int); 159static int vr_miibus_writereg (device_t, int, int, int); 160static void vr_miibus_statchg (device_t); 161 162static void vr_setcfg (struct vr_softc *, int); 163static uint32_t vr_mchash (const uint8_t *); 164static void vr_setmulti (struct vr_softc *); 165static void vr_reset (struct vr_softc *); 166static int vr_list_rx_init (struct vr_softc *); 167static int vr_list_tx_init (struct vr_softc *); 168 169#ifdef VR_USEIOSPACE 170#define VR_RES SYS_RES_IOPORT 171#define VR_RID VR_PCI_LOIO 172#else 173#define VR_RES SYS_RES_MEMORY 174#define VR_RID VR_PCI_LOMEM 175#endif 176 177static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200}; 201 202static devclass_t vr_devclass; 203 204DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 205DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207#define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | (x)) 210 211#define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~(x)) 214 215#define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | (x)) 218 219#define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~(x)) 222 223#define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227#define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231#define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | (x)) 234 235#define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 238 239#ifdef VR_USESWSHIFT 240/* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243static void 244vr_mii_sync(sc) 245 struct vr_softc *sc; 246{ 247 register int i; 248 249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 250 251 for (i = 0; i < 32; i++) { 252 SIO_SET(VR_MIICMD_CLK); 253 DELAY(1); 254 SIO_CLR(VR_MIICMD_CLK); 255 DELAY(1); 256 } 257 258 return; 259} 260 261/* 262 * Clock a series of bits through the MII. 263 */ 264static void 265vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269{ 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285} 286#endif 287 288/* 289 * Read an PHY register through the MII. 290 */ 291static int 292vr_mii_readreg(sc, frame) 293 struct vr_softc *sc; 294 struct vr_mii_frame *frame; 295 296#ifdef VR_USESWSHIFT 297{ 298 int i, ack; 299 300 VR_LOCK(sc); 301 302 /* 303 * Set up frame for RX. 304 */ 305 frame->mii_stdelim = VR_MII_STARTDELIM; 306 frame->mii_opcode = VR_MII_READOP; 307 frame->mii_turnaround = 0; 308 frame->mii_data = 0; 309 310 CSR_WRITE_1(sc, VR_MIICMD, 0); 311 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 312 313 /* 314 * Turn on data xmit. 315 */ 316 SIO_SET(VR_MIICMD_DIR); 317 318 vr_mii_sync(sc); 319 320 /* 321 * Send command/address info. 322 */ 323 vr_mii_send(sc, frame->mii_stdelim, 2); 324 vr_mii_send(sc, frame->mii_opcode, 2); 325 vr_mii_send(sc, frame->mii_phyaddr, 5); 326 vr_mii_send(sc, frame->mii_regaddr, 5); 327 328 /* Idle bit */ 329 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 330 DELAY(1); 331 SIO_SET(VR_MIICMD_CLK); 332 DELAY(1); 333 334 /* Turn off xmit. */ 335 SIO_CLR(VR_MIICMD_DIR); 336 337 /* Check for ack */ 338 SIO_CLR(VR_MIICMD_CLK); 339 DELAY(1); 340 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 344 /* 345 * Now try reading data bits. If the ack failed, we still 346 * need to clock through 16 cycles to keep the PHY(s) in sync. 347 */ 348 if (ack) { 349 for(i = 0; i < 16; i++) { 350 SIO_CLR(VR_MIICMD_CLK); 351 DELAY(1); 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 goto fail; 356 } 357 358 for (i = 0x8000; i; i >>= 1) { 359 SIO_CLR(VR_MIICMD_CLK); 360 DELAY(1); 361 if (!ack) { 362 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 363 frame->mii_data |= i; 364 DELAY(1); 365 } 366 SIO_SET(VR_MIICMD_CLK); 367 DELAY(1); 368 } 369 370fail: 371 372 SIO_CLR(VR_MIICMD_CLK); 373 DELAY(1); 374 SIO_SET(VR_MIICMD_CLK); 375 DELAY(1); 376 377 VR_UNLOCK(sc); 378 379 if (ack) 380 return(1); 381 return(0); 382} 383#else 384{ 385 int s, i; 386 387 s = splimp(); 388 389 /* Set the PHY-adress */ 390 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 391 frame->mii_phyaddr); 392 393 /* Set the register-adress */ 394 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 395 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 396 397 for (i = 0; i < 10000; i++) { 398 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 399 break; 400 DELAY(1); 401 } 402 403 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 404 405 (void)splx(s); 406 407 return(0); 408} 409#endif 410 411 412/* 413 * Write to a PHY register through the MII. 414 */ 415static int 416vr_mii_writereg(sc, frame) 417 struct vr_softc *sc; 418 struct vr_mii_frame *frame; 419 420#ifdef VR_USESWSHIFT 421{ 422 VR_LOCK(sc); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 VR_UNLOCK(sc); 461 462 return(0); 463} 464#else 465{ 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489} 490#endif 491 492static int 493vr_miibus_readreg(dev, phy, reg) 494 device_t dev; 495 int phy, reg; 496{ 497 struct vr_softc *sc; 498 struct vr_mii_frame frame; 499 500 sc = device_get_softc(dev); 501 502 switch (sc->vr_revid) { 503 case REV_ID_VT6102_APOLLO: 504 if (phy != 1) 505 return 0; 506 default: 507 break; 508 } 509 510 bzero((char *)&frame, sizeof(frame)); 511 512 frame.mii_phyaddr = phy; 513 frame.mii_regaddr = reg; 514 vr_mii_readreg(sc, &frame); 515 516 return(frame.mii_data); 517} 518 519static int 520vr_miibus_writereg(dev, phy, reg, data) 521 device_t dev; 522 u_int16_t phy, reg, data; 523{ 524 struct vr_softc *sc; 525 struct vr_mii_frame frame; 526 527 sc = device_get_softc(dev); 528 529 switch (sc->vr_revid) { 530 case REV_ID_VT6102_APOLLO: 531 if (phy != 1) 532 return 0; 533 default: 534 break; 535 } 536 537 bzero((char *)&frame, sizeof(frame)); 538 539 frame.mii_phyaddr = phy; 540 frame.mii_regaddr = reg; 541 frame.mii_data = data; 542 543 vr_mii_writereg(sc, &frame); 544 545 return(0); 546} 547 548static void 549vr_miibus_statchg(dev) 550 device_t dev; 551{ 552 struct vr_softc *sc; 553 struct mii_data *mii; 554 555 sc = device_get_softc(dev); 556 VR_LOCK(sc); 557 mii = device_get_softc(sc->vr_miibus); 558 vr_setcfg(sc, mii->mii_media_active); 559 VR_UNLOCK(sc); 560 561 return; 562} 563 564/* 565 * Calculate CRC of a multicast group address, return the lower 6 bits. 566 */ 567static u_int32_t 568vr_mchash(addr) 569 const uint8_t *addr; 570{ 571 uint32_t crc, carry; 572 int idx, bit; 573 uint8_t data; 574 575 /* Compute CRC for the address value. */ 576 crc = 0xFFFFFFFF; /* initial value */ 577 578 for (idx = 0; idx < 6; idx++) { 579 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 580 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 581 crc <<= 1; 582 if (carry) 583 crc = (crc ^ 0x04c11db6) | carry; 584 } 585 } 586 587 /* return the filter bit position */ 588 return((crc >> 26) & 0x0000003F); 589} 590 591/* 592 * Program the 64-bit multicast hash filter. 593 */ 594static void 595vr_setmulti(sc) 596 struct vr_softc *sc; 597{ 598 struct ifnet *ifp; 599 int h = 0; 600 u_int32_t hashes[2] = { 0, 0 }; 601 struct ifmultiaddr *ifma; 602 u_int8_t rxfilt; 603 int mcnt = 0; 604 605 ifp = &sc->arpcom.ac_if; 606 607 rxfilt = CSR_READ_1(sc, VR_RXCFG); 608 609 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 610 rxfilt |= VR_RXCFG_RX_MULTI; 611 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 612 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 613 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 614 return; 615 } 616 617 /* first, zot all the existing hash bits */ 618 CSR_WRITE_4(sc, VR_MAR0, 0); 619 CSR_WRITE_4(sc, VR_MAR1, 0); 620 621 /* now program new ones */ 622 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 623 if (ifma->ifma_addr->sa_family != AF_LINK) 624 continue; 625 h = vr_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 626 if (h < 32) 627 hashes[0] |= (1 << h); 628 else 629 hashes[1] |= (1 << (h - 32)); 630 mcnt++; 631 } 632 633 if (mcnt) 634 rxfilt |= VR_RXCFG_RX_MULTI; 635 else 636 rxfilt &= ~VR_RXCFG_RX_MULTI; 637 638 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 639 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 640 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 641 642 return; 643} 644 645/* 646 * In order to fiddle with the 647 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 648 * first have to put the transmit and/or receive logic in the idle state. 649 */ 650static void 651vr_setcfg(sc, media) 652 struct vr_softc *sc; 653 int media; 654{ 655 int restart = 0; 656 657 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 658 restart = 1; 659 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 660 } 661 662 if ((media & IFM_GMASK) == IFM_FDX) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 664 else 665 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 667 if (restart) 668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 669 670 return; 671} 672 673static void 674vr_reset(sc) 675 struct vr_softc *sc; 676{ 677 register int i; 678 679 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 680 681 for (i = 0; i < VR_TIMEOUT; i++) { 682 DELAY(10); 683 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 684 break; 685 } 686 if (i == VR_TIMEOUT) { 687 if (sc->vr_revid < REV_ID_VT3065_A) 688 printf("vr%d: reset never completed!\n", sc->vr_unit); 689 else { 690 /* Use newer force reset command */ 691 printf("vr%d: Using force reset command.\n", sc->vr_unit); 692 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 693 } 694 } 695 696 /* Wait a little while for the chip to get its brains in order. */ 697 DELAY(1000); 698 699 return; 700} 701 702/* 703 * Probe for a VIA Rhine chip. Check the PCI vendor and device 704 * IDs against our list and return a device name if we find a match. 705 */ 706static int 707vr_probe(dev) 708 device_t dev; 709{ 710 struct vr_type *t; 711 712 t = vr_devs; 713 714 while(t->vr_name != NULL) { 715 if ((pci_get_vendor(dev) == t->vr_vid) && 716 (pci_get_device(dev) == t->vr_did)) { 717 device_set_desc(dev, t->vr_name); 718 return(0); 719 } 720 t++; 721 } 722 723 return(ENXIO); 724} 725 726/* 727 * Attach the interface. Allocate softc structures, do ifmedia 728 * setup and ethernet/BPF attach. 729 */ 730static int 731vr_attach(dev) 732 device_t dev; 733{ 734 int i; 735 u_char eaddr[ETHER_ADDR_LEN]; 736 struct vr_softc *sc; 737 struct ifnet *ifp; 738 int unit, error = 0, rid; 739 740 sc = device_get_softc(dev); 741 unit = device_get_unit(dev); 742 743 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 744 MTX_DEF | MTX_RECURSE); 745#ifndef BURN_BRIDGES 746 /* 747 * Handle power management nonsense. 748 */ 749 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 750 u_int32_t iobase, membase, irq; 751 752 /* Save important PCI config data. */ 753 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 754 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 755 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 756 757 /* Reset the power state. */ 758 printf("vr%d: chip is in D%d power mode " 759 "-- setting to D0\n", unit, 760 pci_get_powerstate(dev)); 761 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 762 763 /* Restore PCI config data. */ 764 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 765 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 766 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 767 } 768#endif 769 /* 770 * Map control/status registers. 771 */ 772 pci_enable_busmaster(dev); 773 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 774 775 rid = VR_RID; 776 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 777 0, ~0, 1, RF_ACTIVE); 778 779 if (sc->vr_res == NULL) { 780 printf("vr%d: couldn't map ports/memory\n", unit); 781 error = ENXIO; 782 goto fail; 783 } 784 785 sc->vr_btag = rman_get_bustag(sc->vr_res); 786 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 787 788 /* Allocate interrupt */ 789 rid = 0; 790 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 791 RF_SHAREABLE | RF_ACTIVE); 792 793 if (sc->vr_irq == NULL) { 794 printf("vr%d: couldn't map interrupt\n", unit); 795 error = ENXIO; 796 goto fail; 797 } 798 799 /* 800 * Windows may put the chip in suspend mode when it 801 * shuts down. Be sure to kick it in the head to wake it 802 * up again. 803 */ 804 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 805 806 /* Reset the adapter. */ 807 vr_reset(sc); 808 809 /* 810 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 811 * initialization and disable AUTOPOLL. 812 */ 813 pci_write_config(dev, VR_PCI_MODE, 814 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 815 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 816 817 /* 818 * Get station address. The way the Rhine chips work, 819 * you're not allowed to directly access the EEPROM once 820 * they've been programmed a special way. Consequently, 821 * we need to read the node address from the PAR0 and PAR1 822 * registers. 823 */ 824 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 825 DELAY(200); 826 for (i = 0; i < ETHER_ADDR_LEN; i++) 827 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 828 829 /* 830 * A Rhine chip was detected. Inform the world. 831 */ 832 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 833 834 sc->vr_unit = unit; 835 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 836 837 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 838 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 839 840 if (sc->vr_ldata == NULL) { 841 printf("vr%d: no memory for list buffers!\n", unit); 842 error = ENXIO; 843 goto fail; 844 } 845 846 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 847 848 ifp = &sc->arpcom.ac_if; 849 ifp->if_softc = sc; 850 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 851 ifp->if_mtu = ETHERMTU; 852 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 853 ifp->if_ioctl = vr_ioctl; 854 ifp->if_start = vr_start; 855 ifp->if_watchdog = vr_watchdog; 856 ifp->if_init = vr_init; 857 ifp->if_baudrate = 10000000; 858 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 859 860 /* 861 * Do MII setup. 862 */ 863 if (mii_phy_probe(dev, &sc->vr_miibus, 864 vr_ifmedia_upd, vr_ifmedia_sts)) { 865 printf("vr%d: MII without any phy!\n", sc->vr_unit); 866 error = ENXIO; 867 goto fail; 868 } 869 870 callout_handle_init(&sc->vr_stat_ch); 871 872 /* 873 * Call MI attach routine. 874 */ 875 ether_ifattach(ifp, eaddr); 876 877 /* Hook interrupt last to avoid having to lock softc */ 878 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 879 vr_intr, sc, &sc->vr_intrhand); 880 881 if (error) { 882 printf("vr%d: couldn't set up irq\n", unit); 883 ether_ifdetach(ifp); 884 goto fail; 885 } 886 887fail: 888 if (error) 889 vr_detach(dev); 890 891 return(error); 892} 893 894/* 895 * Shutdown hardware and free up resources. This can be called any 896 * time after the mutex has been initialized. It is called in both 897 * the error case in attach and the normal detach case so it needs 898 * to be careful about only freeing resources that have actually been 899 * allocated. 900 */ 901static int 902vr_detach(dev) 903 device_t dev; 904{ 905 struct vr_softc *sc; 906 struct ifnet *ifp; 907 908 sc = device_get_softc(dev); 909 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 910 VR_LOCK(sc); 911 ifp = &sc->arpcom.ac_if; 912 913 /* These should only be active if attach succeeded */ 914 if (device_is_attached(dev)) { 915 vr_stop(sc); 916 ether_ifdetach(ifp); 917 } 918 if (sc->vr_miibus) 919 device_delete_child(dev, sc->vr_miibus); 920 bus_generic_detach(dev); 921 922 if (sc->vr_intrhand) 923 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 924 if (sc->vr_irq) 925 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 926 if (sc->vr_res) 927 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 928 929 if (sc->vr_ldata) 930 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 931 932 VR_UNLOCK(sc); 933 mtx_destroy(&sc->vr_mtx); 934 935 return(0); 936} 937 938/* 939 * Initialize the transmit descriptors. 940 */ 941static int 942vr_list_tx_init(sc) 943 struct vr_softc *sc; 944{ 945 struct vr_chain_data *cd; 946 struct vr_list_data *ld; 947 int i; 948 949 cd = &sc->vr_cdata; 950 ld = sc->vr_ldata; 951 for (i = 0; i < VR_TX_LIST_CNT; i++) { 952 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 953 if (i == (VR_TX_LIST_CNT - 1)) 954 cd->vr_tx_chain[i].vr_nextdesc = 955 &cd->vr_tx_chain[0]; 956 else 957 cd->vr_tx_chain[i].vr_nextdesc = 958 &cd->vr_tx_chain[i + 1]; 959 } 960 961 cd->vr_tx_free = &cd->vr_tx_chain[0]; 962 cd->vr_tx_tail = cd->vr_tx_head = NULL; 963 964 return(0); 965} 966 967 968/* 969 * Initialize the RX descriptors and allocate mbufs for them. Note that 970 * we arrange the descriptors in a closed ring, so that the last descriptor 971 * points back to the first. 972 */ 973static int 974vr_list_rx_init(sc) 975 struct vr_softc *sc; 976{ 977 struct vr_chain_data *cd; 978 struct vr_list_data *ld; 979 int i; 980 981 cd = &sc->vr_cdata; 982 ld = sc->vr_ldata; 983 984 for (i = 0; i < VR_RX_LIST_CNT; i++) { 985 cd->vr_rx_chain[i].vr_ptr = 986 (struct vr_desc *)&ld->vr_rx_list[i]; 987 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 988 return(ENOBUFS); 989 if (i == (VR_RX_LIST_CNT - 1)) { 990 cd->vr_rx_chain[i].vr_nextdesc = 991 &cd->vr_rx_chain[0]; 992 ld->vr_rx_list[i].vr_next = 993 vtophys(&ld->vr_rx_list[0]); 994 } else { 995 cd->vr_rx_chain[i].vr_nextdesc = 996 &cd->vr_rx_chain[i + 1]; 997 ld->vr_rx_list[i].vr_next = 998 vtophys(&ld->vr_rx_list[i + 1]); 999 } 1000 } 1001 1002 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1003 1004 return(0); 1005} 1006 1007/* 1008 * Initialize an RX descriptor and attach an MBUF cluster. 1009 * Note: the length fields are only 11 bits wide, which means the 1010 * largest size we can specify is 2047. This is important because 1011 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1012 * overflow the field and make a mess. 1013 */ 1014static int 1015vr_newbuf(sc, c, m) 1016 struct vr_softc *sc; 1017 struct vr_chain_onefrag *c; 1018 struct mbuf *m; 1019{ 1020 struct mbuf *m_new = NULL; 1021 1022 if (m == NULL) { 1023 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1024 if (m_new == NULL) 1025 return(ENOBUFS); 1026 1027 MCLGET(m_new, M_DONTWAIT); 1028 if (!(m_new->m_flags & M_EXT)) { 1029 m_freem(m_new); 1030 return(ENOBUFS); 1031 } 1032 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1033 } else { 1034 m_new = m; 1035 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1036 m_new->m_data = m_new->m_ext.ext_buf; 1037 } 1038 1039 m_adj(m_new, sizeof(u_int64_t)); 1040 1041 c->vr_mbuf = m_new; 1042 c->vr_ptr->vr_status = VR_RXSTAT; 1043 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1044 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1045 1046 return(0); 1047} 1048 1049/* 1050 * A frame has been uploaded: pass the resulting mbuf chain up to 1051 * the higher level protocols. 1052 */ 1053static void 1054vr_rxeof(sc) 1055 struct vr_softc *sc; 1056{ 1057 struct mbuf *m; 1058 struct ifnet *ifp; 1059 struct vr_chain_onefrag *cur_rx; 1060 int total_len = 0; 1061 u_int32_t rxstat; 1062 1063 VR_LOCK_ASSERT(sc); 1064 1065 ifp = &sc->arpcom.ac_if; 1066 1067 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1068 VR_RXSTAT_OWN)) { 1069 struct mbuf *m0 = NULL; 1070 1071 cur_rx = sc->vr_cdata.vr_rx_head; 1072 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1073 m = cur_rx->vr_mbuf; 1074 1075 /* 1076 * If an error occurs, update stats, clear the 1077 * status word and leave the mbuf cluster in place: 1078 * it should simply get re-used next time this descriptor 1079 * comes up in the ring. 1080 */ 1081 if (rxstat & VR_RXSTAT_RXERR) { 1082 ifp->if_ierrors++; 1083 printf("vr%d: rx error (%02x):", 1084 sc->vr_unit, rxstat & 0x000000ff); 1085 if (rxstat & VR_RXSTAT_CRCERR) 1086 printf(" crc error"); 1087 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1088 printf(" frame alignment error\n"); 1089 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1090 printf(" FIFO overflow"); 1091 if (rxstat & VR_RXSTAT_GIANT) 1092 printf(" received giant packet"); 1093 if (rxstat & VR_RXSTAT_RUNT) 1094 printf(" received runt packet"); 1095 if (rxstat & VR_RXSTAT_BUSERR) 1096 printf(" system bus error"); 1097 if (rxstat & VR_RXSTAT_BUFFERR) 1098 printf("rx buffer error"); 1099 printf("\n"); 1100 vr_newbuf(sc, cur_rx, m); 1101 continue; 1102 } 1103 1104 /* No errors; receive the packet. */ 1105 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1106 1107 /* 1108 * XXX The VIA Rhine chip includes the CRC with every 1109 * received frame, and there's no way to turn this 1110 * behavior off (at least, I can't find anything in 1111 * the manual that explains how to do it) so we have 1112 * to trim off the CRC manually. 1113 */ 1114 total_len -= ETHER_CRC_LEN; 1115 1116 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1117 NULL); 1118 vr_newbuf(sc, cur_rx, m); 1119 if (m0 == NULL) { 1120 ifp->if_ierrors++; 1121 continue; 1122 } 1123 m = m0; 1124 1125 ifp->if_ipackets++; 1126 VR_UNLOCK(sc); 1127 (*ifp->if_input)(ifp, m); 1128 VR_LOCK(sc); 1129 } 1130 1131 return; 1132} 1133 1134static void 1135vr_rxeoc(sc) 1136 struct vr_softc *sc; 1137{ 1138 struct ifnet *ifp; 1139 int i; 1140 1141 ifp = &sc->arpcom.ac_if; 1142 1143 ifp->if_ierrors++; 1144 1145 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1146 DELAY(10000); 1147 1148 for (i = 0x400; 1149 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1150 i--) 1151 ; /* Wait for receiver to stop */ 1152 1153 if (!i) { 1154 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1155 sc->vr_flags |= VR_F_RESTART; 1156 return; 1157 } 1158 1159 vr_rxeof(sc); 1160 1161 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1162 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1163 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1164 1165 return; 1166} 1167 1168/* 1169 * A frame was downloaded to the chip. It's safe for us to clean up 1170 * the list buffers. 1171 */ 1172 1173static void 1174vr_txeof(sc) 1175 struct vr_softc *sc; 1176{ 1177 struct vr_chain *cur_tx; 1178 struct ifnet *ifp; 1179 1180 ifp = &sc->arpcom.ac_if; 1181 1182 /* Reset the timeout timer; if_txeoc will clear it. */ 1183 ifp->if_timer = 5; 1184 1185 /* Sanity check. */ 1186 if (sc->vr_cdata.vr_tx_head == NULL) 1187 return; 1188 1189 /* 1190 * Go through our tx list and free mbufs for those 1191 * frames that have been transmitted. 1192 */ 1193 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1194 u_int32_t txstat; 1195 int i; 1196 1197 cur_tx = sc->vr_cdata.vr_tx_head; 1198 txstat = cur_tx->vr_ptr->vr_status; 1199 1200 if ((txstat & VR_TXSTAT_ABRT) || 1201 (txstat & VR_TXSTAT_UDF)) { 1202 for (i = 0x400; 1203 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1204 i--) 1205 ; /* Wait for chip to shutdown */ 1206 if (!i) { 1207 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1208 sc->vr_flags |= VR_F_RESTART; 1209 break; 1210 } 1211 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1212 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1213 break; 1214 } 1215 1216 if (txstat & VR_TXSTAT_OWN) 1217 break; 1218 1219 if (txstat & VR_TXSTAT_ERRSUM) { 1220 ifp->if_oerrors++; 1221 if (txstat & VR_TXSTAT_DEFER) 1222 ifp->if_collisions++; 1223 if (txstat & VR_TXSTAT_LATECOLL) 1224 ifp->if_collisions++; 1225 } 1226 1227 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1228 1229 ifp->if_opackets++; 1230 if (cur_tx->vr_mbuf != NULL) { 1231 m_freem(cur_tx->vr_mbuf); 1232 cur_tx->vr_mbuf = NULL; 1233 } 1234 1235 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1236 sc->vr_cdata.vr_tx_head = NULL; 1237 sc->vr_cdata.vr_tx_tail = NULL; 1238 break; 1239 } 1240 1241 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1242 } 1243 1244 return; 1245} 1246 1247/* 1248 * TX 'end of channel' interrupt handler. 1249 */ 1250static void 1251vr_txeoc(sc) 1252 struct vr_softc *sc; 1253{ 1254 struct ifnet *ifp; 1255 1256 ifp = &sc->arpcom.ac_if; 1257 1258 if (sc->vr_cdata.vr_tx_head == NULL) { 1259 ifp->if_flags &= ~IFF_OACTIVE; 1260 sc->vr_cdata.vr_tx_tail = NULL; 1261 ifp->if_timer = 0; 1262 } 1263 1264 return; 1265} 1266 1267static void 1268vr_tick(xsc) 1269 void *xsc; 1270{ 1271 struct vr_softc *sc; 1272 struct mii_data *mii; 1273 1274 sc = xsc; 1275 VR_LOCK(sc); 1276 if (sc->vr_flags & VR_F_RESTART) { 1277 printf("vr%d: restarting\n", sc->vr_unit); 1278 vr_stop(sc); 1279 vr_reset(sc); 1280 vr_init(sc); 1281 sc->vr_flags &= ~VR_F_RESTART; 1282 } 1283 1284 mii = device_get_softc(sc->vr_miibus); 1285 mii_tick(mii); 1286 1287 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1288 1289 VR_UNLOCK(sc); 1290 1291 return; 1292} 1293 1294static void 1295vr_intr(arg) 1296 void *arg; 1297{ 1298 struct vr_softc *sc; 1299 struct ifnet *ifp; 1300 u_int16_t status; 1301 1302 sc = arg; 1303 VR_LOCK(sc); 1304 ifp = &sc->arpcom.ac_if; 1305 1306 /* Supress unwanted interrupts. */ 1307 if (!(ifp->if_flags & IFF_UP)) { 1308 vr_stop(sc); 1309 VR_UNLOCK(sc); 1310 return; 1311 } 1312 1313 /* Disable interrupts. */ 1314 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1315 1316 for (;;) { 1317 1318 status = CSR_READ_2(sc, VR_ISR); 1319 if (status) 1320 CSR_WRITE_2(sc, VR_ISR, status); 1321 1322 if ((status & VR_INTRS) == 0) 1323 break; 1324 1325 if (status & VR_ISR_RX_OK) 1326 vr_rxeof(sc); 1327 1328 if (status & VR_ISR_RX_DROPPED) { 1329 printf("vr%d: rx packet lost\n", sc->vr_unit); 1330 ifp->if_ierrors++; 1331 } 1332 1333 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1334 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1335 printf("vr%d: receive error (%04x)", 1336 sc->vr_unit, status); 1337 if (status & VR_ISR_RX_NOBUF) 1338 printf(" no buffers"); 1339 if (status & VR_ISR_RX_OFLOW) 1340 printf(" overflow"); 1341 if (status & VR_ISR_RX_DROPPED) 1342 printf(" packet lost"); 1343 printf("\n"); 1344 vr_rxeoc(sc); 1345 } 1346 1347 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1348 vr_reset(sc); 1349 vr_init(sc); 1350 break; 1351 } 1352 1353 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1354 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1355 vr_txeof(sc); 1356 if ((status & VR_ISR_UDFI) || 1357 (status & VR_ISR_TX_ABRT2) || 1358 (status & VR_ISR_TX_ABRT)) { 1359 ifp->if_oerrors++; 1360 if (sc->vr_cdata.vr_tx_head != NULL) { 1361 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1362 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1363 } 1364 } else 1365 vr_txeoc(sc); 1366 } 1367 1368 } 1369 1370 /* Re-enable interrupts. */ 1371 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1372 1373 if (ifp->if_snd.ifq_head != NULL) { 1374 vr_start(ifp); 1375 } 1376 1377 VR_UNLOCK(sc); 1378 1379 return; 1380} 1381 1382/* 1383 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1384 * pointers to the fragment pointers. 1385 */ 1386static int 1387vr_encap(sc, c, m_head) 1388 struct vr_softc *sc; 1389 struct vr_chain *c; 1390 struct mbuf *m_head; 1391{ 1392 int frag = 0; 1393 struct vr_desc *f = NULL; 1394 int total_len; 1395 struct mbuf *m; 1396 1397 m = m_head; 1398 total_len = 0; 1399 1400 /* 1401 * The VIA Rhine wants packet buffers to be longword 1402 * aligned, but very often our mbufs aren't. Rather than 1403 * waste time trying to decide when to copy and when not 1404 * to copy, just do it all the time. 1405 */ 1406 if (m != NULL) { 1407 struct mbuf *m_new = NULL; 1408 1409 m_new = m_defrag(m_head, M_DONTWAIT); 1410 if (m_new == NULL) { 1411 return(1); 1412 } 1413 1414 m_head = m_new; 1415 /* 1416 * The Rhine chip doesn't auto-pad, so we have to make 1417 * sure to pad short frames out to the minimum frame length 1418 * ourselves. 1419 */ 1420 if (m_head->m_len < VR_MIN_FRAMELEN) { 1421 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1422 m_new->m_len = m_new->m_pkthdr.len; 1423 } 1424 f = c->vr_ptr; 1425 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1426 f->vr_ctl = total_len = m_new->m_len; 1427 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1428 f->vr_status = 0; 1429 frag = 1; 1430 } 1431 1432 c->vr_mbuf = m_head; 1433 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1434 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1435 1436 return(0); 1437} 1438 1439/* 1440 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1441 * to the mbuf data regions directly in the transmit lists. We also save a 1442 * copy of the pointers since the transmit list fragment pointers are 1443 * physical addresses. 1444 */ 1445 1446static void 1447vr_start(ifp) 1448 struct ifnet *ifp; 1449{ 1450 struct vr_softc *sc; 1451 struct mbuf *m_head = NULL; 1452 struct vr_chain *cur_tx = NULL, *start_tx, *prev_tx; 1453 1454 sc = ifp->if_softc; 1455 1456 VR_LOCK(sc); 1457 1458 /* 1459 * Check for an available queue slot. If there are none, 1460 * punt. 1461 */ 1462 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1463 VR_UNLOCK(sc); 1464 return; 1465 } 1466 1467 start_tx = sc->vr_cdata.vr_tx_free; 1468 1469 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1470 IF_DEQUEUE(&ifp->if_snd, m_head); 1471 if (m_head == NULL) 1472 break; 1473 1474 /* Pick a descriptor off the free list. */ 1475 prev_tx = cur_tx; 1476 cur_tx = sc->vr_cdata.vr_tx_free; 1477 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1478 1479 /* Pack the data into the descriptor. */ 1480 if (vr_encap(sc, cur_tx, m_head)) { 1481 /* Rollback, send what we were able to encap. */ 1482 IF_PREPEND(&ifp->if_snd, m_head); 1483 sc->vr_cdata.vr_tx_free = cur_tx; 1484 cur_tx = prev_tx; 1485 break; 1486 } 1487 1488 if (cur_tx != start_tx) 1489 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1490 1491 /* 1492 * If there's a BPF listener, bounce a copy of this frame 1493 * to him. 1494 */ 1495 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1496 1497 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1498 } 1499 1500 /* 1501 * If there are no frames queued, bail. 1502 */ 1503 if (cur_tx == NULL) { 1504 VR_UNLOCK(sc); 1505 return; 1506 } 1507 1508 sc->vr_cdata.vr_tx_tail = cur_tx; 1509 1510 if (sc->vr_cdata.vr_tx_head == NULL) 1511 sc->vr_cdata.vr_tx_head = start_tx; 1512 1513 /* Tell the chip to start transmitting. */ 1514 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1515 1516 /* 1517 * Set a timeout in case the chip goes out to lunch. 1518 */ 1519 ifp->if_timer = 5; 1520 VR_UNLOCK(sc); 1521 1522 return; 1523} 1524 1525static void 1526vr_init(xsc) 1527 void *xsc; 1528{ 1529 struct vr_softc *sc = xsc; 1530 struct ifnet *ifp = &sc->arpcom.ac_if; 1531 struct mii_data *mii; 1532 int i; 1533 1534 VR_LOCK(sc); 1535 1536 mii = device_get_softc(sc->vr_miibus); 1537 1538 /* 1539 * Cancel pending I/O and free all RX/TX buffers. 1540 */ 1541 vr_stop(sc); 1542 vr_reset(sc); 1543 1544 /* 1545 * Set our station address. 1546 */ 1547 for (i = 0; i < ETHER_ADDR_LEN; i++) 1548 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1549 1550 /* Set DMA size */ 1551 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1552 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1553 1554 /* 1555 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1556 * so we must set both. 1557 */ 1558 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1559 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1560 1561 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1562 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1563 1564 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1565 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1566 1567 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1568 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1569 1570 /* Init circular RX list. */ 1571 if (vr_list_rx_init(sc) == ENOBUFS) { 1572 printf("vr%d: initialization failed: no " 1573 "memory for rx buffers\n", sc->vr_unit); 1574 vr_stop(sc); 1575 VR_UNLOCK(sc); 1576 return; 1577 } 1578 1579 /* 1580 * Init tx descriptors. 1581 */ 1582 vr_list_tx_init(sc); 1583 1584 /* If we want promiscuous mode, set the allframes bit. */ 1585 if (ifp->if_flags & IFF_PROMISC) 1586 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1587 else 1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1589 1590 /* Set capture broadcast bit to capture broadcast frames. */ 1591 if (ifp->if_flags & IFF_BROADCAST) 1592 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1593 else 1594 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1595 1596 /* 1597 * Program the multicast filter, if necessary. 1598 */ 1599 vr_setmulti(sc); 1600 1601 /* 1602 * Load the address of the RX list. 1603 */ 1604 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1605 1606 /* Enable receiver and transmitter. */ 1607 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1608 VR_CMD_TX_ON|VR_CMD_RX_ON| 1609 VR_CMD_RX_GO); 1610 1611 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1612 1613 /* 1614 * Enable interrupts. 1615 */ 1616 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1617 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1618 1619 mii_mediachg(mii); 1620 1621 ifp->if_flags |= IFF_RUNNING; 1622 ifp->if_flags &= ~IFF_OACTIVE; 1623 1624 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1625 1626 VR_UNLOCK(sc); 1627 1628 return; 1629} 1630 1631/* 1632 * Set media options. 1633 */ 1634static int 1635vr_ifmedia_upd(ifp) 1636 struct ifnet *ifp; 1637{ 1638 struct vr_softc *sc; 1639 1640 sc = ifp->if_softc; 1641 1642 if (ifp->if_flags & IFF_UP) 1643 vr_init(sc); 1644 1645 return(0); 1646} 1647 1648/* 1649 * Report current media status. 1650 */ 1651static void 1652vr_ifmedia_sts(ifp, ifmr) 1653 struct ifnet *ifp; 1654 struct ifmediareq *ifmr; 1655{ 1656 struct vr_softc *sc; 1657 struct mii_data *mii; 1658 1659 sc = ifp->if_softc; 1660 mii = device_get_softc(sc->vr_miibus); 1661 mii_pollstat(mii); 1662 ifmr->ifm_active = mii->mii_media_active; 1663 ifmr->ifm_status = mii->mii_media_status; 1664 1665 return; 1666} 1667 1668static int 1669vr_ioctl(ifp, command, data) 1670 struct ifnet *ifp; 1671 u_long command; 1672 caddr_t data; 1673{ 1674 struct vr_softc *sc = ifp->if_softc; 1675 struct ifreq *ifr = (struct ifreq *) data; 1676 struct mii_data *mii; 1677 int error = 0; 1678 1679 VR_LOCK(sc); 1680 1681 switch(command) { 1682 case SIOCSIFFLAGS: 1683 if (ifp->if_flags & IFF_UP) { 1684 vr_init(sc); 1685 } else { 1686 if (ifp->if_flags & IFF_RUNNING) 1687 vr_stop(sc); 1688 } 1689 error = 0; 1690 break; 1691 case SIOCADDMULTI: 1692 case SIOCDELMULTI: 1693 vr_setmulti(sc); 1694 error = 0; 1695 break; 1696 case SIOCGIFMEDIA: 1697 case SIOCSIFMEDIA: 1698 mii = device_get_softc(sc->vr_miibus); 1699 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1700 break; 1701 default: 1702 error = ether_ioctl(ifp, command, data); 1703 break; 1704 } 1705 1706 VR_UNLOCK(sc); 1707 1708 return(error); 1709} 1710 1711static void 1712vr_watchdog(ifp) 1713 struct ifnet *ifp; 1714{ 1715 struct vr_softc *sc; 1716 1717 sc = ifp->if_softc; 1718 1719 VR_LOCK(sc); 1720 ifp->if_oerrors++; 1721 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1722 1723 vr_stop(sc); 1724 vr_reset(sc); 1725 vr_init(sc); 1726 1727 if (ifp->if_snd.ifq_head != NULL) 1728 vr_start(ifp); 1729 1730 VR_UNLOCK(sc); 1731 1732 return; 1733} 1734 1735/* 1736 * Stop the adapter and free any mbufs allocated to the 1737 * RX and TX lists. 1738 */ 1739static void 1740vr_stop(sc) 1741 struct vr_softc *sc; 1742{ 1743 register int i; 1744 struct ifnet *ifp; 1745 1746 VR_LOCK(sc); 1747 1748 ifp = &sc->arpcom.ac_if; 1749 ifp->if_timer = 0; 1750 1751 untimeout(vr_tick, sc, sc->vr_stat_ch); 1752 1753 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1754 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1755 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1756 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1757 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1758 1759 /* 1760 * Free data in the RX lists. 1761 */ 1762 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1763 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1764 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1765 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1766 } 1767 } 1768 bzero((char *)&sc->vr_ldata->vr_rx_list, 1769 sizeof(sc->vr_ldata->vr_rx_list)); 1770 1771 /* 1772 * Free the TX list buffers. 1773 */ 1774 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1775 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1776 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1777 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1778 } 1779 } 1780 1781 bzero((char *)&sc->vr_ldata->vr_tx_list, 1782 sizeof(sc->vr_ldata->vr_tx_list)); 1783 1784 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1785 VR_UNLOCK(sc); 1786 1787 return; 1788} 1789 1790/* 1791 * Stop all chip I/O so that the kernel's probe routines don't 1792 * get confused by errant DMAs when rebooting. 1793 */ 1794static void 1795vr_shutdown(dev) 1796 device_t dev; 1797{ 1798 struct vr_softc *sc; 1799 1800 sc = device_get_softc(dev); 1801 1802 vr_stop(sc); 1803 1804 return; 1805} 1806