if_vr.c revision 113545
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * VIA Rhine fast ethernet PCI NIC driver 35 * 36 * Supports various network adapters based on the VIA Rhine 37 * and Rhine II PCI controllers, including the D-Link DFE530TX. 38 * Datasheets are available at http://www.via.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The VIA Rhine controllers are similar in some respects to the 47 * the DEC tulip chips, except less complicated. The controller 48 * uses an MII bus and an external physical layer interface. The 49 * receiver has a one entry perfect filter and a 64-bit hash table 50 * multicast filter. Transmit and receive descriptors are similar 51 * to the tulip. 52 * 53 * The Rhine has a serious flaw in its transmit DMA mechanism: 54 * transmit buffers must be longword aligned. Unfortunately, 55 * FreeBSD doesn't guarantee that mbufs will be filled in starting 56 * at longword boundaries, so we have to do a buffer copy before 57 * transmission. 58 */ 59 60#include <sys/cdefs.h> 61__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 113545 2003-04-16 03:16:57Z mdodd $"); 62 63#include <sys/param.h> 64#include <sys/systm.h> 65#include <sys/sockio.h> 66#include <sys/mbuf.h> 67#include <sys/malloc.h> 68#include <sys/kernel.h> 69#include <sys/socket.h> 70 71#include <net/if.h> 72#include <net/if_arp.h> 73#include <net/ethernet.h> 74#include <net/if_dl.h> 75#include <net/if_media.h> 76 77#include <net/bpf.h> 78 79#include <vm/vm.h> /* for vtophys */ 80#include <vm/pmap.h> /* for vtophys */ 81#include <machine/bus_pio.h> 82#include <machine/bus_memio.h> 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <pci/pcireg.h> 92#include <pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, pci, 1, 1, 1); 99MODULE_DEPEND(vr, ether, 1, 1, 1); 100MODULE_DEPEND(vr, miibus, 1, 1, 1); 101 102/* "controller miibus0" required. See GENERIC if you get errors here. */ 103#include "miibus_if.h" 104 105#undef VR_USESWSHIFT 106 107/* 108 * Various supported device vendors/types and their names. 109 */ 110static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 118 "VIA VT6105 Rhine III 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 120 "VIA VT6105M Rhine III 10/100BaseTX" }, 121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 122 "Delta Electronics Rhine II 10/100BaseTX" }, 123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 124 "Addtron Technology Rhine II 10/100BaseTX" }, 125 { 0, 0, NULL } 126}; 127 128static int vr_probe (device_t); 129static int vr_attach (device_t); 130static int vr_detach (device_t); 131 132static int vr_newbuf (struct vr_softc *, 133 struct vr_chain_onefrag *, 134 struct mbuf *); 135static int vr_encap (struct vr_softc *, struct vr_chain *, 136 struct mbuf * ); 137 138static void vr_rxeof (struct vr_softc *); 139static void vr_rxeoc (struct vr_softc *); 140static void vr_txeof (struct vr_softc *); 141static void vr_txeoc (struct vr_softc *); 142static void vr_tick (void *); 143static void vr_intr (void *); 144static void vr_start (struct ifnet *); 145static int vr_ioctl (struct ifnet *, u_long, caddr_t); 146static void vr_init (void *); 147static void vr_stop (struct vr_softc *); 148static void vr_watchdog (struct ifnet *); 149static void vr_shutdown (device_t); 150static int vr_ifmedia_upd (struct ifnet *); 151static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153#ifdef VR_USESWSHIFT 154static void vr_mii_sync (struct vr_softc *); 155static void vr_mii_send (struct vr_softc *, u_int32_t, int); 156#endif 157static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159static int vr_miibus_readreg (device_t, int, int); 160static int vr_miibus_writereg (device_t, int, int, int); 161static void vr_miibus_statchg (device_t); 162 163static void vr_setcfg (struct vr_softc *, int); 164static u_int8_t vr_calchash (u_int8_t *); 165static void vr_setmulti (struct vr_softc *); 166static void vr_reset (struct vr_softc *); 167static int vr_list_rx_init (struct vr_softc *); 168static int vr_list_tx_init (struct vr_softc *); 169 170#ifdef VR_USEIOSPACE 171#define VR_RES SYS_RES_IOPORT 172#define VR_RID VR_PCI_LOIO 173#else 174#define VR_RES SYS_RES_MEMORY 175#define VR_RID VR_PCI_LOMEM 176#endif 177 178static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195}; 196 197static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201}; 202 203static devclass_t vr_devclass; 204 205DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 206DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 207 208#define VR_SETBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) | (x)) 211 212#define VR_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_1(sc, reg, \ 214 CSR_READ_1(sc, reg) & ~(x)) 215 216#define VR_SETBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) | (x)) 219 220#define VR_CLRBIT16(sc, reg, x) \ 221 CSR_WRITE_2(sc, reg, \ 222 CSR_READ_2(sc, reg) & ~(x)) 223 224#define VR_SETBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | (x)) 227 228#define VR_CLRBIT32(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~(x)) 231 232#define SIO_SET(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) | (x)) 235 236#define SIO_CLR(x) \ 237 CSR_WRITE_1(sc, VR_MIICMD, \ 238 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 239 240#ifdef VR_USESWSHIFT 241/* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244static void 245vr_mii_sync(sc) 246 struct vr_softc *sc; 247{ 248 register int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 259 return; 260} 261 262/* 263 * Clock a series of bits through the MII. 264 */ 265static void 266vr_mii_send(sc, bits, cnt) 267 struct vr_softc *sc; 268 u_int32_t bits; 269 int cnt; 270{ 271 int i; 272 273 SIO_CLR(VR_MIICMD_CLK); 274 275 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 276 if (bits & i) { 277 SIO_SET(VR_MIICMD_DATAIN); 278 } else { 279 SIO_CLR(VR_MIICMD_DATAIN); 280 } 281 DELAY(1); 282 SIO_CLR(VR_MIICMD_CLK); 283 DELAY(1); 284 SIO_SET(VR_MIICMD_CLK); 285 } 286} 287#endif 288 289/* 290 * Read an PHY register through the MII. 291 */ 292static int 293vr_mii_readreg(sc, frame) 294 struct vr_softc *sc; 295 struct vr_mii_frame *frame; 296 297#ifdef VR_USESWSHIFT 298{ 299 int i, ack; 300 301 VR_LOCK(sc); 302 303 /* 304 * Set up frame for RX. 305 */ 306 frame->mii_stdelim = VR_MII_STARTDELIM; 307 frame->mii_opcode = VR_MII_READOP; 308 frame->mii_turnaround = 0; 309 frame->mii_data = 0; 310 311 CSR_WRITE_1(sc, VR_MIICMD, 0); 312 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 313 314 /* 315 * Turn on data xmit. 316 */ 317 SIO_SET(VR_MIICMD_DIR); 318 319 vr_mii_sync(sc); 320 321 /* 322 * Send command/address info. 323 */ 324 vr_mii_send(sc, frame->mii_stdelim, 2); 325 vr_mii_send(sc, frame->mii_opcode, 2); 326 vr_mii_send(sc, frame->mii_phyaddr, 5); 327 vr_mii_send(sc, frame->mii_regaddr, 5); 328 329 /* Idle bit */ 330 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 331 DELAY(1); 332 SIO_SET(VR_MIICMD_CLK); 333 DELAY(1); 334 335 /* Turn off xmit. */ 336 SIO_CLR(VR_MIICMD_DIR); 337 338 /* Check for ack */ 339 SIO_CLR(VR_MIICMD_CLK); 340 DELAY(1); 341 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 342 SIO_SET(VR_MIICMD_CLK); 343 DELAY(1); 344 345 /* 346 * Now try reading data bits. If the ack failed, we still 347 * need to clock through 16 cycles to keep the PHY(s) in sync. 348 */ 349 if (ack) { 350 for(i = 0; i < 16; i++) { 351 SIO_CLR(VR_MIICMD_CLK); 352 DELAY(1); 353 SIO_SET(VR_MIICMD_CLK); 354 DELAY(1); 355 } 356 goto fail; 357 } 358 359 for (i = 0x8000; i; i >>= 1) { 360 SIO_CLR(VR_MIICMD_CLK); 361 DELAY(1); 362 if (!ack) { 363 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 364 frame->mii_data |= i; 365 DELAY(1); 366 } 367 SIO_SET(VR_MIICMD_CLK); 368 DELAY(1); 369 } 370 371fail: 372 373 SIO_CLR(VR_MIICMD_CLK); 374 DELAY(1); 375 SIO_SET(VR_MIICMD_CLK); 376 DELAY(1); 377 378 VR_UNLOCK(sc); 379 380 if (ack) 381 return(1); 382 return(0); 383} 384#else 385{ 386 int s, i; 387 388 s = splimp(); 389 390 /* Set the PHY-adress */ 391 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 392 frame->mii_phyaddr); 393 394 /* Set the register-adress */ 395 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 396 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 397 398 for (i = 0; i < 10000; i++) { 399 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 400 break; 401 DELAY(1); 402 } 403 404 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 405 406 (void)splx(s); 407 408 return(0); 409} 410#endif 411 412 413/* 414 * Write to a PHY register through the MII. 415 */ 416static int 417vr_mii_writereg(sc, frame) 418 struct vr_softc *sc; 419 struct vr_mii_frame *frame; 420 421#ifdef VR_USESWSHIFT 422{ 423 VR_LOCK(sc); 424 425 CSR_WRITE_1(sc, VR_MIICMD, 0); 426 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 427 428 /* 429 * Set up frame for TX. 430 */ 431 432 frame->mii_stdelim = VR_MII_STARTDELIM; 433 frame->mii_opcode = VR_MII_WRITEOP; 434 frame->mii_turnaround = VR_MII_TURNAROUND; 435 436 /* 437 * Turn on data output. 438 */ 439 SIO_SET(VR_MIICMD_DIR); 440 441 vr_mii_sync(sc); 442 443 vr_mii_send(sc, frame->mii_stdelim, 2); 444 vr_mii_send(sc, frame->mii_opcode, 2); 445 vr_mii_send(sc, frame->mii_phyaddr, 5); 446 vr_mii_send(sc, frame->mii_regaddr, 5); 447 vr_mii_send(sc, frame->mii_turnaround, 2); 448 vr_mii_send(sc, frame->mii_data, 16); 449 450 /* Idle bit. */ 451 SIO_SET(VR_MIICMD_CLK); 452 DELAY(1); 453 SIO_CLR(VR_MIICMD_CLK); 454 DELAY(1); 455 456 /* 457 * Turn off xmit. 458 */ 459 SIO_CLR(VR_MIICMD_DIR); 460 461 VR_UNLOCK(sc); 462 463 return(0); 464} 465#else 466{ 467 int s, i; 468 469 s = splimp(); 470 471 /* Set the PHY-adress */ 472 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 473 frame->mii_phyaddr); 474 475 /* Set the register-adress and data to write */ 476 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 477 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 478 479 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 480 481 for (i = 0; i < 10000; i++) { 482 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 483 break; 484 DELAY(1); 485 } 486 487 (void)splx(s); 488 489 return(0); 490} 491#endif 492 493static int 494vr_miibus_readreg(dev, phy, reg) 495 device_t dev; 496 int phy, reg; 497{ 498 struct vr_softc *sc; 499 struct vr_mii_frame frame; 500 501 sc = device_get_softc(dev); 502 503 switch (sc->vr_revid) { 504 case REV_ID_VT6102_APOLLO: 505 if (phy != 1) 506 return 0; 507 default: 508 break; 509 } 510 511 bzero((char *)&frame, sizeof(frame)); 512 513 frame.mii_phyaddr = phy; 514 frame.mii_regaddr = reg; 515 vr_mii_readreg(sc, &frame); 516 517 return(frame.mii_data); 518} 519 520static int 521vr_miibus_writereg(dev, phy, reg, data) 522 device_t dev; 523 u_int16_t phy, reg, data; 524{ 525 struct vr_softc *sc; 526 struct vr_mii_frame frame; 527 528 sc = device_get_softc(dev); 529 530 switch (sc->vr_revid) { 531 case REV_ID_VT6102_APOLLO: 532 if (phy != 1) 533 return 0; 534 default: 535 break; 536 } 537 538 bzero((char *)&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 frame.mii_data = data; 543 544 vr_mii_writereg(sc, &frame); 545 546 return(0); 547} 548 549static void 550vr_miibus_statchg(dev) 551 device_t dev; 552{ 553 struct vr_softc *sc; 554 struct mii_data *mii; 555 556 sc = device_get_softc(dev); 557 VR_LOCK(sc); 558 mii = device_get_softc(sc->vr_miibus); 559 vr_setcfg(sc, mii->mii_media_active); 560 VR_UNLOCK(sc); 561 562 return; 563} 564 565/* 566 * Calculate CRC of a multicast group address, return the lower 6 bits. 567 */ 568static u_int8_t vr_calchash(addr) 569 u_int8_t *addr; 570{ 571 u_int32_t crc, carry; 572 int i, j; 573 u_int8_t c; 574 575 /* Compute CRC for the address value. */ 576 crc = 0xFFFFFFFF; /* initial value */ 577 578 for (i = 0; i < 6; i++) { 579 c = *(addr + i); 580 for (j = 0; j < 8; j++) { 581 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 582 crc <<= 1; 583 c >>= 1; 584 if (carry) 585 crc = (crc ^ 0x04c11db6) | carry; 586 } 587 } 588 589 /* return the filter bit position */ 590 return((crc >> 26) & 0x0000003F); 591} 592 593/* 594 * Program the 64-bit multicast hash filter. 595 */ 596static void 597vr_setmulti(sc) 598 struct vr_softc *sc; 599{ 600 struct ifnet *ifp; 601 int h = 0; 602 u_int32_t hashes[2] = { 0, 0 }; 603 struct ifmultiaddr *ifma; 604 u_int8_t rxfilt; 605 int mcnt = 0; 606 607 ifp = &sc->arpcom.ac_if; 608 609 rxfilt = CSR_READ_1(sc, VR_RXCFG); 610 611 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 612 rxfilt |= VR_RXCFG_RX_MULTI; 613 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 614 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 615 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 616 return; 617 } 618 619 /* first, zot all the existing hash bits */ 620 CSR_WRITE_4(sc, VR_MAR0, 0); 621 CSR_WRITE_4(sc, VR_MAR1, 0); 622 623 /* now program new ones */ 624 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 625 if (ifma->ifma_addr->sa_family != AF_LINK) 626 continue; 627 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 628 if (h < 32) 629 hashes[0] |= (1 << h); 630 else 631 hashes[1] |= (1 << (h - 32)); 632 mcnt++; 633 } 634 635 if (mcnt) 636 rxfilt |= VR_RXCFG_RX_MULTI; 637 else 638 rxfilt &= ~VR_RXCFG_RX_MULTI; 639 640 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 641 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 642 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 643 644 return; 645} 646 647/* 648 * In order to fiddle with the 649 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 650 * first have to put the transmit and/or receive logic in the idle state. 651 */ 652static void 653vr_setcfg(sc, media) 654 struct vr_softc *sc; 655 int media; 656{ 657 int restart = 0; 658 659 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 660 restart = 1; 661 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 662 } 663 664 if ((media & IFM_GMASK) == IFM_FDX) 665 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 else 667 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 668 669 if (restart) 670 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 671 672 return; 673} 674 675static void 676vr_reset(sc) 677 struct vr_softc *sc; 678{ 679 register int i; 680 681 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 682 683 for (i = 0; i < VR_TIMEOUT; i++) { 684 DELAY(10); 685 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 686 break; 687 } 688 if (i == VR_TIMEOUT) { 689 if (sc->vr_revid < REV_ID_VT3065_A) 690 printf("vr%d: reset never completed!\n", sc->vr_unit); 691 else { 692 /* Use newer force reset command */ 693 printf("vr%d: Using force reset command.\n", sc->vr_unit); 694 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 695 } 696 } 697 698 /* Wait a little while for the chip to get its brains in order. */ 699 DELAY(1000); 700 701 return; 702} 703 704/* 705 * Probe for a VIA Rhine chip. Check the PCI vendor and device 706 * IDs against our list and return a device name if we find a match. 707 */ 708static int 709vr_probe(dev) 710 device_t dev; 711{ 712 struct vr_type *t; 713 714 t = vr_devs; 715 716 while(t->vr_name != NULL) { 717 if ((pci_get_vendor(dev) == t->vr_vid) && 718 (pci_get_device(dev) == t->vr_did)) { 719 device_set_desc(dev, t->vr_name); 720 return(0); 721 } 722 t++; 723 } 724 725 return(ENXIO); 726} 727 728/* 729 * Attach the interface. Allocate softc structures, do ifmedia 730 * setup and ethernet/BPF attach. 731 */ 732static int 733vr_attach(dev) 734 device_t dev; 735{ 736 int i; 737 u_char eaddr[ETHER_ADDR_LEN]; 738 struct vr_softc *sc; 739 struct ifnet *ifp; 740 int unit, error = 0, rid; 741 742 sc = device_get_softc(dev); 743 unit = device_get_unit(dev); 744 745 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 746 MTX_DEF | MTX_RECURSE); 747 748 /* 749 * Handle power management nonsense. 750 */ 751 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 752 u_int32_t iobase, membase, irq; 753 754 /* Save important PCI config data. */ 755 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 756 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 757 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 758 759 /* Reset the power state. */ 760 printf("vr%d: chip is in D%d power mode " 761 "-- setting to D0\n", unit, 762 pci_get_powerstate(dev)); 763 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 764 765 /* Restore PCI config data. */ 766 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 767 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 768 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 769 } 770 771 /* 772 * Map control/status registers. 773 */ 774 pci_enable_busmaster(dev); 775 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 776 777 rid = VR_RID; 778 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 779 0, ~0, 1, RF_ACTIVE); 780 781 if (sc->vr_res == NULL) { 782 printf("vr%d: couldn't map ports/memory\n", unit); 783 error = ENXIO; 784 goto fail; 785 } 786 787 sc->vr_btag = rman_get_bustag(sc->vr_res); 788 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 789 790 /* Allocate interrupt */ 791 rid = 0; 792 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 793 RF_SHAREABLE | RF_ACTIVE); 794 795 if (sc->vr_irq == NULL) { 796 printf("vr%d: couldn't map interrupt\n", unit); 797 error = ENXIO; 798 goto fail; 799 } 800 801 /* 802 * Windows may put the chip in suspend mode when it 803 * shuts down. Be sure to kick it in the head to wake it 804 * up again. 805 */ 806 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 807 808 /* Reset the adapter. */ 809 vr_reset(sc); 810 811 /* 812 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 813 * initialization and disable AUTOPOLL. 814 */ 815 pci_write_config(dev, VR_PCI_MODE, 816 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 817 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 818 819 /* 820 * Get station address. The way the Rhine chips work, 821 * you're not allowed to directly access the EEPROM once 822 * they've been programmed a special way. Consequently, 823 * we need to read the node address from the PAR0 and PAR1 824 * registers. 825 */ 826 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 827 DELAY(200); 828 for (i = 0; i < ETHER_ADDR_LEN; i++) 829 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 830 831 /* 832 * A Rhine chip was detected. Inform the world. 833 */ 834 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 835 836 sc->vr_unit = unit; 837 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 838 839 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 840 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 841 842 if (sc->vr_ldata == NULL) { 843 printf("vr%d: no memory for list buffers!\n", unit); 844 error = ENXIO; 845 goto fail; 846 } 847 848 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 849 850 ifp = &sc->arpcom.ac_if; 851 ifp->if_softc = sc; 852 ifp->if_unit = unit; 853 ifp->if_name = "vr"; 854 ifp->if_mtu = ETHERMTU; 855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 856 ifp->if_ioctl = vr_ioctl; 857 ifp->if_output = ether_output; 858 ifp->if_start = vr_start; 859 ifp->if_watchdog = vr_watchdog; 860 ifp->if_init = vr_init; 861 ifp->if_baudrate = 10000000; 862 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 863 864 /* 865 * Do MII setup. 866 */ 867 if (mii_phy_probe(dev, &sc->vr_miibus, 868 vr_ifmedia_upd, vr_ifmedia_sts)) { 869 printf("vr%d: MII without any phy!\n", sc->vr_unit); 870 error = ENXIO; 871 goto fail; 872 } 873 874 callout_handle_init(&sc->vr_stat_ch); 875 876 /* 877 * Call MI attach routine. 878 */ 879 ether_ifattach(ifp, eaddr); 880 881 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 882 vr_intr, sc, &sc->vr_intrhand); 883 884 if (error) { 885 printf("vr%d: couldn't set up irq\n", unit); 886 goto fail; 887 } 888 889fail: 890 if (error) 891 vr_detach(dev); 892 893 return(error); 894} 895 896static int 897vr_detach(dev) 898 device_t dev; 899{ 900 struct vr_softc *sc; 901 struct ifnet *ifp; 902 903 sc = device_get_softc(dev); 904 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 905 VR_LOCK(sc); 906 ifp = &sc->arpcom.ac_if; 907 908 if (device_is_alive(dev)) { 909 if (bus_child_present(dev)) 910 vr_stop(sc); 911 ether_ifdetach(ifp); 912 device_delete_child(dev, sc->vr_miibus); 913 bus_generic_detach(dev); 914 } 915 916 if (sc->vr_intrhand) 917 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 918 if (sc->vr_irq) 919 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 920 if (sc->vr_res) 921 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 922 923 if (sc->vr_ldata) 924 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 925 926 VR_UNLOCK(sc); 927 mtx_destroy(&sc->vr_mtx); 928 929 return(0); 930} 931 932/* 933 * Initialize the transmit descriptors. 934 */ 935static int 936vr_list_tx_init(sc) 937 struct vr_softc *sc; 938{ 939 struct vr_chain_data *cd; 940 struct vr_list_data *ld; 941 int i; 942 943 cd = &sc->vr_cdata; 944 ld = sc->vr_ldata; 945 for (i = 0; i < VR_TX_LIST_CNT; i++) { 946 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 947 if (i == (VR_TX_LIST_CNT - 1)) 948 cd->vr_tx_chain[i].vr_nextdesc = 949 &cd->vr_tx_chain[0]; 950 else 951 cd->vr_tx_chain[i].vr_nextdesc = 952 &cd->vr_tx_chain[i + 1]; 953 } 954 955 cd->vr_tx_free = &cd->vr_tx_chain[0]; 956 cd->vr_tx_tail = cd->vr_tx_head = NULL; 957 958 return(0); 959} 960 961 962/* 963 * Initialize the RX descriptors and allocate mbufs for them. Note that 964 * we arrange the descriptors in a closed ring, so that the last descriptor 965 * points back to the first. 966 */ 967static int 968vr_list_rx_init(sc) 969 struct vr_softc *sc; 970{ 971 struct vr_chain_data *cd; 972 struct vr_list_data *ld; 973 int i; 974 975 cd = &sc->vr_cdata; 976 ld = sc->vr_ldata; 977 978 for (i = 0; i < VR_RX_LIST_CNT; i++) { 979 cd->vr_rx_chain[i].vr_ptr = 980 (struct vr_desc *)&ld->vr_rx_list[i]; 981 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 982 return(ENOBUFS); 983 if (i == (VR_RX_LIST_CNT - 1)) { 984 cd->vr_rx_chain[i].vr_nextdesc = 985 &cd->vr_rx_chain[0]; 986 ld->vr_rx_list[i].vr_next = 987 vtophys(&ld->vr_rx_list[0]); 988 } else { 989 cd->vr_rx_chain[i].vr_nextdesc = 990 &cd->vr_rx_chain[i + 1]; 991 ld->vr_rx_list[i].vr_next = 992 vtophys(&ld->vr_rx_list[i + 1]); 993 } 994 } 995 996 cd->vr_rx_head = &cd->vr_rx_chain[0]; 997 998 return(0); 999} 1000 1001/* 1002 * Initialize an RX descriptor and attach an MBUF cluster. 1003 * Note: the length fields are only 11 bits wide, which means the 1004 * largest size we can specify is 2047. This is important because 1005 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1006 * overflow the field and make a mess. 1007 */ 1008static int 1009vr_newbuf(sc, c, m) 1010 struct vr_softc *sc; 1011 struct vr_chain_onefrag *c; 1012 struct mbuf *m; 1013{ 1014 struct mbuf *m_new = NULL; 1015 1016 if (m == NULL) { 1017 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1018 if (m_new == NULL) 1019 return(ENOBUFS); 1020 1021 MCLGET(m_new, M_DONTWAIT); 1022 if (!(m_new->m_flags & M_EXT)) { 1023 m_freem(m_new); 1024 return(ENOBUFS); 1025 } 1026 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1027 } else { 1028 m_new = m; 1029 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1030 m_new->m_data = m_new->m_ext.ext_buf; 1031 } 1032 1033 m_adj(m_new, sizeof(u_int64_t)); 1034 1035 c->vr_mbuf = m_new; 1036 c->vr_ptr->vr_status = VR_RXSTAT; 1037 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1038 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1039 1040 return(0); 1041} 1042 1043/* 1044 * A frame has been uploaded: pass the resulting mbuf chain up to 1045 * the higher level protocols. 1046 */ 1047static void 1048vr_rxeof(sc) 1049 struct vr_softc *sc; 1050{ 1051 struct mbuf *m; 1052 struct ifnet *ifp; 1053 struct vr_chain_onefrag *cur_rx; 1054 int total_len = 0; 1055 u_int32_t rxstat; 1056 1057 ifp = &sc->arpcom.ac_if; 1058 1059 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1060 VR_RXSTAT_OWN)) { 1061 struct mbuf *m0 = NULL; 1062 1063 cur_rx = sc->vr_cdata.vr_rx_head; 1064 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1065 m = cur_rx->vr_mbuf; 1066 1067 /* 1068 * If an error occurs, update stats, clear the 1069 * status word and leave the mbuf cluster in place: 1070 * it should simply get re-used next time this descriptor 1071 * comes up in the ring. 1072 */ 1073 if (rxstat & VR_RXSTAT_RXERR) { 1074 ifp->if_ierrors++; 1075 printf("vr%d: rx error (%02x):", 1076 sc->vr_unit, rxstat & 0x000000ff); 1077 if (rxstat & VR_RXSTAT_CRCERR) 1078 printf(" crc error"); 1079 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1080 printf(" frame alignment error\n"); 1081 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1082 printf(" FIFO overflow"); 1083 if (rxstat & VR_RXSTAT_GIANT) 1084 printf(" received giant packet"); 1085 if (rxstat & VR_RXSTAT_RUNT) 1086 printf(" received runt packet"); 1087 if (rxstat & VR_RXSTAT_BUSERR) 1088 printf(" system bus error"); 1089 if (rxstat & VR_RXSTAT_BUFFERR) 1090 printf("rx buffer error"); 1091 printf("\n"); 1092 vr_newbuf(sc, cur_rx, m); 1093 continue; 1094 } 1095 1096 /* No errors; receive the packet. */ 1097 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1098 1099 /* 1100 * XXX The VIA Rhine chip includes the CRC with every 1101 * received frame, and there's no way to turn this 1102 * behavior off (at least, I can't find anything in 1103 * the manual that explains how to do it) so we have 1104 * to trim off the CRC manually. 1105 */ 1106 total_len -= ETHER_CRC_LEN; 1107 1108 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1109 NULL); 1110 vr_newbuf(sc, cur_rx, m); 1111 if (m0 == NULL) { 1112 ifp->if_ierrors++; 1113 continue; 1114 } 1115 m = m0; 1116 1117 ifp->if_ipackets++; 1118 (*ifp->if_input)(ifp, m); 1119 } 1120 1121 return; 1122} 1123 1124static void 1125vr_rxeoc(sc) 1126 struct vr_softc *sc; 1127{ 1128 struct ifnet *ifp; 1129 int i; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 ifp->if_ierrors++; 1134 1135 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1136 DELAY(10000); 1137 1138 for (i = 0x400; 1139 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1140 i--) 1141 ; /* Wait for receiver to stop */ 1142 1143 if (!i) { 1144 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1145 sc->vr_flags |= VR_F_RESTART; 1146 return; 1147 } 1148 1149 vr_rxeof(sc); 1150 1151 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1152 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1153 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1154 1155 return; 1156} 1157 1158/* 1159 * A frame was downloaded to the chip. It's safe for us to clean up 1160 * the list buffers. 1161 */ 1162 1163static void 1164vr_txeof(sc) 1165 struct vr_softc *sc; 1166{ 1167 struct vr_chain *cur_tx; 1168 struct ifnet *ifp; 1169 1170 ifp = &sc->arpcom.ac_if; 1171 1172 /* Reset the timeout timer; if_txeoc will clear it. */ 1173 ifp->if_timer = 5; 1174 1175 /* Sanity check. */ 1176 if (sc->vr_cdata.vr_tx_head == NULL) 1177 return; 1178 1179 /* 1180 * Go through our tx list and free mbufs for those 1181 * frames that have been transmitted. 1182 */ 1183 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1184 u_int32_t txstat; 1185 int i; 1186 1187 cur_tx = sc->vr_cdata.vr_tx_head; 1188 txstat = cur_tx->vr_ptr->vr_status; 1189 1190 if ((txstat & VR_TXSTAT_ABRT) || 1191 (txstat & VR_TXSTAT_UDF)) { 1192 for (i = 0x400; 1193 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1194 i--) 1195 ; /* Wait for chip to shutdown */ 1196 if (!i) { 1197 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1198 sc->vr_flags |= VR_F_RESTART; 1199 break; 1200 } 1201 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1202 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1203 break; 1204 } 1205 1206 if (txstat & VR_TXSTAT_OWN) 1207 break; 1208 1209 if (txstat & VR_TXSTAT_ERRSUM) { 1210 ifp->if_oerrors++; 1211 if (txstat & VR_TXSTAT_DEFER) 1212 ifp->if_collisions++; 1213 if (txstat & VR_TXSTAT_LATECOLL) 1214 ifp->if_collisions++; 1215 } 1216 1217 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1218 1219 ifp->if_opackets++; 1220 if (cur_tx->vr_mbuf != NULL) { 1221 m_freem(cur_tx->vr_mbuf); 1222 cur_tx->vr_mbuf = NULL; 1223 } 1224 1225 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1226 sc->vr_cdata.vr_tx_head = NULL; 1227 sc->vr_cdata.vr_tx_tail = NULL; 1228 break; 1229 } 1230 1231 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1232 } 1233 1234 return; 1235} 1236 1237/* 1238 * TX 'end of channel' interrupt handler. 1239 */ 1240static void 1241vr_txeoc(sc) 1242 struct vr_softc *sc; 1243{ 1244 struct ifnet *ifp; 1245 1246 ifp = &sc->arpcom.ac_if; 1247 1248 if (sc->vr_cdata.vr_tx_head == NULL) { 1249 ifp->if_flags &= ~IFF_OACTIVE; 1250 sc->vr_cdata.vr_tx_tail = NULL; 1251 ifp->if_timer = 0; 1252 } 1253 1254 return; 1255} 1256 1257static void 1258vr_tick(xsc) 1259 void *xsc; 1260{ 1261 struct vr_softc *sc; 1262 struct mii_data *mii; 1263 1264 sc = xsc; 1265 VR_LOCK(sc); 1266 if (sc->vr_flags & VR_F_RESTART) { 1267 printf("vr%d: restarting\n", sc->vr_unit); 1268 vr_stop(sc); 1269 vr_reset(sc); 1270 vr_init(sc); 1271 sc->vr_flags &= ~VR_F_RESTART; 1272 } 1273 1274 mii = device_get_softc(sc->vr_miibus); 1275 mii_tick(mii); 1276 1277 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1278 1279 VR_UNLOCK(sc); 1280 1281 return; 1282} 1283 1284static void 1285vr_intr(arg) 1286 void *arg; 1287{ 1288 struct vr_softc *sc; 1289 struct ifnet *ifp; 1290 u_int16_t status; 1291 1292 sc = arg; 1293 VR_LOCK(sc); 1294 ifp = &sc->arpcom.ac_if; 1295 1296 /* Supress unwanted interrupts. */ 1297 if (!(ifp->if_flags & IFF_UP)) { 1298 vr_stop(sc); 1299 VR_UNLOCK(sc); 1300 return; 1301 } 1302 1303 /* Disable interrupts. */ 1304 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1305 1306 for (;;) { 1307 1308 status = CSR_READ_2(sc, VR_ISR); 1309 if (status) 1310 CSR_WRITE_2(sc, VR_ISR, status); 1311 1312 if ((status & VR_INTRS) == 0) 1313 break; 1314 1315 if (status & VR_ISR_RX_OK) 1316 vr_rxeof(sc); 1317 1318 if (status & VR_ISR_RX_DROPPED) { 1319 printf("vr%d: rx packet lost\n", sc->vr_unit); 1320 ifp->if_ierrors++; 1321 } 1322 1323 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1324 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1325 printf("vr%d: receive error (%04x)", 1326 sc->vr_unit, status); 1327 if (status & VR_ISR_RX_NOBUF) 1328 printf(" no buffers"); 1329 if (status & VR_ISR_RX_OFLOW) 1330 printf(" overflow"); 1331 if (status & VR_ISR_RX_DROPPED) 1332 printf(" packet lost"); 1333 printf("\n"); 1334 vr_rxeoc(sc); 1335 } 1336 1337 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1338 vr_reset(sc); 1339 vr_init(sc); 1340 break; 1341 } 1342 1343 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1344 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1345 vr_txeof(sc); 1346 if ((status & VR_ISR_UDFI) || 1347 (status & VR_ISR_TX_ABRT2) || 1348 (status & VR_ISR_TX_ABRT)) { 1349 ifp->if_oerrors++; 1350 if (sc->vr_cdata.vr_tx_head != NULL) { 1351 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1352 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1353 } 1354 } else 1355 vr_txeoc(sc); 1356 } 1357 1358 } 1359 1360 /* Re-enable interrupts. */ 1361 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1362 1363 if (ifp->if_snd.ifq_head != NULL) { 1364 vr_start(ifp); 1365 } 1366 1367 VR_UNLOCK(sc); 1368 1369 return; 1370} 1371 1372/* 1373 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1374 * pointers to the fragment pointers. 1375 */ 1376static int 1377vr_encap(sc, c, m_head) 1378 struct vr_softc *sc; 1379 struct vr_chain *c; 1380 struct mbuf *m_head; 1381{ 1382 int frag = 0; 1383 struct vr_desc *f = NULL; 1384 int total_len; 1385 struct mbuf *m; 1386 1387 m = m_head; 1388 total_len = 0; 1389 1390 /* 1391 * The VIA Rhine wants packet buffers to be longword 1392 * aligned, but very often our mbufs aren't. Rather than 1393 * waste time trying to decide when to copy and when not 1394 * to copy, just do it all the time. 1395 */ 1396 if (m != NULL) { 1397 struct mbuf *m_new = NULL; 1398 1399 m_new = m_defrag(m_head, M_DONTWAIT); 1400 if (m_new == NULL) { 1401 return(1); 1402 } 1403 1404 m_head = m_new; 1405 /* 1406 * The Rhine chip doesn't auto-pad, so we have to make 1407 * sure to pad short frames out to the minimum frame length 1408 * ourselves. 1409 */ 1410 if (m_head->m_len < VR_MIN_FRAMELEN) { 1411 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1412 m_new->m_len = m_new->m_pkthdr.len; 1413 } 1414 f = c->vr_ptr; 1415 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1416 f->vr_ctl = total_len = m_new->m_len; 1417 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1418 f->vr_status = 0; 1419 frag = 1; 1420 } 1421 1422 c->vr_mbuf = m_head; 1423 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1424 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1425 1426 return(0); 1427} 1428 1429/* 1430 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1431 * to the mbuf data regions directly in the transmit lists. We also save a 1432 * copy of the pointers since the transmit list fragment pointers are 1433 * physical addresses. 1434 */ 1435 1436static void 1437vr_start(ifp) 1438 struct ifnet *ifp; 1439{ 1440 struct vr_softc *sc; 1441 struct mbuf *m_head = NULL; 1442 struct vr_chain *cur_tx = NULL, *start_tx, *prev_tx; 1443 1444 sc = ifp->if_softc; 1445 1446 VR_LOCK(sc); 1447 1448 /* 1449 * Check for an available queue slot. If there are none, 1450 * punt. 1451 */ 1452 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1453 VR_UNLOCK(sc); 1454 return; 1455 } 1456 1457 start_tx = sc->vr_cdata.vr_tx_free; 1458 1459 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1460 IF_DEQUEUE(&ifp->if_snd, m_head); 1461 if (m_head == NULL) 1462 break; 1463 1464 /* Pick a descriptor off the free list. */ 1465 prev_tx = cur_tx; 1466 cur_tx = sc->vr_cdata.vr_tx_free; 1467 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1468 1469 /* Pack the data into the descriptor. */ 1470 if (vr_encap(sc, cur_tx, m_head)) { 1471 /* Rollback, send what we were able to encap. */ 1472 IF_PREPEND(&ifp->if_snd, m_head); 1473 sc->vr_cdata.vr_tx_free = cur_tx; 1474 cur_tx = prev_tx; 1475 break; 1476 } 1477 1478 if (cur_tx != start_tx) 1479 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1480 1481 /* 1482 * If there's a BPF listener, bounce a copy of this frame 1483 * to him. 1484 */ 1485 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1486 1487 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1488 } 1489 1490 /* 1491 * If there are no frames queued, bail. 1492 */ 1493 if (cur_tx == NULL) { 1494 VR_UNLOCK(sc); 1495 return; 1496 } 1497 1498 sc->vr_cdata.vr_tx_tail = cur_tx; 1499 1500 if (sc->vr_cdata.vr_tx_head == NULL) 1501 sc->vr_cdata.vr_tx_head = start_tx; 1502 1503 /* Tell the chip to start transmitting. */ 1504 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1505 1506 /* 1507 * Set a timeout in case the chip goes out to lunch. 1508 */ 1509 ifp->if_timer = 5; 1510 VR_UNLOCK(sc); 1511 1512 return; 1513} 1514 1515static void 1516vr_init(xsc) 1517 void *xsc; 1518{ 1519 struct vr_softc *sc = xsc; 1520 struct ifnet *ifp = &sc->arpcom.ac_if; 1521 struct mii_data *mii; 1522 int i; 1523 1524 VR_LOCK(sc); 1525 1526 mii = device_get_softc(sc->vr_miibus); 1527 1528 /* 1529 * Cancel pending I/O and free all RX/TX buffers. 1530 */ 1531 vr_stop(sc); 1532 vr_reset(sc); 1533 1534 /* 1535 * Set our station address. 1536 */ 1537 for (i = 0; i < ETHER_ADDR_LEN; i++) 1538 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1539 1540 /* Set DMA size */ 1541 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1542 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1543 1544 /* 1545 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1546 * so we must set both. 1547 */ 1548 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1549 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1550 1551 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1552 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1553 1554 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1555 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1556 1557 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1558 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1559 1560 /* Init circular RX list. */ 1561 if (vr_list_rx_init(sc) == ENOBUFS) { 1562 printf("vr%d: initialization failed: no " 1563 "memory for rx buffers\n", sc->vr_unit); 1564 vr_stop(sc); 1565 VR_UNLOCK(sc); 1566 return; 1567 } 1568 1569 /* 1570 * Init tx descriptors. 1571 */ 1572 vr_list_tx_init(sc); 1573 1574 /* If we want promiscuous mode, set the allframes bit. */ 1575 if (ifp->if_flags & IFF_PROMISC) 1576 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1577 else 1578 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1579 1580 /* Set capture broadcast bit to capture broadcast frames. */ 1581 if (ifp->if_flags & IFF_BROADCAST) 1582 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1583 else 1584 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1585 1586 /* 1587 * Program the multicast filter, if necessary. 1588 */ 1589 vr_setmulti(sc); 1590 1591 /* 1592 * Load the address of the RX list. 1593 */ 1594 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1595 1596 /* Enable receiver and transmitter. */ 1597 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1598 VR_CMD_TX_ON|VR_CMD_RX_ON| 1599 VR_CMD_RX_GO); 1600 1601 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1602 1603 /* 1604 * Enable interrupts. 1605 */ 1606 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1607 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1608 1609 mii_mediachg(mii); 1610 1611 ifp->if_flags |= IFF_RUNNING; 1612 ifp->if_flags &= ~IFF_OACTIVE; 1613 1614 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1615 1616 VR_UNLOCK(sc); 1617 1618 return; 1619} 1620 1621/* 1622 * Set media options. 1623 */ 1624static int 1625vr_ifmedia_upd(ifp) 1626 struct ifnet *ifp; 1627{ 1628 struct vr_softc *sc; 1629 1630 sc = ifp->if_softc; 1631 1632 if (ifp->if_flags & IFF_UP) 1633 vr_init(sc); 1634 1635 return(0); 1636} 1637 1638/* 1639 * Report current media status. 1640 */ 1641static void 1642vr_ifmedia_sts(ifp, ifmr) 1643 struct ifnet *ifp; 1644 struct ifmediareq *ifmr; 1645{ 1646 struct vr_softc *sc; 1647 struct mii_data *mii; 1648 1649 sc = ifp->if_softc; 1650 mii = device_get_softc(sc->vr_miibus); 1651 mii_pollstat(mii); 1652 ifmr->ifm_active = mii->mii_media_active; 1653 ifmr->ifm_status = mii->mii_media_status; 1654 1655 return; 1656} 1657 1658static int 1659vr_ioctl(ifp, command, data) 1660 struct ifnet *ifp; 1661 u_long command; 1662 caddr_t data; 1663{ 1664 struct vr_softc *sc = ifp->if_softc; 1665 struct ifreq *ifr = (struct ifreq *) data; 1666 struct mii_data *mii; 1667 int error = 0; 1668 1669 VR_LOCK(sc); 1670 1671 switch(command) { 1672 case SIOCSIFFLAGS: 1673 if (ifp->if_flags & IFF_UP) { 1674 vr_init(sc); 1675 } else { 1676 if (ifp->if_flags & IFF_RUNNING) 1677 vr_stop(sc); 1678 } 1679 error = 0; 1680 break; 1681 case SIOCADDMULTI: 1682 case SIOCDELMULTI: 1683 vr_setmulti(sc); 1684 error = 0; 1685 break; 1686 case SIOCGIFMEDIA: 1687 case SIOCSIFMEDIA: 1688 mii = device_get_softc(sc->vr_miibus); 1689 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1690 break; 1691 default: 1692 error = ether_ioctl(ifp, command, data); 1693 break; 1694 } 1695 1696 VR_UNLOCK(sc); 1697 1698 return(error); 1699} 1700 1701static void 1702vr_watchdog(ifp) 1703 struct ifnet *ifp; 1704{ 1705 struct vr_softc *sc; 1706 1707 sc = ifp->if_softc; 1708 1709 VR_LOCK(sc); 1710 ifp->if_oerrors++; 1711 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1712 1713 vr_stop(sc); 1714 vr_reset(sc); 1715 vr_init(sc); 1716 1717 if (ifp->if_snd.ifq_head != NULL) 1718 vr_start(ifp); 1719 1720 VR_UNLOCK(sc); 1721 1722 return; 1723} 1724 1725/* 1726 * Stop the adapter and free any mbufs allocated to the 1727 * RX and TX lists. 1728 */ 1729static void 1730vr_stop(sc) 1731 struct vr_softc *sc; 1732{ 1733 register int i; 1734 struct ifnet *ifp; 1735 1736 VR_LOCK(sc); 1737 1738 ifp = &sc->arpcom.ac_if; 1739 ifp->if_timer = 0; 1740 1741 untimeout(vr_tick, sc, sc->vr_stat_ch); 1742 1743 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1744 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1745 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1746 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1747 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1748 1749 /* 1750 * Free data in the RX lists. 1751 */ 1752 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1753 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1754 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1755 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1756 } 1757 } 1758 bzero((char *)&sc->vr_ldata->vr_rx_list, 1759 sizeof(sc->vr_ldata->vr_rx_list)); 1760 1761 /* 1762 * Free the TX list buffers. 1763 */ 1764 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1765 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1766 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1767 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1768 } 1769 } 1770 1771 bzero((char *)&sc->vr_ldata->vr_tx_list, 1772 sizeof(sc->vr_ldata->vr_tx_list)); 1773 1774 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1775 VR_UNLOCK(sc); 1776 1777 return; 1778} 1779 1780/* 1781 * Stop all chip I/O so that the kernel's probe routines don't 1782 * get confused by errant DMAs when rebooting. 1783 */ 1784static void 1785vr_shutdown(dev) 1786 device_t dev; 1787{ 1788 struct vr_softc *sc; 1789 1790 sc = device_get_softc(dev); 1791 1792 vr_stop(sc); 1793 1794 return; 1795} 1796