if_vr.c revision 113506
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * VIA Rhine fast ethernet PCI NIC driver 35 * 36 * Supports various network adapters based on the VIA Rhine 37 * and Rhine II PCI controllers, including the D-Link DFE530TX. 38 * Datasheets are available at http://www.via.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The VIA Rhine controllers are similar in some respects to the 47 * the DEC tulip chips, except less complicated. The controller 48 * uses an MII bus and an external physical layer interface. The 49 * receiver has a one entry perfect filter and a 64-bit hash table 50 * multicast filter. Transmit and receive descriptors are similar 51 * to the tulip. 52 * 53 * The Rhine has a serious flaw in its transmit DMA mechanism: 54 * transmit buffers must be longword aligned. Unfortunately, 55 * FreeBSD doesn't guarantee that mbufs will be filled in starting 56 * at longword boundaries, so we have to do a buffer copy before 57 * transmission. 58 */ 59 60#include <sys/cdefs.h> 61__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 113506 2003-04-15 06:37:30Z mdodd $"); 62 63#include <sys/param.h> 64#include <sys/systm.h> 65#include <sys/sockio.h> 66#include <sys/mbuf.h> 67#include <sys/malloc.h> 68#include <sys/kernel.h> 69#include <sys/socket.h> 70 71#include <net/if.h> 72#include <net/if_arp.h> 73#include <net/ethernet.h> 74#include <net/if_dl.h> 75#include <net/if_media.h> 76 77#include <net/bpf.h> 78 79#include <vm/vm.h> /* for vtophys */ 80#include <vm/pmap.h> /* for vtophys */ 81#include <machine/bus_pio.h> 82#include <machine/bus_memio.h> 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <pci/pcireg.h> 92#include <pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, pci, 1, 1, 1); 99MODULE_DEPEND(vr, ether, 1, 1, 1); 100MODULE_DEPEND(vr, miibus, 1, 1, 1); 101 102/* "controller miibus0" required. See GENERIC if you get errors here. */ 103#include "miibus_if.h" 104 105#undef VR_USESWSHIFT 106 107/* 108 * Various supported device vendors/types and their names. 109 */ 110static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 118 "VIA VT6105 Rhine III 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 120 "VIA VT6105M Rhine III 10/100BaseTX" }, 121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 122 "Delta Electronics Rhine II 10/100BaseTX" }, 123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 124 "Addtron Technology Rhine II 10/100BaseTX" }, 125 { 0, 0, NULL } 126}; 127 128static int vr_probe (device_t); 129static int vr_attach (device_t); 130static int vr_detach (device_t); 131 132static int vr_newbuf (struct vr_softc *, 133 struct vr_chain_onefrag *, 134 struct mbuf *); 135static int vr_encap (struct vr_softc *, struct vr_chain *, 136 struct mbuf * ); 137 138static void vr_rxeof (struct vr_softc *); 139static void vr_rxeoc (struct vr_softc *); 140static void vr_txeof (struct vr_softc *); 141static void vr_txeoc (struct vr_softc *); 142static void vr_tick (void *); 143static void vr_intr (void *); 144static void vr_start (struct ifnet *); 145static int vr_ioctl (struct ifnet *, u_long, caddr_t); 146static void vr_init (void *); 147static void vr_stop (struct vr_softc *); 148static void vr_watchdog (struct ifnet *); 149static void vr_shutdown (device_t); 150static int vr_ifmedia_upd (struct ifnet *); 151static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153#ifdef VR_USESWSHIFT 154static void vr_mii_sync (struct vr_softc *); 155static void vr_mii_send (struct vr_softc *, u_int32_t, int); 156#endif 157static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159static int vr_miibus_readreg (device_t, int, int); 160static int vr_miibus_writereg (device_t, int, int, int); 161static void vr_miibus_statchg (device_t); 162 163static void vr_setcfg (struct vr_softc *, int); 164static u_int8_t vr_calchash (u_int8_t *); 165static void vr_setmulti (struct vr_softc *); 166static void vr_reset (struct vr_softc *); 167static int vr_list_rx_init (struct vr_softc *); 168static int vr_list_tx_init (struct vr_softc *); 169 170#ifdef VR_USEIOSPACE 171#define VR_RES SYS_RES_IOPORT 172#define VR_RID VR_PCI_LOIO 173#else 174#define VR_RES SYS_RES_MEMORY 175#define VR_RID VR_PCI_LOMEM 176#endif 177 178static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195}; 196 197static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201}; 202 203static devclass_t vr_devclass; 204 205DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 206DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 207 208#define VR_SETBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) | (x)) 211 212#define VR_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_1(sc, reg, \ 214 CSR_READ_1(sc, reg) & ~(x)) 215 216#define VR_SETBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) | (x)) 219 220#define VR_CLRBIT16(sc, reg, x) \ 221 CSR_WRITE_2(sc, reg, \ 222 CSR_READ_2(sc, reg) & ~(x)) 223 224#define VR_SETBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | (x)) 227 228#define VR_CLRBIT32(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~(x)) 231 232#define SIO_SET(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) | (x)) 235 236#define SIO_CLR(x) \ 237 CSR_WRITE_1(sc, VR_MIICMD, \ 238 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 239 240#ifdef VR_USESWSHIFT 241/* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244static void 245vr_mii_sync(sc) 246 struct vr_softc *sc; 247{ 248 register int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 259 return; 260} 261 262/* 263 * Clock a series of bits through the MII. 264 */ 265static void 266vr_mii_send(sc, bits, cnt) 267 struct vr_softc *sc; 268 u_int32_t bits; 269 int cnt; 270{ 271 int i; 272 273 SIO_CLR(VR_MIICMD_CLK); 274 275 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 276 if (bits & i) { 277 SIO_SET(VR_MIICMD_DATAIN); 278 } else { 279 SIO_CLR(VR_MIICMD_DATAIN); 280 } 281 DELAY(1); 282 SIO_CLR(VR_MIICMD_CLK); 283 DELAY(1); 284 SIO_SET(VR_MIICMD_CLK); 285 } 286} 287#endif 288 289/* 290 * Read an PHY register through the MII. 291 */ 292static int 293vr_mii_readreg(sc, frame) 294 struct vr_softc *sc; 295 struct vr_mii_frame *frame; 296 297#ifdef VR_USESWSHIFT 298{ 299 int i, ack; 300 301 VR_LOCK(sc); 302 303 /* 304 * Set up frame for RX. 305 */ 306 frame->mii_stdelim = VR_MII_STARTDELIM; 307 frame->mii_opcode = VR_MII_READOP; 308 frame->mii_turnaround = 0; 309 frame->mii_data = 0; 310 311 CSR_WRITE_1(sc, VR_MIICMD, 0); 312 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 313 314 /* 315 * Turn on data xmit. 316 */ 317 SIO_SET(VR_MIICMD_DIR); 318 319 vr_mii_sync(sc); 320 321 /* 322 * Send command/address info. 323 */ 324 vr_mii_send(sc, frame->mii_stdelim, 2); 325 vr_mii_send(sc, frame->mii_opcode, 2); 326 vr_mii_send(sc, frame->mii_phyaddr, 5); 327 vr_mii_send(sc, frame->mii_regaddr, 5); 328 329 /* Idle bit */ 330 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 331 DELAY(1); 332 SIO_SET(VR_MIICMD_CLK); 333 DELAY(1); 334 335 /* Turn off xmit. */ 336 SIO_CLR(VR_MIICMD_DIR); 337 338 /* Check for ack */ 339 SIO_CLR(VR_MIICMD_CLK); 340 DELAY(1); 341 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 342 SIO_SET(VR_MIICMD_CLK); 343 DELAY(1); 344 345 /* 346 * Now try reading data bits. If the ack failed, we still 347 * need to clock through 16 cycles to keep the PHY(s) in sync. 348 */ 349 if (ack) { 350 for(i = 0; i < 16; i++) { 351 SIO_CLR(VR_MIICMD_CLK); 352 DELAY(1); 353 SIO_SET(VR_MIICMD_CLK); 354 DELAY(1); 355 } 356 goto fail; 357 } 358 359 for (i = 0x8000; i; i >>= 1) { 360 SIO_CLR(VR_MIICMD_CLK); 361 DELAY(1); 362 if (!ack) { 363 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 364 frame->mii_data |= i; 365 DELAY(1); 366 } 367 SIO_SET(VR_MIICMD_CLK); 368 DELAY(1); 369 } 370 371fail: 372 373 SIO_CLR(VR_MIICMD_CLK); 374 DELAY(1); 375 SIO_SET(VR_MIICMD_CLK); 376 DELAY(1); 377 378 VR_UNLOCK(sc); 379 380 if (ack) 381 return(1); 382 return(0); 383} 384#else 385{ 386 int s, i; 387 388 s = splimp(); 389 390 /* Set the PHY-adress */ 391 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 392 frame->mii_phyaddr); 393 394 /* Set the register-adress */ 395 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 396 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 397 398 for (i = 0; i < 10000; i++) { 399 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 400 break; 401 DELAY(1); 402 } 403 404 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 405 406 (void)splx(s); 407 408 return(0); 409} 410#endif 411 412 413/* 414 * Write to a PHY register through the MII. 415 */ 416static int 417vr_mii_writereg(sc, frame) 418 struct vr_softc *sc; 419 struct vr_mii_frame *frame; 420 421#ifdef VR_USESWSHIFT 422{ 423 VR_LOCK(sc); 424 425 CSR_WRITE_1(sc, VR_MIICMD, 0); 426 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 427 428 /* 429 * Set up frame for TX. 430 */ 431 432 frame->mii_stdelim = VR_MII_STARTDELIM; 433 frame->mii_opcode = VR_MII_WRITEOP; 434 frame->mii_turnaround = VR_MII_TURNAROUND; 435 436 /* 437 * Turn on data output. 438 */ 439 SIO_SET(VR_MIICMD_DIR); 440 441 vr_mii_sync(sc); 442 443 vr_mii_send(sc, frame->mii_stdelim, 2); 444 vr_mii_send(sc, frame->mii_opcode, 2); 445 vr_mii_send(sc, frame->mii_phyaddr, 5); 446 vr_mii_send(sc, frame->mii_regaddr, 5); 447 vr_mii_send(sc, frame->mii_turnaround, 2); 448 vr_mii_send(sc, frame->mii_data, 16); 449 450 /* Idle bit. */ 451 SIO_SET(VR_MIICMD_CLK); 452 DELAY(1); 453 SIO_CLR(VR_MIICMD_CLK); 454 DELAY(1); 455 456 /* 457 * Turn off xmit. 458 */ 459 SIO_CLR(VR_MIICMD_DIR); 460 461 VR_UNLOCK(sc); 462 463 return(0); 464} 465#else 466{ 467 int s, i; 468 469 s = splimp(); 470 471 /* Set the PHY-adress */ 472 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 473 frame->mii_phyaddr); 474 475 /* Set the register-adress and data to write */ 476 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 477 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 478 479 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 480 481 for (i = 0; i < 10000; i++) { 482 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 483 break; 484 DELAY(1); 485 } 486 487 (void)splx(s); 488 489 return(0); 490} 491#endif 492 493static int 494vr_miibus_readreg(dev, phy, reg) 495 device_t dev; 496 int phy, reg; 497{ 498 struct vr_softc *sc; 499 struct vr_mii_frame frame; 500 501 sc = device_get_softc(dev); 502 503 switch (sc->vr_revid) { 504 case REV_ID_VT6102_APOLLO: 505 if (phy != 1) 506 return 0; 507 default: 508 break; 509 } 510 511 bzero((char *)&frame, sizeof(frame)); 512 513 frame.mii_phyaddr = phy; 514 frame.mii_regaddr = reg; 515 vr_mii_readreg(sc, &frame); 516 517 return(frame.mii_data); 518} 519 520static int 521vr_miibus_writereg(dev, phy, reg, data) 522 device_t dev; 523 u_int16_t phy, reg, data; 524{ 525 struct vr_softc *sc; 526 struct vr_mii_frame frame; 527 528 sc = device_get_softc(dev); 529 530 switch (sc->vr_revid) { 531 case REV_ID_VT6102_APOLLO: 532 if (phy != 1) 533 return 0; 534 default: 535 break; 536 } 537 538 bzero((char *)&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 frame.mii_data = data; 543 544 vr_mii_writereg(sc, &frame); 545 546 return(0); 547} 548 549static void 550vr_miibus_statchg(dev) 551 device_t dev; 552{ 553 struct vr_softc *sc; 554 struct mii_data *mii; 555 556 sc = device_get_softc(dev); 557 VR_LOCK(sc); 558 mii = device_get_softc(sc->vr_miibus); 559 vr_setcfg(sc, mii->mii_media_active); 560 VR_UNLOCK(sc); 561 562 return; 563} 564 565/* 566 * Calculate CRC of a multicast group address, return the lower 6 bits. 567 */ 568static u_int8_t vr_calchash(addr) 569 u_int8_t *addr; 570{ 571 u_int32_t crc, carry; 572 int i, j; 573 u_int8_t c; 574 575 /* Compute CRC for the address value. */ 576 crc = 0xFFFFFFFF; /* initial value */ 577 578 for (i = 0; i < 6; i++) { 579 c = *(addr + i); 580 for (j = 0; j < 8; j++) { 581 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 582 crc <<= 1; 583 c >>= 1; 584 if (carry) 585 crc = (crc ^ 0x04c11db6) | carry; 586 } 587 } 588 589 /* return the filter bit position */ 590 return((crc >> 26) & 0x0000003F); 591} 592 593/* 594 * Program the 64-bit multicast hash filter. 595 */ 596static void 597vr_setmulti(sc) 598 struct vr_softc *sc; 599{ 600 struct ifnet *ifp; 601 int h = 0; 602 u_int32_t hashes[2] = { 0, 0 }; 603 struct ifmultiaddr *ifma; 604 u_int8_t rxfilt; 605 int mcnt = 0; 606 607 ifp = &sc->arpcom.ac_if; 608 609 rxfilt = CSR_READ_1(sc, VR_RXCFG); 610 611 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 612 rxfilt |= VR_RXCFG_RX_MULTI; 613 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 614 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 615 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 616 return; 617 } 618 619 /* first, zot all the existing hash bits */ 620 CSR_WRITE_4(sc, VR_MAR0, 0); 621 CSR_WRITE_4(sc, VR_MAR1, 0); 622 623 /* now program new ones */ 624 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 625 if (ifma->ifma_addr->sa_family != AF_LINK) 626 continue; 627 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 628 if (h < 32) 629 hashes[0] |= (1 << h); 630 else 631 hashes[1] |= (1 << (h - 32)); 632 mcnt++; 633 } 634 635 if (mcnt) 636 rxfilt |= VR_RXCFG_RX_MULTI; 637 else 638 rxfilt &= ~VR_RXCFG_RX_MULTI; 639 640 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 641 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 642 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 643 644 return; 645} 646 647/* 648 * In order to fiddle with the 649 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 650 * first have to put the transmit and/or receive logic in the idle state. 651 */ 652static void 653vr_setcfg(sc, media) 654 struct vr_softc *sc; 655 int media; 656{ 657 int restart = 0; 658 659 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 660 restart = 1; 661 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 662 } 663 664 if ((media & IFM_GMASK) == IFM_FDX) 665 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 else 667 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 668 669 if (restart) 670 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 671 672 return; 673} 674 675static void 676vr_reset(sc) 677 struct vr_softc *sc; 678{ 679 register int i; 680 681 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 682 683 for (i = 0; i < VR_TIMEOUT; i++) { 684 DELAY(10); 685 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 686 break; 687 } 688 if (i == VR_TIMEOUT) { 689 if (sc->vr_revid < REV_ID_VT3065_A) 690 printf("vr%d: reset never completed!\n", sc->vr_unit); 691 else { 692 /* Use newer force reset command */ 693 printf("vr%d: Using force reset command.\n", sc->vr_unit); 694 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 695 } 696 } 697 698 /* Wait a little while for the chip to get its brains in order. */ 699 DELAY(1000); 700 701 return; 702} 703 704/* 705 * Probe for a VIA Rhine chip. Check the PCI vendor and device 706 * IDs against our list and return a device name if we find a match. 707 */ 708static int 709vr_probe(dev) 710 device_t dev; 711{ 712 struct vr_type *t; 713 714 t = vr_devs; 715 716 while(t->vr_name != NULL) { 717 if ((pci_get_vendor(dev) == t->vr_vid) && 718 (pci_get_device(dev) == t->vr_did)) { 719 device_set_desc(dev, t->vr_name); 720 return(0); 721 } 722 t++; 723 } 724 725 return(ENXIO); 726} 727 728/* 729 * Attach the interface. Allocate softc structures, do ifmedia 730 * setup and ethernet/BPF attach. 731 */ 732static int 733vr_attach(dev) 734 device_t dev; 735{ 736 int i; 737 u_char eaddr[ETHER_ADDR_LEN]; 738 u_int32_t command; 739 struct vr_softc *sc; 740 struct ifnet *ifp; 741 int unit, error = 0, rid; 742 743 sc = device_get_softc(dev); 744 unit = device_get_unit(dev); 745 746 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 747 MTX_DEF | MTX_RECURSE); 748 749 /* 750 * Handle power management nonsense. 751 */ 752 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 753 u_int32_t iobase, membase, irq; 754 755 /* Save important PCI config data. */ 756 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 757 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 758 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 759 760 /* Reset the power state. */ 761 printf("vr%d: chip is in D%d power mode " 762 "-- setting to D0\n", unit, 763 pci_get_powerstate(dev)); 764 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 765 766 /* Restore PCI config data. */ 767 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 768 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 769 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 770 } 771 772 /* 773 * Map control/status registers. 774 */ 775 pci_enable_busmaster(dev); 776 pci_enable_io(dev, SYS_RES_IOPORT); 777 pci_enable_io(dev, SYS_RES_MEMORY); 778 command = pci_read_config(dev, PCIR_COMMAND, 4); 779 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 780 781#ifdef VR_USEIOSPACE 782 if (!(command & PCIM_CMD_PORTEN)) { 783 printf("vr%d: failed to enable I/O ports!\n", unit); 784 error = ENXIO; 785 goto fail; 786 } 787#else 788 if (!(command & PCIM_CMD_MEMEN)) { 789 printf("vr%d: failed to enable memory mapping!\n", unit); 790 error = ENXIO; 791 goto fail; 792 } 793#endif 794 795 rid = VR_RID; 796 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 797 0, ~0, 1, RF_ACTIVE); 798 799 if (sc->vr_res == NULL) { 800 printf("vr%d: couldn't map ports/memory\n", unit); 801 error = ENXIO; 802 goto fail; 803 } 804 805 sc->vr_btag = rman_get_bustag(sc->vr_res); 806 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 807 808 /* Allocate interrupt */ 809 rid = 0; 810 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 811 RF_SHAREABLE | RF_ACTIVE); 812 813 if (sc->vr_irq == NULL) { 814 printf("vr%d: couldn't map interrupt\n", unit); 815 error = ENXIO; 816 goto fail; 817 } 818 819 /* 820 * Windows may put the chip in suspend mode when it 821 * shuts down. Be sure to kick it in the head to wake it 822 * up again. 823 */ 824 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 825 826 /* Reset the adapter. */ 827 vr_reset(sc); 828 829 /* 830 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 831 * initialization and disable AUTOPOLL. 832 */ 833 pci_write_config(dev, VR_PCI_MODE, 834 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 835 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 836 837 /* 838 * Get station address. The way the Rhine chips work, 839 * you're not allowed to directly access the EEPROM once 840 * they've been programmed a special way. Consequently, 841 * we need to read the node address from the PAR0 and PAR1 842 * registers. 843 */ 844 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 845 DELAY(200); 846 for (i = 0; i < ETHER_ADDR_LEN; i++) 847 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 848 849 /* 850 * A Rhine chip was detected. Inform the world. 851 */ 852 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 853 854 sc->vr_unit = unit; 855 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 856 857 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 858 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 859 860 if (sc->vr_ldata == NULL) { 861 printf("vr%d: no memory for list buffers!\n", unit); 862 error = ENXIO; 863 goto fail; 864 } 865 866 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 867 868 ifp = &sc->arpcom.ac_if; 869 ifp->if_softc = sc; 870 ifp->if_unit = unit; 871 ifp->if_name = "vr"; 872 ifp->if_mtu = ETHERMTU; 873 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 874 ifp->if_ioctl = vr_ioctl; 875 ifp->if_output = ether_output; 876 ifp->if_start = vr_start; 877 ifp->if_watchdog = vr_watchdog; 878 ifp->if_init = vr_init; 879 ifp->if_baudrate = 10000000; 880 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 881 882 /* 883 * Do MII setup. 884 */ 885 if (mii_phy_probe(dev, &sc->vr_miibus, 886 vr_ifmedia_upd, vr_ifmedia_sts)) { 887 printf("vr%d: MII without any phy!\n", sc->vr_unit); 888 error = ENXIO; 889 goto fail; 890 } 891 892 callout_handle_init(&sc->vr_stat_ch); 893 894 /* 895 * Call MI attach routine. 896 */ 897 ether_ifattach(ifp, eaddr); 898 899 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 900 vr_intr, sc, &sc->vr_intrhand); 901 902 if (error) { 903 printf("vr%d: couldn't set up irq\n", unit); 904 goto fail; 905 } 906 907fail: 908 if (error) 909 vr_detach(dev); 910 911 return(error); 912} 913 914static int 915vr_detach(dev) 916 device_t dev; 917{ 918 struct vr_softc *sc; 919 struct ifnet *ifp; 920 921 sc = device_get_softc(dev); 922 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 923 VR_LOCK(sc); 924 ifp = &sc->arpcom.ac_if; 925 926 if (device_is_alive(dev)) { 927 if (bus_child_present(dev)) 928 vr_stop(sc); 929 ether_ifdetach(ifp); 930 device_delete_child(dev, sc->vr_miibus); 931 bus_generic_detach(dev); 932 } 933 934 if (sc->vr_intrhand) 935 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 936 if (sc->vr_irq) 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 938 if (sc->vr_res) 939 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 940 941 if (sc->vr_ldata) 942 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 943 944 VR_UNLOCK(sc); 945 mtx_destroy(&sc->vr_mtx); 946 947 return(0); 948} 949 950/* 951 * Initialize the transmit descriptors. 952 */ 953static int 954vr_list_tx_init(sc) 955 struct vr_softc *sc; 956{ 957 struct vr_chain_data *cd; 958 struct vr_list_data *ld; 959 int i; 960 961 cd = &sc->vr_cdata; 962 ld = sc->vr_ldata; 963 for (i = 0; i < VR_TX_LIST_CNT; i++) { 964 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 965 if (i == (VR_TX_LIST_CNT - 1)) 966 cd->vr_tx_chain[i].vr_nextdesc = 967 &cd->vr_tx_chain[0]; 968 else 969 cd->vr_tx_chain[i].vr_nextdesc = 970 &cd->vr_tx_chain[i + 1]; 971 } 972 973 cd->vr_tx_free = &cd->vr_tx_chain[0]; 974 cd->vr_tx_tail = cd->vr_tx_head = NULL; 975 976 return(0); 977} 978 979 980/* 981 * Initialize the RX descriptors and allocate mbufs for them. Note that 982 * we arrange the descriptors in a closed ring, so that the last descriptor 983 * points back to the first. 984 */ 985static int 986vr_list_rx_init(sc) 987 struct vr_softc *sc; 988{ 989 struct vr_chain_data *cd; 990 struct vr_list_data *ld; 991 int i; 992 993 cd = &sc->vr_cdata; 994 ld = sc->vr_ldata; 995 996 for (i = 0; i < VR_RX_LIST_CNT; i++) { 997 cd->vr_rx_chain[i].vr_ptr = 998 (struct vr_desc *)&ld->vr_rx_list[i]; 999 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 1000 return(ENOBUFS); 1001 if (i == (VR_RX_LIST_CNT - 1)) { 1002 cd->vr_rx_chain[i].vr_nextdesc = 1003 &cd->vr_rx_chain[0]; 1004 ld->vr_rx_list[i].vr_next = 1005 vtophys(&ld->vr_rx_list[0]); 1006 } else { 1007 cd->vr_rx_chain[i].vr_nextdesc = 1008 &cd->vr_rx_chain[i + 1]; 1009 ld->vr_rx_list[i].vr_next = 1010 vtophys(&ld->vr_rx_list[i + 1]); 1011 } 1012 } 1013 1014 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1015 1016 return(0); 1017} 1018 1019/* 1020 * Initialize an RX descriptor and attach an MBUF cluster. 1021 * Note: the length fields are only 11 bits wide, which means the 1022 * largest size we can specify is 2047. This is important because 1023 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1024 * overflow the field and make a mess. 1025 */ 1026static int 1027vr_newbuf(sc, c, m) 1028 struct vr_softc *sc; 1029 struct vr_chain_onefrag *c; 1030 struct mbuf *m; 1031{ 1032 struct mbuf *m_new = NULL; 1033 1034 if (m == NULL) { 1035 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1036 if (m_new == NULL) 1037 return(ENOBUFS); 1038 1039 MCLGET(m_new, M_DONTWAIT); 1040 if (!(m_new->m_flags & M_EXT)) { 1041 m_freem(m_new); 1042 return(ENOBUFS); 1043 } 1044 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1045 } else { 1046 m_new = m; 1047 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1048 m_new->m_data = m_new->m_ext.ext_buf; 1049 } 1050 1051 m_adj(m_new, sizeof(u_int64_t)); 1052 1053 c->vr_mbuf = m_new; 1054 c->vr_ptr->vr_status = VR_RXSTAT; 1055 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1056 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1057 1058 return(0); 1059} 1060 1061/* 1062 * A frame has been uploaded: pass the resulting mbuf chain up to 1063 * the higher level protocols. 1064 */ 1065static void 1066vr_rxeof(sc) 1067 struct vr_softc *sc; 1068{ 1069 struct mbuf *m; 1070 struct ifnet *ifp; 1071 struct vr_chain_onefrag *cur_rx; 1072 int total_len = 0; 1073 u_int32_t rxstat; 1074 1075 ifp = &sc->arpcom.ac_if; 1076 1077 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1078 VR_RXSTAT_OWN)) { 1079 struct mbuf *m0 = NULL; 1080 1081 cur_rx = sc->vr_cdata.vr_rx_head; 1082 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1083 m = cur_rx->vr_mbuf; 1084 1085 /* 1086 * If an error occurs, update stats, clear the 1087 * status word and leave the mbuf cluster in place: 1088 * it should simply get re-used next time this descriptor 1089 * comes up in the ring. 1090 */ 1091 if (rxstat & VR_RXSTAT_RXERR) { 1092 ifp->if_ierrors++; 1093 printf("vr%d: rx error (%02x):", 1094 sc->vr_unit, rxstat & 0x000000ff); 1095 if (rxstat & VR_RXSTAT_CRCERR) 1096 printf(" crc error"); 1097 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1098 printf(" frame alignment error\n"); 1099 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1100 printf(" FIFO overflow"); 1101 if (rxstat & VR_RXSTAT_GIANT) 1102 printf(" received giant packet"); 1103 if (rxstat & VR_RXSTAT_RUNT) 1104 printf(" received runt packet"); 1105 if (rxstat & VR_RXSTAT_BUSERR) 1106 printf(" system bus error"); 1107 if (rxstat & VR_RXSTAT_BUFFERR) 1108 printf("rx buffer error"); 1109 printf("\n"); 1110 vr_newbuf(sc, cur_rx, m); 1111 continue; 1112 } 1113 1114 /* No errors; receive the packet. */ 1115 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1116 1117 /* 1118 * XXX The VIA Rhine chip includes the CRC with every 1119 * received frame, and there's no way to turn this 1120 * behavior off (at least, I can't find anything in 1121 * the manual that explains how to do it) so we have 1122 * to trim off the CRC manually. 1123 */ 1124 total_len -= ETHER_CRC_LEN; 1125 1126 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1127 NULL); 1128 vr_newbuf(sc, cur_rx, m); 1129 if (m0 == NULL) { 1130 ifp->if_ierrors++; 1131 continue; 1132 } 1133 m = m0; 1134 1135 ifp->if_ipackets++; 1136 (*ifp->if_input)(ifp, m); 1137 } 1138 1139 return; 1140} 1141 1142static void 1143vr_rxeoc(sc) 1144 struct vr_softc *sc; 1145{ 1146 struct ifnet *ifp; 1147 int i; 1148 1149 ifp = &sc->arpcom.ac_if; 1150 1151 ifp->if_ierrors++; 1152 1153 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1154 DELAY(10000); 1155 1156 for (i = 0x400; 1157 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1158 i--) 1159 ; /* Wait for receiver to stop */ 1160 1161 if (!i) { 1162 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1163 sc->vr_flags |= VR_F_RESTART; 1164 return; 1165 } 1166 1167 vr_rxeof(sc); 1168 1169 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1170 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1171 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1172 1173 return; 1174} 1175 1176/* 1177 * A frame was downloaded to the chip. It's safe for us to clean up 1178 * the list buffers. 1179 */ 1180 1181static void 1182vr_txeof(sc) 1183 struct vr_softc *sc; 1184{ 1185 struct vr_chain *cur_tx; 1186 struct ifnet *ifp; 1187 1188 ifp = &sc->arpcom.ac_if; 1189 1190 /* Reset the timeout timer; if_txeoc will clear it. */ 1191 ifp->if_timer = 5; 1192 1193 /* Sanity check. */ 1194 if (sc->vr_cdata.vr_tx_head == NULL) 1195 return; 1196 1197 /* 1198 * Go through our tx list and free mbufs for those 1199 * frames that have been transmitted. 1200 */ 1201 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1202 u_int32_t txstat; 1203 int i; 1204 1205 cur_tx = sc->vr_cdata.vr_tx_head; 1206 txstat = cur_tx->vr_ptr->vr_status; 1207 1208 if ((txstat & VR_TXSTAT_ABRT) || 1209 (txstat & VR_TXSTAT_UDF)) { 1210 for (i = 0x400; 1211 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1212 i--) 1213 ; /* Wait for chip to shutdown */ 1214 if (!i) { 1215 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1216 sc->vr_flags |= VR_F_RESTART; 1217 break; 1218 } 1219 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1220 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1221 break; 1222 } 1223 1224 if (txstat & VR_TXSTAT_OWN) 1225 break; 1226 1227 if (txstat & VR_TXSTAT_ERRSUM) { 1228 ifp->if_oerrors++; 1229 if (txstat & VR_TXSTAT_DEFER) 1230 ifp->if_collisions++; 1231 if (txstat & VR_TXSTAT_LATECOLL) 1232 ifp->if_collisions++; 1233 } 1234 1235 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1236 1237 ifp->if_opackets++; 1238 if (cur_tx->vr_mbuf != NULL) { 1239 m_freem(cur_tx->vr_mbuf); 1240 cur_tx->vr_mbuf = NULL; 1241 } 1242 1243 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1244 sc->vr_cdata.vr_tx_head = NULL; 1245 sc->vr_cdata.vr_tx_tail = NULL; 1246 break; 1247 } 1248 1249 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1250 } 1251 1252 return; 1253} 1254 1255/* 1256 * TX 'end of channel' interrupt handler. 1257 */ 1258static void 1259vr_txeoc(sc) 1260 struct vr_softc *sc; 1261{ 1262 struct ifnet *ifp; 1263 1264 ifp = &sc->arpcom.ac_if; 1265 1266 if (sc->vr_cdata.vr_tx_head == NULL) { 1267 ifp->if_flags &= ~IFF_OACTIVE; 1268 sc->vr_cdata.vr_tx_tail = NULL; 1269 ifp->if_timer = 0; 1270 } 1271 1272 return; 1273} 1274 1275static void 1276vr_tick(xsc) 1277 void *xsc; 1278{ 1279 struct vr_softc *sc; 1280 struct mii_data *mii; 1281 1282 sc = xsc; 1283 VR_LOCK(sc); 1284 if (sc->vr_flags & VR_F_RESTART) { 1285 printf("vr%d: restarting\n", sc->vr_unit); 1286 vr_stop(sc); 1287 vr_reset(sc); 1288 vr_init(sc); 1289 sc->vr_flags &= ~VR_F_RESTART; 1290 } 1291 1292 mii = device_get_softc(sc->vr_miibus); 1293 mii_tick(mii); 1294 1295 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1296 1297 VR_UNLOCK(sc); 1298 1299 return; 1300} 1301 1302static void 1303vr_intr(arg) 1304 void *arg; 1305{ 1306 struct vr_softc *sc; 1307 struct ifnet *ifp; 1308 u_int16_t status; 1309 1310 sc = arg; 1311 VR_LOCK(sc); 1312 ifp = &sc->arpcom.ac_if; 1313 1314 /* Supress unwanted interrupts. */ 1315 if (!(ifp->if_flags & IFF_UP)) { 1316 vr_stop(sc); 1317 VR_UNLOCK(sc); 1318 return; 1319 } 1320 1321 /* Disable interrupts. */ 1322 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1323 1324 for (;;) { 1325 1326 status = CSR_READ_2(sc, VR_ISR); 1327 if (status) 1328 CSR_WRITE_2(sc, VR_ISR, status); 1329 1330 if ((status & VR_INTRS) == 0) 1331 break; 1332 1333 if (status & VR_ISR_RX_OK) 1334 vr_rxeof(sc); 1335 1336 if (status & VR_ISR_RX_DROPPED) { 1337 printf("vr%d: rx packet lost\n", sc->vr_unit); 1338 ifp->if_ierrors++; 1339 } 1340 1341 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1342 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1343 printf("vr%d: receive error (%04x)", 1344 sc->vr_unit, status); 1345 if (status & VR_ISR_RX_NOBUF) 1346 printf(" no buffers"); 1347 if (status & VR_ISR_RX_OFLOW) 1348 printf(" overflow"); 1349 if (status & VR_ISR_RX_DROPPED) 1350 printf(" packet lost"); 1351 printf("\n"); 1352 vr_rxeoc(sc); 1353 } 1354 1355 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1356 vr_reset(sc); 1357 vr_init(sc); 1358 break; 1359 } 1360 1361 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1362 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1363 vr_txeof(sc); 1364 if ((status & VR_ISR_UDFI) || 1365 (status & VR_ISR_TX_ABRT2) || 1366 (status & VR_ISR_TX_ABRT)) { 1367 ifp->if_oerrors++; 1368 if (sc->vr_cdata.vr_tx_head != NULL) { 1369 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1370 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1371 } 1372 } else 1373 vr_txeoc(sc); 1374 } 1375 1376 } 1377 1378 /* Re-enable interrupts. */ 1379 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1380 1381 if (ifp->if_snd.ifq_head != NULL) { 1382 vr_start(ifp); 1383 } 1384 1385 VR_UNLOCK(sc); 1386 1387 return; 1388} 1389 1390/* 1391 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1392 * pointers to the fragment pointers. 1393 */ 1394static int 1395vr_encap(sc, c, m_head) 1396 struct vr_softc *sc; 1397 struct vr_chain *c; 1398 struct mbuf *m_head; 1399{ 1400 int frag = 0; 1401 struct vr_desc *f = NULL; 1402 int total_len; 1403 struct mbuf *m; 1404 1405 m = m_head; 1406 total_len = 0; 1407 1408 /* 1409 * The VIA Rhine wants packet buffers to be longword 1410 * aligned, but very often our mbufs aren't. Rather than 1411 * waste time trying to decide when to copy and when not 1412 * to copy, just do it all the time. 1413 */ 1414 if (m != NULL) { 1415 struct mbuf *m_new = NULL; 1416 1417 m_new = m_defrag(m_head, M_DONTWAIT); 1418 if (m_new == NULL) { 1419 return(1); 1420 } 1421 1422 m_head = m_new; 1423 /* 1424 * The Rhine chip doesn't auto-pad, so we have to make 1425 * sure to pad short frames out to the minimum frame length 1426 * ourselves. 1427 */ 1428 if (m_head->m_len < VR_MIN_FRAMELEN) { 1429 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1430 m_new->m_len = m_new->m_pkthdr.len; 1431 } 1432 f = c->vr_ptr; 1433 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1434 f->vr_ctl = total_len = m_new->m_len; 1435 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1436 f->vr_status = 0; 1437 frag = 1; 1438 } 1439 1440 c->vr_mbuf = m_head; 1441 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1442 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1443 1444 return(0); 1445} 1446 1447/* 1448 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1449 * to the mbuf data regions directly in the transmit lists. We also save a 1450 * copy of the pointers since the transmit list fragment pointers are 1451 * physical addresses. 1452 */ 1453 1454static void 1455vr_start(ifp) 1456 struct ifnet *ifp; 1457{ 1458 struct vr_softc *sc; 1459 struct mbuf *m_head = NULL; 1460 struct vr_chain *cur_tx = NULL, *start_tx, *prev_tx; 1461 1462 sc = ifp->if_softc; 1463 1464 VR_LOCK(sc); 1465 1466 /* 1467 * Check for an available queue slot. If there are none, 1468 * punt. 1469 */ 1470 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1471 VR_UNLOCK(sc); 1472 return; 1473 } 1474 1475 start_tx = sc->vr_cdata.vr_tx_free; 1476 1477 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1478 IF_DEQUEUE(&ifp->if_snd, m_head); 1479 if (m_head == NULL) 1480 break; 1481 1482 /* Pick a descriptor off the free list. */ 1483 prev_tx = cur_tx; 1484 cur_tx = sc->vr_cdata.vr_tx_free; 1485 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1486 1487 /* Pack the data into the descriptor. */ 1488 if (vr_encap(sc, cur_tx, m_head)) { 1489 /* Rollback, send what we were able to encap. */ 1490 IF_PREPEND(&ifp->if_snd, m_head); 1491 sc->vr_cdata.vr_tx_free = cur_tx; 1492 cur_tx = prev_tx; 1493 break; 1494 } 1495 1496 if (cur_tx != start_tx) 1497 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1498 1499 /* 1500 * If there's a BPF listener, bounce a copy of this frame 1501 * to him. 1502 */ 1503 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1504 1505 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1506 } 1507 1508 /* 1509 * If there are no frames queued, bail. 1510 */ 1511 if (cur_tx == NULL) { 1512 VR_UNLOCK(sc); 1513 return; 1514 } 1515 1516 sc->vr_cdata.vr_tx_tail = cur_tx; 1517 1518 if (sc->vr_cdata.vr_tx_head == NULL) 1519 sc->vr_cdata.vr_tx_head = start_tx; 1520 1521 /* Tell the chip to start transmitting. */ 1522 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1523 1524 /* 1525 * Set a timeout in case the chip goes out to lunch. 1526 */ 1527 ifp->if_timer = 5; 1528 VR_UNLOCK(sc); 1529 1530 return; 1531} 1532 1533static void 1534vr_init(xsc) 1535 void *xsc; 1536{ 1537 struct vr_softc *sc = xsc; 1538 struct ifnet *ifp = &sc->arpcom.ac_if; 1539 struct mii_data *mii; 1540 int i; 1541 1542 VR_LOCK(sc); 1543 1544 mii = device_get_softc(sc->vr_miibus); 1545 1546 /* 1547 * Cancel pending I/O and free all RX/TX buffers. 1548 */ 1549 vr_stop(sc); 1550 vr_reset(sc); 1551 1552 /* 1553 * Set our station address. 1554 */ 1555 for (i = 0; i < ETHER_ADDR_LEN; i++) 1556 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1557 1558 /* Set DMA size */ 1559 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1560 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1561 1562 /* 1563 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1564 * so we must set both. 1565 */ 1566 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1567 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1568 1569 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1570 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1571 1572 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1573 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1574 1575 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1576 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1577 1578 /* Init circular RX list. */ 1579 if (vr_list_rx_init(sc) == ENOBUFS) { 1580 printf("vr%d: initialization failed: no " 1581 "memory for rx buffers\n", sc->vr_unit); 1582 vr_stop(sc); 1583 VR_UNLOCK(sc); 1584 return; 1585 } 1586 1587 /* 1588 * Init tx descriptors. 1589 */ 1590 vr_list_tx_init(sc); 1591 1592 /* If we want promiscuous mode, set the allframes bit. */ 1593 if (ifp->if_flags & IFF_PROMISC) 1594 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1595 else 1596 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1597 1598 /* Set capture broadcast bit to capture broadcast frames. */ 1599 if (ifp->if_flags & IFF_BROADCAST) 1600 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1601 else 1602 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1603 1604 /* 1605 * Program the multicast filter, if necessary. 1606 */ 1607 vr_setmulti(sc); 1608 1609 /* 1610 * Load the address of the RX list. 1611 */ 1612 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1613 1614 /* Enable receiver and transmitter. */ 1615 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1616 VR_CMD_TX_ON|VR_CMD_RX_ON| 1617 VR_CMD_RX_GO); 1618 1619 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1620 1621 /* 1622 * Enable interrupts. 1623 */ 1624 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1625 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1626 1627 mii_mediachg(mii); 1628 1629 ifp->if_flags |= IFF_RUNNING; 1630 ifp->if_flags &= ~IFF_OACTIVE; 1631 1632 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1633 1634 VR_UNLOCK(sc); 1635 1636 return; 1637} 1638 1639/* 1640 * Set media options. 1641 */ 1642static int 1643vr_ifmedia_upd(ifp) 1644 struct ifnet *ifp; 1645{ 1646 struct vr_softc *sc; 1647 1648 sc = ifp->if_softc; 1649 1650 if (ifp->if_flags & IFF_UP) 1651 vr_init(sc); 1652 1653 return(0); 1654} 1655 1656/* 1657 * Report current media status. 1658 */ 1659static void 1660vr_ifmedia_sts(ifp, ifmr) 1661 struct ifnet *ifp; 1662 struct ifmediareq *ifmr; 1663{ 1664 struct vr_softc *sc; 1665 struct mii_data *mii; 1666 1667 sc = ifp->if_softc; 1668 mii = device_get_softc(sc->vr_miibus); 1669 mii_pollstat(mii); 1670 ifmr->ifm_active = mii->mii_media_active; 1671 ifmr->ifm_status = mii->mii_media_status; 1672 1673 return; 1674} 1675 1676static int 1677vr_ioctl(ifp, command, data) 1678 struct ifnet *ifp; 1679 u_long command; 1680 caddr_t data; 1681{ 1682 struct vr_softc *sc = ifp->if_softc; 1683 struct ifreq *ifr = (struct ifreq *) data; 1684 struct mii_data *mii; 1685 int error = 0; 1686 1687 VR_LOCK(sc); 1688 1689 switch(command) { 1690 case SIOCSIFFLAGS: 1691 if (ifp->if_flags & IFF_UP) { 1692 vr_init(sc); 1693 } else { 1694 if (ifp->if_flags & IFF_RUNNING) 1695 vr_stop(sc); 1696 } 1697 error = 0; 1698 break; 1699 case SIOCADDMULTI: 1700 case SIOCDELMULTI: 1701 vr_setmulti(sc); 1702 error = 0; 1703 break; 1704 case SIOCGIFMEDIA: 1705 case SIOCSIFMEDIA: 1706 mii = device_get_softc(sc->vr_miibus); 1707 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1708 break; 1709 default: 1710 error = ether_ioctl(ifp, command, data); 1711 break; 1712 } 1713 1714 VR_UNLOCK(sc); 1715 1716 return(error); 1717} 1718 1719static void 1720vr_watchdog(ifp) 1721 struct ifnet *ifp; 1722{ 1723 struct vr_softc *sc; 1724 1725 sc = ifp->if_softc; 1726 1727 VR_LOCK(sc); 1728 ifp->if_oerrors++; 1729 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1730 1731 vr_stop(sc); 1732 vr_reset(sc); 1733 vr_init(sc); 1734 1735 if (ifp->if_snd.ifq_head != NULL) 1736 vr_start(ifp); 1737 1738 VR_UNLOCK(sc); 1739 1740 return; 1741} 1742 1743/* 1744 * Stop the adapter and free any mbufs allocated to the 1745 * RX and TX lists. 1746 */ 1747static void 1748vr_stop(sc) 1749 struct vr_softc *sc; 1750{ 1751 register int i; 1752 struct ifnet *ifp; 1753 1754 VR_LOCK(sc); 1755 1756 ifp = &sc->arpcom.ac_if; 1757 ifp->if_timer = 0; 1758 1759 untimeout(vr_tick, sc, sc->vr_stat_ch); 1760 1761 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1762 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1763 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1764 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1765 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1766 1767 /* 1768 * Free data in the RX lists. 1769 */ 1770 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1771 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1772 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1773 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1774 } 1775 } 1776 bzero((char *)&sc->vr_ldata->vr_rx_list, 1777 sizeof(sc->vr_ldata->vr_rx_list)); 1778 1779 /* 1780 * Free the TX list buffers. 1781 */ 1782 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1783 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1784 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1785 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1786 } 1787 } 1788 1789 bzero((char *)&sc->vr_ldata->vr_tx_list, 1790 sizeof(sc->vr_ldata->vr_tx_list)); 1791 1792 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1793 VR_UNLOCK(sc); 1794 1795 return; 1796} 1797 1798/* 1799 * Stop all chip I/O so that the kernel's probe routines don't 1800 * get confused by errant DMAs when rebooting. 1801 */ 1802static void 1803vr_shutdown(dev) 1804 device_t dev; 1805{ 1806 struct vr_softc *sc; 1807 1808 sc = device_get_softc(dev); 1809 1810 vr_stop(sc); 1811 1812 return; 1813} 1814