if_vr.c revision 113038
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * VIA Rhine fast ethernet PCI NIC driver 35 * 36 * Supports various network adapters based on the VIA Rhine 37 * and Rhine II PCI controllers, including the D-Link DFE530TX. 38 * Datasheets are available at http://www.via.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The VIA Rhine controllers are similar in some respects to the 47 * the DEC tulip chips, except less complicated. The controller 48 * uses an MII bus and an external physical layer interface. The 49 * receiver has a one entry perfect filter and a 64-bit hash table 50 * multicast filter. Transmit and receive descriptors are similar 51 * to the tulip. 52 * 53 * The Rhine has a serious flaw in its transmit DMA mechanism: 54 * transmit buffers must be longword aligned. Unfortunately, 55 * FreeBSD doesn't guarantee that mbufs will be filled in starting 56 * at longword boundaries, so we have to do a buffer copy before 57 * transmission. 58 */ 59 60#include <sys/cdefs.h> 61__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 113038 2003-04-03 21:36:33Z obrien $"); 62 63#include <sys/param.h> 64#include <sys/systm.h> 65#include <sys/sockio.h> 66#include <sys/mbuf.h> 67#include <sys/malloc.h> 68#include <sys/kernel.h> 69#include <sys/socket.h> 70 71#include <net/if.h> 72#include <net/if_arp.h> 73#include <net/ethernet.h> 74#include <net/if_dl.h> 75#include <net/if_media.h> 76 77#include <net/bpf.h> 78 79#include <vm/vm.h> /* for vtophys */ 80#include <vm/pmap.h> /* for vtophys */ 81#include <machine/bus_pio.h> 82#include <machine/bus_memio.h> 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <pci/pcireg.h> 92#include <pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, miibus, 1, 1, 1); 99 100/* "controller miibus0" required. See GENERIC if you get errors here. */ 101#include "miibus_if.h" 102 103#undef VR_USESWSHIFT 104 105/* 106 * Various supported device vendors/types and their names. 107 */ 108static struct vr_type vr_devs[] = { 109 { VIA_VENDORID, VIA_DEVICEID_RHINE, 110 "VIA VT3043 Rhine I 10/100BaseTX" }, 111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 112 "VIA VT86C100A Rhine II 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 114 "VIA VT6102 Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 116 "VIA VT6105 Rhine III 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 118 "VIA VT6105M Rhine III 10/100BaseTX" }, 119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 120 "Delta Electronics Rhine II 10/100BaseTX" }, 121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 122 "Addtron Technology Rhine II 10/100BaseTX" }, 123 { 0, 0, NULL } 124}; 125 126static int vr_probe (device_t); 127static int vr_attach (device_t); 128static int vr_detach (device_t); 129 130static int vr_newbuf (struct vr_softc *, 131 struct vr_chain_onefrag *, 132 struct mbuf *); 133static int vr_encap (struct vr_softc *, struct vr_chain *, 134 struct mbuf * ); 135 136static void vr_rxeof (struct vr_softc *); 137static void vr_rxeoc (struct vr_softc *); 138static void vr_txeof (struct vr_softc *); 139static void vr_txeoc (struct vr_softc *); 140static void vr_tick (void *); 141static void vr_intr (void *); 142static void vr_start (struct ifnet *); 143static int vr_ioctl (struct ifnet *, u_long, caddr_t); 144static void vr_init (void *); 145static void vr_stop (struct vr_softc *); 146static void vr_watchdog (struct ifnet *); 147static void vr_shutdown (device_t); 148static int vr_ifmedia_upd (struct ifnet *); 149static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 150 151#ifdef VR_USESWSHIFT 152static void vr_mii_sync (struct vr_softc *); 153static void vr_mii_send (struct vr_softc *, u_int32_t, int); 154#endif 155static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 156static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 157static int vr_miibus_readreg (device_t, int, int); 158static int vr_miibus_writereg (device_t, int, int, int); 159static void vr_miibus_statchg (device_t); 160 161static void vr_setcfg (struct vr_softc *, int); 162static u_int8_t vr_calchash (u_int8_t *); 163static void vr_setmulti (struct vr_softc *); 164static void vr_reset (struct vr_softc *); 165static int vr_list_rx_init (struct vr_softc *); 166static int vr_list_tx_init (struct vr_softc *); 167 168#ifdef VR_USEIOSPACE 169#define VR_RES SYS_RES_IOPORT 170#define VR_RID VR_PCI_LOIO 171#else 172#define VR_RES SYS_RES_MEMORY 173#define VR_RID VR_PCI_LOMEM 174#endif 175 176static device_method_t vr_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, vr_probe), 179 DEVMETHOD(device_attach, vr_attach), 180 DEVMETHOD(device_detach, vr_detach), 181 DEVMETHOD(device_shutdown, vr_shutdown), 182 183 /* bus interface */ 184 DEVMETHOD(bus_print_child, bus_generic_print_child), 185 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 186 187 /* MII interface */ 188 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 189 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 190 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 191 192 { 0, 0 } 193}; 194 195static driver_t vr_driver = { 196 "vr", 197 vr_methods, 198 sizeof(struct vr_softc) 199}; 200 201static devclass_t vr_devclass; 202 203DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 204DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 205 206#define VR_SETBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) | (x)) 209 210#define VR_CLRBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) & ~(x)) 213 214#define VR_SETBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) | (x)) 217 218#define VR_CLRBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) & ~(x)) 221 222#define VR_SETBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define VR_CLRBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 237 238#ifdef VR_USESWSHIFT 239/* 240 * Sync the PHYs by setting data bit and strobing the clock 32 times. 241 */ 242static void 243vr_mii_sync(sc) 244 struct vr_softc *sc; 245{ 246 register int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 257 return; 258} 259 260/* 261 * Clock a series of bits through the MII. 262 */ 263static void 264vr_mii_send(sc, bits, cnt) 265 struct vr_softc *sc; 266 u_int32_t bits; 267 int cnt; 268{ 269 int i; 270 271 SIO_CLR(VR_MIICMD_CLK); 272 273 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 274 if (bits & i) { 275 SIO_SET(VR_MIICMD_DATAIN); 276 } else { 277 SIO_CLR(VR_MIICMD_DATAIN); 278 } 279 DELAY(1); 280 SIO_CLR(VR_MIICMD_CLK); 281 DELAY(1); 282 SIO_SET(VR_MIICMD_CLK); 283 } 284} 285#endif 286 287/* 288 * Read an PHY register through the MII. 289 */ 290static int 291vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295#ifdef VR_USESWSHIFT 296{ 297 int i, ack; 298 299 VR_LOCK(sc); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 VR_UNLOCK(sc); 377 378 if (ack) 379 return(1); 380 return(0); 381} 382#else 383{ 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407} 408#endif 409 410 411/* 412 * Write to a PHY register through the MII. 413 */ 414static int 415vr_mii_writereg(sc, frame) 416 struct vr_softc *sc; 417 struct vr_mii_frame *frame; 418 419#ifdef VR_USESWSHIFT 420{ 421 VR_LOCK(sc); 422 423 CSR_WRITE_1(sc, VR_MIICMD, 0); 424 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 425 426 /* 427 * Set up frame for TX. 428 */ 429 430 frame->mii_stdelim = VR_MII_STARTDELIM; 431 frame->mii_opcode = VR_MII_WRITEOP; 432 frame->mii_turnaround = VR_MII_TURNAROUND; 433 434 /* 435 * Turn on data output. 436 */ 437 SIO_SET(VR_MIICMD_DIR); 438 439 vr_mii_sync(sc); 440 441 vr_mii_send(sc, frame->mii_stdelim, 2); 442 vr_mii_send(sc, frame->mii_opcode, 2); 443 vr_mii_send(sc, frame->mii_phyaddr, 5); 444 vr_mii_send(sc, frame->mii_regaddr, 5); 445 vr_mii_send(sc, frame->mii_turnaround, 2); 446 vr_mii_send(sc, frame->mii_data, 16); 447 448 /* Idle bit. */ 449 SIO_SET(VR_MIICMD_CLK); 450 DELAY(1); 451 SIO_CLR(VR_MIICMD_CLK); 452 DELAY(1); 453 454 /* 455 * Turn off xmit. 456 */ 457 SIO_CLR(VR_MIICMD_DIR); 458 459 VR_UNLOCK(sc); 460 461 return(0); 462} 463#else 464{ 465 int s, i; 466 467 s = splimp(); 468 469 /* Set the PHY-adress */ 470 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 471 frame->mii_phyaddr); 472 473 /* Set the register-adress and data to write */ 474 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 475 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 476 477 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 478 479 for (i = 0; i < 10000; i++) { 480 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 481 break; 482 DELAY(1); 483 } 484 485 (void)splx(s); 486 487 return(0); 488} 489#endif 490 491static int 492vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516} 517 518static int 519vr_miibus_writereg(dev, phy, reg, data) 520 device_t dev; 521 u_int16_t phy, reg, data; 522{ 523 struct vr_softc *sc; 524 struct vr_mii_frame frame; 525 526 sc = device_get_softc(dev); 527 528 switch (sc->vr_revid) { 529 case REV_ID_VT6102_APOLLO: 530 if (phy != 1) 531 return 0; 532 default: 533 break; 534 } 535 536 bzero((char *)&frame, sizeof(frame)); 537 538 frame.mii_phyaddr = phy; 539 frame.mii_regaddr = reg; 540 frame.mii_data = data; 541 542 vr_mii_writereg(sc, &frame); 543 544 return(0); 545} 546 547static void 548vr_miibus_statchg(dev) 549 device_t dev; 550{ 551 struct vr_softc *sc; 552 struct mii_data *mii; 553 554 sc = device_get_softc(dev); 555 VR_LOCK(sc); 556 mii = device_get_softc(sc->vr_miibus); 557 vr_setcfg(sc, mii->mii_media_active); 558 VR_UNLOCK(sc); 559 560 return; 561} 562 563/* 564 * Calculate CRC of a multicast group address, return the lower 6 bits. 565 */ 566static u_int8_t vr_calchash(addr) 567 u_int8_t *addr; 568{ 569 u_int32_t crc, carry; 570 int i, j; 571 u_int8_t c; 572 573 /* Compute CRC for the address value. */ 574 crc = 0xFFFFFFFF; /* initial value */ 575 576 for (i = 0; i < 6; i++) { 577 c = *(addr + i); 578 for (j = 0; j < 8; j++) { 579 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 580 crc <<= 1; 581 c >>= 1; 582 if (carry) 583 crc = (crc ^ 0x04c11db6) | carry; 584 } 585 } 586 587 /* return the filter bit position */ 588 return((crc >> 26) & 0x0000003F); 589} 590 591/* 592 * Program the 64-bit multicast hash filter. 593 */ 594static void 595vr_setmulti(sc) 596 struct vr_softc *sc; 597{ 598 struct ifnet *ifp; 599 int h = 0; 600 u_int32_t hashes[2] = { 0, 0 }; 601 struct ifmultiaddr *ifma; 602 u_int8_t rxfilt; 603 int mcnt = 0; 604 605 ifp = &sc->arpcom.ac_if; 606 607 rxfilt = CSR_READ_1(sc, VR_RXCFG); 608 609 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 610 rxfilt |= VR_RXCFG_RX_MULTI; 611 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 612 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 613 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 614 return; 615 } 616 617 /* first, zot all the existing hash bits */ 618 CSR_WRITE_4(sc, VR_MAR0, 0); 619 CSR_WRITE_4(sc, VR_MAR1, 0); 620 621 /* now program new ones */ 622 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 623 if (ifma->ifma_addr->sa_family != AF_LINK) 624 continue; 625 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 626 if (h < 32) 627 hashes[0] |= (1 << h); 628 else 629 hashes[1] |= (1 << (h - 32)); 630 mcnt++; 631 } 632 633 if (mcnt) 634 rxfilt |= VR_RXCFG_RX_MULTI; 635 else 636 rxfilt &= ~VR_RXCFG_RX_MULTI; 637 638 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 639 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 640 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 641 642 return; 643} 644 645/* 646 * In order to fiddle with the 647 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 648 * first have to put the transmit and/or receive logic in the idle state. 649 */ 650static void 651vr_setcfg(sc, media) 652 struct vr_softc *sc; 653 int media; 654{ 655 int restart = 0; 656 657 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 658 restart = 1; 659 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 660 } 661 662 if ((media & IFM_GMASK) == IFM_FDX) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 664 else 665 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 667 if (restart) 668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 669 670 return; 671} 672 673static void 674vr_reset(sc) 675 struct vr_softc *sc; 676{ 677 register int i; 678 679 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 680 681 for (i = 0; i < VR_TIMEOUT; i++) { 682 DELAY(10); 683 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 684 break; 685 } 686 if (i == VR_TIMEOUT) { 687 if (sc->vr_revid < REV_ID_VT3065_A) 688 printf("vr%d: reset never completed!\n", sc->vr_unit); 689 else { 690 /* Use newer force reset command */ 691 printf("vr%d: Using force reset command.\n", sc->vr_unit); 692 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 693 } 694 } 695 696 /* Wait a little while for the chip to get its brains in order. */ 697 DELAY(1000); 698 699 return; 700} 701 702/* 703 * Probe for a VIA Rhine chip. Check the PCI vendor and device 704 * IDs against our list and return a device name if we find a match. 705 */ 706static int 707vr_probe(dev) 708 device_t dev; 709{ 710 struct vr_type *t; 711 712 t = vr_devs; 713 714 while(t->vr_name != NULL) { 715 if ((pci_get_vendor(dev) == t->vr_vid) && 716 (pci_get_device(dev) == t->vr_did)) { 717 device_set_desc(dev, t->vr_name); 718 return(0); 719 } 720 t++; 721 } 722 723 return(ENXIO); 724} 725 726/* 727 * Attach the interface. Allocate softc structures, do ifmedia 728 * setup and ethernet/BPF attach. 729 */ 730static int 731vr_attach(dev) 732 device_t dev; 733{ 734 int i; 735 u_char eaddr[ETHER_ADDR_LEN]; 736 u_int32_t command; 737 struct vr_softc *sc; 738 struct ifnet *ifp; 739 int unit, error = 0, rid; 740 741 sc = device_get_softc(dev); 742 unit = device_get_unit(dev); 743 744 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 745 MTX_DEF | MTX_RECURSE); 746 747 /* 748 * Handle power management nonsense. 749 */ 750 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 751 u_int32_t iobase, membase, irq; 752 753 /* Save important PCI config data. */ 754 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 755 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 756 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 757 758 /* Reset the power state. */ 759 printf("vr%d: chip is in D%d power mode " 760 "-- setting to D0\n", unit, 761 pci_get_powerstate(dev)); 762 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 763 764 /* Restore PCI config data. */ 765 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 766 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 767 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 768 } 769 770 /* 771 * Map control/status registers. 772 */ 773 pci_enable_busmaster(dev); 774 pci_enable_io(dev, SYS_RES_IOPORT); 775 pci_enable_io(dev, SYS_RES_MEMORY); 776 command = pci_read_config(dev, PCIR_COMMAND, 4); 777 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 778 779#ifdef VR_USEIOSPACE 780 if (!(command & PCIM_CMD_PORTEN)) { 781 printf("vr%d: failed to enable I/O ports!\n", unit); 782 error = ENXIO; 783 goto fail; 784 } 785#else 786 if (!(command & PCIM_CMD_MEMEN)) { 787 printf("vr%d: failed to enable memory mapping!\n", unit); 788 error = ENXIO; 789 goto fail; 790 } 791#endif 792 793 rid = VR_RID; 794 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 795 0, ~0, 1, RF_ACTIVE); 796 797 if (sc->vr_res == NULL) { 798 printf("vr%d: couldn't map ports/memory\n", unit); 799 error = ENXIO; 800 goto fail; 801 } 802 803 sc->vr_btag = rman_get_bustag(sc->vr_res); 804 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 805 806 /* Allocate interrupt */ 807 rid = 0; 808 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 809 RF_SHAREABLE | RF_ACTIVE); 810 811 if (sc->vr_irq == NULL) { 812 printf("vr%d: couldn't map interrupt\n", unit); 813 error = ENXIO; 814 goto fail; 815 } 816 817 /* 818 * Windows may put the chip in suspend mode when it 819 * shuts down. Be sure to kick it in the head to wake it 820 * up again. 821 */ 822 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 823 824 /* Reset the adapter. */ 825 vr_reset(sc); 826 827 /* 828 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 829 * initialization and disable AUTOPOLL. 830 */ 831 pci_write_config(dev, VR_PCI_MODE, 832 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 833 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 834 835 /* 836 * Get station address. The way the Rhine chips work, 837 * you're not allowed to directly access the EEPROM once 838 * they've been programmed a special way. Consequently, 839 * we need to read the node address from the PAR0 and PAR1 840 * registers. 841 */ 842 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 843 DELAY(200); 844 for (i = 0; i < ETHER_ADDR_LEN; i++) 845 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 846 847 /* 848 * A Rhine chip was detected. Inform the world. 849 */ 850 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 851 852 sc->vr_unit = unit; 853 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 854 855 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 856 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 857 858 if (sc->vr_ldata == NULL) { 859 printf("vr%d: no memory for list buffers!\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863 864 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 865 866 ifp = &sc->arpcom.ac_if; 867 ifp->if_softc = sc; 868 ifp->if_unit = unit; 869 ifp->if_name = "vr"; 870 ifp->if_mtu = ETHERMTU; 871 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 872 ifp->if_ioctl = vr_ioctl; 873 ifp->if_output = ether_output; 874 ifp->if_start = vr_start; 875 ifp->if_watchdog = vr_watchdog; 876 ifp->if_init = vr_init; 877 ifp->if_baudrate = 10000000; 878 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 879 880 /* 881 * Do MII setup. 882 */ 883 if (mii_phy_probe(dev, &sc->vr_miibus, 884 vr_ifmedia_upd, vr_ifmedia_sts)) { 885 printf("vr%d: MII without any phy!\n", sc->vr_unit); 886 error = ENXIO; 887 goto fail; 888 } 889 890 callout_handle_init(&sc->vr_stat_ch); 891 892 /* 893 * Call MI attach routine. 894 */ 895 ether_ifattach(ifp, eaddr); 896 897 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 898 vr_intr, sc, &sc->vr_intrhand); 899 900 if (error) { 901 printf("vr%d: couldn't set up irq\n", unit); 902 goto fail; 903 } 904 905fail: 906 if (error) 907 vr_detach(dev); 908 909 return(error); 910} 911 912static int 913vr_detach(dev) 914 device_t dev; 915{ 916 struct vr_softc *sc; 917 struct ifnet *ifp; 918 919 sc = device_get_softc(dev); 920 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 921 VR_LOCK(sc); 922 ifp = &sc->arpcom.ac_if; 923 924 if (device_is_alive(dev)) { 925 if (bus_child_present(dev)) 926 vr_stop(sc); 927 ether_ifdetach(ifp); 928 device_delete_child(dev, sc->vr_miibus); 929 bus_generic_detach(dev); 930 } 931 932 if (sc->vr_intrhand) 933 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 934 if (sc->vr_irq) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 936 if (sc->vr_res) 937 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 938 939 if (sc->vr_ldata) 940 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 941 942 VR_UNLOCK(sc); 943 mtx_destroy(&sc->vr_mtx); 944 945 return(0); 946} 947 948/* 949 * Initialize the transmit descriptors. 950 */ 951static int 952vr_list_tx_init(sc) 953 struct vr_softc *sc; 954{ 955 struct vr_chain_data *cd; 956 struct vr_list_data *ld; 957 int i; 958 959 cd = &sc->vr_cdata; 960 ld = sc->vr_ldata; 961 for (i = 0; i < VR_TX_LIST_CNT; i++) { 962 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 963 if (i == (VR_TX_LIST_CNT - 1)) 964 cd->vr_tx_chain[i].vr_nextdesc = 965 &cd->vr_tx_chain[0]; 966 else 967 cd->vr_tx_chain[i].vr_nextdesc = 968 &cd->vr_tx_chain[i + 1]; 969 } 970 971 cd->vr_tx_free = &cd->vr_tx_chain[0]; 972 cd->vr_tx_tail = cd->vr_tx_head = NULL; 973 974 return(0); 975} 976 977 978/* 979 * Initialize the RX descriptors and allocate mbufs for them. Note that 980 * we arrange the descriptors in a closed ring, so that the last descriptor 981 * points back to the first. 982 */ 983static int 984vr_list_rx_init(sc) 985 struct vr_softc *sc; 986{ 987 struct vr_chain_data *cd; 988 struct vr_list_data *ld; 989 int i; 990 991 cd = &sc->vr_cdata; 992 ld = sc->vr_ldata; 993 994 for (i = 0; i < VR_RX_LIST_CNT; i++) { 995 cd->vr_rx_chain[i].vr_ptr = 996 (struct vr_desc *)&ld->vr_rx_list[i]; 997 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 998 return(ENOBUFS); 999 if (i == (VR_RX_LIST_CNT - 1)) { 1000 cd->vr_rx_chain[i].vr_nextdesc = 1001 &cd->vr_rx_chain[0]; 1002 ld->vr_rx_list[i].vr_next = 1003 vtophys(&ld->vr_rx_list[0]); 1004 } else { 1005 cd->vr_rx_chain[i].vr_nextdesc = 1006 &cd->vr_rx_chain[i + 1]; 1007 ld->vr_rx_list[i].vr_next = 1008 vtophys(&ld->vr_rx_list[i + 1]); 1009 } 1010 } 1011 1012 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1013 1014 return(0); 1015} 1016 1017/* 1018 * Initialize an RX descriptor and attach an MBUF cluster. 1019 * Note: the length fields are only 11 bits wide, which means the 1020 * largest size we can specify is 2047. This is important because 1021 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1022 * overflow the field and make a mess. 1023 */ 1024static int 1025vr_newbuf(sc, c, m) 1026 struct vr_softc *sc; 1027 struct vr_chain_onefrag *c; 1028 struct mbuf *m; 1029{ 1030 struct mbuf *m_new = NULL; 1031 1032 if (m == NULL) { 1033 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1034 if (m_new == NULL) 1035 return(ENOBUFS); 1036 1037 MCLGET(m_new, M_DONTWAIT); 1038 if (!(m_new->m_flags & M_EXT)) { 1039 m_freem(m_new); 1040 return(ENOBUFS); 1041 } 1042 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1043 } else { 1044 m_new = m; 1045 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1046 m_new->m_data = m_new->m_ext.ext_buf; 1047 } 1048 1049 m_adj(m_new, sizeof(u_int64_t)); 1050 1051 c->vr_mbuf = m_new; 1052 c->vr_ptr->vr_status = VR_RXSTAT; 1053 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1054 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1055 1056 return(0); 1057} 1058 1059/* 1060 * A frame has been uploaded: pass the resulting mbuf chain up to 1061 * the higher level protocols. 1062 */ 1063static void 1064vr_rxeof(sc) 1065 struct vr_softc *sc; 1066{ 1067 struct mbuf *m; 1068 struct ifnet *ifp; 1069 struct vr_chain_onefrag *cur_rx; 1070 int total_len = 0; 1071 u_int32_t rxstat; 1072 1073 ifp = &sc->arpcom.ac_if; 1074 1075 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1076 VR_RXSTAT_OWN)) { 1077 struct mbuf *m0 = NULL; 1078 1079 cur_rx = sc->vr_cdata.vr_rx_head; 1080 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1081 m = cur_rx->vr_mbuf; 1082 1083 /* 1084 * If an error occurs, update stats, clear the 1085 * status word and leave the mbuf cluster in place: 1086 * it should simply get re-used next time this descriptor 1087 * comes up in the ring. 1088 */ 1089 if (rxstat & VR_RXSTAT_RXERR) { 1090 ifp->if_ierrors++; 1091 printf("vr%d: rx error (%02x):", 1092 sc->vr_unit, rxstat & 0x000000ff); 1093 if (rxstat & VR_RXSTAT_CRCERR) 1094 printf(" crc error"); 1095 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1096 printf(" frame alignment error\n"); 1097 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1098 printf(" FIFO overflow"); 1099 if (rxstat & VR_RXSTAT_GIANT) 1100 printf(" received giant packet"); 1101 if (rxstat & VR_RXSTAT_RUNT) 1102 printf(" received runt packet"); 1103 if (rxstat & VR_RXSTAT_BUSERR) 1104 printf(" system bus error"); 1105 if (rxstat & VR_RXSTAT_BUFFERR) 1106 printf("rx buffer error"); 1107 printf("\n"); 1108 vr_newbuf(sc, cur_rx, m); 1109 continue; 1110 } 1111 1112 /* No errors; receive the packet. */ 1113 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1114 1115 /* 1116 * XXX The VIA Rhine chip includes the CRC with every 1117 * received frame, and there's no way to turn this 1118 * behavior off (at least, I can't find anything in 1119 * the manual that explains how to do it) so we have 1120 * to trim off the CRC manually. 1121 */ 1122 total_len -= ETHER_CRC_LEN; 1123 1124 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1125 NULL); 1126 vr_newbuf(sc, cur_rx, m); 1127 if (m0 == NULL) { 1128 ifp->if_ierrors++; 1129 continue; 1130 } 1131 m = m0; 1132 1133 ifp->if_ipackets++; 1134 (*ifp->if_input)(ifp, m); 1135 } 1136 1137 return; 1138} 1139 1140static void 1141vr_rxeoc(sc) 1142 struct vr_softc *sc; 1143{ 1144 struct ifnet *ifp; 1145 int i; 1146 1147 ifp = &sc->arpcom.ac_if; 1148 1149 ifp->if_ierrors++; 1150 1151 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1152 DELAY(10000); 1153 1154 for (i = 0x400; 1155 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1156 i--) 1157 ; /* Wait for receiver to stop */ 1158 1159 if (!i) { 1160 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1161 sc->vr_flags |= VR_F_RESTART; 1162 return; 1163 } 1164 1165 vr_rxeof(sc); 1166 1167 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1168 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1169 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1170 1171 return; 1172} 1173 1174/* 1175 * A frame was downloaded to the chip. It's safe for us to clean up 1176 * the list buffers. 1177 */ 1178 1179static void 1180vr_txeof(sc) 1181 struct vr_softc *sc; 1182{ 1183 struct vr_chain *cur_tx; 1184 struct ifnet *ifp; 1185 1186 ifp = &sc->arpcom.ac_if; 1187 1188 /* Reset the timeout timer; if_txeoc will clear it. */ 1189 ifp->if_timer = 5; 1190 1191 /* Sanity check. */ 1192 if (sc->vr_cdata.vr_tx_head == NULL) 1193 return; 1194 1195 /* 1196 * Go through our tx list and free mbufs for those 1197 * frames that have been transmitted. 1198 */ 1199 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1200 u_int32_t txstat; 1201 int i; 1202 1203 cur_tx = sc->vr_cdata.vr_tx_head; 1204 txstat = cur_tx->vr_ptr->vr_status; 1205 1206 if ((txstat & VR_TXSTAT_ABRT) || 1207 (txstat & VR_TXSTAT_UDF)) { 1208 for (i = 0x400; 1209 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1210 i--) 1211 ; /* Wait for chip to shutdown */ 1212 if (!i) { 1213 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1214 sc->vr_flags |= VR_F_RESTART; 1215 break; 1216 } 1217 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1218 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1219 break; 1220 } 1221 1222 if (txstat & VR_TXSTAT_OWN) 1223 break; 1224 1225 if (txstat & VR_TXSTAT_ERRSUM) { 1226 ifp->if_oerrors++; 1227 if (txstat & VR_TXSTAT_DEFER) 1228 ifp->if_collisions++; 1229 if (txstat & VR_TXSTAT_LATECOLL) 1230 ifp->if_collisions++; 1231 } 1232 1233 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1234 1235 ifp->if_opackets++; 1236 if (cur_tx->vr_mbuf != NULL) { 1237 m_freem(cur_tx->vr_mbuf); 1238 cur_tx->vr_mbuf = NULL; 1239 } 1240 1241 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1242 sc->vr_cdata.vr_tx_head = NULL; 1243 sc->vr_cdata.vr_tx_tail = NULL; 1244 break; 1245 } 1246 1247 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1248 } 1249 1250 return; 1251} 1252 1253/* 1254 * TX 'end of channel' interrupt handler. 1255 */ 1256static void 1257vr_txeoc(sc) 1258 struct vr_softc *sc; 1259{ 1260 struct ifnet *ifp; 1261 1262 ifp = &sc->arpcom.ac_if; 1263 1264 if (sc->vr_cdata.vr_tx_head == NULL) { 1265 ifp->if_flags &= ~IFF_OACTIVE; 1266 sc->vr_cdata.vr_tx_tail = NULL; 1267 ifp->if_timer = 0; 1268 } 1269 1270 return; 1271} 1272 1273static void 1274vr_tick(xsc) 1275 void *xsc; 1276{ 1277 struct vr_softc *sc; 1278 struct mii_data *mii; 1279 1280 sc = xsc; 1281 VR_LOCK(sc); 1282 if (sc->vr_flags & VR_F_RESTART) { 1283 printf("vr%d: restarting\n", sc->vr_unit); 1284 vr_stop(sc); 1285 vr_reset(sc); 1286 vr_init(sc); 1287 sc->vr_flags &= ~VR_F_RESTART; 1288 } 1289 1290 mii = device_get_softc(sc->vr_miibus); 1291 mii_tick(mii); 1292 1293 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1294 1295 VR_UNLOCK(sc); 1296 1297 return; 1298} 1299 1300static void 1301vr_intr(arg) 1302 void *arg; 1303{ 1304 struct vr_softc *sc; 1305 struct ifnet *ifp; 1306 u_int16_t status; 1307 1308 sc = arg; 1309 VR_LOCK(sc); 1310 ifp = &sc->arpcom.ac_if; 1311 1312 /* Supress unwanted interrupts. */ 1313 if (!(ifp->if_flags & IFF_UP)) { 1314 vr_stop(sc); 1315 VR_UNLOCK(sc); 1316 return; 1317 } 1318 1319 /* Disable interrupts. */ 1320 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1321 1322 for (;;) { 1323 1324 status = CSR_READ_2(sc, VR_ISR); 1325 if (status) 1326 CSR_WRITE_2(sc, VR_ISR, status); 1327 1328 if ((status & VR_INTRS) == 0) 1329 break; 1330 1331 if (status & VR_ISR_RX_OK) 1332 vr_rxeof(sc); 1333 1334 if (status & VR_ISR_RX_DROPPED) { 1335 printf("vr%d: rx packet lost\n", sc->vr_unit); 1336 ifp->if_ierrors++; 1337 } 1338 1339 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1340 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1341 printf("vr%d: receive error (%04x)", 1342 sc->vr_unit, status); 1343 if (status & VR_ISR_RX_NOBUF) 1344 printf(" no buffers"); 1345 if (status & VR_ISR_RX_OFLOW) 1346 printf(" overflow"); 1347 if (status & VR_ISR_RX_DROPPED) 1348 printf(" packet lost"); 1349 printf("\n"); 1350 vr_rxeoc(sc); 1351 } 1352 1353 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1354 vr_reset(sc); 1355 vr_init(sc); 1356 break; 1357 } 1358 1359 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1360 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1361 vr_txeof(sc); 1362 if ((status & VR_ISR_UDFI) || 1363 (status & VR_ISR_TX_ABRT2) || 1364 (status & VR_ISR_TX_ABRT)) { 1365 ifp->if_oerrors++; 1366 if (sc->vr_cdata.vr_tx_head != NULL) { 1367 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1368 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1369 } 1370 } else 1371 vr_txeoc(sc); 1372 } 1373 1374 } 1375 1376 /* Re-enable interrupts. */ 1377 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1378 1379 if (ifp->if_snd.ifq_head != NULL) { 1380 vr_start(ifp); 1381 } 1382 1383 VR_UNLOCK(sc); 1384 1385 return; 1386} 1387 1388/* 1389 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1390 * pointers to the fragment pointers. 1391 */ 1392static int 1393vr_encap(sc, c, m_head) 1394 struct vr_softc *sc; 1395 struct vr_chain *c; 1396 struct mbuf *m_head; 1397{ 1398 int frag = 0; 1399 struct vr_desc *f = NULL; 1400 int total_len; 1401 struct mbuf *m; 1402 1403 m = m_head; 1404 total_len = 0; 1405 1406 /* 1407 * The VIA Rhine wants packet buffers to be longword 1408 * aligned, but very often our mbufs aren't. Rather than 1409 * waste time trying to decide when to copy and when not 1410 * to copy, just do it all the time. 1411 */ 1412 if (m != NULL) { 1413 struct mbuf *m_new = NULL; 1414 1415 m_new = m_defrag(m_head, M_DONTWAIT); 1416 if (m_new == NULL) { 1417 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1418 return(1); 1419 } 1420 1421 m_head = m_new; 1422 /* 1423 * The Rhine chip doesn't auto-pad, so we have to make 1424 * sure to pad short frames out to the minimum frame length 1425 * ourselves. 1426 */ 1427 if (m_head->m_len < VR_MIN_FRAMELEN) { 1428 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1429 m_new->m_len = m_new->m_pkthdr.len; 1430 } 1431 f = c->vr_ptr; 1432 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1433 f->vr_ctl = total_len = m_new->m_len; 1434 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1435 f->vr_status = 0; 1436 frag = 1; 1437 } 1438 1439 c->vr_mbuf = m_head; 1440 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1441 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1442 1443 return(0); 1444} 1445 1446/* 1447 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1448 * to the mbuf data regions directly in the transmit lists. We also save a 1449 * copy of the pointers since the transmit list fragment pointers are 1450 * physical addresses. 1451 */ 1452 1453static void 1454vr_start(ifp) 1455 struct ifnet *ifp; 1456{ 1457 struct vr_softc *sc; 1458 struct mbuf *m_head = NULL; 1459 struct vr_chain *cur_tx = NULL, *start_tx; 1460 1461 sc = ifp->if_softc; 1462 1463 VR_LOCK(sc); 1464 if (ifp->if_flags & IFF_OACTIVE) { 1465 VR_UNLOCK(sc); 1466 return; 1467 } 1468 1469 /* 1470 * Check for an available queue slot. If there are none, 1471 * punt. 1472 */ 1473 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1474 ifp->if_flags |= IFF_OACTIVE; 1475 return; 1476 } 1477 1478 start_tx = sc->vr_cdata.vr_tx_free; 1479 1480 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1481 IF_DEQUEUE(&ifp->if_snd, m_head); 1482 if (m_head == NULL) 1483 break; 1484 1485 /* Pick a descriptor off the free list. */ 1486 cur_tx = sc->vr_cdata.vr_tx_free; 1487 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1488 1489 /* Pack the data into the descriptor. */ 1490 if (vr_encap(sc, cur_tx, m_head)) { 1491 IF_PREPEND(&ifp->if_snd, m_head); 1492 ifp->if_flags |= IFF_OACTIVE; 1493 cur_tx = NULL; 1494 break; 1495 } 1496 1497 if (cur_tx != start_tx) 1498 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1499 1500 /* 1501 * If there's a BPF listener, bounce a copy of this frame 1502 * to him. 1503 */ 1504 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1505 1506 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1507 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1508 } 1509 1510 /* 1511 * If there are no frames queued, bail. 1512 */ 1513 if (cur_tx == NULL) { 1514 VR_UNLOCK(sc); 1515 return; 1516 } 1517 1518 sc->vr_cdata.vr_tx_tail = cur_tx; 1519 1520 if (sc->vr_cdata.vr_tx_head == NULL) 1521 sc->vr_cdata.vr_tx_head = start_tx; 1522 1523 /* 1524 * Set a timeout in case the chip goes out to lunch. 1525 */ 1526 ifp->if_timer = 5; 1527 VR_UNLOCK(sc); 1528 1529 return; 1530} 1531 1532static void 1533vr_init(xsc) 1534 void *xsc; 1535{ 1536 struct vr_softc *sc = xsc; 1537 struct ifnet *ifp = &sc->arpcom.ac_if; 1538 struct mii_data *mii; 1539 int i; 1540 1541 VR_LOCK(sc); 1542 1543 mii = device_get_softc(sc->vr_miibus); 1544 1545 /* 1546 * Cancel pending I/O and free all RX/TX buffers. 1547 */ 1548 vr_stop(sc); 1549 vr_reset(sc); 1550 1551 /* 1552 * Set our station address. 1553 */ 1554 for (i = 0; i < ETHER_ADDR_LEN; i++) 1555 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1556 1557 /* Set DMA size */ 1558 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1559 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1560 1561 /* 1562 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1563 * so we must set both. 1564 */ 1565 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1566 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1567 1568 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1569 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1570 1571 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1572 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1573 1574 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1575 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1576 1577 /* Init circular RX list. */ 1578 if (vr_list_rx_init(sc) == ENOBUFS) { 1579 printf("vr%d: initialization failed: no " 1580 "memory for rx buffers\n", sc->vr_unit); 1581 vr_stop(sc); 1582 VR_UNLOCK(sc); 1583 return; 1584 } 1585 1586 /* 1587 * Init tx descriptors. 1588 */ 1589 vr_list_tx_init(sc); 1590 1591 /* If we want promiscuous mode, set the allframes bit. */ 1592 if (ifp->if_flags & IFF_PROMISC) 1593 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1594 else 1595 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1596 1597 /* Set capture broadcast bit to capture broadcast frames. */ 1598 if (ifp->if_flags & IFF_BROADCAST) 1599 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1600 else 1601 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1602 1603 /* 1604 * Program the multicast filter, if necessary. 1605 */ 1606 vr_setmulti(sc); 1607 1608 /* 1609 * Load the address of the RX list. 1610 */ 1611 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1612 1613 /* Enable receiver and transmitter. */ 1614 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1615 VR_CMD_TX_ON|VR_CMD_RX_ON| 1616 VR_CMD_RX_GO); 1617 1618 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1619 1620 /* 1621 * Enable interrupts. 1622 */ 1623 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1624 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1625 1626 mii_mediachg(mii); 1627 1628 ifp->if_flags |= IFF_RUNNING; 1629 ifp->if_flags &= ~IFF_OACTIVE; 1630 1631 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1632 1633 VR_UNLOCK(sc); 1634 1635 return; 1636} 1637 1638/* 1639 * Set media options. 1640 */ 1641static int 1642vr_ifmedia_upd(ifp) 1643 struct ifnet *ifp; 1644{ 1645 struct vr_softc *sc; 1646 1647 sc = ifp->if_softc; 1648 1649 if (ifp->if_flags & IFF_UP) 1650 vr_init(sc); 1651 1652 return(0); 1653} 1654 1655/* 1656 * Report current media status. 1657 */ 1658static void 1659vr_ifmedia_sts(ifp, ifmr) 1660 struct ifnet *ifp; 1661 struct ifmediareq *ifmr; 1662{ 1663 struct vr_softc *sc; 1664 struct mii_data *mii; 1665 1666 sc = ifp->if_softc; 1667 mii = device_get_softc(sc->vr_miibus); 1668 mii_pollstat(mii); 1669 ifmr->ifm_active = mii->mii_media_active; 1670 ifmr->ifm_status = mii->mii_media_status; 1671 1672 return; 1673} 1674 1675static int 1676vr_ioctl(ifp, command, data) 1677 struct ifnet *ifp; 1678 u_long command; 1679 caddr_t data; 1680{ 1681 struct vr_softc *sc = ifp->if_softc; 1682 struct ifreq *ifr = (struct ifreq *) data; 1683 struct mii_data *mii; 1684 int error = 0; 1685 1686 VR_LOCK(sc); 1687 1688 switch(command) { 1689 case SIOCSIFFLAGS: 1690 if (ifp->if_flags & IFF_UP) { 1691 vr_init(sc); 1692 } else { 1693 if (ifp->if_flags & IFF_RUNNING) 1694 vr_stop(sc); 1695 } 1696 error = 0; 1697 break; 1698 case SIOCADDMULTI: 1699 case SIOCDELMULTI: 1700 vr_setmulti(sc); 1701 error = 0; 1702 break; 1703 case SIOCGIFMEDIA: 1704 case SIOCSIFMEDIA: 1705 mii = device_get_softc(sc->vr_miibus); 1706 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1707 break; 1708 default: 1709 error = ether_ioctl(ifp, command, data); 1710 break; 1711 } 1712 1713 VR_UNLOCK(sc); 1714 1715 return(error); 1716} 1717 1718static void 1719vr_watchdog(ifp) 1720 struct ifnet *ifp; 1721{ 1722 struct vr_softc *sc; 1723 1724 sc = ifp->if_softc; 1725 1726 VR_LOCK(sc); 1727 ifp->if_oerrors++; 1728 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1729 1730 vr_stop(sc); 1731 vr_reset(sc); 1732 vr_init(sc); 1733 1734 if (ifp->if_snd.ifq_head != NULL) 1735 vr_start(ifp); 1736 1737 VR_UNLOCK(sc); 1738 1739 return; 1740} 1741 1742/* 1743 * Stop the adapter and free any mbufs allocated to the 1744 * RX and TX lists. 1745 */ 1746static void 1747vr_stop(sc) 1748 struct vr_softc *sc; 1749{ 1750 register int i; 1751 struct ifnet *ifp; 1752 1753 VR_LOCK(sc); 1754 1755 ifp = &sc->arpcom.ac_if; 1756 ifp->if_timer = 0; 1757 1758 untimeout(vr_tick, sc, sc->vr_stat_ch); 1759 1760 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1761 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1762 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1763 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1764 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1765 1766 /* 1767 * Free data in the RX lists. 1768 */ 1769 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1770 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1771 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1772 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1773 } 1774 } 1775 bzero((char *)&sc->vr_ldata->vr_rx_list, 1776 sizeof(sc->vr_ldata->vr_rx_list)); 1777 1778 /* 1779 * Free the TX list buffers. 1780 */ 1781 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1782 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1783 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1784 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1785 } 1786 } 1787 1788 bzero((char *)&sc->vr_ldata->vr_tx_list, 1789 sizeof(sc->vr_ldata->vr_tx_list)); 1790 1791 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1792 VR_UNLOCK(sc); 1793 1794 return; 1795} 1796 1797/* 1798 * Stop all chip I/O so that the kernel's probe routines don't 1799 * get confused by errant DMAs when rebooting. 1800 */ 1801static void 1802vr_shutdown(dev) 1803 device_t dev; 1804{ 1805 struct vr_softc *sc; 1806 1807 sc = device_get_softc(dev); 1808 1809 vr_stop(sc); 1810 1811 return; 1812} 1813