if_vr.c revision 87846
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/vr/if_vr.c 87846 2001-12-14 05:56:35Z luigi $ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3741502Swpaul * 3841502Swpaul * Supports various network adapters based on the VIA Rhine 3941502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4041502Swpaul * Datasheets are available at http://www.via.com.tw. 4141502Swpaul * 4241502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4341502Swpaul * Electrical Engineering Department 4441502Swpaul * Columbia University, New York City 4541502Swpaul */ 4641502Swpaul 4741502Swpaul/* 4841502Swpaul * The VIA Rhine controllers are similar in some respects to the 4941502Swpaul * the DEC tulip chips, except less complicated. The controller 5041502Swpaul * uses an MII bus and an external physical layer interface. The 5141502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5241502Swpaul * multicast filter. Transmit and receive descriptors are similar 5341502Swpaul * to the tulip. 5441502Swpaul * 5541502Swpaul * The Rhine has a serious flaw in its transmit DMA mechanism: 5641502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5741502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5841502Swpaul * at longword boundaries, so we have to do a buffer copy before 5941502Swpaul * transmission. 6041502Swpaul */ 6141502Swpaul 6241502Swpaul#include <sys/param.h> 6341502Swpaul#include <sys/systm.h> 6441502Swpaul#include <sys/sockio.h> 6541502Swpaul#include <sys/mbuf.h> 6641502Swpaul#include <sys/malloc.h> 6741502Swpaul#include <sys/kernel.h> 6841502Swpaul#include <sys/socket.h> 6941502Swpaul 7041502Swpaul#include <net/if.h> 7141502Swpaul#include <net/if_arp.h> 7241502Swpaul#include <net/ethernet.h> 7341502Swpaul#include <net/if_dl.h> 7441502Swpaul#include <net/if_media.h> 7541502Swpaul 7641502Swpaul#include <net/bpf.h> 7741502Swpaul 7841502Swpaul#include <vm/vm.h> /* for vtophys */ 7941502Swpaul#include <vm/pmap.h> /* for vtophys */ 8041502Swpaul#include <machine/bus_pio.h> 8141502Swpaul#include <machine/bus_memio.h> 8241502Swpaul#include <machine/bus.h> 8349610Swpaul#include <machine/resource.h> 8449610Swpaul#include <sys/bus.h> 8549610Swpaul#include <sys/rman.h> 8641502Swpaul 8751432Swpaul#include <dev/mii/mii.h> 8851432Swpaul#include <dev/mii/miivar.h> 8951432Swpaul 9041502Swpaul#include <pci/pcireg.h> 9141502Swpaul#include <pci/pcivar.h> 9241502Swpaul 9341502Swpaul#define VR_USEIOSPACE 9441502Swpaul 9541502Swpaul#include <pci/if_vrreg.h> 9641502Swpaul 9759758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 9859758Speter 9951432Swpaul/* "controller miibus0" required. See GENERIC if you get errors here. */ 10051432Swpaul#include "miibus_if.h" 10151432Swpaul 10241502Swpaul#ifndef lint 10341591Sarchiestatic const char rcsid[] = 10450477Speter "$FreeBSD: head/sys/dev/vr/if_vr.c 87846 2001-12-14 05:56:35Z luigi $"; 10541502Swpaul#endif 10641502Swpaul 10741502Swpaul/* 10841502Swpaul * Various supported device vendors/types and their names. 10941502Swpaul */ 11041502Swpaulstatic struct vr_type vr_devs[] = { 11141502Swpaul { VIA_VENDORID, VIA_DEVICEID_RHINE, 11241502Swpaul "VIA VT3043 Rhine I 10/100BaseTX" }, 11341502Swpaul { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 11441502Swpaul "VIA VT86C100A Rhine II 10/100BaseTX" }, 11562653Swpaul { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 11662653Swpaul "VIA VT6102 Rhine II 10/100BaseTX" }, 11744238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 11844238Swpaul "Delta Electronics Rhine II 10/100BaseTX" }, 11944238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 12044238Swpaul "Addtron Technology Rhine II 10/100BaseTX" }, 12141502Swpaul { 0, 0, NULL } 12241502Swpaul}; 12341502Swpaul 12449610Swpaulstatic int vr_probe __P((device_t)); 12549610Swpaulstatic int vr_attach __P((device_t)); 12649610Swpaulstatic int vr_detach __P((device_t)); 12741502Swpaul 12841502Swpaulstatic int vr_newbuf __P((struct vr_softc *, 12949610Swpaul struct vr_chain_onefrag *, 13049610Swpaul struct mbuf *)); 13141502Swpaulstatic int vr_encap __P((struct vr_softc *, struct vr_chain *, 13241502Swpaul struct mbuf * )); 13341502Swpaul 13441502Swpaulstatic void vr_rxeof __P((struct vr_softc *)); 13541502Swpaulstatic void vr_rxeoc __P((struct vr_softc *)); 13641502Swpaulstatic void vr_txeof __P((struct vr_softc *)); 13741502Swpaulstatic void vr_txeoc __P((struct vr_softc *)); 13851432Swpaulstatic void vr_tick __P((void *)); 13941502Swpaulstatic void vr_intr __P((void *)); 14041502Swpaulstatic void vr_start __P((struct ifnet *)); 14141502Swpaulstatic int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 14241502Swpaulstatic void vr_init __P((void *)); 14341502Swpaulstatic void vr_stop __P((struct vr_softc *)); 14441502Swpaulstatic void vr_watchdog __P((struct ifnet *)); 14549610Swpaulstatic void vr_shutdown __P((device_t)); 14641502Swpaulstatic int vr_ifmedia_upd __P((struct ifnet *)); 14741502Swpaulstatic void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 14841502Swpaul 14941502Swpaulstatic void vr_mii_sync __P((struct vr_softc *)); 15041502Swpaulstatic void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 15141502Swpaulstatic int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 15241502Swpaulstatic int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 15351432Swpaulstatic int vr_miibus_readreg __P((device_t, int, int)); 15451432Swpaulstatic int vr_miibus_writereg __P((device_t, int, int, int)); 15551432Swpaulstatic void vr_miibus_statchg __P((device_t)); 15641502Swpaul 15751432Swpaulstatic void vr_setcfg __P((struct vr_softc *, int)); 15841502Swpaulstatic u_int8_t vr_calchash __P((u_int8_t *)); 15941502Swpaulstatic void vr_setmulti __P((struct vr_softc *)); 16041502Swpaulstatic void vr_reset __P((struct vr_softc *)); 16141502Swpaulstatic int vr_list_rx_init __P((struct vr_softc *)); 16241502Swpaulstatic int vr_list_tx_init __P((struct vr_softc *)); 16341502Swpaul 16449610Swpaul#ifdef VR_USEIOSPACE 16549610Swpaul#define VR_RES SYS_RES_IOPORT 16649610Swpaul#define VR_RID VR_PCI_LOIO 16749610Swpaul#else 16849610Swpaul#define VR_RES SYS_RES_MEMORY 16949610Swpaul#define VR_RID VR_PCI_LOMEM 17049610Swpaul#endif 17149610Swpaul 17249610Swpaulstatic device_method_t vr_methods[] = { 17349610Swpaul /* Device interface */ 17449610Swpaul DEVMETHOD(device_probe, vr_probe), 17549610Swpaul DEVMETHOD(device_attach, vr_attach), 17649610Swpaul DEVMETHOD(device_detach, vr_detach), 17749610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 17851432Swpaul 17951432Swpaul /* bus interface */ 18051432Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18151432Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18251432Swpaul 18351432Swpaul /* MII interface */ 18451432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 18551432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 18651432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 18751432Swpaul 18849610Swpaul { 0, 0 } 18949610Swpaul}; 19049610Swpaul 19149610Swpaulstatic driver_t vr_driver = { 19251455Swpaul "vr", 19349610Swpaul vr_methods, 19449610Swpaul sizeof(struct vr_softc) 19549610Swpaul}; 19649610Swpaul 19749610Swpaulstatic devclass_t vr_devclass; 19849610Swpaul 19951533SwpaulDRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 20051473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 20149610Swpaul 20241502Swpaul#define VR_SETBIT(sc, reg, x) \ 20341502Swpaul CSR_WRITE_1(sc, reg, \ 20441502Swpaul CSR_READ_1(sc, reg) | x) 20541502Swpaul 20641502Swpaul#define VR_CLRBIT(sc, reg, x) \ 20741502Swpaul CSR_WRITE_1(sc, reg, \ 20841502Swpaul CSR_READ_1(sc, reg) & ~x) 20941502Swpaul 21041502Swpaul#define VR_SETBIT16(sc, reg, x) \ 21141502Swpaul CSR_WRITE_2(sc, reg, \ 21241502Swpaul CSR_READ_2(sc, reg) | x) 21341502Swpaul 21441502Swpaul#define VR_CLRBIT16(sc, reg, x) \ 21541502Swpaul CSR_WRITE_2(sc, reg, \ 21641502Swpaul CSR_READ_2(sc, reg) & ~x) 21741502Swpaul 21841502Swpaul#define VR_SETBIT32(sc, reg, x) \ 21941502Swpaul CSR_WRITE_4(sc, reg, \ 22041502Swpaul CSR_READ_4(sc, reg) | x) 22141502Swpaul 22241502Swpaul#define VR_CLRBIT32(sc, reg, x) \ 22341502Swpaul CSR_WRITE_4(sc, reg, \ 22441502Swpaul CSR_READ_4(sc, reg) & ~x) 22541502Swpaul 22641502Swpaul#define SIO_SET(x) \ 22741502Swpaul CSR_WRITE_1(sc, VR_MIICMD, \ 22841502Swpaul CSR_READ_1(sc, VR_MIICMD) | x) 22941502Swpaul 23041502Swpaul#define SIO_CLR(x) \ 23141502Swpaul CSR_WRITE_1(sc, VR_MIICMD, \ 23241502Swpaul CSR_READ_1(sc, VR_MIICMD) & ~x) 23341502Swpaul 23441502Swpaul/* 23541502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 23641502Swpaul */ 23741502Swpaulstatic void vr_mii_sync(sc) 23841502Swpaul struct vr_softc *sc; 23941502Swpaul{ 24041502Swpaul register int i; 24141502Swpaul 24241502Swpaul SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 24341502Swpaul 24441502Swpaul for (i = 0; i < 32; i++) { 24541502Swpaul SIO_SET(VR_MIICMD_CLK); 24641502Swpaul DELAY(1); 24741502Swpaul SIO_CLR(VR_MIICMD_CLK); 24841502Swpaul DELAY(1); 24941502Swpaul } 25041502Swpaul 25141502Swpaul return; 25241502Swpaul} 25341502Swpaul 25441502Swpaul/* 25541502Swpaul * Clock a series of bits through the MII. 25641502Swpaul */ 25741502Swpaulstatic void vr_mii_send(sc, bits, cnt) 25841502Swpaul struct vr_softc *sc; 25941502Swpaul u_int32_t bits; 26041502Swpaul int cnt; 26141502Swpaul{ 26241502Swpaul int i; 26341502Swpaul 26441502Swpaul SIO_CLR(VR_MIICMD_CLK); 26541502Swpaul 26641502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 26741502Swpaul if (bits & i) { 26841502Swpaul SIO_SET(VR_MIICMD_DATAIN); 26941502Swpaul } else { 27041502Swpaul SIO_CLR(VR_MIICMD_DATAIN); 27141502Swpaul } 27241502Swpaul DELAY(1); 27341502Swpaul SIO_CLR(VR_MIICMD_CLK); 27441502Swpaul DELAY(1); 27541502Swpaul SIO_SET(VR_MIICMD_CLK); 27641502Swpaul } 27741502Swpaul} 27841502Swpaul 27941502Swpaul/* 28041502Swpaul * Read an PHY register through the MII. 28141502Swpaul */ 28241502Swpaulstatic int vr_mii_readreg(sc, frame) 28341502Swpaul struct vr_softc *sc; 28441502Swpaul struct vr_mii_frame *frame; 28541502Swpaul 28641502Swpaul{ 28767087Swpaul int i, ack; 28841502Swpaul 28967087Swpaul VR_LOCK(sc); 29041502Swpaul 29141502Swpaul /* 29241502Swpaul * Set up frame for RX. 29341502Swpaul */ 29441502Swpaul frame->mii_stdelim = VR_MII_STARTDELIM; 29541502Swpaul frame->mii_opcode = VR_MII_READOP; 29641502Swpaul frame->mii_turnaround = 0; 29741502Swpaul frame->mii_data = 0; 29841502Swpaul 29941502Swpaul CSR_WRITE_1(sc, VR_MIICMD, 0); 30041502Swpaul VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 30141502Swpaul 30241502Swpaul /* 30341502Swpaul * Turn on data xmit. 30441502Swpaul */ 30541502Swpaul SIO_SET(VR_MIICMD_DIR); 30641502Swpaul 30741502Swpaul vr_mii_sync(sc); 30841502Swpaul 30941502Swpaul /* 31041502Swpaul * Send command/address info. 31141502Swpaul */ 31241502Swpaul vr_mii_send(sc, frame->mii_stdelim, 2); 31341502Swpaul vr_mii_send(sc, frame->mii_opcode, 2); 31441502Swpaul vr_mii_send(sc, frame->mii_phyaddr, 5); 31541502Swpaul vr_mii_send(sc, frame->mii_regaddr, 5); 31641502Swpaul 31741502Swpaul /* Idle bit */ 31841502Swpaul SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 31941502Swpaul DELAY(1); 32041502Swpaul SIO_SET(VR_MIICMD_CLK); 32141502Swpaul DELAY(1); 32241502Swpaul 32341502Swpaul /* Turn off xmit. */ 32441502Swpaul SIO_CLR(VR_MIICMD_DIR); 32541502Swpaul 32641502Swpaul /* Check for ack */ 32741502Swpaul SIO_CLR(VR_MIICMD_CLK); 32841502Swpaul DELAY(1); 32941502Swpaul SIO_SET(VR_MIICMD_CLK); 33041502Swpaul DELAY(1); 33141502Swpaul ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 33241502Swpaul 33341502Swpaul /* 33441502Swpaul * Now try reading data bits. If the ack failed, we still 33541502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 33641502Swpaul */ 33741502Swpaul if (ack) { 33841502Swpaul for(i = 0; i < 16; i++) { 33941502Swpaul SIO_CLR(VR_MIICMD_CLK); 34041502Swpaul DELAY(1); 34141502Swpaul SIO_SET(VR_MIICMD_CLK); 34241502Swpaul DELAY(1); 34341502Swpaul } 34441502Swpaul goto fail; 34541502Swpaul } 34641502Swpaul 34741502Swpaul for (i = 0x8000; i; i >>= 1) { 34841502Swpaul SIO_CLR(VR_MIICMD_CLK); 34941502Swpaul DELAY(1); 35041502Swpaul if (!ack) { 35141502Swpaul if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 35241502Swpaul frame->mii_data |= i; 35341502Swpaul DELAY(1); 35441502Swpaul } 35541502Swpaul SIO_SET(VR_MIICMD_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul } 35841502Swpaul 35941502Swpaulfail: 36041502Swpaul 36141502Swpaul SIO_CLR(VR_MIICMD_CLK); 36241502Swpaul DELAY(1); 36341502Swpaul SIO_SET(VR_MIICMD_CLK); 36441502Swpaul DELAY(1); 36541502Swpaul 36667087Swpaul VR_UNLOCK(sc); 36741502Swpaul 36841502Swpaul if (ack) 36941502Swpaul return(1); 37041502Swpaul return(0); 37141502Swpaul} 37241502Swpaul 37341502Swpaul/* 37441502Swpaul * Write to a PHY register through the MII. 37541502Swpaul */ 37641502Swpaulstatic int vr_mii_writereg(sc, frame) 37741502Swpaul struct vr_softc *sc; 37841502Swpaul struct vr_mii_frame *frame; 37941502Swpaul 38041502Swpaul{ 38167087Swpaul VR_LOCK(sc); 38241502Swpaul 38341502Swpaul CSR_WRITE_1(sc, VR_MIICMD, 0); 38441502Swpaul VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 38541502Swpaul 38641502Swpaul /* 38741502Swpaul * Set up frame for TX. 38841502Swpaul */ 38941502Swpaul 39041502Swpaul frame->mii_stdelim = VR_MII_STARTDELIM; 39141502Swpaul frame->mii_opcode = VR_MII_WRITEOP; 39241502Swpaul frame->mii_turnaround = VR_MII_TURNAROUND; 39341502Swpaul 39441502Swpaul /* 39541502Swpaul * Turn on data output. 39641502Swpaul */ 39741502Swpaul SIO_SET(VR_MIICMD_DIR); 39841502Swpaul 39941502Swpaul vr_mii_sync(sc); 40041502Swpaul 40141502Swpaul vr_mii_send(sc, frame->mii_stdelim, 2); 40241502Swpaul vr_mii_send(sc, frame->mii_opcode, 2); 40341502Swpaul vr_mii_send(sc, frame->mii_phyaddr, 5); 40441502Swpaul vr_mii_send(sc, frame->mii_regaddr, 5); 40541502Swpaul vr_mii_send(sc, frame->mii_turnaround, 2); 40641502Swpaul vr_mii_send(sc, frame->mii_data, 16); 40741502Swpaul 40841502Swpaul /* Idle bit. */ 40941502Swpaul SIO_SET(VR_MIICMD_CLK); 41041502Swpaul DELAY(1); 41141502Swpaul SIO_CLR(VR_MIICMD_CLK); 41241502Swpaul DELAY(1); 41341502Swpaul 41441502Swpaul /* 41541502Swpaul * Turn off xmit. 41641502Swpaul */ 41741502Swpaul SIO_CLR(VR_MIICMD_DIR); 41841502Swpaul 41967087Swpaul VR_UNLOCK(sc); 42041502Swpaul 42141502Swpaul return(0); 42241502Swpaul} 42341502Swpaul 42451432Swpaulstatic int vr_miibus_readreg(dev, phy, reg) 42551432Swpaul device_t dev; 42651432Swpaul int phy, reg; 42751432Swpaul{ 42841502Swpaul struct vr_softc *sc; 42941502Swpaul struct vr_mii_frame frame; 43041502Swpaul 43151432Swpaul sc = device_get_softc(dev); 43241502Swpaul bzero((char *)&frame, sizeof(frame)); 43341502Swpaul 43451432Swpaul frame.mii_phyaddr = phy; 43541502Swpaul frame.mii_regaddr = reg; 43641502Swpaul vr_mii_readreg(sc, &frame); 43741502Swpaul 43841502Swpaul return(frame.mii_data); 43941502Swpaul} 44041502Swpaul 44151432Swpaulstatic int vr_miibus_writereg(dev, phy, reg, data) 44251432Swpaul device_t dev; 44351432Swpaul u_int16_t phy, reg, data; 44451432Swpaul{ 44541502Swpaul struct vr_softc *sc; 44641502Swpaul struct vr_mii_frame frame; 44741502Swpaul 44851432Swpaul sc = device_get_softc(dev); 44941502Swpaul bzero((char *)&frame, sizeof(frame)); 45041502Swpaul 45151432Swpaul frame.mii_phyaddr = phy; 45241502Swpaul frame.mii_regaddr = reg; 45341502Swpaul frame.mii_data = data; 45441502Swpaul 45541502Swpaul vr_mii_writereg(sc, &frame); 45641502Swpaul 45751432Swpaul return(0); 45851432Swpaul} 45951432Swpaul 46051432Swpaulstatic void vr_miibus_statchg(dev) 46151432Swpaul device_t dev; 46251432Swpaul{ 46351432Swpaul struct vr_softc *sc; 46451432Swpaul struct mii_data *mii; 46551432Swpaul 46651432Swpaul sc = device_get_softc(dev); 46767087Swpaul VR_LOCK(sc); 46851432Swpaul mii = device_get_softc(sc->vr_miibus); 46951432Swpaul vr_setcfg(sc, mii->mii_media_active); 47067087Swpaul VR_UNLOCK(sc); 47151432Swpaul 47241502Swpaul return; 47341502Swpaul} 47441502Swpaul 47541502Swpaul/* 47641502Swpaul * Calculate CRC of a multicast group address, return the lower 6 bits. 47741502Swpaul */ 47841502Swpaulstatic u_int8_t vr_calchash(addr) 47941502Swpaul u_int8_t *addr; 48041502Swpaul{ 48141502Swpaul u_int32_t crc, carry; 48241502Swpaul int i, j; 48341502Swpaul u_int8_t c; 48441502Swpaul 48541502Swpaul /* Compute CRC for the address value. */ 48641502Swpaul crc = 0xFFFFFFFF; /* initial value */ 48741502Swpaul 48841502Swpaul for (i = 0; i < 6; i++) { 48941502Swpaul c = *(addr + i); 49041502Swpaul for (j = 0; j < 8; j++) { 49141502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 49241502Swpaul crc <<= 1; 49341502Swpaul c >>= 1; 49441502Swpaul if (carry) 49541502Swpaul crc = (crc ^ 0x04c11db6) | carry; 49641502Swpaul } 49741502Swpaul } 49841502Swpaul 49941502Swpaul /* return the filter bit position */ 50041502Swpaul return((crc >> 26) & 0x0000003F); 50141502Swpaul} 50241502Swpaul 50341502Swpaul/* 50441502Swpaul * Program the 64-bit multicast hash filter. 50541502Swpaul */ 50641502Swpaulstatic void vr_setmulti(sc) 50741502Swpaul struct vr_softc *sc; 50841502Swpaul{ 50941502Swpaul struct ifnet *ifp; 51041502Swpaul int h = 0; 51141502Swpaul u_int32_t hashes[2] = { 0, 0 }; 51241502Swpaul struct ifmultiaddr *ifma; 51341502Swpaul u_int8_t rxfilt; 51441502Swpaul int mcnt = 0; 51541502Swpaul 51641502Swpaul ifp = &sc->arpcom.ac_if; 51741502Swpaul 51841502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 51941502Swpaul 52041502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 52141502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 52241502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 52341502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 52441502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 52541502Swpaul return; 52641502Swpaul } 52741502Swpaul 52841502Swpaul /* first, zot all the existing hash bits */ 52941502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0); 53041502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0); 53141502Swpaul 53241502Swpaul /* now program new ones */ 53372084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 53441502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 53541502Swpaul continue; 53641502Swpaul h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 53741502Swpaul if (h < 32) 53841502Swpaul hashes[0] |= (1 << h); 53941502Swpaul else 54041502Swpaul hashes[1] |= (1 << (h - 32)); 54141502Swpaul mcnt++; 54241502Swpaul } 54341502Swpaul 54441502Swpaul if (mcnt) 54541502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 54641502Swpaul else 54741502Swpaul rxfilt &= ~VR_RXCFG_RX_MULTI; 54841502Swpaul 54941502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 55041502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 55141502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 55241502Swpaul 55341502Swpaul return; 55441502Swpaul} 55541502Swpaul 55641502Swpaul/* 55741502Swpaul * In order to fiddle with the 55841502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 55941502Swpaul * first have to put the transmit and/or receive logic in the idle state. 56041502Swpaul */ 56151432Swpaulstatic void vr_setcfg(sc, media) 56241502Swpaul struct vr_softc *sc; 56351432Swpaul int media; 56441502Swpaul{ 56541502Swpaul int restart = 0; 56641502Swpaul 56741502Swpaul if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 56841502Swpaul restart = 1; 56941502Swpaul VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 57041502Swpaul } 57141502Swpaul 57251432Swpaul if ((media & IFM_GMASK) == IFM_FDX) 57341502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 57441502Swpaul else 57541502Swpaul VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 57641502Swpaul 57741502Swpaul if (restart) 57841502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 57941502Swpaul 58041502Swpaul return; 58141502Swpaul} 58241502Swpaul 58341502Swpaulstatic void vr_reset(sc) 58441502Swpaul struct vr_softc *sc; 58541502Swpaul{ 58641502Swpaul register int i; 58741502Swpaul 58841502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 58941502Swpaul 59041502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 59141502Swpaul DELAY(10); 59241502Swpaul if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 59341502Swpaul break; 59441502Swpaul } 59541502Swpaul if (i == VR_TIMEOUT) 59641502Swpaul printf("vr%d: reset never completed!\n", sc->vr_unit); 59741502Swpaul 59841502Swpaul /* Wait a little while for the chip to get its brains in order. */ 59941502Swpaul DELAY(1000); 60041502Swpaul 60141502Swpaul return; 60241502Swpaul} 60341502Swpaul 60441502Swpaul/* 60541502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 60641502Swpaul * IDs against our list and return a device name if we find a match. 60741502Swpaul */ 60849610Swpaulstatic int vr_probe(dev) 60949610Swpaul device_t dev; 61041502Swpaul{ 61141502Swpaul struct vr_type *t; 61241502Swpaul 61341502Swpaul t = vr_devs; 61441502Swpaul 61541502Swpaul while(t->vr_name != NULL) { 61649610Swpaul if ((pci_get_vendor(dev) == t->vr_vid) && 61749610Swpaul (pci_get_device(dev) == t->vr_did)) { 61849610Swpaul device_set_desc(dev, t->vr_name); 61949610Swpaul return(0); 62041502Swpaul } 62141502Swpaul t++; 62241502Swpaul } 62341502Swpaul 62449610Swpaul return(ENXIO); 62541502Swpaul} 62641502Swpaul 62741502Swpaul/* 62841502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 62941502Swpaul * setup and ethernet/BPF attach. 63041502Swpaul */ 63149610Swpaulstatic int vr_attach(dev) 63249610Swpaul device_t dev; 63341502Swpaul{ 63467087Swpaul int i; 63541502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 63641502Swpaul u_int32_t command; 63741502Swpaul struct vr_softc *sc; 63841502Swpaul struct ifnet *ifp; 63949610Swpaul int unit, error = 0, rid; 64041502Swpaul 64149610Swpaul sc = device_get_softc(dev); 64249610Swpaul unit = device_get_unit(dev); 64349610Swpaul bzero(sc, sizeof(struct vr_softc *)); 64441502Swpaul 64571228Sbmilekic mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 64669583Swpaul VR_LOCK(sc); 64769583Swpaul 64841502Swpaul /* 64941502Swpaul * Handle power management nonsense. 65041502Swpaul */ 65172813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 65272813Swpaul u_int32_t iobase, membase, irq; 65341502Swpaul 65472813Swpaul /* Save important PCI config data. */ 65572813Swpaul iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 65672813Swpaul membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 65772813Swpaul irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 65841502Swpaul 65972813Swpaul /* Reset the power state. */ 66072813Swpaul printf("vr%d: chip is in D%d power mode " 66172813Swpaul "-- setting to D0\n", unit, 66272813Swpaul pci_get_powerstate(dev)); 66372813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 66441502Swpaul 66541502Swpaul /* Restore PCI config data. */ 66672813Swpaul pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 66772813Swpaul pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 66872813Swpaul pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 66941502Swpaul } 67041502Swpaul 67141502Swpaul /* 67241502Swpaul * Map control/status registers. 67341502Swpaul */ 67472813Swpaul pci_enable_busmaster(dev); 67579472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 67679472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 67761041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 67841502Swpaul 67941502Swpaul#ifdef VR_USEIOSPACE 68041502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 68141502Swpaul printf("vr%d: failed to enable I/O ports!\n", unit); 68241502Swpaul free(sc, M_DEVBUF); 68341502Swpaul goto fail; 68441502Swpaul } 68541502Swpaul#else 68641502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 68741502Swpaul printf("vr%d: failed to enable memory mapping!\n", unit); 68841502Swpaul goto fail; 68941502Swpaul } 69049610Swpaul#endif 69141502Swpaul 69249610Swpaul rid = VR_RID; 69349610Swpaul sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 69449610Swpaul 0, ~0, 1, RF_ACTIVE); 69549610Swpaul 69649610Swpaul if (sc->vr_res == NULL) { 69749610Swpaul printf("vr%d: couldn't map ports/memory\n", unit); 69849610Swpaul error = ENXIO; 69941502Swpaul goto fail; 70041502Swpaul } 70141502Swpaul 70249610Swpaul sc->vr_btag = rman_get_bustag(sc->vr_res); 70349610Swpaul sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 70441502Swpaul 70541502Swpaul /* Allocate interrupt */ 70649610Swpaul rid = 0; 70749610Swpaul sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 70849610Swpaul RF_SHAREABLE | RF_ACTIVE); 70949610Swpaul 71049610Swpaul if (sc->vr_irq == NULL) { 71141502Swpaul printf("vr%d: couldn't map interrupt\n", unit); 71249610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 71349610Swpaul error = ENXIO; 71441502Swpaul goto fail; 71541502Swpaul } 71641502Swpaul 71749610Swpaul error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 71849610Swpaul vr_intr, sc, &sc->vr_intrhand); 71949610Swpaul 72049610Swpaul if (error) { 72149610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 72249610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 72349610Swpaul printf("vr%d: couldn't set up irq\n", unit); 72449610Swpaul goto fail; 72549610Swpaul } 72649610Swpaul 72776586Swpaul /* 72876586Swpaul * Windows may put the chip in suspend mode when it 72976586Swpaul * shuts down. Be sure to kick it in the head to wake it 73076586Swpaul * up again. 73176586Swpaul */ 73276586Swpaul VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 73376586Swpaul 73441502Swpaul /* Reset the adapter. */ 73541502Swpaul vr_reset(sc); 73641502Swpaul 73741502Swpaul /* 73841502Swpaul * Get station address. The way the Rhine chips work, 73941502Swpaul * you're not allowed to directly access the EEPROM once 74041502Swpaul * they've been programmed a special way. Consequently, 74141502Swpaul * we need to read the node address from the PAR0 and PAR1 74241502Swpaul * registers. 74341502Swpaul */ 74441502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 74541502Swpaul DELAY(200); 74641502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 74741502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 74841502Swpaul 74941502Swpaul /* 75041502Swpaul * A Rhine chip was detected. Inform the world. 75141502Swpaul */ 75241502Swpaul printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 75341502Swpaul 75441502Swpaul sc->vr_unit = unit; 75541502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 75641502Swpaul 75751432Swpaul sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 75851657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 75951432Swpaul 76051432Swpaul if (sc->vr_ldata == NULL) { 76141502Swpaul printf("vr%d: no memory for list buffers!\n", unit); 76249610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 76349610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 76449610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 76549610Swpaul error = ENXIO; 76649610Swpaul goto fail; 76741502Swpaul } 76841502Swpaul 76941502Swpaul bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 77041502Swpaul 77141502Swpaul ifp = &sc->arpcom.ac_if; 77241502Swpaul ifp->if_softc = sc; 77341502Swpaul ifp->if_unit = unit; 77441502Swpaul ifp->if_name = "vr"; 77541502Swpaul ifp->if_mtu = ETHERMTU; 77641502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 77741502Swpaul ifp->if_ioctl = vr_ioctl; 77841502Swpaul ifp->if_output = ether_output; 77941502Swpaul ifp->if_start = vr_start; 78041502Swpaul ifp->if_watchdog = vr_watchdog; 78141502Swpaul ifp->if_init = vr_init; 78241502Swpaul ifp->if_baudrate = 10000000; 78343515Swpaul ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 78441502Swpaul 78551432Swpaul /* 78651432Swpaul * Do MII setup. 78751432Swpaul */ 78851432Swpaul if (mii_phy_probe(dev, &sc->vr_miibus, 78951432Swpaul vr_ifmedia_upd, vr_ifmedia_sts)) { 79041502Swpaul printf("vr%d: MII without any phy!\n", sc->vr_unit); 79149610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 79249610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 79349610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 79451432Swpaul contigfree(sc->vr_ldata, 79551432Swpaul sizeof(struct vr_list_data), M_DEVBUF); 79649610Swpaul error = ENXIO; 79741502Swpaul goto fail; 79841502Swpaul } 79941502Swpaul 80051432Swpaul callout_handle_init(&sc->vr_stat_ch); 80141502Swpaul 80241502Swpaul /* 80363090Sarchie * Call MI attach routine. 80441502Swpaul */ 80563090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 80667087Swpaul VR_UNLOCK(sc); 80767087Swpaul return(0); 80841502Swpaul 80941502Swpaulfail: 81067087Swpaul VR_UNLOCK(sc); 81167087Swpaul mtx_destroy(&sc->vr_mtx); 81267087Swpaul 81349610Swpaul return(error); 81441502Swpaul} 81541502Swpaul 81649610Swpaulstatic int vr_detach(dev) 81749610Swpaul device_t dev; 81849610Swpaul{ 81949610Swpaul struct vr_softc *sc; 82049610Swpaul struct ifnet *ifp; 82149610Swpaul 82249610Swpaul sc = device_get_softc(dev); 82367087Swpaul VR_LOCK(sc); 82449610Swpaul ifp = &sc->arpcom.ac_if; 82549610Swpaul 82649610Swpaul vr_stop(sc); 82763090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 82849610Swpaul 82951432Swpaul bus_generic_detach(dev); 83051432Swpaul device_delete_child(dev, sc->vr_miibus); 83151432Swpaul 83249610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 83349610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 83449610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 83549610Swpaul 83651432Swpaul contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 83749610Swpaul 83867087Swpaul VR_UNLOCK(sc); 83967087Swpaul mtx_destroy(&sc->vr_mtx); 84049610Swpaul 84149610Swpaul return(0); 84249610Swpaul} 84349610Swpaul 84441502Swpaul/* 84541502Swpaul * Initialize the transmit descriptors. 84641502Swpaul */ 84741502Swpaulstatic int vr_list_tx_init(sc) 84841502Swpaul struct vr_softc *sc; 84941502Swpaul{ 85041502Swpaul struct vr_chain_data *cd; 85141502Swpaul struct vr_list_data *ld; 85241502Swpaul int i; 85341502Swpaul 85441502Swpaul cd = &sc->vr_cdata; 85541502Swpaul ld = sc->vr_ldata; 85641502Swpaul for (i = 0; i < VR_TX_LIST_CNT; i++) { 85741502Swpaul cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 85841502Swpaul if (i == (VR_TX_LIST_CNT - 1)) 85941502Swpaul cd->vr_tx_chain[i].vr_nextdesc = 86041502Swpaul &cd->vr_tx_chain[0]; 86141502Swpaul else 86241502Swpaul cd->vr_tx_chain[i].vr_nextdesc = 86341502Swpaul &cd->vr_tx_chain[i + 1]; 86441502Swpaul } 86541502Swpaul 86641502Swpaul cd->vr_tx_free = &cd->vr_tx_chain[0]; 86741502Swpaul cd->vr_tx_tail = cd->vr_tx_head = NULL; 86841502Swpaul 86941502Swpaul return(0); 87041502Swpaul} 87141502Swpaul 87241502Swpaul 87341502Swpaul/* 87441502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 87541502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 87641502Swpaul * points back to the first. 87741502Swpaul */ 87841502Swpaulstatic int vr_list_rx_init(sc) 87941502Swpaul struct vr_softc *sc; 88041502Swpaul{ 88141502Swpaul struct vr_chain_data *cd; 88241502Swpaul struct vr_list_data *ld; 88341502Swpaul int i; 88441502Swpaul 88541502Swpaul cd = &sc->vr_cdata; 88641502Swpaul ld = sc->vr_ldata; 88741502Swpaul 88841502Swpaul for (i = 0; i < VR_RX_LIST_CNT; i++) { 88941502Swpaul cd->vr_rx_chain[i].vr_ptr = 89041502Swpaul (struct vr_desc *)&ld->vr_rx_list[i]; 89149610Swpaul if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 89241502Swpaul return(ENOBUFS); 89341502Swpaul if (i == (VR_RX_LIST_CNT - 1)) { 89441502Swpaul cd->vr_rx_chain[i].vr_nextdesc = 89541502Swpaul &cd->vr_rx_chain[0]; 89641502Swpaul ld->vr_rx_list[i].vr_next = 89741502Swpaul vtophys(&ld->vr_rx_list[0]); 89841502Swpaul } else { 89941502Swpaul cd->vr_rx_chain[i].vr_nextdesc = 90041502Swpaul &cd->vr_rx_chain[i + 1]; 90141502Swpaul ld->vr_rx_list[i].vr_next = 90241502Swpaul vtophys(&ld->vr_rx_list[i + 1]); 90341502Swpaul } 90441502Swpaul } 90541502Swpaul 90641502Swpaul cd->vr_rx_head = &cd->vr_rx_chain[0]; 90741502Swpaul 90841502Swpaul return(0); 90941502Swpaul} 91041502Swpaul 91141502Swpaul/* 91241502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 91341502Swpaul * Note: the length fields are only 11 bits wide, which means the 91441502Swpaul * largest size we can specify is 2047. This is important because 91541502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 91641502Swpaul * overflow the field and make a mess. 91741502Swpaul */ 91849610Swpaulstatic int vr_newbuf(sc, c, m) 91941502Swpaul struct vr_softc *sc; 92041502Swpaul struct vr_chain_onefrag *c; 92149610Swpaul struct mbuf *m; 92241502Swpaul{ 92341502Swpaul struct mbuf *m_new = NULL; 92441502Swpaul 92549610Swpaul if (m == NULL) { 92649610Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 92787846Sluigi if (m_new == NULL) 92849610Swpaul return(ENOBUFS); 92941502Swpaul 93049610Swpaul MCLGET(m_new, M_DONTWAIT); 93149610Swpaul if (!(m_new->m_flags & M_EXT)) { 93249610Swpaul m_freem(m_new); 93349610Swpaul return(ENOBUFS); 93449610Swpaul } 93549610Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 93649610Swpaul } else { 93749610Swpaul m_new = m; 93849610Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 93949610Swpaul m_new->m_data = m_new->m_ext.ext_buf; 94041502Swpaul } 94141502Swpaul 94249610Swpaul m_adj(m_new, sizeof(u_int64_t)); 94349610Swpaul 94441502Swpaul c->vr_mbuf = m_new; 94541502Swpaul c->vr_ptr->vr_status = VR_RXSTAT; 94641502Swpaul c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 94742491Swpaul c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 94841502Swpaul 94941502Swpaul return(0); 95041502Swpaul} 95141502Swpaul 95241502Swpaul/* 95341502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 95441502Swpaul * the higher level protocols. 95541502Swpaul */ 95641502Swpaulstatic void vr_rxeof(sc) 95741502Swpaul struct vr_softc *sc; 95841502Swpaul{ 95941502Swpaul struct ether_header *eh; 96041502Swpaul struct mbuf *m; 96141502Swpaul struct ifnet *ifp; 96241502Swpaul struct vr_chain_onefrag *cur_rx; 96341502Swpaul int total_len = 0; 96441502Swpaul u_int32_t rxstat; 96541502Swpaul 96641502Swpaul ifp = &sc->arpcom.ac_if; 96741502Swpaul 96841502Swpaul while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 96941502Swpaul VR_RXSTAT_OWN)) { 97049610Swpaul struct mbuf *m0 = NULL; 97149610Swpaul 97241502Swpaul cur_rx = sc->vr_cdata.vr_rx_head; 97341502Swpaul sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 97449610Swpaul m = cur_rx->vr_mbuf; 97541502Swpaul 97641502Swpaul /* 97741502Swpaul * If an error occurs, update stats, clear the 97841502Swpaul * status word and leave the mbuf cluster in place: 97941502Swpaul * it should simply get re-used next time this descriptor 98041502Swpaul * comes up in the ring. 98141502Swpaul */ 98241502Swpaul if (rxstat & VR_RXSTAT_RXERR) { 98341502Swpaul ifp->if_ierrors++; 98441502Swpaul printf("vr%d: rx error: ", sc->vr_unit); 98541502Swpaul switch(rxstat & 0x000000FF) { 98641502Swpaul case VR_RXSTAT_CRCERR: 98741502Swpaul printf("crc error\n"); 98841502Swpaul break; 98941502Swpaul case VR_RXSTAT_FRAMEALIGNERR: 99041502Swpaul printf("frame alignment error\n"); 99141502Swpaul break; 99241502Swpaul case VR_RXSTAT_FIFOOFLOW: 99341502Swpaul printf("FIFO overflow\n"); 99441502Swpaul break; 99541502Swpaul case VR_RXSTAT_GIANT: 99641502Swpaul printf("received giant packet\n"); 99741502Swpaul break; 99841502Swpaul case VR_RXSTAT_RUNT: 99941502Swpaul printf("received runt packet\n"); 100041502Swpaul break; 100141502Swpaul case VR_RXSTAT_BUSERR: 100241502Swpaul printf("system bus error\n"); 100341502Swpaul break; 100441502Swpaul case VR_RXSTAT_BUFFERR: 100541502Swpaul printf("rx buffer error\n"); 100641502Swpaul break; 100741502Swpaul default: 100841502Swpaul printf("unknown rx error\n"); 100941502Swpaul break; 101041502Swpaul } 101149610Swpaul vr_newbuf(sc, cur_rx, m); 101241502Swpaul continue; 101341502Swpaul } 101441502Swpaul 101541502Swpaul /* No errors; receive the packet. */ 101641502Swpaul total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 101741502Swpaul 101841502Swpaul /* 101942048Swpaul * XXX The VIA Rhine chip includes the CRC with every 102042048Swpaul * received frame, and there's no way to turn this 102142048Swpaul * behavior off (at least, I can't find anything in 102242048Swpaul * the manual that explains how to do it) so we have 102342048Swpaul * to trim off the CRC manually. 102442048Swpaul */ 102542048Swpaul total_len -= ETHER_CRC_LEN; 102642048Swpaul 102778508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 102878508Sbmilekic NULL); 102949610Swpaul vr_newbuf(sc, cur_rx, m); 103049610Swpaul if (m0 == NULL) { 103141502Swpaul ifp->if_ierrors++; 103241502Swpaul continue; 103341502Swpaul } 103449610Swpaul m = m0; 103541502Swpaul 103641502Swpaul ifp->if_ipackets++; 103741502Swpaul eh = mtod(m, struct ether_header *); 103849610Swpaul 103941502Swpaul /* Remove header from mbuf and pass it on. */ 104041502Swpaul m_adj(m, sizeof(struct ether_header)); 104141502Swpaul ether_input(ifp, eh, m); 104241502Swpaul } 104341502Swpaul 104441502Swpaul return; 104541502Swpaul} 104641502Swpaul 104741502Swpaulvoid vr_rxeoc(sc) 104841502Swpaul struct vr_softc *sc; 104941502Swpaul{ 105041502Swpaul 105141502Swpaul vr_rxeof(sc); 105241502Swpaul VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 105341502Swpaul CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 105441502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 105541502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 105641502Swpaul 105741502Swpaul return; 105841502Swpaul} 105941502Swpaul 106041502Swpaul/* 106141502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 106241502Swpaul * the list buffers. 106341502Swpaul */ 106441502Swpaul 106541502Swpaulstatic void vr_txeof(sc) 106641502Swpaul struct vr_softc *sc; 106741502Swpaul{ 106841502Swpaul struct vr_chain *cur_tx; 106941502Swpaul struct ifnet *ifp; 107041502Swpaul 107141502Swpaul ifp = &sc->arpcom.ac_if; 107241502Swpaul 107341502Swpaul /* Clear the timeout timer. */ 107441502Swpaul ifp->if_timer = 0; 107541502Swpaul 107641502Swpaul /* Sanity check. */ 107741502Swpaul if (sc->vr_cdata.vr_tx_head == NULL) 107841502Swpaul return; 107941502Swpaul 108041502Swpaul /* 108141502Swpaul * Go through our tx list and free mbufs for those 108241502Swpaul * frames that have been transmitted. 108341502Swpaul */ 108441502Swpaul while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 108541502Swpaul u_int32_t txstat; 108641502Swpaul 108741502Swpaul cur_tx = sc->vr_cdata.vr_tx_head; 108841502Swpaul txstat = cur_tx->vr_ptr->vr_status; 108941502Swpaul 109042491Swpaul if (txstat & VR_TXSTAT_OWN) 109141502Swpaul break; 109241502Swpaul 109341502Swpaul if (txstat & VR_TXSTAT_ERRSUM) { 109441502Swpaul ifp->if_oerrors++; 109541502Swpaul if (txstat & VR_TXSTAT_DEFER) 109641502Swpaul ifp->if_collisions++; 109741502Swpaul if (txstat & VR_TXSTAT_LATECOLL) 109841502Swpaul ifp->if_collisions++; 109941502Swpaul } 110041502Swpaul 110141502Swpaul ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 110241502Swpaul 110341502Swpaul ifp->if_opackets++; 110451432Swpaul if (cur_tx->vr_mbuf != NULL) { 110551432Swpaul m_freem(cur_tx->vr_mbuf); 110651432Swpaul cur_tx->vr_mbuf = NULL; 110751432Swpaul } 110841502Swpaul 110941502Swpaul if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 111041502Swpaul sc->vr_cdata.vr_tx_head = NULL; 111141502Swpaul sc->vr_cdata.vr_tx_tail = NULL; 111241502Swpaul break; 111341502Swpaul } 111441502Swpaul 111541502Swpaul sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 111641502Swpaul } 111741502Swpaul 111841502Swpaul return; 111941502Swpaul} 112041502Swpaul 112141502Swpaul/* 112241502Swpaul * TX 'end of channel' interrupt handler. 112341502Swpaul */ 112441502Swpaulstatic void vr_txeoc(sc) 112541502Swpaul struct vr_softc *sc; 112641502Swpaul{ 112741502Swpaul struct ifnet *ifp; 112841502Swpaul 112941502Swpaul ifp = &sc->arpcom.ac_if; 113041502Swpaul 113141502Swpaul ifp->if_timer = 0; 113241502Swpaul 113341502Swpaul if (sc->vr_cdata.vr_tx_head == NULL) { 113441502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 113541502Swpaul sc->vr_cdata.vr_tx_tail = NULL; 113641502Swpaul } 113741502Swpaul 113841502Swpaul return; 113941502Swpaul} 114041502Swpaul 114151432Swpaulstatic void vr_tick(xsc) 114251432Swpaul void *xsc; 114351432Swpaul{ 114451432Swpaul struct vr_softc *sc; 114551432Swpaul struct mii_data *mii; 114651432Swpaul 114751432Swpaul sc = xsc; 114867087Swpaul VR_LOCK(sc); 114951432Swpaul mii = device_get_softc(sc->vr_miibus); 115051432Swpaul mii_tick(mii); 115151432Swpaul 115251432Swpaul sc->vr_stat_ch = timeout(vr_tick, sc, hz); 115351432Swpaul 115467087Swpaul VR_UNLOCK(sc); 115551432Swpaul 115651432Swpaul return; 115751432Swpaul} 115851432Swpaul 115941502Swpaulstatic void vr_intr(arg) 116041502Swpaul void *arg; 116141502Swpaul{ 116241502Swpaul struct vr_softc *sc; 116341502Swpaul struct ifnet *ifp; 116441502Swpaul u_int16_t status; 116541502Swpaul 116641502Swpaul sc = arg; 116767087Swpaul VR_LOCK(sc); 116841502Swpaul ifp = &sc->arpcom.ac_if; 116941502Swpaul 117041502Swpaul /* Supress unwanted interrupts. */ 117141502Swpaul if (!(ifp->if_flags & IFF_UP)) { 117241502Swpaul vr_stop(sc); 117367087Swpaul VR_UNLOCK(sc); 117441502Swpaul return; 117541502Swpaul } 117641502Swpaul 117741502Swpaul /* Disable interrupts. */ 117841502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 117941502Swpaul 118041502Swpaul for (;;) { 118141502Swpaul 118241502Swpaul status = CSR_READ_2(sc, VR_ISR); 118341502Swpaul if (status) 118441502Swpaul CSR_WRITE_2(sc, VR_ISR, status); 118541502Swpaul 118641502Swpaul if ((status & VR_INTRS) == 0) 118741502Swpaul break; 118841502Swpaul 118941502Swpaul if (status & VR_ISR_RX_OK) 119041502Swpaul vr_rxeof(sc); 119141502Swpaul 119241502Swpaul if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 119341502Swpaul (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 119441502Swpaul (status & VR_ISR_RX_DROPPED)) { 119541502Swpaul vr_rxeof(sc); 119641502Swpaul vr_rxeoc(sc); 119741502Swpaul } 119841502Swpaul 119941502Swpaul if (status & VR_ISR_TX_OK) { 120041502Swpaul vr_txeof(sc); 120141502Swpaul vr_txeoc(sc); 120241502Swpaul } 120341502Swpaul 120441502Swpaul if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 120541502Swpaul ifp->if_oerrors++; 120641502Swpaul vr_txeof(sc); 120741502Swpaul if (sc->vr_cdata.vr_tx_head != NULL) { 120841502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 120941502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 121041502Swpaul } 121141502Swpaul } 121241502Swpaul 121341502Swpaul if (status & VR_ISR_BUSERR) { 121441502Swpaul vr_reset(sc); 121541502Swpaul vr_init(sc); 121641502Swpaul } 121741502Swpaul } 121841502Swpaul 121941502Swpaul /* Re-enable interrupts. */ 122041502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 122141502Swpaul 122241502Swpaul if (ifp->if_snd.ifq_head != NULL) { 122341502Swpaul vr_start(ifp); 122441502Swpaul } 122541502Swpaul 122667087Swpaul VR_UNLOCK(sc); 122767087Swpaul 122841502Swpaul return; 122941502Swpaul} 123041502Swpaul 123141502Swpaul/* 123241502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 123341502Swpaul * pointers to the fragment pointers. 123441502Swpaul */ 123541502Swpaulstatic int vr_encap(sc, c, m_head) 123641502Swpaul struct vr_softc *sc; 123741502Swpaul struct vr_chain *c; 123841502Swpaul struct mbuf *m_head; 123941502Swpaul{ 124041502Swpaul int frag = 0; 124141502Swpaul struct vr_desc *f = NULL; 124241502Swpaul int total_len; 124341502Swpaul struct mbuf *m; 124441502Swpaul 124541502Swpaul m = m_head; 124641502Swpaul total_len = 0; 124741502Swpaul 124841502Swpaul /* 124941502Swpaul * The VIA Rhine wants packet buffers to be longword 125041502Swpaul * aligned, but very often our mbufs aren't. Rather than 125141502Swpaul * waste time trying to decide when to copy and when not 125241502Swpaul * to copy, just do it all the time. 125341502Swpaul */ 125441502Swpaul if (m != NULL) { 125541502Swpaul struct mbuf *m_new = NULL; 125641502Swpaul 125741502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 125841502Swpaul if (m_new == NULL) { 125971271Swpaul printf("vr%d: no memory for tx list\n", sc->vr_unit); 126041502Swpaul return(1); 126141502Swpaul } 126241502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 126341502Swpaul MCLGET(m_new, M_DONTWAIT); 126441502Swpaul if (!(m_new->m_flags & M_EXT)) { 126541502Swpaul m_freem(m_new); 126671271Swpaul printf("vr%d: no memory for tx list\n", 126741502Swpaul sc->vr_unit); 126841502Swpaul return(1); 126941502Swpaul } 127041502Swpaul } 127141502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 127241502Swpaul mtod(m_new, caddr_t)); 127341502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 127441502Swpaul m_freem(m_head); 127541502Swpaul m_head = m_new; 127641502Swpaul /* 127741502Swpaul * The Rhine chip doesn't auto-pad, so we have to make 127841502Swpaul * sure to pad short frames out to the minimum frame length 127941502Swpaul * ourselves. 128041502Swpaul */ 128141502Swpaul if (m_head->m_len < VR_MIN_FRAMELEN) { 128241502Swpaul m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 128341502Swpaul m_new->m_len = m_new->m_pkthdr.len; 128441502Swpaul } 128541502Swpaul f = c->vr_ptr; 128641502Swpaul f->vr_data = vtophys(mtod(m_new, caddr_t)); 128741502Swpaul f->vr_ctl = total_len = m_new->m_len; 128841502Swpaul f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 128941502Swpaul f->vr_status = 0; 129041502Swpaul frag = 1; 129141502Swpaul } 129241502Swpaul 129341502Swpaul c->vr_mbuf = m_head; 129442491Swpaul c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 129541502Swpaul c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 129641502Swpaul 129741502Swpaul return(0); 129841502Swpaul} 129941502Swpaul 130041502Swpaul/* 130141502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 130241502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 130341502Swpaul * copy of the pointers since the transmit list fragment pointers are 130441502Swpaul * physical addresses. 130541502Swpaul */ 130641502Swpaul 130741502Swpaulstatic void vr_start(ifp) 130841502Swpaul struct ifnet *ifp; 130941502Swpaul{ 131041502Swpaul struct vr_softc *sc; 131141502Swpaul struct mbuf *m_head = NULL; 131241502Swpaul struct vr_chain *cur_tx = NULL, *start_tx; 131341502Swpaul 131441502Swpaul sc = ifp->if_softc; 131541502Swpaul 131667087Swpaul VR_LOCK(sc); 131767087Swpaul if (ifp->if_flags & IFF_OACTIVE) { 131867087Swpaul VR_UNLOCK(sc); 131941502Swpaul return; 132067087Swpaul } 132141502Swpaul 132241502Swpaul /* 132341502Swpaul * Check for an available queue slot. If there are none, 132441502Swpaul * punt. 132541502Swpaul */ 132641502Swpaul if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 132741502Swpaul ifp->if_flags |= IFF_OACTIVE; 132841502Swpaul return; 132941502Swpaul } 133041502Swpaul 133141502Swpaul start_tx = sc->vr_cdata.vr_tx_free; 133241502Swpaul 133341502Swpaul while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 133441502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 133541502Swpaul if (m_head == NULL) 133641502Swpaul break; 133741502Swpaul 133841502Swpaul /* Pick a descriptor off the free list. */ 133941502Swpaul cur_tx = sc->vr_cdata.vr_tx_free; 134041502Swpaul sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 134141502Swpaul 134241502Swpaul /* Pack the data into the descriptor. */ 134371271Swpaul if (vr_encap(sc, cur_tx, m_head)) { 134471271Swpaul IF_PREPEND(&ifp->if_snd, m_head); 134571275Swpaul ifp->if_flags |= IFF_OACTIVE; 134671271Swpaul cur_tx = NULL; 134771271Swpaul break; 134871271Swpaul } 134941502Swpaul 135041502Swpaul if (cur_tx != start_tx) 135141502Swpaul VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 135241502Swpaul 135341502Swpaul /* 135441502Swpaul * If there's a BPF listener, bounce a copy of this frame 135541502Swpaul * to him. 135641502Swpaul */ 135741502Swpaul if (ifp->if_bpf) 135841502Swpaul bpf_mtap(ifp, cur_tx->vr_mbuf); 135951583Swpaul 136042491Swpaul VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 136151432Swpaul VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 136241502Swpaul } 136341502Swpaul 136441502Swpaul /* 136541526Swpaul * If there are no frames queued, bail. 136641526Swpaul */ 136767087Swpaul if (cur_tx == NULL) { 136867087Swpaul VR_UNLOCK(sc); 136941526Swpaul return; 137067087Swpaul } 137141526Swpaul 137241502Swpaul sc->vr_cdata.vr_tx_tail = cur_tx; 137341502Swpaul 137442491Swpaul if (sc->vr_cdata.vr_tx_head == NULL) 137541502Swpaul sc->vr_cdata.vr_tx_head = start_tx; 137641502Swpaul 137741502Swpaul /* 137841502Swpaul * Set a timeout in case the chip goes out to lunch. 137941502Swpaul */ 138041502Swpaul ifp->if_timer = 5; 138167087Swpaul VR_UNLOCK(sc); 138241502Swpaul 138341502Swpaul return; 138441502Swpaul} 138541502Swpaul 138641502Swpaulstatic void vr_init(xsc) 138741502Swpaul void *xsc; 138841502Swpaul{ 138941502Swpaul struct vr_softc *sc = xsc; 139041502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 139151432Swpaul struct mii_data *mii; 139273963Swpaul int i; 139341502Swpaul 139467087Swpaul VR_LOCK(sc); 139541502Swpaul 139651432Swpaul mii = device_get_softc(sc->vr_miibus); 139741502Swpaul 139841502Swpaul /* 139941502Swpaul * Cancel pending I/O and free all RX/TX buffers. 140041502Swpaul */ 140141502Swpaul vr_stop(sc); 140241502Swpaul vr_reset(sc); 140341502Swpaul 140473963Swpaul /* 140573963Swpaul * Set our station address. 140673963Swpaul */ 140773963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 140873963Swpaul CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 140973963Swpaul 141041502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 141141502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 141241502Swpaul 141341502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 141441502Swpaul VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 141541502Swpaul 141641502Swpaul /* Init circular RX list. */ 141741502Swpaul if (vr_list_rx_init(sc) == ENOBUFS) { 141841502Swpaul printf("vr%d: initialization failed: no " 141941502Swpaul "memory for rx buffers\n", sc->vr_unit); 142041502Swpaul vr_stop(sc); 142167087Swpaul VR_UNLOCK(sc); 142241502Swpaul return; 142341502Swpaul } 142441502Swpaul 142541502Swpaul /* 142641502Swpaul * Init tx descriptors. 142741502Swpaul */ 142841502Swpaul vr_list_tx_init(sc); 142941502Swpaul 143041502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 143141502Swpaul if (ifp->if_flags & IFF_PROMISC) 143241502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 143341502Swpaul else 143441502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 143541502Swpaul 143641502Swpaul /* Set capture broadcast bit to capture broadcast frames. */ 143741502Swpaul if (ifp->if_flags & IFF_BROADCAST) 143841502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 143941502Swpaul else 144041502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 144141502Swpaul 144241502Swpaul /* 144341502Swpaul * Program the multicast filter, if necessary. 144441502Swpaul */ 144541502Swpaul vr_setmulti(sc); 144641502Swpaul 144741502Swpaul /* 144841502Swpaul * Load the address of the RX list. 144941502Swpaul */ 145041502Swpaul CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 145141502Swpaul 145241502Swpaul /* Enable receiver and transmitter. */ 145341502Swpaul CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 145441502Swpaul VR_CMD_TX_ON|VR_CMD_RX_ON| 145541502Swpaul VR_CMD_RX_GO); 145641502Swpaul 145741502Swpaul CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 145841502Swpaul 145941502Swpaul /* 146041502Swpaul * Enable interrupts. 146141502Swpaul */ 146241502Swpaul CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 146341502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 146441502Swpaul 146551432Swpaul mii_mediachg(mii); 146641502Swpaul 146741502Swpaul ifp->if_flags |= IFF_RUNNING; 146841502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 146941502Swpaul 147051432Swpaul sc->vr_stat_ch = timeout(vr_tick, sc, hz); 147151432Swpaul 147267087Swpaul VR_UNLOCK(sc); 147367087Swpaul 147441502Swpaul return; 147541502Swpaul} 147641502Swpaul 147741502Swpaul/* 147841502Swpaul * Set media options. 147941502Swpaul */ 148041502Swpaulstatic int vr_ifmedia_upd(ifp) 148141502Swpaul struct ifnet *ifp; 148241502Swpaul{ 148341502Swpaul struct vr_softc *sc; 148441502Swpaul 148541502Swpaul sc = ifp->if_softc; 148641502Swpaul 148751432Swpaul if (ifp->if_flags & IFF_UP) 148851432Swpaul vr_init(sc); 148941502Swpaul 149041502Swpaul return(0); 149141502Swpaul} 149241502Swpaul 149341502Swpaul/* 149441502Swpaul * Report current media status. 149541502Swpaul */ 149641502Swpaulstatic void vr_ifmedia_sts(ifp, ifmr) 149741502Swpaul struct ifnet *ifp; 149841502Swpaul struct ifmediareq *ifmr; 149941502Swpaul{ 150041502Swpaul struct vr_softc *sc; 150151432Swpaul struct mii_data *mii; 150241502Swpaul 150341502Swpaul sc = ifp->if_softc; 150451432Swpaul mii = device_get_softc(sc->vr_miibus); 150551432Swpaul mii_pollstat(mii); 150651432Swpaul ifmr->ifm_active = mii->mii_media_active; 150751432Swpaul ifmr->ifm_status = mii->mii_media_status; 150841502Swpaul 150941502Swpaul return; 151041502Swpaul} 151141502Swpaul 151241502Swpaulstatic int vr_ioctl(ifp, command, data) 151341502Swpaul struct ifnet *ifp; 151441502Swpaul u_long command; 151541502Swpaul caddr_t data; 151641502Swpaul{ 151741502Swpaul struct vr_softc *sc = ifp->if_softc; 151841502Swpaul struct ifreq *ifr = (struct ifreq *) data; 151951432Swpaul struct mii_data *mii; 152067087Swpaul int error = 0; 152141502Swpaul 152267087Swpaul VR_LOCK(sc); 152341502Swpaul 152441502Swpaul switch(command) { 152541502Swpaul case SIOCSIFADDR: 152641502Swpaul case SIOCGIFADDR: 152741502Swpaul case SIOCSIFMTU: 152841502Swpaul error = ether_ioctl(ifp, command, data); 152941502Swpaul break; 153041502Swpaul case SIOCSIFFLAGS: 153141502Swpaul if (ifp->if_flags & IFF_UP) { 153241502Swpaul vr_init(sc); 153341502Swpaul } else { 153441502Swpaul if (ifp->if_flags & IFF_RUNNING) 153541502Swpaul vr_stop(sc); 153641502Swpaul } 153741502Swpaul error = 0; 153841502Swpaul break; 153941502Swpaul case SIOCADDMULTI: 154041502Swpaul case SIOCDELMULTI: 154141502Swpaul vr_setmulti(sc); 154241502Swpaul error = 0; 154341502Swpaul break; 154441502Swpaul case SIOCGIFMEDIA: 154541502Swpaul case SIOCSIFMEDIA: 154651432Swpaul mii = device_get_softc(sc->vr_miibus); 154751432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 154841502Swpaul break; 154941502Swpaul default: 155041502Swpaul error = EINVAL; 155141502Swpaul break; 155241502Swpaul } 155341502Swpaul 155467087Swpaul VR_UNLOCK(sc); 155541502Swpaul 155641502Swpaul return(error); 155741502Swpaul} 155841502Swpaul 155941502Swpaulstatic void vr_watchdog(ifp) 156041502Swpaul struct ifnet *ifp; 156141502Swpaul{ 156241502Swpaul struct vr_softc *sc; 156341502Swpaul 156441502Swpaul sc = ifp->if_softc; 156541502Swpaul 156667087Swpaul VR_LOCK(sc); 156741502Swpaul ifp->if_oerrors++; 156841502Swpaul printf("vr%d: watchdog timeout\n", sc->vr_unit); 156941502Swpaul 157041502Swpaul vr_stop(sc); 157141502Swpaul vr_reset(sc); 157241502Swpaul vr_init(sc); 157341502Swpaul 157441502Swpaul if (ifp->if_snd.ifq_head != NULL) 157541502Swpaul vr_start(ifp); 157641502Swpaul 157767087Swpaul VR_UNLOCK(sc); 157867087Swpaul 157941502Swpaul return; 158041502Swpaul} 158141502Swpaul 158241502Swpaul/* 158341502Swpaul * Stop the adapter and free any mbufs allocated to the 158441502Swpaul * RX and TX lists. 158541502Swpaul */ 158641502Swpaulstatic void vr_stop(sc) 158741502Swpaul struct vr_softc *sc; 158841502Swpaul{ 158941502Swpaul register int i; 159041502Swpaul struct ifnet *ifp; 159141502Swpaul 159267087Swpaul VR_LOCK(sc); 159367087Swpaul 159441502Swpaul ifp = &sc->arpcom.ac_if; 159541502Swpaul ifp->if_timer = 0; 159641502Swpaul 159751432Swpaul untimeout(vr_tick, sc, sc->vr_stat_ch); 159851432Swpaul 159941502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 160041502Swpaul VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 160141502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 160241502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 160341502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 160441502Swpaul 160541502Swpaul /* 160641502Swpaul * Free data in the RX lists. 160741502Swpaul */ 160841502Swpaul for (i = 0; i < VR_RX_LIST_CNT; i++) { 160941502Swpaul if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 161041502Swpaul m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 161141502Swpaul sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 161241502Swpaul } 161341502Swpaul } 161441502Swpaul bzero((char *)&sc->vr_ldata->vr_rx_list, 161541502Swpaul sizeof(sc->vr_ldata->vr_rx_list)); 161641502Swpaul 161741502Swpaul /* 161841502Swpaul * Free the TX list buffers. 161941502Swpaul */ 162041502Swpaul for (i = 0; i < VR_TX_LIST_CNT; i++) { 162141502Swpaul if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 162241502Swpaul m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 162341502Swpaul sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 162441502Swpaul } 162541502Swpaul } 162641502Swpaul 162741502Swpaul bzero((char *)&sc->vr_ldata->vr_tx_list, 162841502Swpaul sizeof(sc->vr_ldata->vr_tx_list)); 162941502Swpaul 163041502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 163167087Swpaul VR_UNLOCK(sc); 163241502Swpaul 163341502Swpaul return; 163441502Swpaul} 163541502Swpaul 163641502Swpaul/* 163741502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 163841502Swpaul * get confused by errant DMAs when rebooting. 163941502Swpaul */ 164049610Swpaulstatic void vr_shutdown(dev) 164149610Swpaul device_t dev; 164241502Swpaul{ 164349610Swpaul struct vr_softc *sc; 164441502Swpaul 164549610Swpaul sc = device_get_softc(dev); 164649610Swpaul 164741502Swpaul vr_stop(sc); 164841502Swpaul 164941502Swpaul return; 165041502Swpaul} 1651