if_vr.c revision 63090
1582Srgrimes/* 2582Srgrimes * Copyright (c) 1997, 1998 3582Srgrimes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4582Srgrimes * 5582Srgrimes * Redistribution and use in source and binary forms, with or without 6582Srgrimes * modification, are permitted provided that the following conditions 7582Srgrimes * are met: 8582Srgrimes * 1. Redistributions of source code must retain the above copyright 9582Srgrimes * notice, this list of conditions and the following disclaimer. 10582Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 11582Srgrimes * notice, this list of conditions and the following disclaimer in the 12582Srgrimes * documentation and/or other materials provided with the distribution. 13582Srgrimes * 3. All advertising materials mentioning features or use of this software 14582Srgrimes * must display the following acknowledgement: 15582Srgrimes * This product includes software developed by Bill Paul. 16582Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 17582Srgrimes * may be used to endorse or promote products derived from this software 18582Srgrimes * without specific prior written permission. 19582Srgrimes * 20582Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21582Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22582Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23582Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24582Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25582Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26582Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27582Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28582Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29582Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30582Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 31582Srgrimes * 32582Srgrimes * $FreeBSD: head/sys/dev/vr/if_vr.c 63090 2000-07-13 22:54:34Z archie $ 33582Srgrimes */ 3450477Speter 35582Srgrimes/* 36582Srgrimes * VIA Rhine fast ethernet PCI NIC driver 37582Srgrimes * 38582Srgrimes * Supports various network adapters based on the VIA Rhine 39582Srgrimes * and Rhine II PCI controllers, including the D-Link DFE530TX. 40582Srgrimes * Datasheets are available at http://www.via.com.tw. 41582Srgrimes * 42582Srgrimes * Written by Bill Paul <wpaul@ctr.columbia.edu> 43582Srgrimes * Electrical Engineering Department 44582Srgrimes * Columbia University, New York City 45582Srgrimes */ 46582Srgrimes 47582Srgrimes/* 48582Srgrimes * The VIA Rhine controllers are similar in some respects to the 49582Srgrimes * the DEC tulip chips, except less complicated. The controller 50582Srgrimes * uses an MII bus and an external physical layer interface. The 51582Srgrimes * receiver has a one entry perfect filter and a 64-bit hash table 52582Srgrimes * multicast filter. Transmit and receive descriptors are similar 53582Srgrimes * to the tulip. 54582Srgrimes * 55582Srgrimes * The Rhine has a serious flaw in its transmit DMA mechanism: 56582Srgrimes * transmit buffers must be longword aligned. Unfortunately, 57582Srgrimes * FreeBSD doesn't guarantee that mbufs will be filled in starting 58582Srgrimes * at longword boundaries, so we have to do a buffer copy before 59582Srgrimes * transmission. 60582Srgrimes */ 61582Srgrimes 62582Srgrimes#include <sys/param.h> 63582Srgrimes#include <sys/systm.h> 64582Srgrimes#include <sys/sockio.h> 65582Srgrimes#include <sys/mbuf.h> 66582Srgrimes#include <sys/malloc.h> 67582Srgrimes#include <sys/kernel.h> 68582Srgrimes#include <sys/socket.h> 69582Srgrimes 70582Srgrimes#include <net/if.h> 71582Srgrimes#include <net/if_arp.h> 72582Srgrimes#include <net/ethernet.h> 73582Srgrimes#include <net/if_dl.h> 74582Srgrimes#include <net/if_media.h> 75582Srgrimes 76582Srgrimes#include <net/bpf.h> 77582Srgrimes 78582Srgrimes#include <vm/vm.h> /* for vtophys */ 79582Srgrimes#include <vm/pmap.h> /* for vtophys */ 80582Srgrimes#include <machine/clock.h> /* for DELAY */ 81582Srgrimes#include <machine/bus_pio.h> 82582Srgrimes#include <machine/bus_memio.h> 83582Srgrimes#include <machine/bus.h> 84582Srgrimes#include <machine/resource.h> 85582Srgrimes#include <sys/bus.h> 86582Srgrimes#include <sys/rman.h> 87582Srgrimes 88582Srgrimes#include <dev/mii/mii.h> 89582Srgrimes#include <dev/mii/miivar.h> 90582Srgrimes 91582Srgrimes#include <pci/pcireg.h> 92582Srgrimes#include <pci/pcivar.h> 93582Srgrimes 94582Srgrimes#define VR_USEIOSPACE 95582Srgrimes 96582Srgrimes#include <pci/if_vrreg.h> 97582Srgrimes 98582SrgrimesMODULE_DEPEND(vr, miibus, 1, 1, 1); 99582Srgrimes 100582Srgrimes/* "controller miibus0" required. See GENERIC if you get errors here. */ 101582Srgrimes#include "miibus_if.h" 102582Srgrimes 103582Srgrimes#ifndef lint 104582Srgrimesstatic const char rcsid[] = 105582Srgrimes "$FreeBSD: head/sys/dev/vr/if_vr.c 63090 2000-07-13 22:54:34Z archie $"; 106582Srgrimes#endif 107582Srgrimes 108582Srgrimes/* 109582Srgrimes * Various supported device vendors/types and their names. 110582Srgrimes */ 111582Srgrimesstatic struct vr_type vr_devs[] = { 112582Srgrimes { VIA_VENDORID, VIA_DEVICEID_RHINE, 113582Srgrimes "VIA VT3043 Rhine I 10/100BaseTX" }, 114582Srgrimes { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115582Srgrimes "VIA VT86C100A Rhine II 10/100BaseTX" }, 116582Srgrimes { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117582Srgrimes "VIA VT6102 Rhine II 10/100BaseTX" }, 118582Srgrimes { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 119582Srgrimes "Delta Electronics Rhine II 10/100BaseTX" }, 120582Srgrimes { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 121582Srgrimes "Addtron Technology Rhine II 10/100BaseTX" }, 122582Srgrimes { 0, 0, NULL } 123582Srgrimes}; 124582Srgrimes 125582Srgrimesstatic int vr_probe __P((device_t)); 126582Srgrimesstatic int vr_attach __P((device_t)); 127582Srgrimesstatic int vr_detach __P((device_t)); 128582Srgrimes 129582Srgrimesstatic int vr_newbuf __P((struct vr_softc *, 130582Srgrimes struct vr_chain_onefrag *, 131582Srgrimes struct mbuf *)); 132582Srgrimesstatic int vr_encap __P((struct vr_softc *, struct vr_chain *, 133582Srgrimes struct mbuf * )); 134582Srgrimes 135582Srgrimesstatic void vr_rxeof __P((struct vr_softc *)); 136582Srgrimesstatic void vr_rxeoc __P((struct vr_softc *)); 137582Srgrimesstatic void vr_txeof __P((struct vr_softc *)); 138582Srgrimesstatic void vr_txeoc __P((struct vr_softc *)); 139582Srgrimesstatic void vr_tick __P((void *)); 140582Srgrimesstatic void vr_intr __P((void *)); 141582Srgrimesstatic void vr_start __P((struct ifnet *)); 142582Srgrimesstatic int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 143582Srgrimesstatic void vr_init __P((void *)); 144582Srgrimesstatic void vr_stop __P((struct vr_softc *)); 145582Srgrimesstatic void vr_watchdog __P((struct ifnet *)); 146582Srgrimesstatic void vr_shutdown __P((device_t)); 147582Srgrimesstatic int vr_ifmedia_upd __P((struct ifnet *)); 148582Srgrimesstatic void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 149582Srgrimes 150582Srgrimesstatic void vr_mii_sync __P((struct vr_softc *)); 151582Srgrimesstatic void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 152582Srgrimesstatic int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 153582Srgrimesstatic int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 154582Srgrimesstatic int vr_miibus_readreg __P((device_t, int, int)); 155582Srgrimesstatic int vr_miibus_writereg __P((device_t, int, int, int)); 156582Srgrimesstatic void vr_miibus_statchg __P((device_t)); 157582Srgrimes 158582Srgrimesstatic void vr_setcfg __P((struct vr_softc *, int)); 159582Srgrimesstatic u_int8_t vr_calchash __P((u_int8_t *)); 160582Srgrimesstatic void vr_setmulti __P((struct vr_softc *)); 161582Srgrimesstatic void vr_reset __P((struct vr_softc *)); 162582Srgrimesstatic int vr_list_rx_init __P((struct vr_softc *)); 163582Srgrimesstatic int vr_list_tx_init __P((struct vr_softc *)); 164582Srgrimes 165582Srgrimes#ifdef VR_USEIOSPACE 166582Srgrimes#define VR_RES SYS_RES_IOPORT 167582Srgrimes#define VR_RID VR_PCI_LOIO 168582Srgrimes#else 169582Srgrimes#define VR_RES SYS_RES_MEMORY 170582Srgrimes#define VR_RID VR_PCI_LOMEM 171582Srgrimes#endif 172582Srgrimes 173582Srgrimesstatic device_method_t vr_methods[] = { 174582Srgrimes /* Device interface */ 175582Srgrimes DEVMETHOD(device_probe, vr_probe), 176582Srgrimes DEVMETHOD(device_attach, vr_attach), 177582Srgrimes DEVMETHOD(device_detach, vr_detach), 178582Srgrimes DEVMETHOD(device_shutdown, vr_shutdown), 179582Srgrimes 180582Srgrimes /* bus interface */ 181582Srgrimes DEVMETHOD(bus_print_child, bus_generic_print_child), 182582Srgrimes DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183582Srgrimes 184582Srgrimes /* MII interface */ 185582Srgrimes DEVMETHOD(miibus_readreg, vr_miibus_readreg), 186582Srgrimes DEVMETHOD(miibus_writereg, vr_miibus_writereg), 187582Srgrimes DEVMETHOD(miibus_statchg, vr_miibus_statchg), 188582Srgrimes 189582Srgrimes { 0, 0 } 190582Srgrimes}; 191582Srgrimes 192582Srgrimesstatic driver_t vr_driver = { 193582Srgrimes "vr", 194582Srgrimes vr_methods, 195582Srgrimes sizeof(struct vr_softc) 196582Srgrimes}; 197582Srgrimes 198582Srgrimesstatic devclass_t vr_devclass; 199582Srgrimes 200582SrgrimesDRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 201582SrgrimesDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 202582Srgrimes 203582Srgrimes#define VR_SETBIT(sc, reg, x) \ 204582Srgrimes CSR_WRITE_1(sc, reg, \ 205582Srgrimes CSR_READ_1(sc, reg) | x) 206582Srgrimes 207582Srgrimes#define VR_CLRBIT(sc, reg, x) \ 208582Srgrimes CSR_WRITE_1(sc, reg, \ 209582Srgrimes CSR_READ_1(sc, reg) & ~x) 210582Srgrimes 211582Srgrimes#define VR_SETBIT16(sc, reg, x) \ 212582Srgrimes CSR_WRITE_2(sc, reg, \ 213582Srgrimes CSR_READ_2(sc, reg) | x) 214582Srgrimes 215582Srgrimes#define VR_CLRBIT16(sc, reg, x) \ 216582Srgrimes CSR_WRITE_2(sc, reg, \ 217582Srgrimes CSR_READ_2(sc, reg) & ~x) 218582Srgrimes 219582Srgrimes#define VR_SETBIT32(sc, reg, x) \ 220582Srgrimes CSR_WRITE_4(sc, reg, \ 221582Srgrimes CSR_READ_4(sc, reg) | x) 222582Srgrimes 223582Srgrimes#define VR_CLRBIT32(sc, reg, x) \ 224582Srgrimes CSR_WRITE_4(sc, reg, \ 225582Srgrimes CSR_READ_4(sc, reg) & ~x) 226582Srgrimes 227582Srgrimes#define SIO_SET(x) \ 228582Srgrimes CSR_WRITE_1(sc, VR_MIICMD, \ 229582Srgrimes CSR_READ_1(sc, VR_MIICMD) | x) 230582Srgrimes 231582Srgrimes#define SIO_CLR(x) \ 232582Srgrimes CSR_WRITE_1(sc, VR_MIICMD, \ 233582Srgrimes CSR_READ_1(sc, VR_MIICMD) & ~x) 234582Srgrimes 235582Srgrimes/* 236582Srgrimes * Sync the PHYs by setting data bit and strobing the clock 32 times. 237582Srgrimes */ 238582Srgrimesstatic void vr_mii_sync(sc) 239582Srgrimes struct vr_softc *sc; 240582Srgrimes{ 241582Srgrimes register int i; 242582Srgrimes 243582Srgrimes SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 244582Srgrimes 245582Srgrimes for (i = 0; i < 32; i++) { 246582Srgrimes SIO_SET(VR_MIICMD_CLK); 247582Srgrimes DELAY(1); 248582Srgrimes SIO_CLR(VR_MIICMD_CLK); 249582Srgrimes DELAY(1); 250582Srgrimes } 251582Srgrimes 252582Srgrimes return; 253582Srgrimes} 254582Srgrimes 255582Srgrimes/* 256582Srgrimes * Clock a series of bits through the MII. 257582Srgrimes */ 258582Srgrimesstatic void vr_mii_send(sc, bits, cnt) 259582Srgrimes struct vr_softc *sc; 260582Srgrimes u_int32_t bits; 261582Srgrimes int cnt; 262582Srgrimes{ 263582Srgrimes int i; 264582Srgrimes 265582Srgrimes SIO_CLR(VR_MIICMD_CLK); 266582Srgrimes 267582Srgrimes for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 268582Srgrimes if (bits & i) { 269582Srgrimes SIO_SET(VR_MIICMD_DATAIN); 270582Srgrimes } else { 271582Srgrimes SIO_CLR(VR_MIICMD_DATAIN); 272582Srgrimes } 273582Srgrimes DELAY(1); 274582Srgrimes SIO_CLR(VR_MIICMD_CLK); 275582Srgrimes DELAY(1); 276582Srgrimes SIO_SET(VR_MIICMD_CLK); 277582Srgrimes } 278582Srgrimes} 279582Srgrimes 280582Srgrimes/* 281582Srgrimes * Read an PHY register through the MII. 282582Srgrimes */ 283582Srgrimesstatic int vr_mii_readreg(sc, frame) 284582Srgrimes struct vr_softc *sc; 285582Srgrimes struct vr_mii_frame *frame; 286582Srgrimes 287582Srgrimes{ 288582Srgrimes int i, ack, s; 289582Srgrimes 290582Srgrimes s = splimp(); 291582Srgrimes 292582Srgrimes /* 293582Srgrimes * Set up frame for RX. 294582Srgrimes */ 29535210Sbde frame->mii_stdelim = VR_MII_STARTDELIM; 296582Srgrimes frame->mii_opcode = VR_MII_READOP; 297582Srgrimes frame->mii_turnaround = 0; 298582Srgrimes frame->mii_data = 0; 299582Srgrimes 300582Srgrimes CSR_WRITE_1(sc, VR_MIICMD, 0); 301582Srgrimes VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302582Srgrimes 303582Srgrimes /* 304582Srgrimes * Turn on data xmit. 305582Srgrimes */ 306582Srgrimes SIO_SET(VR_MIICMD_DIR); 307582Srgrimes 308582Srgrimes vr_mii_sync(sc); 309582Srgrimes 310582Srgrimes /* 311582Srgrimes * Send command/address info. 31247108Sbde */ 31347108Sbde vr_mii_send(sc, frame->mii_stdelim, 2); 31438232Sbde vr_mii_send(sc, frame->mii_opcode, 2); 315582Srgrimes vr_mii_send(sc, frame->mii_phyaddr, 5); 31647108Sbde vr_mii_send(sc, frame->mii_regaddr, 5); 317582Srgrimes 318582Srgrimes /* Idle bit */ 31947108Sbde SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 32047108Sbde DELAY(1); 32147108Sbde SIO_SET(VR_MIICMD_CLK); 32247108Sbde DELAY(1); 32347108Sbde 32447108Sbde /* Turn off xmit. */ 32547108Sbde SIO_CLR(VR_MIICMD_DIR); 326112734Smdodd 32735210Sbde /* Check for ack */ 328582Srgrimes SIO_CLR(VR_MIICMD_CLK); 329582Srgrimes DELAY(1); 330582Srgrimes SIO_SET(VR_MIICMD_CLK); 331582Srgrimes DELAY(1); 332582Srgrimes ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 333582Srgrimes 334112734Smdodd /* 335 * Now try reading data bits. If the ack failed, we still 336 * need to clock through 16 cycles to keep the PHY(s) in sync. 337 */ 338 if (ack) { 339 for(i = 0; i < 16; i++) { 340 SIO_CLR(VR_MIICMD_CLK); 341 DELAY(1); 342 SIO_SET(VR_MIICMD_CLK); 343 DELAY(1); 344 } 345 goto fail; 346 } 347 348 for (i = 0x8000; i; i >>= 1) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 if (!ack) { 352 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 353 frame->mii_data |= i; 354 DELAY(1); 355 } 356 SIO_SET(VR_MIICMD_CLK); 357 DELAY(1); 358 } 359 360fail: 361 362 SIO_CLR(VR_MIICMD_CLK); 363 DELAY(1); 364 SIO_SET(VR_MIICMD_CLK); 365 DELAY(1); 366 367 splx(s); 368 369 if (ack) 370 return(1); 371 return(0); 372} 373 374/* 375 * Write to a PHY register through the MII. 376 */ 377static int vr_mii_writereg(sc, frame) 378 struct vr_softc *sc; 379 struct vr_mii_frame *frame; 380 381{ 382 int s; 383 384 s = splimp(); 385 386 CSR_WRITE_1(sc, VR_MIICMD, 0); 387 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 388 389 /* 390 * Set up frame for TX. 391 */ 392 393 frame->mii_stdelim = VR_MII_STARTDELIM; 394 frame->mii_opcode = VR_MII_WRITEOP; 395 frame->mii_turnaround = VR_MII_TURNAROUND; 396 397 /* 398 * Turn on data output. 399 */ 400 SIO_SET(VR_MIICMD_DIR); 401 402 vr_mii_sync(sc); 403 404 vr_mii_send(sc, frame->mii_stdelim, 2); 405 vr_mii_send(sc, frame->mii_opcode, 2); 406 vr_mii_send(sc, frame->mii_phyaddr, 5); 407 vr_mii_send(sc, frame->mii_regaddr, 5); 408 vr_mii_send(sc, frame->mii_turnaround, 2); 409 vr_mii_send(sc, frame->mii_data, 16); 410 411 /* Idle bit. */ 412 SIO_SET(VR_MIICMD_CLK); 413 DELAY(1); 414 SIO_CLR(VR_MIICMD_CLK); 415 DELAY(1); 416 417 /* 418 * Turn off xmit. 419 */ 420 SIO_CLR(VR_MIICMD_DIR); 421 422 splx(s); 423 424 return(0); 425} 426 427static int vr_miibus_readreg(dev, phy, reg) 428 device_t dev; 429 int phy, reg; 430{ 431 struct vr_softc *sc; 432 struct vr_mii_frame frame; 433 434 sc = device_get_softc(dev); 435 bzero((char *)&frame, sizeof(frame)); 436 437 frame.mii_phyaddr = phy; 438 frame.mii_regaddr = reg; 439 vr_mii_readreg(sc, &frame); 440 441 return(frame.mii_data); 442} 443 444static int vr_miibus_writereg(dev, phy, reg, data) 445 device_t dev; 446 u_int16_t phy, reg, data; 447{ 448 struct vr_softc *sc; 449 struct vr_mii_frame frame; 450 451 sc = device_get_softc(dev); 452 bzero((char *)&frame, sizeof(frame)); 453 454 frame.mii_phyaddr = phy; 455 frame.mii_regaddr = reg; 456 frame.mii_data = data; 457 458 vr_mii_writereg(sc, &frame); 459 460 return(0); 461} 462 463static void vr_miibus_statchg(dev) 464 device_t dev; 465{ 466 struct vr_softc *sc; 467 struct mii_data *mii; 468 469 sc = device_get_softc(dev); 470 mii = device_get_softc(sc->vr_miibus); 471 vr_setcfg(sc, mii->mii_media_active); 472 473 return; 474} 475 476/* 477 * Calculate CRC of a multicast group address, return the lower 6 bits. 478 */ 479static u_int8_t vr_calchash(addr) 480 u_int8_t *addr; 481{ 482 u_int32_t crc, carry; 483 int i, j; 484 u_int8_t c; 485 486 /* Compute CRC for the address value. */ 487 crc = 0xFFFFFFFF; /* initial value */ 488 489 for (i = 0; i < 6; i++) { 490 c = *(addr + i); 491 for (j = 0; j < 8; j++) { 492 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 493 crc <<= 1; 494 c >>= 1; 495 if (carry) 496 crc = (crc ^ 0x04c11db6) | carry; 497 } 498 } 499 500 /* return the filter bit position */ 501 return((crc >> 26) & 0x0000003F); 502} 503 504/* 505 * Program the 64-bit multicast hash filter. 506 */ 507static void vr_setmulti(sc) 508 struct vr_softc *sc; 509{ 510 struct ifnet *ifp; 511 int h = 0; 512 u_int32_t hashes[2] = { 0, 0 }; 513 struct ifmultiaddr *ifma; 514 u_int8_t rxfilt; 515 int mcnt = 0; 516 517 ifp = &sc->arpcom.ac_if; 518 519 rxfilt = CSR_READ_1(sc, VR_RXCFG); 520 521 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 522 rxfilt |= VR_RXCFG_RX_MULTI; 523 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 524 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 525 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 526 return; 527 } 528 529 /* first, zot all the existing hash bits */ 530 CSR_WRITE_4(sc, VR_MAR0, 0); 531 CSR_WRITE_4(sc, VR_MAR1, 0); 532 533 /* now program new ones */ 534 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 535 ifma = ifma->ifma_link.le_next) { 536 if (ifma->ifma_addr->sa_family != AF_LINK) 537 continue; 538 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 539 if (h < 32) 540 hashes[0] |= (1 << h); 541 else 542 hashes[1] |= (1 << (h - 32)); 543 mcnt++; 544 } 545 546 if (mcnt) 547 rxfilt |= VR_RXCFG_RX_MULTI; 548 else 549 rxfilt &= ~VR_RXCFG_RX_MULTI; 550 551 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 552 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 553 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 554 555 return; 556} 557 558/* 559 * In order to fiddle with the 560 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 561 * first have to put the transmit and/or receive logic in the idle state. 562 */ 563static void vr_setcfg(sc, media) 564 struct vr_softc *sc; 565 int media; 566{ 567 int restart = 0; 568 569 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 570 restart = 1; 571 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 572 } 573 574 if ((media & IFM_GMASK) == IFM_FDX) 575 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 else 577 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 578 579 if (restart) 580 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 581 582 return; 583} 584 585static void vr_reset(sc) 586 struct vr_softc *sc; 587{ 588 register int i; 589 590 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 591 592 for (i = 0; i < VR_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 595 break; 596 } 597 if (i == VR_TIMEOUT) 598 printf("vr%d: reset never completed!\n", sc->vr_unit); 599 600 /* Wait a little while for the chip to get its brains in order. */ 601 DELAY(1000); 602 603 return; 604} 605 606/* 607 * Probe for a VIA Rhine chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 */ 610static int vr_probe(dev) 611 device_t dev; 612{ 613 struct vr_type *t; 614 615 t = vr_devs; 616 617 while(t->vr_name != NULL) { 618 if ((pci_get_vendor(dev) == t->vr_vid) && 619 (pci_get_device(dev) == t->vr_did)) { 620 device_set_desc(dev, t->vr_name); 621 return(0); 622 } 623 t++; 624 } 625 626 return(ENXIO); 627} 628 629/* 630 * Attach the interface. Allocate softc structures, do ifmedia 631 * setup and ethernet/BPF attach. 632 */ 633static int vr_attach(dev) 634 device_t dev; 635{ 636 int i, s; 637 u_char eaddr[ETHER_ADDR_LEN]; 638 u_int32_t command; 639 struct vr_softc *sc; 640 struct ifnet *ifp; 641 int unit, error = 0, rid; 642 643 s = splimp(); 644 645 sc = device_get_softc(dev); 646 unit = device_get_unit(dev); 647 bzero(sc, sizeof(struct vr_softc *)); 648 649 /* 650 * Handle power management nonsense. 651 */ 652 653 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 654 if (command == 0x01) { 655 656 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 657 if (command & VR_PSTATE_MASK) { 658 u_int32_t iobase, membase, irq; 659 660 /* Save important PCI config data. */ 661 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 662 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 663 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 664 665 /* Reset the power state. */ 666 printf("vr%d: chip is in D%d power mode " 667 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 668 command &= 0xFFFFFFFC; 669 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 670 671 /* Restore PCI config data. */ 672 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 673 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 674 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 675 } 676 } 677 678 /* 679 * Map control/status registers. 680 */ 681 command = pci_read_config(dev, PCIR_COMMAND, 4); 682 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 683 pci_write_config(dev, PCIR_COMMAND, command, 4); 684 command = pci_read_config(dev, PCIR_COMMAND, 4); 685 686#ifdef VR_USEIOSPACE 687 if (!(command & PCIM_CMD_PORTEN)) { 688 printf("vr%d: failed to enable I/O ports!\n", unit); 689 free(sc, M_DEVBUF); 690 goto fail; 691 } 692#else 693 if (!(command & PCIM_CMD_MEMEN)) { 694 printf("vr%d: failed to enable memory mapping!\n", unit); 695 goto fail; 696 } 697#endif 698 699 rid = VR_RID; 700 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 701 0, ~0, 1, RF_ACTIVE); 702 703 if (sc->vr_res == NULL) { 704 printf("vr%d: couldn't map ports/memory\n", unit); 705 error = ENXIO; 706 goto fail; 707 } 708 709 sc->vr_btag = rman_get_bustag(sc->vr_res); 710 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 711 712 /* Allocate interrupt */ 713 rid = 0; 714 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 715 RF_SHAREABLE | RF_ACTIVE); 716 717 if (sc->vr_irq == NULL) { 718 printf("vr%d: couldn't map interrupt\n", unit); 719 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 720 error = ENXIO; 721 goto fail; 722 } 723 724 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 725 vr_intr, sc, &sc->vr_intrhand); 726 727 if (error) { 728 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 729 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 730 printf("vr%d: couldn't set up irq\n", unit); 731 goto fail; 732 } 733 734 /* Reset the adapter. */ 735 vr_reset(sc); 736 737 /* 738 * Get station address. The way the Rhine chips work, 739 * you're not allowed to directly access the EEPROM once 740 * they've been programmed a special way. Consequently, 741 * we need to read the node address from the PAR0 and PAR1 742 * registers. 743 */ 744 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 745 DELAY(200); 746 for (i = 0; i < ETHER_ADDR_LEN; i++) 747 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 748 749 /* 750 * A Rhine chip was detected. Inform the world. 751 */ 752 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 753 754 sc->vr_unit = unit; 755 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 756 757 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 758 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 759 760 if (sc->vr_ldata == NULL) { 761 printf("vr%d: no memory for list buffers!\n", unit); 762 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 764 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 765 error = ENXIO; 766 goto fail; 767 } 768 769 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 770 771 ifp = &sc->arpcom.ac_if; 772 ifp->if_softc = sc; 773 ifp->if_unit = unit; 774 ifp->if_name = "vr"; 775 ifp->if_mtu = ETHERMTU; 776 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 777 ifp->if_ioctl = vr_ioctl; 778 ifp->if_output = ether_output; 779 ifp->if_start = vr_start; 780 ifp->if_watchdog = vr_watchdog; 781 ifp->if_init = vr_init; 782 ifp->if_baudrate = 10000000; 783 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 784 785 /* 786 * Do MII setup. 787 */ 788 if (mii_phy_probe(dev, &sc->vr_miibus, 789 vr_ifmedia_upd, vr_ifmedia_sts)) { 790 printf("vr%d: MII without any phy!\n", sc->vr_unit); 791 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 793 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 794 contigfree(sc->vr_ldata, 795 sizeof(struct vr_list_data), M_DEVBUF); 796 error = ENXIO; 797 goto fail; 798 } 799 800 callout_handle_init(&sc->vr_stat_ch); 801 802 /* 803 * Call MI attach routine. 804 */ 805 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 806 807fail: 808 splx(s); 809 return(error); 810} 811 812static int vr_detach(dev) 813 device_t dev; 814{ 815 struct vr_softc *sc; 816 struct ifnet *ifp; 817 int s; 818 819 s = splimp(); 820 821 sc = device_get_softc(dev); 822 ifp = &sc->arpcom.ac_if; 823 824 vr_stop(sc); 825 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 826 827 bus_generic_detach(dev); 828 device_delete_child(dev, sc->vr_miibus); 829 830 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 831 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 832 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 833 834 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 835 836 splx(s); 837 838 return(0); 839} 840 841/* 842 * Initialize the transmit descriptors. 843 */ 844static int vr_list_tx_init(sc) 845 struct vr_softc *sc; 846{ 847 struct vr_chain_data *cd; 848 struct vr_list_data *ld; 849 int i; 850 851 cd = &sc->vr_cdata; 852 ld = sc->vr_ldata; 853 for (i = 0; i < VR_TX_LIST_CNT; i++) { 854 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 855 if (i == (VR_TX_LIST_CNT - 1)) 856 cd->vr_tx_chain[i].vr_nextdesc = 857 &cd->vr_tx_chain[0]; 858 else 859 cd->vr_tx_chain[i].vr_nextdesc = 860 &cd->vr_tx_chain[i + 1]; 861 } 862 863 cd->vr_tx_free = &cd->vr_tx_chain[0]; 864 cd->vr_tx_tail = cd->vr_tx_head = NULL; 865 866 return(0); 867} 868 869 870/* 871 * Initialize the RX descriptors and allocate mbufs for them. Note that 872 * we arrange the descriptors in a closed ring, so that the last descriptor 873 * points back to the first. 874 */ 875static int vr_list_rx_init(sc) 876 struct vr_softc *sc; 877{ 878 struct vr_chain_data *cd; 879 struct vr_list_data *ld; 880 int i; 881 882 cd = &sc->vr_cdata; 883 ld = sc->vr_ldata; 884 885 for (i = 0; i < VR_RX_LIST_CNT; i++) { 886 cd->vr_rx_chain[i].vr_ptr = 887 (struct vr_desc *)&ld->vr_rx_list[i]; 888 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 889 return(ENOBUFS); 890 if (i == (VR_RX_LIST_CNT - 1)) { 891 cd->vr_rx_chain[i].vr_nextdesc = 892 &cd->vr_rx_chain[0]; 893 ld->vr_rx_list[i].vr_next = 894 vtophys(&ld->vr_rx_list[0]); 895 } else { 896 cd->vr_rx_chain[i].vr_nextdesc = 897 &cd->vr_rx_chain[i + 1]; 898 ld->vr_rx_list[i].vr_next = 899 vtophys(&ld->vr_rx_list[i + 1]); 900 } 901 } 902 903 cd->vr_rx_head = &cd->vr_rx_chain[0]; 904 905 return(0); 906} 907 908/* 909 * Initialize an RX descriptor and attach an MBUF cluster. 910 * Note: the length fields are only 11 bits wide, which means the 911 * largest size we can specify is 2047. This is important because 912 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 913 * overflow the field and make a mess. 914 */ 915static int vr_newbuf(sc, c, m) 916 struct vr_softc *sc; 917 struct vr_chain_onefrag *c; 918 struct mbuf *m; 919{ 920 struct mbuf *m_new = NULL; 921 922 if (m == NULL) { 923 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 924 if (m_new == NULL) { 925 printf("vr%d: no memory for rx list " 926 "-- packet dropped!\n", sc->vr_unit); 927 return(ENOBUFS); 928 } 929 930 MCLGET(m_new, M_DONTWAIT); 931 if (!(m_new->m_flags & M_EXT)) { 932 printf("vr%d: no memory for rx list " 933 "-- packet dropped!\n", sc->vr_unit); 934 m_freem(m_new); 935 return(ENOBUFS); 936 } 937 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 938 } else { 939 m_new = m; 940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 941 m_new->m_data = m_new->m_ext.ext_buf; 942 } 943 944 m_adj(m_new, sizeof(u_int64_t)); 945 946 c->vr_mbuf = m_new; 947 c->vr_ptr->vr_status = VR_RXSTAT; 948 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 949 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 950 951 return(0); 952} 953 954/* 955 * A frame has been uploaded: pass the resulting mbuf chain up to 956 * the higher level protocols. 957 */ 958static void vr_rxeof(sc) 959 struct vr_softc *sc; 960{ 961 struct ether_header *eh; 962 struct mbuf *m; 963 struct ifnet *ifp; 964 struct vr_chain_onefrag *cur_rx; 965 int total_len = 0; 966 u_int32_t rxstat; 967 968 ifp = &sc->arpcom.ac_if; 969 970 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 971 VR_RXSTAT_OWN)) { 972 struct mbuf *m0 = NULL; 973 974 cur_rx = sc->vr_cdata.vr_rx_head; 975 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 976 m = cur_rx->vr_mbuf; 977 978 /* 979 * If an error occurs, update stats, clear the 980 * status word and leave the mbuf cluster in place: 981 * it should simply get re-used next time this descriptor 982 * comes up in the ring. 983 */ 984 if (rxstat & VR_RXSTAT_RXERR) { 985 ifp->if_ierrors++; 986 printf("vr%d: rx error: ", sc->vr_unit); 987 switch(rxstat & 0x000000FF) { 988 case VR_RXSTAT_CRCERR: 989 printf("crc error\n"); 990 break; 991 case VR_RXSTAT_FRAMEALIGNERR: 992 printf("frame alignment error\n"); 993 break; 994 case VR_RXSTAT_FIFOOFLOW: 995 printf("FIFO overflow\n"); 996 break; 997 case VR_RXSTAT_GIANT: 998 printf("received giant packet\n"); 999 break; 1000 case VR_RXSTAT_RUNT: 1001 printf("received runt packet\n"); 1002 break; 1003 case VR_RXSTAT_BUSERR: 1004 printf("system bus error\n"); 1005 break; 1006 case VR_RXSTAT_BUFFERR: 1007 printf("rx buffer error\n"); 1008 break; 1009 default: 1010 printf("unknown rx error\n"); 1011 break; 1012 } 1013 vr_newbuf(sc, cur_rx, m); 1014 continue; 1015 } 1016 1017 /* No errors; receive the packet. */ 1018 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1019 1020 /* 1021 * XXX The VIA Rhine chip includes the CRC with every 1022 * received frame, and there's no way to turn this 1023 * behavior off (at least, I can't find anything in 1024 * the manual that explains how to do it) so we have 1025 * to trim off the CRC manually. 1026 */ 1027 total_len -= ETHER_CRC_LEN; 1028 1029 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1030 total_len + ETHER_ALIGN, 0, ifp, NULL); 1031 vr_newbuf(sc, cur_rx, m); 1032 if (m0 == NULL) { 1033 ifp->if_ierrors++; 1034 continue; 1035 } 1036 m_adj(m0, ETHER_ALIGN); 1037 m = m0; 1038 1039 ifp->if_ipackets++; 1040 eh = mtod(m, struct ether_header *); 1041 1042 /* Remove header from mbuf and pass it on. */ 1043 m_adj(m, sizeof(struct ether_header)); 1044 ether_input(ifp, eh, m); 1045 } 1046 1047 return; 1048} 1049 1050void vr_rxeoc(sc) 1051 struct vr_softc *sc; 1052{ 1053 1054 vr_rxeof(sc); 1055 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1056 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1057 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1058 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1059 1060 return; 1061} 1062 1063/* 1064 * A frame was downloaded to the chip. It's safe for us to clean up 1065 * the list buffers. 1066 */ 1067 1068static void vr_txeof(sc) 1069 struct vr_softc *sc; 1070{ 1071 struct vr_chain *cur_tx; 1072 struct ifnet *ifp; 1073 1074 ifp = &sc->arpcom.ac_if; 1075 1076 /* Clear the timeout timer. */ 1077 ifp->if_timer = 0; 1078 1079 /* Sanity check. */ 1080 if (sc->vr_cdata.vr_tx_head == NULL) 1081 return; 1082 1083 /* 1084 * Go through our tx list and free mbufs for those 1085 * frames that have been transmitted. 1086 */ 1087 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1088 u_int32_t txstat; 1089 1090 cur_tx = sc->vr_cdata.vr_tx_head; 1091 txstat = cur_tx->vr_ptr->vr_status; 1092 1093 if (txstat & VR_TXSTAT_OWN) 1094 break; 1095 1096 if (txstat & VR_TXSTAT_ERRSUM) { 1097 ifp->if_oerrors++; 1098 if (txstat & VR_TXSTAT_DEFER) 1099 ifp->if_collisions++; 1100 if (txstat & VR_TXSTAT_LATECOLL) 1101 ifp->if_collisions++; 1102 } 1103 1104 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1105 1106 ifp->if_opackets++; 1107 if (cur_tx->vr_mbuf != NULL) { 1108 m_freem(cur_tx->vr_mbuf); 1109 cur_tx->vr_mbuf = NULL; 1110 } 1111 1112 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1113 sc->vr_cdata.vr_tx_head = NULL; 1114 sc->vr_cdata.vr_tx_tail = NULL; 1115 break; 1116 } 1117 1118 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1119 } 1120 1121 return; 1122} 1123 1124/* 1125 * TX 'end of channel' interrupt handler. 1126 */ 1127static void vr_txeoc(sc) 1128 struct vr_softc *sc; 1129{ 1130 struct ifnet *ifp; 1131 1132 ifp = &sc->arpcom.ac_if; 1133 1134 ifp->if_timer = 0; 1135 1136 if (sc->vr_cdata.vr_tx_head == NULL) { 1137 ifp->if_flags &= ~IFF_OACTIVE; 1138 sc->vr_cdata.vr_tx_tail = NULL; 1139 } 1140 1141 return; 1142} 1143 1144static void vr_tick(xsc) 1145 void *xsc; 1146{ 1147 struct vr_softc *sc; 1148 struct mii_data *mii; 1149 int s; 1150 1151 s = splimp(); 1152 1153 sc = xsc; 1154 mii = device_get_softc(sc->vr_miibus); 1155 mii_tick(mii); 1156 1157 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1158 1159 splx(s); 1160 1161 return; 1162} 1163 1164static void vr_intr(arg) 1165 void *arg; 1166{ 1167 struct vr_softc *sc; 1168 struct ifnet *ifp; 1169 u_int16_t status; 1170 1171 sc = arg; 1172 ifp = &sc->arpcom.ac_if; 1173 1174 /* Supress unwanted interrupts. */ 1175 if (!(ifp->if_flags & IFF_UP)) { 1176 vr_stop(sc); 1177 return; 1178 } 1179 1180 /* Disable interrupts. */ 1181 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1182 1183 for (;;) { 1184 1185 status = CSR_READ_2(sc, VR_ISR); 1186 if (status) 1187 CSR_WRITE_2(sc, VR_ISR, status); 1188 1189 if ((status & VR_INTRS) == 0) 1190 break; 1191 1192 if (status & VR_ISR_RX_OK) 1193 vr_rxeof(sc); 1194 1195 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1196 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1197 (status & VR_ISR_RX_DROPPED)) { 1198 vr_rxeof(sc); 1199 vr_rxeoc(sc); 1200 } 1201 1202 if (status & VR_ISR_TX_OK) { 1203 vr_txeof(sc); 1204 vr_txeoc(sc); 1205 } 1206 1207 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1208 ifp->if_oerrors++; 1209 vr_txeof(sc); 1210 if (sc->vr_cdata.vr_tx_head != NULL) { 1211 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1212 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1213 } 1214 } 1215 1216 if (status & VR_ISR_BUSERR) { 1217 vr_reset(sc); 1218 vr_init(sc); 1219 } 1220 } 1221 1222 /* Re-enable interrupts. */ 1223 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1224 1225 if (ifp->if_snd.ifq_head != NULL) { 1226 vr_start(ifp); 1227 } 1228 1229 return; 1230} 1231 1232/* 1233 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1234 * pointers to the fragment pointers. 1235 */ 1236static int vr_encap(sc, c, m_head) 1237 struct vr_softc *sc; 1238 struct vr_chain *c; 1239 struct mbuf *m_head; 1240{ 1241 int frag = 0; 1242 struct vr_desc *f = NULL; 1243 int total_len; 1244 struct mbuf *m; 1245 1246 m = m_head; 1247 total_len = 0; 1248 1249 /* 1250 * The VIA Rhine wants packet buffers to be longword 1251 * aligned, but very often our mbufs aren't. Rather than 1252 * waste time trying to decide when to copy and when not 1253 * to copy, just do it all the time. 1254 */ 1255 if (m != NULL) { 1256 struct mbuf *m_new = NULL; 1257 1258 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1259 if (m_new == NULL) { 1260 printf("vr%d: no memory for tx list", sc->vr_unit); 1261 return(1); 1262 } 1263 if (m_head->m_pkthdr.len > MHLEN) { 1264 MCLGET(m_new, M_DONTWAIT); 1265 if (!(m_new->m_flags & M_EXT)) { 1266 m_freem(m_new); 1267 printf("vr%d: no memory for tx list", 1268 sc->vr_unit); 1269 return(1); 1270 } 1271 } 1272 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1273 mtod(m_new, caddr_t)); 1274 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1275 m_freem(m_head); 1276 m_head = m_new; 1277 /* 1278 * The Rhine chip doesn't auto-pad, so we have to make 1279 * sure to pad short frames out to the minimum frame length 1280 * ourselves. 1281 */ 1282 if (m_head->m_len < VR_MIN_FRAMELEN) { 1283 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1284 m_new->m_len = m_new->m_pkthdr.len; 1285 } 1286 f = c->vr_ptr; 1287 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1288 f->vr_ctl = total_len = m_new->m_len; 1289 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1290 f->vr_status = 0; 1291 frag = 1; 1292 } 1293 1294 c->vr_mbuf = m_head; 1295 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1296 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1297 1298 return(0); 1299} 1300 1301/* 1302 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1303 * to the mbuf data regions directly in the transmit lists. We also save a 1304 * copy of the pointers since the transmit list fragment pointers are 1305 * physical addresses. 1306 */ 1307 1308static void vr_start(ifp) 1309 struct ifnet *ifp; 1310{ 1311 struct vr_softc *sc; 1312 struct mbuf *m_head = NULL; 1313 struct vr_chain *cur_tx = NULL, *start_tx; 1314 1315 sc = ifp->if_softc; 1316 1317 if (ifp->if_flags & IFF_OACTIVE) 1318 return; 1319 1320 /* 1321 * Check for an available queue slot. If there are none, 1322 * punt. 1323 */ 1324 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1325 ifp->if_flags |= IFF_OACTIVE; 1326 return; 1327 } 1328 1329 start_tx = sc->vr_cdata.vr_tx_free; 1330 1331 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1332 IF_DEQUEUE(&ifp->if_snd, m_head); 1333 if (m_head == NULL) 1334 break; 1335 1336 /* Pick a descriptor off the free list. */ 1337 cur_tx = sc->vr_cdata.vr_tx_free; 1338 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1339 1340 /* Pack the data into the descriptor. */ 1341 vr_encap(sc, cur_tx, m_head); 1342 1343 if (cur_tx != start_tx) 1344 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1345 1346 /* 1347 * If there's a BPF listener, bounce a copy of this frame 1348 * to him. 1349 */ 1350 if (ifp->if_bpf) 1351 bpf_mtap(ifp, cur_tx->vr_mbuf); 1352 1353 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1354 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1355 } 1356 1357 /* 1358 * If there are no frames queued, bail. 1359 */ 1360 if (cur_tx == NULL) 1361 return; 1362 1363 sc->vr_cdata.vr_tx_tail = cur_tx; 1364 1365 if (sc->vr_cdata.vr_tx_head == NULL) 1366 sc->vr_cdata.vr_tx_head = start_tx; 1367 1368 /* 1369 * Set a timeout in case the chip goes out to lunch. 1370 */ 1371 ifp->if_timer = 5; 1372 1373 return; 1374} 1375 1376static void vr_init(xsc) 1377 void *xsc; 1378{ 1379 struct vr_softc *sc = xsc; 1380 struct ifnet *ifp = &sc->arpcom.ac_if; 1381 struct mii_data *mii; 1382 int s; 1383 1384 s = splimp(); 1385 1386 mii = device_get_softc(sc->vr_miibus); 1387 1388 /* 1389 * Cancel pending I/O and free all RX/TX buffers. 1390 */ 1391 vr_stop(sc); 1392 vr_reset(sc); 1393 1394 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1395 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1396 1397 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1398 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1399 1400 /* Init circular RX list. */ 1401 if (vr_list_rx_init(sc) == ENOBUFS) { 1402 printf("vr%d: initialization failed: no " 1403 "memory for rx buffers\n", sc->vr_unit); 1404 vr_stop(sc); 1405 (void)splx(s); 1406 return; 1407 } 1408 1409 /* 1410 * Init tx descriptors. 1411 */ 1412 vr_list_tx_init(sc); 1413 1414 /* If we want promiscuous mode, set the allframes bit. */ 1415 if (ifp->if_flags & IFF_PROMISC) 1416 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1417 else 1418 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1419 1420 /* Set capture broadcast bit to capture broadcast frames. */ 1421 if (ifp->if_flags & IFF_BROADCAST) 1422 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1423 else 1424 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1425 1426 /* 1427 * Program the multicast filter, if necessary. 1428 */ 1429 vr_setmulti(sc); 1430 1431 /* 1432 * Load the address of the RX list. 1433 */ 1434 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1435 1436 /* Enable receiver and transmitter. */ 1437 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1438 VR_CMD_TX_ON|VR_CMD_RX_ON| 1439 VR_CMD_RX_GO); 1440 1441 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1442 1443 /* 1444 * Enable interrupts. 1445 */ 1446 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1447 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1448 1449 mii_mediachg(mii); 1450 1451 ifp->if_flags |= IFF_RUNNING; 1452 ifp->if_flags &= ~IFF_OACTIVE; 1453 1454 (void)splx(s); 1455 1456 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1457 1458 return; 1459} 1460 1461/* 1462 * Set media options. 1463 */ 1464static int vr_ifmedia_upd(ifp) 1465 struct ifnet *ifp; 1466{ 1467 struct vr_softc *sc; 1468 1469 sc = ifp->if_softc; 1470 1471 if (ifp->if_flags & IFF_UP) 1472 vr_init(sc); 1473 1474 return(0); 1475} 1476 1477/* 1478 * Report current media status. 1479 */ 1480static void vr_ifmedia_sts(ifp, ifmr) 1481 struct ifnet *ifp; 1482 struct ifmediareq *ifmr; 1483{ 1484 struct vr_softc *sc; 1485 struct mii_data *mii; 1486 1487 sc = ifp->if_softc; 1488 mii = device_get_softc(sc->vr_miibus); 1489 mii_pollstat(mii); 1490 ifmr->ifm_active = mii->mii_media_active; 1491 ifmr->ifm_status = mii->mii_media_status; 1492 1493 return; 1494} 1495 1496static int vr_ioctl(ifp, command, data) 1497 struct ifnet *ifp; 1498 u_long command; 1499 caddr_t data; 1500{ 1501 struct vr_softc *sc = ifp->if_softc; 1502 struct ifreq *ifr = (struct ifreq *) data; 1503 struct mii_data *mii; 1504 int s, error = 0; 1505 1506 s = splimp(); 1507 1508 switch(command) { 1509 case SIOCSIFADDR: 1510 case SIOCGIFADDR: 1511 case SIOCSIFMTU: 1512 error = ether_ioctl(ifp, command, data); 1513 break; 1514 case SIOCSIFFLAGS: 1515 if (ifp->if_flags & IFF_UP) { 1516 vr_init(sc); 1517 } else { 1518 if (ifp->if_flags & IFF_RUNNING) 1519 vr_stop(sc); 1520 } 1521 error = 0; 1522 break; 1523 case SIOCADDMULTI: 1524 case SIOCDELMULTI: 1525 vr_setmulti(sc); 1526 error = 0; 1527 break; 1528 case SIOCGIFMEDIA: 1529 case SIOCSIFMEDIA: 1530 mii = device_get_softc(sc->vr_miibus); 1531 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1532 break; 1533 default: 1534 error = EINVAL; 1535 break; 1536 } 1537 1538 (void)splx(s); 1539 1540 return(error); 1541} 1542 1543static void vr_watchdog(ifp) 1544 struct ifnet *ifp; 1545{ 1546 struct vr_softc *sc; 1547 1548 sc = ifp->if_softc; 1549 1550 ifp->if_oerrors++; 1551 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1552 1553 vr_stop(sc); 1554 vr_reset(sc); 1555 vr_init(sc); 1556 1557 if (ifp->if_snd.ifq_head != NULL) 1558 vr_start(ifp); 1559 1560 return; 1561} 1562 1563/* 1564 * Stop the adapter and free any mbufs allocated to the 1565 * RX and TX lists. 1566 */ 1567static void vr_stop(sc) 1568 struct vr_softc *sc; 1569{ 1570 register int i; 1571 struct ifnet *ifp; 1572 1573 ifp = &sc->arpcom.ac_if; 1574 ifp->if_timer = 0; 1575 1576 untimeout(vr_tick, sc, sc->vr_stat_ch); 1577 1578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1579 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1580 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1581 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1582 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1583 1584 /* 1585 * Free data in the RX lists. 1586 */ 1587 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1588 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1589 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1590 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1591 } 1592 } 1593 bzero((char *)&sc->vr_ldata->vr_rx_list, 1594 sizeof(sc->vr_ldata->vr_rx_list)); 1595 1596 /* 1597 * Free the TX list buffers. 1598 */ 1599 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1600 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1601 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1602 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1603 } 1604 } 1605 1606 bzero((char *)&sc->vr_ldata->vr_tx_list, 1607 sizeof(sc->vr_ldata->vr_tx_list)); 1608 1609 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1610 1611 return; 1612} 1613 1614/* 1615 * Stop all chip I/O so that the kernel's probe routines don't 1616 * get confused by errant DMAs when rebooting. 1617 */ 1618static void vr_shutdown(dev) 1619 device_t dev; 1620{ 1621 struct vr_softc *sc; 1622 1623 sc = device_get_softc(dev); 1624 1625 vr_stop(sc); 1626 1627 return; 1628} 1629