if_vr.c revision 51583
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/vr/if_vr.c 51583 1999-09-23 03:32:57Z wpaul $ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3741502Swpaul * 3841502Swpaul * Supports various network adapters based on the VIA Rhine 3941502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4041502Swpaul * Datasheets are available at http://www.via.com.tw. 4141502Swpaul * 4241502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4341502Swpaul * Electrical Engineering Department 4441502Swpaul * Columbia University, New York City 4541502Swpaul */ 4641502Swpaul 4741502Swpaul/* 4841502Swpaul * The VIA Rhine controllers are similar in some respects to the 4941502Swpaul * the DEC tulip chips, except less complicated. The controller 5041502Swpaul * uses an MII bus and an external physical layer interface. The 5141502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5241502Swpaul * multicast filter. Transmit and receive descriptors are similar 5341502Swpaul * to the tulip. 5441502Swpaul * 5541502Swpaul * The Rhine has a serious flaw in its transmit DMA mechanism: 5641502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5741502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5841502Swpaul * at longword boundaries, so we have to do a buffer copy before 5941502Swpaul * transmission. 6041502Swpaul */ 6141502Swpaul 6241502Swpaul#include <sys/param.h> 6341502Swpaul#include <sys/systm.h> 6441502Swpaul#include <sys/sockio.h> 6541502Swpaul#include <sys/mbuf.h> 6641502Swpaul#include <sys/malloc.h> 6741502Swpaul#include <sys/kernel.h> 6841502Swpaul#include <sys/socket.h> 6941502Swpaul 7041502Swpaul#include <net/if.h> 7141502Swpaul#include <net/if_arp.h> 7241502Swpaul#include <net/ethernet.h> 7341502Swpaul#include <net/if_dl.h> 7441502Swpaul#include <net/if_media.h> 7541502Swpaul 7641502Swpaul#include <net/bpf.h> 7741502Swpaul 7851354Swpaul#include "opt_bdg.h" 7951354Swpaul#ifdef BRIDGE 8051354Swpaul#include <net/bridge.h> 8151354Swpaul#endif /* BRIDGE */ 8251354Swpaul 8341502Swpaul#include <vm/vm.h> /* for vtophys */ 8441502Swpaul#include <vm/pmap.h> /* for vtophys */ 8541502Swpaul#include <machine/clock.h> /* for DELAY */ 8641502Swpaul#include <machine/bus_pio.h> 8741502Swpaul#include <machine/bus_memio.h> 8841502Swpaul#include <machine/bus.h> 8949610Swpaul#include <machine/resource.h> 9049610Swpaul#include <sys/bus.h> 9149610Swpaul#include <sys/rman.h> 9241502Swpaul 9351432Swpaul#include <dev/mii/mii.h> 9451432Swpaul#include <dev/mii/miivar.h> 9551432Swpaul 9641502Swpaul#include <pci/pcireg.h> 9741502Swpaul#include <pci/pcivar.h> 9841502Swpaul 9941502Swpaul#define VR_USEIOSPACE 10041502Swpaul 10141502Swpaul#include <pci/if_vrreg.h> 10241502Swpaul 10351432Swpaul/* "controller miibus0" required. See GENERIC if you get errors here. */ 10451432Swpaul#include "miibus_if.h" 10551432Swpaul 10641502Swpaul#ifndef lint 10741591Sarchiestatic const char rcsid[] = 10850477Speter "$FreeBSD: head/sys/dev/vr/if_vr.c 51583 1999-09-23 03:32:57Z wpaul $"; 10941502Swpaul#endif 11041502Swpaul 11141502Swpaul/* 11241502Swpaul * Various supported device vendors/types and their names. 11341502Swpaul */ 11441502Swpaulstatic struct vr_type vr_devs[] = { 11541502Swpaul { VIA_VENDORID, VIA_DEVICEID_RHINE, 11641502Swpaul "VIA VT3043 Rhine I 10/100BaseTX" }, 11741502Swpaul { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 11841502Swpaul "VIA VT86C100A Rhine II 10/100BaseTX" }, 11944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 12044238Swpaul "Delta Electronics Rhine II 10/100BaseTX" }, 12144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 12244238Swpaul "Addtron Technology Rhine II 10/100BaseTX" }, 12341502Swpaul { 0, 0, NULL } 12441502Swpaul}; 12541502Swpaul 12649610Swpaulstatic int vr_probe __P((device_t)); 12749610Swpaulstatic int vr_attach __P((device_t)); 12849610Swpaulstatic int vr_detach __P((device_t)); 12941502Swpaul 13041502Swpaulstatic int vr_newbuf __P((struct vr_softc *, 13149610Swpaul struct vr_chain_onefrag *, 13249610Swpaul struct mbuf *)); 13341502Swpaulstatic int vr_encap __P((struct vr_softc *, struct vr_chain *, 13441502Swpaul struct mbuf * )); 13541502Swpaul 13641502Swpaulstatic void vr_rxeof __P((struct vr_softc *)); 13741502Swpaulstatic void vr_rxeoc __P((struct vr_softc *)); 13841502Swpaulstatic void vr_txeof __P((struct vr_softc *)); 13941502Swpaulstatic void vr_txeoc __P((struct vr_softc *)); 14051432Swpaulstatic void vr_tick __P((void *)); 14141502Swpaulstatic void vr_intr __P((void *)); 14241502Swpaulstatic void vr_start __P((struct ifnet *)); 14341502Swpaulstatic int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 14441502Swpaulstatic void vr_init __P((void *)); 14541502Swpaulstatic void vr_stop __P((struct vr_softc *)); 14641502Swpaulstatic void vr_watchdog __P((struct ifnet *)); 14749610Swpaulstatic void vr_shutdown __P((device_t)); 14841502Swpaulstatic int vr_ifmedia_upd __P((struct ifnet *)); 14941502Swpaulstatic void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 15041502Swpaul 15141502Swpaulstatic void vr_mii_sync __P((struct vr_softc *)); 15241502Swpaulstatic void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 15341502Swpaulstatic int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 15441502Swpaulstatic int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 15551432Swpaulstatic int vr_miibus_readreg __P((device_t, int, int)); 15651432Swpaulstatic int vr_miibus_writereg __P((device_t, int, int, int)); 15751432Swpaulstatic void vr_miibus_statchg __P((device_t)); 15841502Swpaul 15951432Swpaulstatic void vr_setcfg __P((struct vr_softc *, int)); 16041502Swpaulstatic u_int8_t vr_calchash __P((u_int8_t *)); 16141502Swpaulstatic void vr_setmulti __P((struct vr_softc *)); 16241502Swpaulstatic void vr_reset __P((struct vr_softc *)); 16341502Swpaulstatic int vr_list_rx_init __P((struct vr_softc *)); 16441502Swpaulstatic int vr_list_tx_init __P((struct vr_softc *)); 16541502Swpaul 16649610Swpaul#ifdef VR_USEIOSPACE 16749610Swpaul#define VR_RES SYS_RES_IOPORT 16849610Swpaul#define VR_RID VR_PCI_LOIO 16949610Swpaul#else 17049610Swpaul#define VR_RES SYS_RES_MEMORY 17149610Swpaul#define VR_RID VR_PCI_LOMEM 17249610Swpaul#endif 17349610Swpaul 17449610Swpaulstatic device_method_t vr_methods[] = { 17549610Swpaul /* Device interface */ 17649610Swpaul DEVMETHOD(device_probe, vr_probe), 17749610Swpaul DEVMETHOD(device_attach, vr_attach), 17849610Swpaul DEVMETHOD(device_detach, vr_detach), 17949610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 18051432Swpaul 18151432Swpaul /* bus interface */ 18251432Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18351432Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18451432Swpaul 18551432Swpaul /* MII interface */ 18651432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 18751432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 18851432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 18951432Swpaul 19049610Swpaul { 0, 0 } 19149610Swpaul}; 19249610Swpaul 19349610Swpaulstatic driver_t vr_driver = { 19451455Swpaul "vr", 19549610Swpaul vr_methods, 19649610Swpaul sizeof(struct vr_softc) 19749610Swpaul}; 19849610Swpaul 19949610Swpaulstatic devclass_t vr_devclass; 20049610Swpaul 20151533SwpaulDRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 20251473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 20349610Swpaul 20441502Swpaul#define VR_SETBIT(sc, reg, x) \ 20541502Swpaul CSR_WRITE_1(sc, reg, \ 20641502Swpaul CSR_READ_1(sc, reg) | x) 20741502Swpaul 20841502Swpaul#define VR_CLRBIT(sc, reg, x) \ 20941502Swpaul CSR_WRITE_1(sc, reg, \ 21041502Swpaul CSR_READ_1(sc, reg) & ~x) 21141502Swpaul 21241502Swpaul#define VR_SETBIT16(sc, reg, x) \ 21341502Swpaul CSR_WRITE_2(sc, reg, \ 21441502Swpaul CSR_READ_2(sc, reg) | x) 21541502Swpaul 21641502Swpaul#define VR_CLRBIT16(sc, reg, x) \ 21741502Swpaul CSR_WRITE_2(sc, reg, \ 21841502Swpaul CSR_READ_2(sc, reg) & ~x) 21941502Swpaul 22041502Swpaul#define VR_SETBIT32(sc, reg, x) \ 22141502Swpaul CSR_WRITE_4(sc, reg, \ 22241502Swpaul CSR_READ_4(sc, reg) | x) 22341502Swpaul 22441502Swpaul#define VR_CLRBIT32(sc, reg, x) \ 22541502Swpaul CSR_WRITE_4(sc, reg, \ 22641502Swpaul CSR_READ_4(sc, reg) & ~x) 22741502Swpaul 22841502Swpaul#define SIO_SET(x) \ 22941502Swpaul CSR_WRITE_1(sc, VR_MIICMD, \ 23041502Swpaul CSR_READ_1(sc, VR_MIICMD) | x) 23141502Swpaul 23241502Swpaul#define SIO_CLR(x) \ 23341502Swpaul CSR_WRITE_1(sc, VR_MIICMD, \ 23441502Swpaul CSR_READ_1(sc, VR_MIICMD) & ~x) 23541502Swpaul 23641502Swpaul/* 23741502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 23841502Swpaul */ 23941502Swpaulstatic void vr_mii_sync(sc) 24041502Swpaul struct vr_softc *sc; 24141502Swpaul{ 24241502Swpaul register int i; 24341502Swpaul 24441502Swpaul SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 24541502Swpaul 24641502Swpaul for (i = 0; i < 32; i++) { 24741502Swpaul SIO_SET(VR_MIICMD_CLK); 24841502Swpaul DELAY(1); 24941502Swpaul SIO_CLR(VR_MIICMD_CLK); 25041502Swpaul DELAY(1); 25141502Swpaul } 25241502Swpaul 25341502Swpaul return; 25441502Swpaul} 25541502Swpaul 25641502Swpaul/* 25741502Swpaul * Clock a series of bits through the MII. 25841502Swpaul */ 25941502Swpaulstatic void vr_mii_send(sc, bits, cnt) 26041502Swpaul struct vr_softc *sc; 26141502Swpaul u_int32_t bits; 26241502Swpaul int cnt; 26341502Swpaul{ 26441502Swpaul int i; 26541502Swpaul 26641502Swpaul SIO_CLR(VR_MIICMD_CLK); 26741502Swpaul 26841502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 26941502Swpaul if (bits & i) { 27041502Swpaul SIO_SET(VR_MIICMD_DATAIN); 27141502Swpaul } else { 27241502Swpaul SIO_CLR(VR_MIICMD_DATAIN); 27341502Swpaul } 27441502Swpaul DELAY(1); 27541502Swpaul SIO_CLR(VR_MIICMD_CLK); 27641502Swpaul DELAY(1); 27741502Swpaul SIO_SET(VR_MIICMD_CLK); 27841502Swpaul } 27941502Swpaul} 28041502Swpaul 28141502Swpaul/* 28241502Swpaul * Read an PHY register through the MII. 28341502Swpaul */ 28441502Swpaulstatic int vr_mii_readreg(sc, frame) 28541502Swpaul struct vr_softc *sc; 28641502Swpaul struct vr_mii_frame *frame; 28741502Swpaul 28841502Swpaul{ 28941502Swpaul int i, ack, s; 29041502Swpaul 29141502Swpaul s = splimp(); 29241502Swpaul 29341502Swpaul /* 29441502Swpaul * Set up frame for RX. 29541502Swpaul */ 29641502Swpaul frame->mii_stdelim = VR_MII_STARTDELIM; 29741502Swpaul frame->mii_opcode = VR_MII_READOP; 29841502Swpaul frame->mii_turnaround = 0; 29941502Swpaul frame->mii_data = 0; 30041502Swpaul 30141502Swpaul CSR_WRITE_1(sc, VR_MIICMD, 0); 30241502Swpaul VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 30341502Swpaul 30441502Swpaul /* 30541502Swpaul * Turn on data xmit. 30641502Swpaul */ 30741502Swpaul SIO_SET(VR_MIICMD_DIR); 30841502Swpaul 30941502Swpaul vr_mii_sync(sc); 31041502Swpaul 31141502Swpaul /* 31241502Swpaul * Send command/address info. 31341502Swpaul */ 31441502Swpaul vr_mii_send(sc, frame->mii_stdelim, 2); 31541502Swpaul vr_mii_send(sc, frame->mii_opcode, 2); 31641502Swpaul vr_mii_send(sc, frame->mii_phyaddr, 5); 31741502Swpaul vr_mii_send(sc, frame->mii_regaddr, 5); 31841502Swpaul 31941502Swpaul /* Idle bit */ 32041502Swpaul SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 32141502Swpaul DELAY(1); 32241502Swpaul SIO_SET(VR_MIICMD_CLK); 32341502Swpaul DELAY(1); 32441502Swpaul 32541502Swpaul /* Turn off xmit. */ 32641502Swpaul SIO_CLR(VR_MIICMD_DIR); 32741502Swpaul 32841502Swpaul /* Check for ack */ 32941502Swpaul SIO_CLR(VR_MIICMD_CLK); 33041502Swpaul DELAY(1); 33141502Swpaul SIO_SET(VR_MIICMD_CLK); 33241502Swpaul DELAY(1); 33341502Swpaul ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 33441502Swpaul 33541502Swpaul /* 33641502Swpaul * Now try reading data bits. If the ack failed, we still 33741502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 33841502Swpaul */ 33941502Swpaul if (ack) { 34041502Swpaul for(i = 0; i < 16; i++) { 34141502Swpaul SIO_CLR(VR_MIICMD_CLK); 34241502Swpaul DELAY(1); 34341502Swpaul SIO_SET(VR_MIICMD_CLK); 34441502Swpaul DELAY(1); 34541502Swpaul } 34641502Swpaul goto fail; 34741502Swpaul } 34841502Swpaul 34941502Swpaul for (i = 0x8000; i; i >>= 1) { 35041502Swpaul SIO_CLR(VR_MIICMD_CLK); 35141502Swpaul DELAY(1); 35241502Swpaul if (!ack) { 35341502Swpaul if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 35441502Swpaul frame->mii_data |= i; 35541502Swpaul DELAY(1); 35641502Swpaul } 35741502Swpaul SIO_SET(VR_MIICMD_CLK); 35841502Swpaul DELAY(1); 35941502Swpaul } 36041502Swpaul 36141502Swpaulfail: 36241502Swpaul 36341502Swpaul SIO_CLR(VR_MIICMD_CLK); 36441502Swpaul DELAY(1); 36541502Swpaul SIO_SET(VR_MIICMD_CLK); 36641502Swpaul DELAY(1); 36741502Swpaul 36841502Swpaul splx(s); 36941502Swpaul 37041502Swpaul if (ack) 37141502Swpaul return(1); 37241502Swpaul return(0); 37341502Swpaul} 37441502Swpaul 37541502Swpaul/* 37641502Swpaul * Write to a PHY register through the MII. 37741502Swpaul */ 37841502Swpaulstatic int vr_mii_writereg(sc, frame) 37941502Swpaul struct vr_softc *sc; 38041502Swpaul struct vr_mii_frame *frame; 38141502Swpaul 38241502Swpaul{ 38341502Swpaul int s; 38441502Swpaul 38541502Swpaul s = splimp(); 38641502Swpaul 38741502Swpaul CSR_WRITE_1(sc, VR_MIICMD, 0); 38841502Swpaul VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 38941502Swpaul 39041502Swpaul /* 39141502Swpaul * Set up frame for TX. 39241502Swpaul */ 39341502Swpaul 39441502Swpaul frame->mii_stdelim = VR_MII_STARTDELIM; 39541502Swpaul frame->mii_opcode = VR_MII_WRITEOP; 39641502Swpaul frame->mii_turnaround = VR_MII_TURNAROUND; 39741502Swpaul 39841502Swpaul /* 39941502Swpaul * Turn on data output. 40041502Swpaul */ 40141502Swpaul SIO_SET(VR_MIICMD_DIR); 40241502Swpaul 40341502Swpaul vr_mii_sync(sc); 40441502Swpaul 40541502Swpaul vr_mii_send(sc, frame->mii_stdelim, 2); 40641502Swpaul vr_mii_send(sc, frame->mii_opcode, 2); 40741502Swpaul vr_mii_send(sc, frame->mii_phyaddr, 5); 40841502Swpaul vr_mii_send(sc, frame->mii_regaddr, 5); 40941502Swpaul vr_mii_send(sc, frame->mii_turnaround, 2); 41041502Swpaul vr_mii_send(sc, frame->mii_data, 16); 41141502Swpaul 41241502Swpaul /* Idle bit. */ 41341502Swpaul SIO_SET(VR_MIICMD_CLK); 41441502Swpaul DELAY(1); 41541502Swpaul SIO_CLR(VR_MIICMD_CLK); 41641502Swpaul DELAY(1); 41741502Swpaul 41841502Swpaul /* 41941502Swpaul * Turn off xmit. 42041502Swpaul */ 42141502Swpaul SIO_CLR(VR_MIICMD_DIR); 42241502Swpaul 42341502Swpaul splx(s); 42441502Swpaul 42541502Swpaul return(0); 42641502Swpaul} 42741502Swpaul 42851432Swpaulstatic int vr_miibus_readreg(dev, phy, reg) 42951432Swpaul device_t dev; 43051432Swpaul int phy, reg; 43151432Swpaul{ 43241502Swpaul struct vr_softc *sc; 43341502Swpaul struct vr_mii_frame frame; 43441502Swpaul 43551432Swpaul sc = device_get_softc(dev); 43641502Swpaul bzero((char *)&frame, sizeof(frame)); 43741502Swpaul 43851432Swpaul frame.mii_phyaddr = phy; 43941502Swpaul frame.mii_regaddr = reg; 44041502Swpaul vr_mii_readreg(sc, &frame); 44141502Swpaul 44241502Swpaul return(frame.mii_data); 44341502Swpaul} 44441502Swpaul 44551432Swpaulstatic int vr_miibus_writereg(dev, phy, reg, data) 44651432Swpaul device_t dev; 44751432Swpaul u_int16_t phy, reg, data; 44851432Swpaul{ 44941502Swpaul struct vr_softc *sc; 45041502Swpaul struct vr_mii_frame frame; 45141502Swpaul 45251432Swpaul sc = device_get_softc(dev); 45341502Swpaul bzero((char *)&frame, sizeof(frame)); 45441502Swpaul 45551432Swpaul frame.mii_phyaddr = phy; 45641502Swpaul frame.mii_regaddr = reg; 45741502Swpaul frame.mii_data = data; 45841502Swpaul 45941502Swpaul vr_mii_writereg(sc, &frame); 46041502Swpaul 46151432Swpaul return(0); 46251432Swpaul} 46351432Swpaul 46451432Swpaulstatic void vr_miibus_statchg(dev) 46551432Swpaul device_t dev; 46651432Swpaul{ 46751432Swpaul struct vr_softc *sc; 46851432Swpaul struct mii_data *mii; 46951432Swpaul 47051432Swpaul sc = device_get_softc(dev); 47151432Swpaul mii = device_get_softc(sc->vr_miibus); 47251432Swpaul vr_setcfg(sc, mii->mii_media_active); 47351432Swpaul 47441502Swpaul return; 47541502Swpaul} 47641502Swpaul 47741502Swpaul/* 47841502Swpaul * Calculate CRC of a multicast group address, return the lower 6 bits. 47941502Swpaul */ 48041502Swpaulstatic u_int8_t vr_calchash(addr) 48141502Swpaul u_int8_t *addr; 48241502Swpaul{ 48341502Swpaul u_int32_t crc, carry; 48441502Swpaul int i, j; 48541502Swpaul u_int8_t c; 48641502Swpaul 48741502Swpaul /* Compute CRC for the address value. */ 48841502Swpaul crc = 0xFFFFFFFF; /* initial value */ 48941502Swpaul 49041502Swpaul for (i = 0; i < 6; i++) { 49141502Swpaul c = *(addr + i); 49241502Swpaul for (j = 0; j < 8; j++) { 49341502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 49441502Swpaul crc <<= 1; 49541502Swpaul c >>= 1; 49641502Swpaul if (carry) 49741502Swpaul crc = (crc ^ 0x04c11db6) | carry; 49841502Swpaul } 49941502Swpaul } 50041502Swpaul 50141502Swpaul /* return the filter bit position */ 50241502Swpaul return((crc >> 26) & 0x0000003F); 50341502Swpaul} 50441502Swpaul 50541502Swpaul/* 50641502Swpaul * Program the 64-bit multicast hash filter. 50741502Swpaul */ 50841502Swpaulstatic void vr_setmulti(sc) 50941502Swpaul struct vr_softc *sc; 51041502Swpaul{ 51141502Swpaul struct ifnet *ifp; 51241502Swpaul int h = 0; 51341502Swpaul u_int32_t hashes[2] = { 0, 0 }; 51441502Swpaul struct ifmultiaddr *ifma; 51541502Swpaul u_int8_t rxfilt; 51641502Swpaul int mcnt = 0; 51741502Swpaul 51841502Swpaul ifp = &sc->arpcom.ac_if; 51941502Swpaul 52041502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 52141502Swpaul 52241502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 52341502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 52441502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 52541502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 52641502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 52741502Swpaul return; 52841502Swpaul } 52941502Swpaul 53041502Swpaul /* first, zot all the existing hash bits */ 53141502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0); 53241502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0); 53341502Swpaul 53441502Swpaul /* now program new ones */ 53541502Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 53641502Swpaul ifma = ifma->ifma_link.le_next) { 53741502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 53841502Swpaul continue; 53941502Swpaul h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 54041502Swpaul if (h < 32) 54141502Swpaul hashes[0] |= (1 << h); 54241502Swpaul else 54341502Swpaul hashes[1] |= (1 << (h - 32)); 54441502Swpaul mcnt++; 54541502Swpaul } 54641502Swpaul 54741502Swpaul if (mcnt) 54841502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 54941502Swpaul else 55041502Swpaul rxfilt &= ~VR_RXCFG_RX_MULTI; 55141502Swpaul 55241502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 55341502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 55441502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 55541502Swpaul 55641502Swpaul return; 55741502Swpaul} 55841502Swpaul 55941502Swpaul/* 56041502Swpaul * In order to fiddle with the 56141502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 56241502Swpaul * first have to put the transmit and/or receive logic in the idle state. 56341502Swpaul */ 56451432Swpaulstatic void vr_setcfg(sc, media) 56541502Swpaul struct vr_softc *sc; 56651432Swpaul int media; 56741502Swpaul{ 56841502Swpaul int restart = 0; 56941502Swpaul 57041502Swpaul if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 57141502Swpaul restart = 1; 57241502Swpaul VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 57341502Swpaul } 57441502Swpaul 57551432Swpaul if ((media & IFM_GMASK) == IFM_FDX) 57641502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 57741502Swpaul else 57841502Swpaul VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 57941502Swpaul 58041502Swpaul if (restart) 58141502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 58241502Swpaul 58341502Swpaul return; 58441502Swpaul} 58541502Swpaul 58641502Swpaulstatic void vr_reset(sc) 58741502Swpaul struct vr_softc *sc; 58841502Swpaul{ 58941502Swpaul register int i; 59041502Swpaul 59141502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 59241502Swpaul 59341502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 59441502Swpaul DELAY(10); 59541502Swpaul if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 59641502Swpaul break; 59741502Swpaul } 59841502Swpaul if (i == VR_TIMEOUT) 59941502Swpaul printf("vr%d: reset never completed!\n", sc->vr_unit); 60041502Swpaul 60141502Swpaul /* Wait a little while for the chip to get its brains in order. */ 60241502Swpaul DELAY(1000); 60341502Swpaul 60441502Swpaul return; 60541502Swpaul} 60641502Swpaul 60741502Swpaul/* 60841502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 60941502Swpaul * IDs against our list and return a device name if we find a match. 61041502Swpaul */ 61149610Swpaulstatic int vr_probe(dev) 61249610Swpaul device_t dev; 61341502Swpaul{ 61441502Swpaul struct vr_type *t; 61541502Swpaul 61641502Swpaul t = vr_devs; 61741502Swpaul 61841502Swpaul while(t->vr_name != NULL) { 61949610Swpaul if ((pci_get_vendor(dev) == t->vr_vid) && 62049610Swpaul (pci_get_device(dev) == t->vr_did)) { 62149610Swpaul device_set_desc(dev, t->vr_name); 62249610Swpaul return(0); 62341502Swpaul } 62441502Swpaul t++; 62541502Swpaul } 62641502Swpaul 62749610Swpaul return(ENXIO); 62841502Swpaul} 62941502Swpaul 63041502Swpaul/* 63141502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 63241502Swpaul * setup and ethernet/BPF attach. 63341502Swpaul */ 63449610Swpaulstatic int vr_attach(dev) 63549610Swpaul device_t dev; 63641502Swpaul{ 63751432Swpaul int i, s; 63841502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 63941502Swpaul u_int32_t command; 64041502Swpaul struct vr_softc *sc; 64141502Swpaul struct ifnet *ifp; 64249610Swpaul int unit, error = 0, rid; 64341502Swpaul 64441502Swpaul s = splimp(); 64541502Swpaul 64649610Swpaul sc = device_get_softc(dev); 64749610Swpaul unit = device_get_unit(dev); 64849610Swpaul bzero(sc, sizeof(struct vr_softc *)); 64941502Swpaul 65041502Swpaul /* 65141502Swpaul * Handle power management nonsense. 65241502Swpaul */ 65341502Swpaul 65449610Swpaul command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 65541502Swpaul if (command == 0x01) { 65641502Swpaul 65749610Swpaul command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 65841502Swpaul if (command & VR_PSTATE_MASK) { 65941502Swpaul u_int32_t iobase, membase, irq; 66041502Swpaul 66141502Swpaul /* Save important PCI config data. */ 66249610Swpaul iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 66349610Swpaul membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 66449610Swpaul irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 66541502Swpaul 66641502Swpaul /* Reset the power state. */ 66741502Swpaul printf("vr%d: chip is in D%d power mode " 66841502Swpaul "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 66941502Swpaul command &= 0xFFFFFFFC; 67049610Swpaul pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 67141502Swpaul 67241502Swpaul /* Restore PCI config data. */ 67349610Swpaul pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 67449610Swpaul pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 67549610Swpaul pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 67641502Swpaul } 67741502Swpaul } 67841502Swpaul 67941502Swpaul /* 68041502Swpaul * Map control/status registers. 68141502Swpaul */ 68249610Swpaul command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 68341502Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 68449610Swpaul pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 68549610Swpaul command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 68641502Swpaul 68741502Swpaul#ifdef VR_USEIOSPACE 68841502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 68941502Swpaul printf("vr%d: failed to enable I/O ports!\n", unit); 69041502Swpaul free(sc, M_DEVBUF); 69141502Swpaul goto fail; 69241502Swpaul } 69341502Swpaul#else 69441502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 69541502Swpaul printf("vr%d: failed to enable memory mapping!\n", unit); 69641502Swpaul goto fail; 69741502Swpaul } 69849610Swpaul#endif 69941502Swpaul 70049610Swpaul rid = VR_RID; 70149610Swpaul sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 70249610Swpaul 0, ~0, 1, RF_ACTIVE); 70349610Swpaul 70449610Swpaul if (sc->vr_res == NULL) { 70549610Swpaul printf("vr%d: couldn't map ports/memory\n", unit); 70649610Swpaul error = ENXIO; 70741502Swpaul goto fail; 70841502Swpaul } 70941502Swpaul 71049610Swpaul sc->vr_btag = rman_get_bustag(sc->vr_res); 71149610Swpaul sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 71241502Swpaul 71341502Swpaul /* Allocate interrupt */ 71449610Swpaul rid = 0; 71549610Swpaul sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 71649610Swpaul RF_SHAREABLE | RF_ACTIVE); 71749610Swpaul 71849610Swpaul if (sc->vr_irq == NULL) { 71941502Swpaul printf("vr%d: couldn't map interrupt\n", unit); 72049610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 72149610Swpaul error = ENXIO; 72241502Swpaul goto fail; 72341502Swpaul } 72441502Swpaul 72549610Swpaul error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 72649610Swpaul vr_intr, sc, &sc->vr_intrhand); 72749610Swpaul 72849610Swpaul if (error) { 72949610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 73049610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 73149610Swpaul printf("vr%d: couldn't set up irq\n", unit); 73249610Swpaul goto fail; 73349610Swpaul } 73449610Swpaul 73541502Swpaul /* Reset the adapter. */ 73641502Swpaul vr_reset(sc); 73741502Swpaul 73841502Swpaul /* 73941502Swpaul * Get station address. The way the Rhine chips work, 74041502Swpaul * you're not allowed to directly access the EEPROM once 74141502Swpaul * they've been programmed a special way. Consequently, 74241502Swpaul * we need to read the node address from the PAR0 and PAR1 74341502Swpaul * registers. 74441502Swpaul */ 74541502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 74641502Swpaul DELAY(200); 74741502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 74841502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 74941502Swpaul 75041502Swpaul /* 75141502Swpaul * A Rhine chip was detected. Inform the world. 75241502Swpaul */ 75341502Swpaul printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 75441502Swpaul 75541502Swpaul sc->vr_unit = unit; 75641502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 75741502Swpaul 75851432Swpaul sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 75951432Swpaul M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 76051432Swpaul 76151432Swpaul if (sc->vr_ldata == NULL) { 76241502Swpaul printf("vr%d: no memory for list buffers!\n", unit); 76349610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 76449610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 76549610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 76649610Swpaul error = ENXIO; 76749610Swpaul goto fail; 76841502Swpaul } 76941502Swpaul 77041502Swpaul bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 77141502Swpaul 77241502Swpaul ifp = &sc->arpcom.ac_if; 77341502Swpaul ifp->if_softc = sc; 77441502Swpaul ifp->if_unit = unit; 77541502Swpaul ifp->if_name = "vr"; 77641502Swpaul ifp->if_mtu = ETHERMTU; 77741502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 77841502Swpaul ifp->if_ioctl = vr_ioctl; 77941502Swpaul ifp->if_output = ether_output; 78041502Swpaul ifp->if_start = vr_start; 78141502Swpaul ifp->if_watchdog = vr_watchdog; 78241502Swpaul ifp->if_init = vr_init; 78341502Swpaul ifp->if_baudrate = 10000000; 78443515Swpaul ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 78541502Swpaul 78651432Swpaul /* 78751432Swpaul * Do MII setup. 78851432Swpaul */ 78951432Swpaul if (mii_phy_probe(dev, &sc->vr_miibus, 79051432Swpaul vr_ifmedia_upd, vr_ifmedia_sts)) { 79141502Swpaul printf("vr%d: MII without any phy!\n", sc->vr_unit); 79249610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 79349610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 79449610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 79551432Swpaul contigfree(sc->vr_ldata, 79651432Swpaul sizeof(struct vr_list_data), M_DEVBUF); 79749610Swpaul error = ENXIO; 79841502Swpaul goto fail; 79941502Swpaul } 80041502Swpaul 80151432Swpaul callout_handle_init(&sc->vr_stat_ch); 80241502Swpaul 80341502Swpaul /* 80441502Swpaul * Call MI attach routines. 80541502Swpaul */ 80641502Swpaul if_attach(ifp); 80741502Swpaul ether_ifattach(ifp); 80841502Swpaul 80941502Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 81041502Swpaul 81141502Swpaulfail: 81241502Swpaul splx(s); 81349610Swpaul return(error); 81441502Swpaul} 81541502Swpaul 81649610Swpaulstatic int vr_detach(dev) 81749610Swpaul device_t dev; 81849610Swpaul{ 81949610Swpaul struct vr_softc *sc; 82049610Swpaul struct ifnet *ifp; 82149610Swpaul int s; 82249610Swpaul 82349610Swpaul s = splimp(); 82449610Swpaul 82549610Swpaul sc = device_get_softc(dev); 82649610Swpaul ifp = &sc->arpcom.ac_if; 82749610Swpaul 82849610Swpaul vr_stop(sc); 82949610Swpaul if_detach(ifp); 83049610Swpaul 83151432Swpaul bus_generic_detach(dev); 83251432Swpaul device_delete_child(dev, sc->vr_miibus); 83351432Swpaul 83449610Swpaul bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 83549610Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 83649610Swpaul bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 83749610Swpaul 83851432Swpaul contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 83949610Swpaul 84049610Swpaul splx(s); 84149610Swpaul 84249610Swpaul return(0); 84349610Swpaul} 84449610Swpaul 84541502Swpaul/* 84641502Swpaul * Initialize the transmit descriptors. 84741502Swpaul */ 84841502Swpaulstatic int vr_list_tx_init(sc) 84941502Swpaul struct vr_softc *sc; 85041502Swpaul{ 85141502Swpaul struct vr_chain_data *cd; 85241502Swpaul struct vr_list_data *ld; 85341502Swpaul int i; 85441502Swpaul 85541502Swpaul cd = &sc->vr_cdata; 85641502Swpaul ld = sc->vr_ldata; 85741502Swpaul for (i = 0; i < VR_TX_LIST_CNT; i++) { 85841502Swpaul cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 85941502Swpaul if (i == (VR_TX_LIST_CNT - 1)) 86041502Swpaul cd->vr_tx_chain[i].vr_nextdesc = 86141502Swpaul &cd->vr_tx_chain[0]; 86241502Swpaul else 86341502Swpaul cd->vr_tx_chain[i].vr_nextdesc = 86441502Swpaul &cd->vr_tx_chain[i + 1]; 86541502Swpaul } 86641502Swpaul 86741502Swpaul cd->vr_tx_free = &cd->vr_tx_chain[0]; 86841502Swpaul cd->vr_tx_tail = cd->vr_tx_head = NULL; 86941502Swpaul 87041502Swpaul return(0); 87141502Swpaul} 87241502Swpaul 87341502Swpaul 87441502Swpaul/* 87541502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 87641502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 87741502Swpaul * points back to the first. 87841502Swpaul */ 87941502Swpaulstatic int vr_list_rx_init(sc) 88041502Swpaul struct vr_softc *sc; 88141502Swpaul{ 88241502Swpaul struct vr_chain_data *cd; 88341502Swpaul struct vr_list_data *ld; 88441502Swpaul int i; 88541502Swpaul 88641502Swpaul cd = &sc->vr_cdata; 88741502Swpaul ld = sc->vr_ldata; 88841502Swpaul 88941502Swpaul for (i = 0; i < VR_RX_LIST_CNT; i++) { 89041502Swpaul cd->vr_rx_chain[i].vr_ptr = 89141502Swpaul (struct vr_desc *)&ld->vr_rx_list[i]; 89249610Swpaul if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 89341502Swpaul return(ENOBUFS); 89441502Swpaul if (i == (VR_RX_LIST_CNT - 1)) { 89541502Swpaul cd->vr_rx_chain[i].vr_nextdesc = 89641502Swpaul &cd->vr_rx_chain[0]; 89741502Swpaul ld->vr_rx_list[i].vr_next = 89841502Swpaul vtophys(&ld->vr_rx_list[0]); 89941502Swpaul } else { 90041502Swpaul cd->vr_rx_chain[i].vr_nextdesc = 90141502Swpaul &cd->vr_rx_chain[i + 1]; 90241502Swpaul ld->vr_rx_list[i].vr_next = 90341502Swpaul vtophys(&ld->vr_rx_list[i + 1]); 90441502Swpaul } 90541502Swpaul } 90641502Swpaul 90741502Swpaul cd->vr_rx_head = &cd->vr_rx_chain[0]; 90841502Swpaul 90941502Swpaul return(0); 91041502Swpaul} 91141502Swpaul 91241502Swpaul/* 91341502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 91441502Swpaul * Note: the length fields are only 11 bits wide, which means the 91541502Swpaul * largest size we can specify is 2047. This is important because 91641502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 91741502Swpaul * overflow the field and make a mess. 91841502Swpaul */ 91949610Swpaulstatic int vr_newbuf(sc, c, m) 92041502Swpaul struct vr_softc *sc; 92141502Swpaul struct vr_chain_onefrag *c; 92249610Swpaul struct mbuf *m; 92341502Swpaul{ 92441502Swpaul struct mbuf *m_new = NULL; 92541502Swpaul 92649610Swpaul if (m == NULL) { 92749610Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 92849610Swpaul if (m_new == NULL) { 92949610Swpaul printf("vr%d: no memory for rx list " 93049610Swpaul "-- packet dropped!\n", sc->vr_unit); 93149610Swpaul return(ENOBUFS); 93249610Swpaul } 93341502Swpaul 93449610Swpaul MCLGET(m_new, M_DONTWAIT); 93549610Swpaul if (!(m_new->m_flags & M_EXT)) { 93649610Swpaul printf("vr%d: no memory for rx list " 93749610Swpaul "-- packet dropped!\n", sc->vr_unit); 93849610Swpaul m_freem(m_new); 93949610Swpaul return(ENOBUFS); 94049610Swpaul } 94149610Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 94249610Swpaul } else { 94349610Swpaul m_new = m; 94449610Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 94549610Swpaul m_new->m_data = m_new->m_ext.ext_buf; 94641502Swpaul } 94741502Swpaul 94849610Swpaul m_adj(m_new, sizeof(u_int64_t)); 94949610Swpaul 95041502Swpaul c->vr_mbuf = m_new; 95141502Swpaul c->vr_ptr->vr_status = VR_RXSTAT; 95241502Swpaul c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 95342491Swpaul c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 95441502Swpaul 95541502Swpaul return(0); 95641502Swpaul} 95741502Swpaul 95841502Swpaul/* 95941502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 96041502Swpaul * the higher level protocols. 96141502Swpaul */ 96241502Swpaulstatic void vr_rxeof(sc) 96341502Swpaul struct vr_softc *sc; 96441502Swpaul{ 96541502Swpaul struct ether_header *eh; 96641502Swpaul struct mbuf *m; 96741502Swpaul struct ifnet *ifp; 96841502Swpaul struct vr_chain_onefrag *cur_rx; 96941502Swpaul int total_len = 0; 97041502Swpaul u_int32_t rxstat; 97141502Swpaul 97241502Swpaul ifp = &sc->arpcom.ac_if; 97341502Swpaul 97441502Swpaul while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 97541502Swpaul VR_RXSTAT_OWN)) { 97649610Swpaul struct mbuf *m0 = NULL; 97749610Swpaul 97841502Swpaul cur_rx = sc->vr_cdata.vr_rx_head; 97941502Swpaul sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 98049610Swpaul m = cur_rx->vr_mbuf; 98141502Swpaul 98241502Swpaul /* 98341502Swpaul * If an error occurs, update stats, clear the 98441502Swpaul * status word and leave the mbuf cluster in place: 98541502Swpaul * it should simply get re-used next time this descriptor 98641502Swpaul * comes up in the ring. 98741502Swpaul */ 98841502Swpaul if (rxstat & VR_RXSTAT_RXERR) { 98941502Swpaul ifp->if_ierrors++; 99041502Swpaul printf("vr%d: rx error: ", sc->vr_unit); 99141502Swpaul switch(rxstat & 0x000000FF) { 99241502Swpaul case VR_RXSTAT_CRCERR: 99341502Swpaul printf("crc error\n"); 99441502Swpaul break; 99541502Swpaul case VR_RXSTAT_FRAMEALIGNERR: 99641502Swpaul printf("frame alignment error\n"); 99741502Swpaul break; 99841502Swpaul case VR_RXSTAT_FIFOOFLOW: 99941502Swpaul printf("FIFO overflow\n"); 100041502Swpaul break; 100141502Swpaul case VR_RXSTAT_GIANT: 100241502Swpaul printf("received giant packet\n"); 100341502Swpaul break; 100441502Swpaul case VR_RXSTAT_RUNT: 100541502Swpaul printf("received runt packet\n"); 100641502Swpaul break; 100741502Swpaul case VR_RXSTAT_BUSERR: 100841502Swpaul printf("system bus error\n"); 100941502Swpaul break; 101041502Swpaul case VR_RXSTAT_BUFFERR: 101141502Swpaul printf("rx buffer error\n"); 101241502Swpaul break; 101341502Swpaul default: 101441502Swpaul printf("unknown rx error\n"); 101541502Swpaul break; 101641502Swpaul } 101749610Swpaul vr_newbuf(sc, cur_rx, m); 101841502Swpaul continue; 101941502Swpaul } 102041502Swpaul 102141502Swpaul /* No errors; receive the packet. */ 102241502Swpaul total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 102341502Swpaul 102441502Swpaul /* 102542048Swpaul * XXX The VIA Rhine chip includes the CRC with every 102642048Swpaul * received frame, and there's no way to turn this 102742048Swpaul * behavior off (at least, I can't find anything in 102842048Swpaul * the manual that explains how to do it) so we have 102942048Swpaul * to trim off the CRC manually. 103042048Swpaul */ 103142048Swpaul total_len -= ETHER_CRC_LEN; 103242048Swpaul 103349610Swpaul m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 103449610Swpaul total_len + ETHER_ALIGN, 0, ifp, NULL); 103549610Swpaul vr_newbuf(sc, cur_rx, m); 103649610Swpaul if (m0 == NULL) { 103741502Swpaul ifp->if_ierrors++; 103841502Swpaul continue; 103941502Swpaul } 104049610Swpaul m_adj(m0, ETHER_ALIGN); 104149610Swpaul m = m0; 104241502Swpaul 104341502Swpaul ifp->if_ipackets++; 104441502Swpaul eh = mtod(m, struct ether_header *); 104549610Swpaul 104641502Swpaul /* 104741502Swpaul * Handle BPF listeners. Let the BPF user see the packet, but 104841502Swpaul * don't pass it up to the ether_input() layer unless it's 104941502Swpaul * a broadcast packet, multicast packet, matches our ethernet 105041502Swpaul * address or the interface is in promiscuous mode. 105141502Swpaul */ 105241502Swpaul if (ifp->if_bpf) { 105341502Swpaul bpf_mtap(ifp, m); 105441502Swpaul if (ifp->if_flags & IFF_PROMISC && 105541502Swpaul (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 105641502Swpaul ETHER_ADDR_LEN) && 105741502Swpaul (eh->ether_dhost[0] & 1) == 0)) { 105841502Swpaul m_freem(m); 105941502Swpaul continue; 106041502Swpaul } 106141502Swpaul } 106251583Swpaul 106351354Swpaul#ifdef BRIDGE 106451354Swpaul if (do_bridge) { 106551354Swpaul struct ifnet *bdg_ifp; 106651354Swpaul bdg_ifp = bridge_in(m); 106751354Swpaul if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 106851354Swpaul bdg_forward(&m, bdg_ifp); 106951354Swpaul if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 107051354Swpaul (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 107151354Swpaul m_freem(m); 107251354Swpaul continue; 107351354Swpaul } 107451354Swpaul } 107551354Swpaul#endif /* BRIDGE */ 107651354Swpaul 107741502Swpaul /* Remove header from mbuf and pass it on. */ 107841502Swpaul m_adj(m, sizeof(struct ether_header)); 107941502Swpaul ether_input(ifp, eh, m); 108041502Swpaul } 108141502Swpaul 108241502Swpaul return; 108341502Swpaul} 108441502Swpaul 108541502Swpaulvoid vr_rxeoc(sc) 108641502Swpaul struct vr_softc *sc; 108741502Swpaul{ 108841502Swpaul 108941502Swpaul vr_rxeof(sc); 109041502Swpaul VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 109141502Swpaul CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 109241502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 109341502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 109441502Swpaul 109541502Swpaul return; 109641502Swpaul} 109741502Swpaul 109841502Swpaul/* 109941502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 110041502Swpaul * the list buffers. 110141502Swpaul */ 110241502Swpaul 110341502Swpaulstatic void vr_txeof(sc) 110441502Swpaul struct vr_softc *sc; 110541502Swpaul{ 110641502Swpaul struct vr_chain *cur_tx; 110741502Swpaul struct ifnet *ifp; 110841502Swpaul 110941502Swpaul ifp = &sc->arpcom.ac_if; 111041502Swpaul 111141502Swpaul /* Clear the timeout timer. */ 111241502Swpaul ifp->if_timer = 0; 111341502Swpaul 111441502Swpaul /* Sanity check. */ 111541502Swpaul if (sc->vr_cdata.vr_tx_head == NULL) 111641502Swpaul return; 111741502Swpaul 111841502Swpaul /* 111941502Swpaul * Go through our tx list and free mbufs for those 112041502Swpaul * frames that have been transmitted. 112141502Swpaul */ 112241502Swpaul while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 112341502Swpaul u_int32_t txstat; 112441502Swpaul 112541502Swpaul cur_tx = sc->vr_cdata.vr_tx_head; 112641502Swpaul txstat = cur_tx->vr_ptr->vr_status; 112741502Swpaul 112842491Swpaul if (txstat & VR_TXSTAT_OWN) 112941502Swpaul break; 113041502Swpaul 113141502Swpaul if (txstat & VR_TXSTAT_ERRSUM) { 113241502Swpaul ifp->if_oerrors++; 113341502Swpaul if (txstat & VR_TXSTAT_DEFER) 113441502Swpaul ifp->if_collisions++; 113541502Swpaul if (txstat & VR_TXSTAT_LATECOLL) 113641502Swpaul ifp->if_collisions++; 113741502Swpaul } 113841502Swpaul 113941502Swpaul ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 114041502Swpaul 114141502Swpaul ifp->if_opackets++; 114251432Swpaul if (cur_tx->vr_mbuf != NULL) { 114351432Swpaul m_freem(cur_tx->vr_mbuf); 114451432Swpaul cur_tx->vr_mbuf = NULL; 114551432Swpaul } 114641502Swpaul 114741502Swpaul if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 114841502Swpaul sc->vr_cdata.vr_tx_head = NULL; 114941502Swpaul sc->vr_cdata.vr_tx_tail = NULL; 115041502Swpaul break; 115141502Swpaul } 115241502Swpaul 115341502Swpaul sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 115441502Swpaul } 115541502Swpaul 115641502Swpaul return; 115741502Swpaul} 115841502Swpaul 115941502Swpaul/* 116041502Swpaul * TX 'end of channel' interrupt handler. 116141502Swpaul */ 116241502Swpaulstatic void vr_txeoc(sc) 116341502Swpaul struct vr_softc *sc; 116441502Swpaul{ 116541502Swpaul struct ifnet *ifp; 116641502Swpaul 116741502Swpaul ifp = &sc->arpcom.ac_if; 116841502Swpaul 116941502Swpaul ifp->if_timer = 0; 117041502Swpaul 117141502Swpaul if (sc->vr_cdata.vr_tx_head == NULL) { 117241502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 117341502Swpaul sc->vr_cdata.vr_tx_tail = NULL; 117441502Swpaul } 117541502Swpaul 117641502Swpaul return; 117741502Swpaul} 117841502Swpaul 117951432Swpaulstatic void vr_tick(xsc) 118051432Swpaul void *xsc; 118151432Swpaul{ 118251432Swpaul struct vr_softc *sc; 118351432Swpaul struct mii_data *mii; 118451432Swpaul int s; 118551432Swpaul 118651432Swpaul s = splimp(); 118751432Swpaul 118851432Swpaul sc = xsc; 118951432Swpaul mii = device_get_softc(sc->vr_miibus); 119051432Swpaul mii_tick(mii); 119151432Swpaul 119251432Swpaul sc->vr_stat_ch = timeout(vr_tick, sc, hz); 119351432Swpaul 119451432Swpaul splx(s); 119551432Swpaul 119651432Swpaul return; 119751432Swpaul} 119851432Swpaul 119941502Swpaulstatic void vr_intr(arg) 120041502Swpaul void *arg; 120141502Swpaul{ 120241502Swpaul struct vr_softc *sc; 120341502Swpaul struct ifnet *ifp; 120441502Swpaul u_int16_t status; 120541502Swpaul 120641502Swpaul sc = arg; 120741502Swpaul ifp = &sc->arpcom.ac_if; 120841502Swpaul 120941502Swpaul /* Supress unwanted interrupts. */ 121041502Swpaul if (!(ifp->if_flags & IFF_UP)) { 121141502Swpaul vr_stop(sc); 121241502Swpaul return; 121341502Swpaul } 121441502Swpaul 121541502Swpaul /* Disable interrupts. */ 121641502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 121741502Swpaul 121841502Swpaul for (;;) { 121941502Swpaul 122041502Swpaul status = CSR_READ_2(sc, VR_ISR); 122141502Swpaul if (status) 122241502Swpaul CSR_WRITE_2(sc, VR_ISR, status); 122341502Swpaul 122441502Swpaul if ((status & VR_INTRS) == 0) 122541502Swpaul break; 122641502Swpaul 122741502Swpaul if (status & VR_ISR_RX_OK) 122841502Swpaul vr_rxeof(sc); 122941502Swpaul 123041502Swpaul if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 123141502Swpaul (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 123241502Swpaul (status & VR_ISR_RX_DROPPED)) { 123341502Swpaul vr_rxeof(sc); 123441502Swpaul vr_rxeoc(sc); 123541502Swpaul } 123641502Swpaul 123741502Swpaul if (status & VR_ISR_TX_OK) { 123841502Swpaul vr_txeof(sc); 123941502Swpaul vr_txeoc(sc); 124041502Swpaul } 124141502Swpaul 124241502Swpaul if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 124341502Swpaul ifp->if_oerrors++; 124441502Swpaul vr_txeof(sc); 124541502Swpaul if (sc->vr_cdata.vr_tx_head != NULL) { 124641502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 124741502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 124841502Swpaul } 124941502Swpaul } 125041502Swpaul 125141502Swpaul if (status & VR_ISR_BUSERR) { 125241502Swpaul vr_reset(sc); 125341502Swpaul vr_init(sc); 125441502Swpaul } 125541502Swpaul } 125641502Swpaul 125741502Swpaul /* Re-enable interrupts. */ 125841502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 125941502Swpaul 126041502Swpaul if (ifp->if_snd.ifq_head != NULL) { 126141502Swpaul vr_start(ifp); 126241502Swpaul } 126341502Swpaul 126441502Swpaul return; 126541502Swpaul} 126641502Swpaul 126741502Swpaul/* 126841502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 126941502Swpaul * pointers to the fragment pointers. 127041502Swpaul */ 127141502Swpaulstatic int vr_encap(sc, c, m_head) 127241502Swpaul struct vr_softc *sc; 127341502Swpaul struct vr_chain *c; 127441502Swpaul struct mbuf *m_head; 127541502Swpaul{ 127641502Swpaul int frag = 0; 127741502Swpaul struct vr_desc *f = NULL; 127841502Swpaul int total_len; 127941502Swpaul struct mbuf *m; 128041502Swpaul 128141502Swpaul m = m_head; 128241502Swpaul total_len = 0; 128341502Swpaul 128441502Swpaul /* 128541502Swpaul * The VIA Rhine wants packet buffers to be longword 128641502Swpaul * aligned, but very often our mbufs aren't. Rather than 128741502Swpaul * waste time trying to decide when to copy and when not 128841502Swpaul * to copy, just do it all the time. 128941502Swpaul */ 129041502Swpaul if (m != NULL) { 129141502Swpaul struct mbuf *m_new = NULL; 129241502Swpaul 129341502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 129441502Swpaul if (m_new == NULL) { 129541502Swpaul printf("vr%d: no memory for tx list", sc->vr_unit); 129641502Swpaul return(1); 129741502Swpaul } 129841502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 129941502Swpaul MCLGET(m_new, M_DONTWAIT); 130041502Swpaul if (!(m_new->m_flags & M_EXT)) { 130141502Swpaul m_freem(m_new); 130241502Swpaul printf("vr%d: no memory for tx list", 130341502Swpaul sc->vr_unit); 130441502Swpaul return(1); 130541502Swpaul } 130641502Swpaul } 130741502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 130841502Swpaul mtod(m_new, caddr_t)); 130941502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 131041502Swpaul m_freem(m_head); 131141502Swpaul m_head = m_new; 131241502Swpaul /* 131341502Swpaul * The Rhine chip doesn't auto-pad, so we have to make 131441502Swpaul * sure to pad short frames out to the minimum frame length 131541502Swpaul * ourselves. 131641502Swpaul */ 131741502Swpaul if (m_head->m_len < VR_MIN_FRAMELEN) { 131841502Swpaul m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 131941502Swpaul m_new->m_len = m_new->m_pkthdr.len; 132041502Swpaul } 132141502Swpaul f = c->vr_ptr; 132241502Swpaul f->vr_data = vtophys(mtod(m_new, caddr_t)); 132341502Swpaul f->vr_ctl = total_len = m_new->m_len; 132441502Swpaul f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 132541502Swpaul f->vr_status = 0; 132641502Swpaul frag = 1; 132741502Swpaul } 132841502Swpaul 132941502Swpaul c->vr_mbuf = m_head; 133042491Swpaul c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 133141502Swpaul c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 133241502Swpaul 133341502Swpaul return(0); 133441502Swpaul} 133541502Swpaul 133641502Swpaul/* 133741502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 133841502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 133941502Swpaul * copy of the pointers since the transmit list fragment pointers are 134041502Swpaul * physical addresses. 134141502Swpaul */ 134241502Swpaul 134341502Swpaulstatic void vr_start(ifp) 134441502Swpaul struct ifnet *ifp; 134541502Swpaul{ 134641502Swpaul struct vr_softc *sc; 134741502Swpaul struct mbuf *m_head = NULL; 134841502Swpaul struct vr_chain *cur_tx = NULL, *start_tx; 134941502Swpaul 135041502Swpaul sc = ifp->if_softc; 135141502Swpaul 135251432Swpaul if (ifp->if_flags & IFF_OACTIVE) 135341502Swpaul return; 135441502Swpaul 135541502Swpaul /* 135641502Swpaul * Check for an available queue slot. If there are none, 135741502Swpaul * punt. 135841502Swpaul */ 135941502Swpaul if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 136041502Swpaul ifp->if_flags |= IFF_OACTIVE; 136141502Swpaul return; 136241502Swpaul } 136341502Swpaul 136441502Swpaul start_tx = sc->vr_cdata.vr_tx_free; 136541502Swpaul 136641502Swpaul while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 136741502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 136841502Swpaul if (m_head == NULL) 136941502Swpaul break; 137041502Swpaul 137141502Swpaul /* Pick a descriptor off the free list. */ 137241502Swpaul cur_tx = sc->vr_cdata.vr_tx_free; 137341502Swpaul sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 137441502Swpaul 137541502Swpaul /* Pack the data into the descriptor. */ 137641502Swpaul vr_encap(sc, cur_tx, m_head); 137741502Swpaul 137841502Swpaul if (cur_tx != start_tx) 137941502Swpaul VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 138041502Swpaul 138141502Swpaul /* 138241502Swpaul * If there's a BPF listener, bounce a copy of this frame 138341502Swpaul * to him. 138441502Swpaul */ 138541502Swpaul if (ifp->if_bpf) 138641502Swpaul bpf_mtap(ifp, cur_tx->vr_mbuf); 138751583Swpaul 138842491Swpaul VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 138951432Swpaul VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 139041502Swpaul } 139141502Swpaul 139241502Swpaul /* 139341526Swpaul * If there are no frames queued, bail. 139441526Swpaul */ 139541526Swpaul if (cur_tx == NULL) 139641526Swpaul return; 139741526Swpaul 139841502Swpaul sc->vr_cdata.vr_tx_tail = cur_tx; 139941502Swpaul 140042491Swpaul if (sc->vr_cdata.vr_tx_head == NULL) 140141502Swpaul sc->vr_cdata.vr_tx_head = start_tx; 140241502Swpaul 140341502Swpaul /* 140441502Swpaul * Set a timeout in case the chip goes out to lunch. 140541502Swpaul */ 140641502Swpaul ifp->if_timer = 5; 140741502Swpaul 140841502Swpaul return; 140941502Swpaul} 141041502Swpaul 141141502Swpaulstatic void vr_init(xsc) 141241502Swpaul void *xsc; 141341502Swpaul{ 141441502Swpaul struct vr_softc *sc = xsc; 141541502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 141651432Swpaul struct mii_data *mii; 141741502Swpaul int s; 141841502Swpaul 141941502Swpaul s = splimp(); 142041502Swpaul 142151432Swpaul mii = device_get_softc(sc->vr_miibus); 142241502Swpaul 142341502Swpaul /* 142441502Swpaul * Cancel pending I/O and free all RX/TX buffers. 142541502Swpaul */ 142641502Swpaul vr_stop(sc); 142741502Swpaul vr_reset(sc); 142841502Swpaul 142941502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 143041502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 143141502Swpaul 143241502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 143341502Swpaul VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 143441502Swpaul 143541502Swpaul /* Init circular RX list. */ 143641502Swpaul if (vr_list_rx_init(sc) == ENOBUFS) { 143741502Swpaul printf("vr%d: initialization failed: no " 143841502Swpaul "memory for rx buffers\n", sc->vr_unit); 143941502Swpaul vr_stop(sc); 144041502Swpaul (void)splx(s); 144141502Swpaul return; 144241502Swpaul } 144341502Swpaul 144441502Swpaul /* 144541502Swpaul * Init tx descriptors. 144641502Swpaul */ 144741502Swpaul vr_list_tx_init(sc); 144841502Swpaul 144941502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 145041502Swpaul if (ifp->if_flags & IFF_PROMISC) 145141502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 145241502Swpaul else 145341502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 145441502Swpaul 145541502Swpaul /* Set capture broadcast bit to capture broadcast frames. */ 145641502Swpaul if (ifp->if_flags & IFF_BROADCAST) 145741502Swpaul VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 145841502Swpaul else 145941502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 146041502Swpaul 146141502Swpaul /* 146241502Swpaul * Program the multicast filter, if necessary. 146341502Swpaul */ 146441502Swpaul vr_setmulti(sc); 146541502Swpaul 146641502Swpaul /* 146741502Swpaul * Load the address of the RX list. 146841502Swpaul */ 146941502Swpaul CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 147041502Swpaul 147141502Swpaul /* Enable receiver and transmitter. */ 147241502Swpaul CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 147341502Swpaul VR_CMD_TX_ON|VR_CMD_RX_ON| 147441502Swpaul VR_CMD_RX_GO); 147541502Swpaul 147641502Swpaul CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 147741502Swpaul 147841502Swpaul /* 147941502Swpaul * Enable interrupts. 148041502Swpaul */ 148141502Swpaul CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 148241502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 148341502Swpaul 148451432Swpaul mii_mediachg(mii); 148541502Swpaul 148641502Swpaul ifp->if_flags |= IFF_RUNNING; 148741502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 148841502Swpaul 148941502Swpaul (void)splx(s); 149041502Swpaul 149151432Swpaul sc->vr_stat_ch = timeout(vr_tick, sc, hz); 149251432Swpaul 149341502Swpaul return; 149441502Swpaul} 149541502Swpaul 149641502Swpaul/* 149741502Swpaul * Set media options. 149841502Swpaul */ 149941502Swpaulstatic int vr_ifmedia_upd(ifp) 150041502Swpaul struct ifnet *ifp; 150141502Swpaul{ 150241502Swpaul struct vr_softc *sc; 150341502Swpaul 150441502Swpaul sc = ifp->if_softc; 150541502Swpaul 150651432Swpaul if (ifp->if_flags & IFF_UP) 150751432Swpaul vr_init(sc); 150841502Swpaul 150941502Swpaul return(0); 151041502Swpaul} 151141502Swpaul 151241502Swpaul/* 151341502Swpaul * Report current media status. 151441502Swpaul */ 151541502Swpaulstatic void vr_ifmedia_sts(ifp, ifmr) 151641502Swpaul struct ifnet *ifp; 151741502Swpaul struct ifmediareq *ifmr; 151841502Swpaul{ 151941502Swpaul struct vr_softc *sc; 152051432Swpaul struct mii_data *mii; 152141502Swpaul 152241502Swpaul sc = ifp->if_softc; 152351432Swpaul mii = device_get_softc(sc->vr_miibus); 152451432Swpaul mii_pollstat(mii); 152551432Swpaul ifmr->ifm_active = mii->mii_media_active; 152651432Swpaul ifmr->ifm_status = mii->mii_media_status; 152741502Swpaul 152841502Swpaul return; 152941502Swpaul} 153041502Swpaul 153141502Swpaulstatic int vr_ioctl(ifp, command, data) 153241502Swpaul struct ifnet *ifp; 153341502Swpaul u_long command; 153441502Swpaul caddr_t data; 153541502Swpaul{ 153641502Swpaul struct vr_softc *sc = ifp->if_softc; 153741502Swpaul struct ifreq *ifr = (struct ifreq *) data; 153851432Swpaul struct mii_data *mii; 153941502Swpaul int s, error = 0; 154041502Swpaul 154141502Swpaul s = splimp(); 154241502Swpaul 154341502Swpaul switch(command) { 154441502Swpaul case SIOCSIFADDR: 154541502Swpaul case SIOCGIFADDR: 154641502Swpaul case SIOCSIFMTU: 154741502Swpaul error = ether_ioctl(ifp, command, data); 154841502Swpaul break; 154941502Swpaul case SIOCSIFFLAGS: 155041502Swpaul if (ifp->if_flags & IFF_UP) { 155141502Swpaul vr_init(sc); 155241502Swpaul } else { 155341502Swpaul if (ifp->if_flags & IFF_RUNNING) 155441502Swpaul vr_stop(sc); 155541502Swpaul } 155641502Swpaul error = 0; 155741502Swpaul break; 155841502Swpaul case SIOCADDMULTI: 155941502Swpaul case SIOCDELMULTI: 156041502Swpaul vr_setmulti(sc); 156141502Swpaul error = 0; 156241502Swpaul break; 156341502Swpaul case SIOCGIFMEDIA: 156441502Swpaul case SIOCSIFMEDIA: 156551432Swpaul mii = device_get_softc(sc->vr_miibus); 156651432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 156741502Swpaul break; 156841502Swpaul default: 156941502Swpaul error = EINVAL; 157041502Swpaul break; 157141502Swpaul } 157241502Swpaul 157341502Swpaul (void)splx(s); 157441502Swpaul 157541502Swpaul return(error); 157641502Swpaul} 157741502Swpaul 157841502Swpaulstatic void vr_watchdog(ifp) 157941502Swpaul struct ifnet *ifp; 158041502Swpaul{ 158141502Swpaul struct vr_softc *sc; 158241502Swpaul 158341502Swpaul sc = ifp->if_softc; 158441502Swpaul 158541502Swpaul ifp->if_oerrors++; 158641502Swpaul printf("vr%d: watchdog timeout\n", sc->vr_unit); 158741502Swpaul 158841502Swpaul vr_stop(sc); 158941502Swpaul vr_reset(sc); 159041502Swpaul vr_init(sc); 159141502Swpaul 159241502Swpaul if (ifp->if_snd.ifq_head != NULL) 159341502Swpaul vr_start(ifp); 159441502Swpaul 159541502Swpaul return; 159641502Swpaul} 159741502Swpaul 159841502Swpaul/* 159941502Swpaul * Stop the adapter and free any mbufs allocated to the 160041502Swpaul * RX and TX lists. 160141502Swpaul */ 160241502Swpaulstatic void vr_stop(sc) 160341502Swpaul struct vr_softc *sc; 160441502Swpaul{ 160541502Swpaul register int i; 160641502Swpaul struct ifnet *ifp; 160741502Swpaul 160841502Swpaul ifp = &sc->arpcom.ac_if; 160941502Swpaul ifp->if_timer = 0; 161041502Swpaul 161151432Swpaul untimeout(vr_tick, sc, sc->vr_stat_ch); 161251432Swpaul 161341502Swpaul VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 161441502Swpaul VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 161541502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 161641502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 161741502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 161841502Swpaul 161941502Swpaul /* 162041502Swpaul * Free data in the RX lists. 162141502Swpaul */ 162241502Swpaul for (i = 0; i < VR_RX_LIST_CNT; i++) { 162341502Swpaul if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 162441502Swpaul m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 162541502Swpaul sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 162641502Swpaul } 162741502Swpaul } 162841502Swpaul bzero((char *)&sc->vr_ldata->vr_rx_list, 162941502Swpaul sizeof(sc->vr_ldata->vr_rx_list)); 163041502Swpaul 163141502Swpaul /* 163241502Swpaul * Free the TX list buffers. 163341502Swpaul */ 163441502Swpaul for (i = 0; i < VR_TX_LIST_CNT; i++) { 163541502Swpaul if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 163641502Swpaul m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 163741502Swpaul sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 163841502Swpaul } 163941502Swpaul } 164041502Swpaul 164141502Swpaul bzero((char *)&sc->vr_ldata->vr_tx_list, 164241502Swpaul sizeof(sc->vr_ldata->vr_tx_list)); 164341502Swpaul 164441502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 164541502Swpaul 164641502Swpaul return; 164741502Swpaul} 164841502Swpaul 164941502Swpaul/* 165041502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 165141502Swpaul * get confused by errant DMAs when rebooting. 165241502Swpaul */ 165349610Swpaulstatic void vr_shutdown(dev) 165449610Swpaul device_t dev; 165541502Swpaul{ 165649610Swpaul struct vr_softc *sc; 165741502Swpaul 165849610Swpaul sc = device_get_softc(dev); 165949610Swpaul 166041502Swpaul vr_stop(sc); 166141502Swpaul 166241502Swpaul return; 166341502Swpaul} 1664