if_vr.c revision 227843
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 227843 2011-11-22 21:28:20Z marius $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various network adapters based on the VIA Rhine 4041502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4141502Swpaul * Datasheets are available at http://www.via.com.tw. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 47131503Sbms 4841502Swpaul/* 4941502Swpaul * The VIA Rhine controllers are similar in some respects to the 5041502Swpaul * the DEC tulip chips, except less complicated. The controller 5141502Swpaul * uses an MII bus and an external physical layer interface. The 5241502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5341502Swpaul * multicast filter. Transmit and receive descriptors are similar 5441502Swpaul * to the tulip. 5541502Swpaul * 56168953Sphk * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 5741502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5841502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5941502Swpaul * at longword boundaries, so we have to do a buffer copy before 6041502Swpaul * transmission. 6141502Swpaul */ 6241502Swpaul 63150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 64150968Sglebius#include "opt_device_polling.h" 65150968Sglebius#endif 66150968Sglebius 6741502Swpaul#include <sys/param.h> 6841502Swpaul#include <sys/systm.h> 69177050Syongari#include <sys/bus.h> 70177050Syongari#include <sys/endian.h> 71177050Syongari#include <sys/kernel.h> 72177050Syongari#include <sys/malloc.h> 7341502Swpaul#include <sys/mbuf.h> 74129878Sphk#include <sys/module.h> 75177050Syongari#include <sys/rman.h> 7641502Swpaul#include <sys/socket.h> 77177050Syongari#include <sys/sockio.h> 78177050Syongari#include <sys/sysctl.h> 79177050Syongari#include <sys/taskqueue.h> 8041502Swpaul 81177050Syongari#include <net/bpf.h> 8241502Swpaul#include <net/if.h> 8341502Swpaul#include <net/ethernet.h> 8441502Swpaul#include <net/if_dl.h> 8541502Swpaul#include <net/if_media.h> 86147256Sbrooks#include <net/if_types.h> 87177050Syongari#include <net/if_vlan_var.h> 8841502Swpaul 89177050Syongari#include <dev/mii/mii.h> 9051432Swpaul#include <dev/mii/miivar.h> 9151432Swpaul 92172555Syongari#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9441502Swpaul 95177050Syongari#include <machine/bus.h> 9641502Swpaul 97177047Syongari#include <dev/vr/if_vrreg.h> 9841502Swpaul 99177050Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 100177050Syongari#include "miibus_if.h" 101177050Syongari 102113506SmdoddMODULE_DEPEND(vr, pci, 1, 1, 1); 103113506SmdoddMODULE_DEPEND(vr, ether, 1, 1, 1); 10459758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 10559758Speter 106177050Syongari/* Define to show Rx/Tx error status. */ 107177050Syongari#undef VR_SHOW_ERRORS 108177050Syongari#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 10951432Swpaul 11041502Swpaul/* 111177050Syongari * Various supported device vendors/types, their names & quirks. 11241502Swpaul */ 113168952Sphk#define VR_Q_NEEDALIGN (1<<0) 114168952Sphk#define VR_Q_CSUM (1<<1) 115177050Syongari#define VR_Q_CAM (1<<2) 116168952Sphk 117226171Smariusstatic const struct vr_type { 118168952Sphk u_int16_t vr_vid; 119168952Sphk u_int16_t vr_did; 120168952Sphk int vr_quirks; 121226171Smarius const char *vr_name; 122226171Smarius} const vr_devs[] = { 123168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE, 124168827Sphk VR_Q_NEEDALIGN, 125168827Sphk "VIA VT3043 Rhine I 10/100BaseTX" }, 126168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127168827Sphk VR_Q_NEEDALIGN, 128168827Sphk "VIA VT86C100A Rhine II 10/100BaseTX" }, 129168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130168827Sphk 0, 131168827Sphk "VIA VT6102 Rhine II 10/100BaseTX" }, 132168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133168827Sphk 0, 134168827Sphk "VIA VT6105 Rhine III 10/100BaseTX" }, 135168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136185962Syongari VR_Q_CSUM, 137168827Sphk "VIA VT6105M Rhine III 10/100BaseTX" }, 138168827Sphk { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139168827Sphk VR_Q_NEEDALIGN, 140168827Sphk "Delta Electronics Rhine II 10/100BaseTX" }, 141168827Sphk { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142168827Sphk VR_Q_NEEDALIGN, 143168827Sphk "Addtron Technology Rhine II 10/100BaseTX" }, 144168813Sphk { 0, 0, 0, NULL } 14541502Swpaul}; 14641502Swpaul 147142407Simpstatic int vr_probe(device_t); 148142407Simpstatic int vr_attach(device_t); 149142407Simpstatic int vr_detach(device_t); 150177050Syongaristatic int vr_shutdown(device_t); 151177050Syongaristatic int vr_suspend(device_t); 152177050Syongaristatic int vr_resume(device_t); 15341502Swpaul 154177050Syongaristatic void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155177050Syongaristatic int vr_dma_alloc(struct vr_softc *); 156177050Syongaristatic void vr_dma_free(struct vr_softc *); 157177050Syongaristatic __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158177050Syongaristatic int vr_newbuf(struct vr_softc *, int); 15941502Swpaul 160177050Syongari#ifndef __NO_STRICT_ALIGNMENT 161177050Syongaristatic __inline void vr_fixup_rx(struct mbuf *); 162177050Syongari#endif 163193096Sattiliostatic int vr_rxeof(struct vr_softc *); 164142407Simpstatic void vr_txeof(struct vr_softc *); 165142407Simpstatic void vr_tick(void *); 166177050Syongaristatic int vr_error(struct vr_softc *, uint16_t); 167177050Syongaristatic void vr_tx_underrun(struct vr_softc *); 168142407Simpstatic void vr_intr(void *); 169142407Simpstatic void vr_start(struct ifnet *); 170142407Simpstatic void vr_start_locked(struct ifnet *); 171177050Syongaristatic int vr_encap(struct vr_softc *, struct mbuf **); 172142407Simpstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 173142407Simpstatic void vr_init(void *); 174142407Simpstatic void vr_init_locked(struct vr_softc *); 175177050Syongaristatic void vr_tx_start(struct vr_softc *); 176177050Syongaristatic void vr_rx_start(struct vr_softc *); 177177050Syongaristatic int vr_tx_stop(struct vr_softc *); 178177050Syongaristatic int vr_rx_stop(struct vr_softc *); 179142407Simpstatic void vr_stop(struct vr_softc *); 180177050Syongaristatic void vr_watchdog(struct vr_softc *); 181142407Simpstatic int vr_ifmedia_upd(struct ifnet *); 182142407Simpstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 18341502Swpaul 184177050Syongaristatic int vr_miibus_readreg(device_t, int, int); 185177050Syongaristatic int vr_miibus_writereg(device_t, int, int, int); 186142407Simpstatic void vr_miibus_statchg(device_t); 18741502Swpaul 188180552Syongaristatic void vr_cam_mask(struct vr_softc *, uint32_t, int); 189180552Syongaristatic int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 190177050Syongaristatic void vr_set_filter(struct vr_softc *); 191168946Sphkstatic void vr_reset(const struct vr_softc *); 192177050Syongaristatic int vr_tx_ring_init(struct vr_softc *); 193177050Syongaristatic int vr_rx_ring_init(struct vr_softc *); 194177050Syongaristatic void vr_setwol(struct vr_softc *); 195177050Syongaristatic void vr_clrwol(struct vr_softc *); 196177050Syongaristatic int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 19741502Swpaul 198226171Smariusstatic const struct vr_tx_threshold_table { 199177050Syongari int tx_cfg; 200177050Syongari int bcr_cfg; 201177050Syongari int value; 202226171Smarius} const vr_tx_threshold_tables[] = { 203177050Syongari { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 204177050Syongari { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 205177050Syongari { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 206177050Syongari { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 207177050Syongari { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 208177050Syongari { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 209177050Syongari}; 21049610Swpaul 21149610Swpaulstatic device_method_t vr_methods[] = { 21249610Swpaul /* Device interface */ 21349610Swpaul DEVMETHOD(device_probe, vr_probe), 21449610Swpaul DEVMETHOD(device_attach, vr_attach), 21549610Swpaul DEVMETHOD(device_detach, vr_detach), 21649610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 217177050Syongari DEVMETHOD(device_suspend, vr_suspend), 218177050Syongari DEVMETHOD(device_resume, vr_resume), 21951432Swpaul 22051432Swpaul /* MII interface */ 22151432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 22251432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 22351432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 22451432Swpaul 225227843Smarius DEVMETHOD_END 22649610Swpaul}; 22749610Swpaul 22849610Swpaulstatic driver_t vr_driver = { 22951455Swpaul "vr", 23049610Swpaul vr_methods, 23149610Swpaul sizeof(struct vr_softc) 23249610Swpaul}; 23349610Swpaul 23449610Swpaulstatic devclass_t vr_devclass; 23549610Swpaul 236113506SmdoddDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 23751473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 23849610Swpaul 239102336Salfredstatic int 240177050Syongarivr_miibus_readreg(device_t dev, int phy, int reg) 24141502Swpaul{ 242177050Syongari struct vr_softc *sc; 243177050Syongari int i; 24441502Swpaul 245177050Syongari sc = device_get_softc(dev); 246110168Ssilby 247131503Sbms /* Set the register address. */ 248177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 249110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 250131503Sbms 251177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 252177050Syongari DELAY(1); 253110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 254110168Ssilby break; 255110168Ssilby } 256177050Syongari if (i == VR_MII_TIMEOUT) 257177050Syongari device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 258110168Ssilby 259177050Syongari return (CSR_READ_2(sc, VR_MIIDATA)); 260110168Ssilby} 261110168Ssilby 262102336Salfredstatic int 263177050Syongarivr_miibus_writereg(device_t dev, int phy, int reg, int data) 26441502Swpaul{ 265177050Syongari struct vr_softc *sc; 266177050Syongari int i; 26741502Swpaul 268177050Syongari sc = device_get_softc(dev); 269110168Ssilby 270131503Sbms /* Set the register address and data to write. */ 271177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 272177050Syongari CSR_WRITE_2(sc, VR_MIIDATA, data); 273110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 274110168Ssilby 275177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 276177050Syongari DELAY(1); 277110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 278110168Ssilby break; 279110168Ssilby } 280177050Syongari if (i == VR_MII_TIMEOUT) 281177050Syongari device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 282177050Syongari reg); 283110168Ssilby 284131503Sbms return (0); 285110168Ssilby} 286110168Ssilby 287177050Syongari/* 288177050Syongari * In order to fiddle with the 289177050Syongari * 'full-duplex' and '100Mbps' bits in the netconfig register, we 290177050Syongari * first have to put the transmit and/or receive logic in the idle state. 291177050Syongari */ 292177050Syongaristatic void 293223405Syongarivr_miibus_statchg(device_t dev) 29451432Swpaul{ 295177050Syongari struct vr_softc *sc; 296177050Syongari struct mii_data *mii; 297177050Syongari struct ifnet *ifp; 298177050Syongari int lfdx, mfdx; 299177050Syongari uint8_t cr0, cr1, fc; 30041502Swpaul 301223405Syongari sc = device_get_softc(dev); 302177050Syongari mii = device_get_softc(sc->vr_miibus); 303177050Syongari ifp = sc->vr_ifp; 304177050Syongari if (mii == NULL || ifp == NULL || 305223405Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 306177050Syongari return; 30741502Swpaul 308223405Syongari sc->vr_link = 0; 309223405Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 310223405Syongari (IFM_ACTIVE | IFM_AVALID)) { 311223405Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 312223405Syongari case IFM_10_T: 313223405Syongari case IFM_100_TX: 314177050Syongari sc->vr_link = 1; 315223405Syongari break; 316223405Syongari default: 317223405Syongari break; 318223405Syongari } 319223405Syongari } 320177050Syongari 321177050Syongari if (sc->vr_link != 0) { 322177050Syongari cr0 = CSR_READ_1(sc, VR_CR0); 323177050Syongari cr1 = CSR_READ_1(sc, VR_CR1); 324177050Syongari mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 325177050Syongari lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 326177050Syongari if (mfdx != lfdx) { 327177050Syongari if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 328177050Syongari if (vr_tx_stop(sc) != 0 || 329177050Syongari vr_rx_stop(sc) != 0) { 330177050Syongari device_printf(sc->vr_dev, 331177050Syongari "%s: Tx/Rx shutdown error -- " 332177050Syongari "resetting\n", __func__); 333177050Syongari sc->vr_flags |= VR_F_RESTART; 334177050Syongari VR_UNLOCK(sc); 335177050Syongari return; 336177050Syongari } 337177050Syongari } 338177050Syongari if (lfdx) 339177050Syongari cr1 |= VR_CR1_FULLDUPLEX; 340177050Syongari else 341177050Syongari cr1 &= ~VR_CR1_FULLDUPLEX; 342177050Syongari CSR_WRITE_1(sc, VR_CR1, cr1); 343177050Syongari } 344177050Syongari fc = 0; 345177050Syongari#ifdef notyet 346177050Syongari /* Configure flow-control. */ 347177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 348177050Syongari fc = CSR_READ_1(sc, VR_FLOWCR1); 349177050Syongari fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 350177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 351177050Syongari IFM_ETH_RXPAUSE) != 0) 352177050Syongari fc |= VR_FLOWCR1_RXPAUSE; 353177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 354177050Syongari IFM_ETH_TXPAUSE) != 0) 355177050Syongari fc |= VR_FLOWCR1_TXPAUSE; 356177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, fc); 357177050Syongari } else if (sc->vr_revid >= REV_ID_VT6102_A) { 358177050Syongari /* No Tx puase capability available for Rhine II. */ 359177050Syongari fc = CSR_READ_1(sc, VR_MISC_CR0); 360177050Syongari fc &= ~VR_MISCCR0_RXPAUSE; 361177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 362177050Syongari IFM_ETH_RXPAUSE) != 0) 363177050Syongari fc |= VR_MISCCR0_RXPAUSE; 364177050Syongari CSR_WRITE_1(sc, VR_MISC_CR0, fc); 365177050Syongari } 366177050Syongari#endif 367177050Syongari vr_rx_start(sc); 368177050Syongari vr_tx_start(sc); 369177050Syongari } else { 370177050Syongari if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 371177050Syongari device_printf(sc->vr_dev, 372177050Syongari "%s: Tx/Rx shutdown error -- resetting\n", 373177050Syongari __func__); 374177050Syongari sc->vr_flags |= VR_F_RESTART; 375177050Syongari } 376177050Syongari } 37751432Swpaul} 37851432Swpaul 379180552Syongari 380180552Syongaristatic void 381180552Syongarivr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 382180552Syongari{ 383180552Syongari 384180552Syongari if (type == VR_MCAST_CAM) 385180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 386180552Syongari else 387180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 388180552Syongari CSR_WRITE_4(sc, VR_CAMMASK, mask); 389180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 390180552Syongari} 391180552Syongari 392177050Syongaristatic int 393180552Syongarivr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 39451432Swpaul{ 395177050Syongari int i; 39651432Swpaul 397180552Syongari if (type == VR_MCAST_CAM) { 398180552Syongari if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 399180552Syongari return (EINVAL); 400180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 401180552Syongari } else 402180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 403177050Syongari 404177050Syongari /* Set CAM entry address. */ 405177050Syongari CSR_WRITE_1(sc, VR_CAMADDR, idx); 406177050Syongari /* Set CAM entry data. */ 407180552Syongari if (type == VR_MCAST_CAM) { 408180552Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) 409180552Syongari CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 410180552Syongari } else { 411180552Syongari CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 412180552Syongari CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 413180552Syongari } 414180552Syongari DELAY(10); 415177050Syongari /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 416180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 417177050Syongari for (i = 0; i < VR_TIMEOUT; i++) { 418177050Syongari DELAY(1); 419177050Syongari if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 420177050Syongari break; 421177050Syongari } 422177050Syongari 423177050Syongari if (i == VR_TIMEOUT) 424177050Syongari device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 425177050Syongari __func__); 426180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 427177050Syongari 428177050Syongari return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 42941502Swpaul} 43041502Swpaul 43141502Swpaul/* 43241502Swpaul * Program the 64-bit multicast hash filter. 43341502Swpaul */ 434102336Salfredstatic void 435177050Syongarivr_set_filter(struct vr_softc *sc) 43641502Swpaul{ 437177050Syongari struct ifnet *ifp; 438177050Syongari int h; 439131503Sbms uint32_t hashes[2] = { 0, 0 }; 44041502Swpaul struct ifmultiaddr *ifma; 441131503Sbms uint8_t rxfilt; 442177050Syongari int error, mcnt; 443177050Syongari uint32_t cam_mask; 44441502Swpaul 445131518Sbms VR_LOCK_ASSERT(sc); 44641502Swpaul 447177050Syongari ifp = sc->vr_ifp; 44841502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 449185014Syongari rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 450185014Syongari VR_RXCFG_RX_MULTI); 451177050Syongari if (ifp->if_flags & IFF_BROADCAST) 452177050Syongari rxfilt |= VR_RXCFG_RX_BROAD; 45341502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 45441502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 455177050Syongari if (ifp->if_flags & IFF_PROMISC) 456177050Syongari rxfilt |= VR_RXCFG_RX_PROMISC; 45741502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 45841502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 45941502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 46041502Swpaul return; 46141502Swpaul } 46241502Swpaul 463131503Sbms /* Now program new ones. */ 464177050Syongari error = 0; 465180552Syongari mcnt = 0; 466195049Srwatson if_maddr_rlock(ifp); 467177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 468177050Syongari /* 469177050Syongari * For hardwares that have CAM capability, use 470177050Syongari * 32 entries multicast perfect filter. 471177050Syongari */ 472177050Syongari cam_mask = 0; 473177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 474177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 475177050Syongari continue; 476180552Syongari error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 477177050Syongari LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 478177050Syongari if (error != 0) { 479177050Syongari cam_mask = 0; 480177050Syongari break; 481177050Syongari } 482177050Syongari cam_mask |= 1 << mcnt; 483177050Syongari mcnt++; 484177050Syongari } 485180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 48641502Swpaul } 487177050Syongari 488177050Syongari if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 489177050Syongari /* 490177050Syongari * If there are too many multicast addresses or 491177050Syongari * setting multicast CAM filter failed, use hash 492177050Syongari * table based filtering. 493177050Syongari */ 494180552Syongari mcnt = 0; 495177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 496177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 497177050Syongari continue; 498177050Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 499177050Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 500177050Syongari if (h < 32) 501177050Syongari hashes[0] |= (1 << h); 502177050Syongari else 503177050Syongari hashes[1] |= (1 << (h - 32)); 504177050Syongari mcnt++; 505177050Syongari } 506177050Syongari } 507195049Srwatson if_maddr_runlock(ifp); 50841502Swpaul 509177050Syongari if (mcnt > 0) 51041502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 51141502Swpaul 51241502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 51341502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 51441502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 51541502Swpaul} 51641502Swpaul 517102336Salfredstatic void 518168946Sphkvr_reset(const struct vr_softc *sc) 51941502Swpaul{ 520177050Syongari int i; 52141502Swpaul 522151773Sjhb /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 523131518Sbms 524177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 525177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 526177050Syongari /* VT86C100A needs more delay after reset. */ 527177050Syongari DELAY(100); 528177050Syongari } 52941502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 53041502Swpaul DELAY(10); 531177050Syongari if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 53241502Swpaul break; 53341502Swpaul } 534107220Ssilby if (i == VR_TIMEOUT) { 535177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 536162315Sglebius device_printf(sc->vr_dev, "reset never completed!\n"); 537107220Ssilby else { 538177050Syongari /* Use newer force reset command. */ 539177050Syongari device_printf(sc->vr_dev, 540177050Syongari "Using force reset command.\n"); 541107220Ssilby VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 542177050Syongari /* 543177050Syongari * Wait a little while for the chip to get its brains 544177050Syongari * in order. 545177050Syongari */ 546177050Syongari DELAY(2000); 547107220Ssilby } 548107220Ssilby } 54941502Swpaul 55041502Swpaul} 55141502Swpaul 55241502Swpaul/* 55341502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 554168813Sphk * IDs against our list and return a match or NULL 555168813Sphk */ 556226171Smariusstatic const struct vr_type * 557168813Sphkvr_match(device_t dev) 558168813Sphk{ 559226171Smarius const struct vr_type *t = vr_devs; 560168813Sphk 561168813Sphk for (t = vr_devs; t->vr_name != NULL; t++) 562168813Sphk if ((pci_get_vendor(dev) == t->vr_vid) && 563168813Sphk (pci_get_device(dev) == t->vr_did)) 564168813Sphk return (t); 565168813Sphk return (NULL); 566168813Sphk} 567168813Sphk 568168813Sphk/* 569168813Sphk * Probe for a VIA Rhine chip. Check the PCI vendor and device 57041502Swpaul * IDs against our list and return a device name if we find a match. 57141502Swpaul */ 572102336Salfredstatic int 573131503Sbmsvr_probe(device_t dev) 57441502Swpaul{ 575226171Smarius const struct vr_type *t; 57641502Swpaul 577168813Sphk t = vr_match(dev); 578168813Sphk if (t != NULL) { 579168813Sphk device_set_desc(dev, t->vr_name); 580168813Sphk return (BUS_PROBE_DEFAULT); 58141502Swpaul } 582131503Sbms return (ENXIO); 58341502Swpaul} 58441502Swpaul 58541502Swpaul/* 58641502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 58741502Swpaul * setup and ethernet/BPF attach. 58841502Swpaul */ 589102336Salfredstatic int 590168946Sphkvr_attach(device_t dev) 59141502Swpaul{ 59241502Swpaul struct vr_softc *sc; 59341502Swpaul struct ifnet *ifp; 594226171Smarius const struct vr_type *t; 595177050Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 596177050Syongari int error, rid; 597213893Smarius int i, phy, pmc; 59841502Swpaul 59949610Swpaul sc = device_get_softc(dev); 600162315Sglebius sc->vr_dev = dev; 601168813Sphk t = vr_match(dev); 602168813Sphk KASSERT(t != NULL, ("Lost if_vr device match")); 603168813Sphk sc->vr_quirks = t->vr_quirks; 604168813Sphk device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 60541502Swpaul 60693818Sjhb mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 607131518Sbms MTX_DEF); 608151911Sjhb callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 609177050Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 610177050Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 611177050Syongari OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 612177050Syongari vr_sysctl_stats, "I", "Statistics"); 613151911Sjhb 614177050Syongari error = 0; 615177050Syongari 61641502Swpaul /* 61741502Swpaul * Map control/status registers. 61841502Swpaul */ 61972813Swpaul pci_enable_busmaster(dev); 620177050Syongari sc->vr_revid = pci_get_revid(dev); 621177050Syongari device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 62241502Swpaul 623177050Syongari sc->vr_res_id = PCIR_BAR(0); 624177050Syongari sc->vr_res_type = SYS_RES_IOPORT; 625177050Syongari sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 626177050Syongari &sc->vr_res_id, RF_ACTIVE); 62749610Swpaul if (sc->vr_res == NULL) { 628177050Syongari device_printf(dev, "couldn't map ports\n"); 62949610Swpaul error = ENXIO; 63041502Swpaul goto fail; 63141502Swpaul } 63241502Swpaul 633177050Syongari /* Allocate interrupt. */ 63449610Swpaul rid = 0; 635127135Snjl sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 63649610Swpaul RF_SHAREABLE | RF_ACTIVE); 63749610Swpaul 63849610Swpaul if (sc->vr_irq == NULL) { 639151773Sjhb device_printf(dev, "couldn't map interrupt\n"); 64049610Swpaul error = ENXIO; 64141502Swpaul goto fail; 64241502Swpaul } 64341502Swpaul 644151773Sjhb /* Allocate ifnet structure. */ 645151773Sjhb ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 646151773Sjhb if (ifp == NULL) { 647177050Syongari device_printf(dev, "couldn't allocate ifnet structure\n"); 648151773Sjhb error = ENOSPC; 649151773Sjhb goto fail; 650151773Sjhb } 651151773Sjhb ifp->if_softc = sc; 652151773Sjhb if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 653151773Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 654151773Sjhb ifp->if_ioctl = vr_ioctl; 655151773Sjhb ifp->if_start = vr_start; 656151773Sjhb ifp->if_init = vr_init; 657177050Syongari IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 658177050Syongari ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 659151773Sjhb IFQ_SET_READY(&ifp->if_snd); 660168827Sphk 661177050Syongari /* Configure Tx FIFO threshold. */ 662177050Syongari sc->vr_txthresh = VR_TXTHRESH_MIN; 663177050Syongari if (sc->vr_revid < REV_ID_VT6105_A0) { 664177050Syongari /* 665177050Syongari * Use store and forward mode for Rhine I/II. 666177050Syongari * Otherwise they produce a lot of Tx underruns and 667177050Syongari * it would take a while to get working FIFO threshold 668177050Syongari * value. 669177050Syongari */ 670177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 671177050Syongari } 672177050Syongari if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 673177050Syongari ifp->if_hwassist = VR_CSUM_FEATURES; 674168827Sphk ifp->if_capabilities |= IFCAP_HWCSUM; 675177050Syongari /* 676177050Syongari * To update checksum field the hardware may need to 677177050Syongari * store entire frames into FIFO before transmitting. 678177050Syongari */ 679177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 680168827Sphk } 681168827Sphk 682177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A && 683219902Sjhb pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 684177050Syongari ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 685177050Syongari 686177050Syongari /* Rhine supports oversized VLAN frame. */ 687168973Sphk ifp->if_capabilities |= IFCAP_VLAN_MTU; 688151773Sjhb ifp->if_capenable = ifp->if_capabilities; 689151773Sjhb#ifdef DEVICE_POLLING 690151773Sjhb ifp->if_capabilities |= IFCAP_POLLING; 691151773Sjhb#endif 692151773Sjhb 69376586Swpaul /* 69476586Swpaul * Windows may put the chip in suspend mode when it 69576586Swpaul * shuts down. Be sure to kick it in the head to wake it 69676586Swpaul * up again. 69776586Swpaul */ 698219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 699172555Syongari VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 70076586Swpaul 701131503Sbms /* 70241502Swpaul * Get station address. The way the Rhine chips work, 70341502Swpaul * you're not allowed to directly access the EEPROM once 70441502Swpaul * they've been programmed a special way. Consequently, 70541502Swpaul * we need to read the node address from the PAR0 and PAR1 70641502Swpaul * registers. 707177050Syongari * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 708177050Syongari * VR_CFGC and VR_CFGD such that memory mapped IO configured 709177050Syongari * by driver is reset to default state. 71041502Swpaul */ 71141502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 712177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 713177050Syongari DELAY(1); 714177050Syongari if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 715177050Syongari break; 716177050Syongari } 717177050Syongari if (i == 0) 718177050Syongari device_printf(dev, "Reloading EEPROM timeout!\n"); 71941502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 72041502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 72141502Swpaul 722177050Syongari /* Reset the adapter. */ 723177050Syongari vr_reset(sc); 724177050Syongari /* Ack intr & disable further interrupts. */ 725177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 726177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 727177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A) 728177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 72951432Swpaul 730177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 731177050Syongari pci_write_config(dev, VR_PCI_MODE2, 732177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 733177050Syongari VR_MODE2_MODE10T, 1); 734177050Syongari } else { 735177050Syongari /* Report error instead of retrying forever. */ 736177050Syongari pci_write_config(dev, VR_PCI_MODE2, 737177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 738177050Syongari VR_MODE2_PCEROPT, 1); 739177050Syongari /* Detect MII coding error. */ 740177050Syongari pci_write_config(dev, VR_PCI_MODE3, 741177050Syongari pci_read_config(dev, VR_PCI_MODE3, 1) | 742177050Syongari VR_MODE3_MIION, 1); 743177050Syongari if (sc->vr_revid >= REV_ID_VT6105_LOM && 744177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 745177050Syongari pci_write_config(dev, VR_PCI_MODE2, 746177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 747177050Syongari VR_MODE2_MODE10T, 1); 748177050Syongari /* Enable Memory-Read-Multiple. */ 749177050Syongari if (sc->vr_revid >= REV_ID_VT6107_A1 && 750177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 751177050Syongari pci_write_config(dev, VR_PCI_MODE2, 752177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 753177050Syongari VR_MODE2_MRDPL, 1); 754177050Syongari } 755177050Syongari /* Disable MII AUTOPOLL. */ 756177050Syongari VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 757177050Syongari 758177050Syongari if (vr_dma_alloc(sc) != 0) { 75949610Swpaul error = ENXIO; 76049610Swpaul goto fail; 76141502Swpaul } 76241502Swpaul 763213893Smarius /* Do MII setup. */ 764177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) 765213893Smarius phy = 1; 766177050Syongari else 767213893Smarius phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 768213893Smarius error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 769213893Smarius vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 770213893Smarius if (error != 0) { 771213893Smarius device_printf(dev, "attaching PHYs failed\n"); 77241502Swpaul goto fail; 77341502Swpaul } 77441502Swpaul 775131503Sbms /* Call MI attach routine. */ 776106936Ssam ether_ifattach(ifp, eaddr); 777177050Syongari /* 778177050Syongari * Tell the upper layer(s) we support long frames. 779177050Syongari * Must appear after the call to ether_ifattach() because 780177050Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 781177050Syongari */ 782177050Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 78341502Swpaul 784177050Syongari /* Hook interrupt last to avoid having to lock softc. */ 785131518Sbms error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 786166901Spiso NULL, vr_intr, sc, &sc->vr_intrhand); 787112872Snjl 788112872Snjl if (error) { 789151773Sjhb device_printf(dev, "couldn't set up irq\n"); 790113609Snjl ether_ifdetach(ifp); 791112872Snjl goto fail; 792112872Snjl } 793112872Snjl 79441502Swpaulfail: 795112872Snjl if (error) 796112872Snjl vr_detach(dev); 79767087Swpaul 798131503Sbms return (error); 79941502Swpaul} 80041502Swpaul 801113609Snjl/* 802113609Snjl * Shutdown hardware and free up resources. This can be called any 803113609Snjl * time after the mutex has been initialized. It is called in both 804113609Snjl * the error case in attach and the normal detach case so it needs 805113609Snjl * to be careful about only freeing resources that have actually been 806113609Snjl * allocated. 807113609Snjl */ 808102336Salfredstatic int 809131503Sbmsvr_detach(device_t dev) 81049610Swpaul{ 811131503Sbms struct vr_softc *sc = device_get_softc(dev); 812147256Sbrooks struct ifnet *ifp = sc->vr_ifp; 81349610Swpaul 814112880Sjhb KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 815131518Sbms 816150789Sglebius#ifdef DEVICE_POLLING 817177050Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 818150789Sglebius ether_poll_deregister(ifp); 819150789Sglebius#endif 820150789Sglebius 821177050Syongari /* These should only be active if attach succeeded. */ 822113812Simp if (device_is_attached(dev)) { 823151911Sjhb VR_LOCK(sc); 824177050Syongari sc->vr_detach = 1; 825113609Snjl vr_stop(sc); 826151911Sjhb VR_UNLOCK(sc); 827151911Sjhb callout_drain(&sc->vr_stat_callout); 828112872Snjl ether_ifdetach(ifp); 829113609Snjl } 830113609Snjl if (sc->vr_miibus) 831112872Snjl device_delete_child(dev, sc->vr_miibus); 832113609Snjl bus_generic_detach(dev); 83349610Swpaul 834112872Snjl if (sc->vr_intrhand) 835112872Snjl bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 836112872Snjl if (sc->vr_irq) 837112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 838112872Snjl if (sc->vr_res) 839177050Syongari bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 840177050Syongari sc->vr_res); 84151432Swpaul 842151297Sru if (ifp) 843151297Sru if_free(ifp); 844151297Sru 845177050Syongari vr_dma_free(sc); 84649610Swpaul 84767087Swpaul mtx_destroy(&sc->vr_mtx); 84849610Swpaul 849131503Sbms return (0); 85049610Swpaul} 85149610Swpaul 852177050Syongaristruct vr_dmamap_arg { 853177050Syongari bus_addr_t vr_busaddr; 854177050Syongari}; 855177050Syongari 856177050Syongaristatic void 857177050Syongarivr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 858177050Syongari{ 859177050Syongari struct vr_dmamap_arg *ctx; 860177050Syongari 861177050Syongari if (error != 0) 862177050Syongari return; 863177050Syongari ctx = arg; 864177050Syongari ctx->vr_busaddr = segs[0].ds_addr; 865177050Syongari} 866177050Syongari 867177050Syongaristatic int 868177050Syongarivr_dma_alloc(struct vr_softc *sc) 869177050Syongari{ 870177050Syongari struct vr_dmamap_arg ctx; 871177050Syongari struct vr_txdesc *txd; 872177050Syongari struct vr_rxdesc *rxd; 873177050Syongari bus_size_t tx_alignment; 874177050Syongari int error, i; 875177050Syongari 876177050Syongari /* Create parent DMA tag. */ 877177050Syongari error = bus_dma_tag_create( 878177050Syongari bus_get_dma_tag(sc->vr_dev), /* parent */ 879177050Syongari 1, 0, /* alignment, boundary */ 880177050Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 881177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 882177050Syongari NULL, NULL, /* filter, filterarg */ 883177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 884177050Syongari 0, /* nsegments */ 885177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 886177050Syongari 0, /* flags */ 887177050Syongari NULL, NULL, /* lockfunc, lockarg */ 888177050Syongari &sc->vr_cdata.vr_parent_tag); 889177050Syongari if (error != 0) { 890177050Syongari device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 891177050Syongari goto fail; 892177050Syongari } 893177050Syongari /* Create tag for Tx ring. */ 894177050Syongari error = bus_dma_tag_create( 895177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 896177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 897177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 898177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 899177050Syongari NULL, NULL, /* filter, filterarg */ 900177050Syongari VR_TX_RING_SIZE, /* maxsize */ 901177050Syongari 1, /* nsegments */ 902177050Syongari VR_TX_RING_SIZE, /* maxsegsize */ 903177050Syongari 0, /* flags */ 904177050Syongari NULL, NULL, /* lockfunc, lockarg */ 905177050Syongari &sc->vr_cdata.vr_tx_ring_tag); 906177050Syongari if (error != 0) { 907177050Syongari device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 908177050Syongari goto fail; 909177050Syongari } 910177050Syongari 911177050Syongari /* Create tag for Rx ring. */ 912177050Syongari error = bus_dma_tag_create( 913177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 914177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 915177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 916177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 917177050Syongari NULL, NULL, /* filter, filterarg */ 918177050Syongari VR_RX_RING_SIZE, /* maxsize */ 919177050Syongari 1, /* nsegments */ 920177050Syongari VR_RX_RING_SIZE, /* maxsegsize */ 921177050Syongari 0, /* flags */ 922177050Syongari NULL, NULL, /* lockfunc, lockarg */ 923177050Syongari &sc->vr_cdata.vr_rx_ring_tag); 924177050Syongari if (error != 0) { 925177050Syongari device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 926177050Syongari goto fail; 927177050Syongari } 928177050Syongari 929177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 930177050Syongari tx_alignment = sizeof(uint32_t); 931177050Syongari else 932177050Syongari tx_alignment = 1; 933177050Syongari /* Create tag for Tx buffers. */ 934177050Syongari error = bus_dma_tag_create( 935177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 936177050Syongari tx_alignment, 0, /* alignment, boundary */ 937177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 938177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 939177050Syongari NULL, NULL, /* filter, filterarg */ 940177050Syongari MCLBYTES * VR_MAXFRAGS, /* maxsize */ 941177050Syongari VR_MAXFRAGS, /* nsegments */ 942177050Syongari MCLBYTES, /* maxsegsize */ 943177050Syongari 0, /* flags */ 944177050Syongari NULL, NULL, /* lockfunc, lockarg */ 945177050Syongari &sc->vr_cdata.vr_tx_tag); 946177050Syongari if (error != 0) { 947177050Syongari device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 948177050Syongari goto fail; 949177050Syongari } 950177050Syongari 951177050Syongari /* Create tag for Rx buffers. */ 952177050Syongari error = bus_dma_tag_create( 953177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 954177050Syongari VR_RX_ALIGN, 0, /* alignment, boundary */ 955177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 956177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 957177050Syongari NULL, NULL, /* filter, filterarg */ 958177050Syongari MCLBYTES, /* maxsize */ 959177050Syongari 1, /* nsegments */ 960177050Syongari MCLBYTES, /* maxsegsize */ 961177050Syongari 0, /* flags */ 962177050Syongari NULL, NULL, /* lockfunc, lockarg */ 963177050Syongari &sc->vr_cdata.vr_rx_tag); 964177050Syongari if (error != 0) { 965177050Syongari device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 966177050Syongari goto fail; 967177050Syongari } 968177050Syongari 969177050Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 970177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 971177050Syongari (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 972177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 973177050Syongari if (error != 0) { 974177050Syongari device_printf(sc->vr_dev, 975177050Syongari "failed to allocate DMA'able memory for Tx ring\n"); 976177050Syongari goto fail; 977177050Syongari } 978177050Syongari 979177050Syongari ctx.vr_busaddr = 0; 980177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 981177050Syongari sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 982177050Syongari VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 983177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 984177050Syongari device_printf(sc->vr_dev, 985177050Syongari "failed to load DMA'able memory for Tx ring\n"); 986177050Syongari goto fail; 987177050Syongari } 988177050Syongari sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 989177050Syongari 990177050Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 991177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 992177050Syongari (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 993177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 994177050Syongari if (error != 0) { 995177050Syongari device_printf(sc->vr_dev, 996177050Syongari "failed to allocate DMA'able memory for Rx ring\n"); 997177050Syongari goto fail; 998177050Syongari } 999177050Syongari 1000177050Syongari ctx.vr_busaddr = 0; 1001177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1002177050Syongari sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1003177050Syongari VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1004177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1005177050Syongari device_printf(sc->vr_dev, 1006177050Syongari "failed to load DMA'able memory for Rx ring\n"); 1007177050Syongari goto fail; 1008177050Syongari } 1009177050Syongari sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1010177050Syongari 1011177050Syongari /* Create DMA maps for Tx buffers. */ 1012177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1013177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1014177050Syongari txd->tx_m = NULL; 1015177050Syongari txd->tx_dmamap = NULL; 1016177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1017177050Syongari &txd->tx_dmamap); 1018177050Syongari if (error != 0) { 1019177050Syongari device_printf(sc->vr_dev, 1020177050Syongari "failed to create Tx dmamap\n"); 1021177050Syongari goto fail; 1022177050Syongari } 1023177050Syongari } 1024177050Syongari /* Create DMA maps for Rx buffers. */ 1025177050Syongari if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1026177050Syongari &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1027177050Syongari device_printf(sc->vr_dev, 1028177050Syongari "failed to create spare Rx dmamap\n"); 1029177050Syongari goto fail; 1030177050Syongari } 1031177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1032177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1033177050Syongari rxd->rx_m = NULL; 1034177050Syongari rxd->rx_dmamap = NULL; 1035177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1036177050Syongari &rxd->rx_dmamap); 1037177050Syongari if (error != 0) { 1038177050Syongari device_printf(sc->vr_dev, 1039177050Syongari "failed to create Rx dmamap\n"); 1040177050Syongari goto fail; 1041177050Syongari } 1042177050Syongari } 1043177050Syongari 1044177050Syongarifail: 1045177050Syongari return (error); 1046177050Syongari} 1047177050Syongari 1048177050Syongaristatic void 1049177050Syongarivr_dma_free(struct vr_softc *sc) 1050177050Syongari{ 1051177050Syongari struct vr_txdesc *txd; 1052177050Syongari struct vr_rxdesc *rxd; 1053177050Syongari int i; 1054177050Syongari 1055177050Syongari /* Tx ring. */ 1056177050Syongari if (sc->vr_cdata.vr_tx_ring_tag) { 1057177050Syongari if (sc->vr_cdata.vr_tx_ring_map) 1058177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1059177050Syongari sc->vr_cdata.vr_tx_ring_map); 1060177050Syongari if (sc->vr_cdata.vr_tx_ring_map && 1061177050Syongari sc->vr_rdata.vr_tx_ring) 1062177050Syongari bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1063177050Syongari sc->vr_rdata.vr_tx_ring, 1064177050Syongari sc->vr_cdata.vr_tx_ring_map); 1065177050Syongari sc->vr_rdata.vr_tx_ring = NULL; 1066177050Syongari sc->vr_cdata.vr_tx_ring_map = NULL; 1067177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1068177050Syongari sc->vr_cdata.vr_tx_ring_tag = NULL; 1069177050Syongari } 1070177050Syongari /* Rx ring. */ 1071177050Syongari if (sc->vr_cdata.vr_rx_ring_tag) { 1072177050Syongari if (sc->vr_cdata.vr_rx_ring_map) 1073177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1074177050Syongari sc->vr_cdata.vr_rx_ring_map); 1075177050Syongari if (sc->vr_cdata.vr_rx_ring_map && 1076177050Syongari sc->vr_rdata.vr_rx_ring) 1077177050Syongari bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1078177050Syongari sc->vr_rdata.vr_rx_ring, 1079177050Syongari sc->vr_cdata.vr_rx_ring_map); 1080177050Syongari sc->vr_rdata.vr_rx_ring = NULL; 1081177050Syongari sc->vr_cdata.vr_rx_ring_map = NULL; 1082177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1083177050Syongari sc->vr_cdata.vr_rx_ring_tag = NULL; 1084177050Syongari } 1085177050Syongari /* Tx buffers. */ 1086177050Syongari if (sc->vr_cdata.vr_tx_tag) { 1087177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1088177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1089177050Syongari if (txd->tx_dmamap) { 1090177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1091177050Syongari txd->tx_dmamap); 1092177050Syongari txd->tx_dmamap = NULL; 1093177050Syongari } 1094177050Syongari } 1095177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1096177050Syongari sc->vr_cdata.vr_tx_tag = NULL; 1097177050Syongari } 1098177050Syongari /* Rx buffers. */ 1099177050Syongari if (sc->vr_cdata.vr_rx_tag) { 1100177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1101177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1102177050Syongari if (rxd->rx_dmamap) { 1103177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1104177050Syongari rxd->rx_dmamap); 1105177050Syongari rxd->rx_dmamap = NULL; 1106177050Syongari } 1107177050Syongari } 1108177050Syongari if (sc->vr_cdata.vr_rx_sparemap) { 1109177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1110177050Syongari sc->vr_cdata.vr_rx_sparemap); 1111177050Syongari sc->vr_cdata.vr_rx_sparemap = 0; 1112177050Syongari } 1113177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1114177050Syongari sc->vr_cdata.vr_rx_tag = NULL; 1115177050Syongari } 1116177050Syongari 1117177050Syongari if (sc->vr_cdata.vr_parent_tag) { 1118177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1119177050Syongari sc->vr_cdata.vr_parent_tag = NULL; 1120177050Syongari } 1121177050Syongari} 1122177050Syongari 112341502Swpaul/* 112441502Swpaul * Initialize the transmit descriptors. 112541502Swpaul */ 1126102336Salfredstatic int 1127177050Syongarivr_tx_ring_init(struct vr_softc *sc) 112841502Swpaul{ 1129177050Syongari struct vr_ring_data *rd; 1130177050Syongari struct vr_txdesc *txd; 1131177050Syongari bus_addr_t addr; 113241502Swpaul int i; 113341502Swpaul 1134177050Syongari sc->vr_cdata.vr_tx_prod = 0; 1135177050Syongari sc->vr_cdata.vr_tx_cons = 0; 1136177050Syongari sc->vr_cdata.vr_tx_cnt = 0; 1137177050Syongari sc->vr_cdata.vr_tx_pkts = 0; 1138177050Syongari 1139177050Syongari rd = &sc->vr_rdata; 1140177050Syongari bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1141177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1142177050Syongari if (i == VR_TX_RING_CNT - 1) 1143177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 1144177050Syongari else 1145177050Syongari addr = VR_TX_RING_ADDR(sc, i + 1); 1146177050Syongari rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1147177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1148177050Syongari txd->tx_m = NULL; 114941502Swpaul } 115041502Swpaul 1151177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1152177050Syongari sc->vr_cdata.vr_tx_ring_map, 1153177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1154177050Syongari 1155131503Sbms return (0); 115641502Swpaul} 115741502Swpaul 115841502Swpaul/* 115941502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 116041502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 116141502Swpaul * points back to the first. 116241502Swpaul */ 1163102336Salfredstatic int 1164177050Syongarivr_rx_ring_init(struct vr_softc *sc) 116541502Swpaul{ 1166177050Syongari struct vr_ring_data *rd; 1167177050Syongari struct vr_rxdesc *rxd; 1168177050Syongari bus_addr_t addr; 116941502Swpaul int i; 117041502Swpaul 1171177050Syongari sc->vr_cdata.vr_rx_cons = 0; 1172131518Sbms 1173177050Syongari rd = &sc->vr_rdata; 1174177050Syongari bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1175177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1176177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1177177050Syongari rxd->rx_m = NULL; 1178177050Syongari rxd->desc = &rd->vr_rx_ring[i]; 1179177050Syongari if (i == VR_RX_RING_CNT - 1) 1180177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 1181177050Syongari else 1182177050Syongari addr = VR_RX_RING_ADDR(sc, i + 1); 1183177050Syongari rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1184177050Syongari if (vr_newbuf(sc, i) != 0) 1185131503Sbms return (ENOBUFS); 118641502Swpaul } 118741502Swpaul 1188177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1189177050Syongari sc->vr_cdata.vr_rx_ring_map, 1190177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 119141502Swpaul 1192131503Sbms return (0); 119341502Swpaul} 119441502Swpaul 1195177050Syongaristatic __inline void 1196177050Syongarivr_discard_rxbuf(struct vr_rxdesc *rxd) 1197177050Syongari{ 1198177050Syongari struct vr_desc *desc; 1199177050Syongari 1200177050Syongari desc = rxd->desc; 1201177050Syongari desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1202177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 1203177050Syongari} 1204177050Syongari 120541502Swpaul/* 120641502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 120741502Swpaul * Note: the length fields are only 11 bits wide, which means the 120841502Swpaul * largest size we can specify is 2047. This is important because 120941502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 121041502Swpaul * overflow the field and make a mess. 121141502Swpaul */ 1212102336Salfredstatic int 1213177050Syongarivr_newbuf(struct vr_softc *sc, int idx) 121441502Swpaul{ 1215177050Syongari struct vr_desc *desc; 1216177050Syongari struct vr_rxdesc *rxd; 1217177050Syongari struct mbuf *m; 1218177050Syongari bus_dma_segment_t segs[1]; 1219177050Syongari bus_dmamap_t map; 1220177050Syongari int nsegs; 122141502Swpaul 1222177050Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1223177050Syongari if (m == NULL) 1224177050Syongari return (ENOBUFS); 1225177050Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 1226177050Syongari m_adj(m, sizeof(uint64_t)); 1227177050Syongari 1228177050Syongari if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1229177050Syongari sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1230177050Syongari m_freem(m); 1231177050Syongari return (ENOBUFS); 123241502Swpaul } 1233177050Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 123441502Swpaul 1235177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1236177050Syongari if (rxd->rx_m != NULL) { 1237177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1238177050Syongari BUS_DMASYNC_POSTREAD); 1239177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1240177050Syongari } 1241177050Syongari map = rxd->rx_dmamap; 1242177050Syongari rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1243177050Syongari sc->vr_cdata.vr_rx_sparemap = map; 1244177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1245177050Syongari BUS_DMASYNC_PREREAD); 1246177050Syongari rxd->rx_m = m; 1247177050Syongari desc = rxd->desc; 1248177050Syongari desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1249177050Syongari desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1250177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 125149610Swpaul 1252131503Sbms return (0); 125341502Swpaul} 125441502Swpaul 1255177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1256177050Syongaristatic __inline void 1257177050Syongarivr_fixup_rx(struct mbuf *m) 1258177050Syongari{ 1259177050Syongari uint16_t *src, *dst; 1260177050Syongari int i; 1261177050Syongari 1262177050Syongari src = mtod(m, uint16_t *); 1263177050Syongari dst = src - 1; 1264177050Syongari 1265177050Syongari for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1266177050Syongari *dst++ = *src++; 1267177050Syongari 1268177050Syongari m->m_data -= ETHER_ALIGN; 1269177050Syongari} 1270177050Syongari#endif 1271177050Syongari 127241502Swpaul/* 127341502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 127441502Swpaul * the higher level protocols. 127541502Swpaul */ 1276193096Sattiliostatic int 1277131503Sbmsvr_rxeof(struct vr_softc *sc) 127841502Swpaul{ 1279177050Syongari struct vr_rxdesc *rxd; 1280177050Syongari struct mbuf *m; 1281131503Sbms struct ifnet *ifp; 1282168952Sphk struct vr_desc *cur_rx; 1283193096Sattilio int cons, prog, total_len, rx_npkts; 1284168827Sphk uint32_t rxstat, rxctl; 128541502Swpaul 1286122689Ssam VR_LOCK_ASSERT(sc); 1287147256Sbrooks ifp = sc->vr_ifp; 1288177050Syongari cons = sc->vr_cdata.vr_rx_cons; 1289193096Sattilio rx_npkts = 0; 129041502Swpaul 1291177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1292177050Syongari sc->vr_cdata.vr_rx_ring_map, 1293177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1294177050Syongari 1295177050Syongari for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1296127901Sru#ifdef DEVICE_POLLING 1297150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1298127901Sru if (sc->rxcycles <= 0) 1299127901Sru break; 1300127901Sru sc->rxcycles--; 1301127901Sru } 1302150789Sglebius#endif 1303177050Syongari cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1304177050Syongari rxstat = le32toh(cur_rx->vr_status); 1305177050Syongari rxctl = le32toh(cur_rx->vr_ctl); 1306177050Syongari if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1307177050Syongari break; 130841502Swpaul 1309177050Syongari prog++; 1310177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1311177050Syongari m = rxd->rx_m; 1312177050Syongari 131341502Swpaul /* 131441502Swpaul * If an error occurs, update stats, clear the 131541502Swpaul * status word and leave the mbuf cluster in place: 131641502Swpaul * it should simply get re-used next time this descriptor 1317131503Sbms * comes up in the ring. 1318177050Syongari * We don't support SG in Rx path yet, so discard 1319177050Syongari * partial frame. 132041502Swpaul */ 1321180551Syongari if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1322180551Syongari (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1323177050Syongari (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 132441502Swpaul ifp->if_ierrors++; 1325177050Syongari sc->vr_stat.rx_errors++; 1326110131Ssilby if (rxstat & VR_RXSTAT_CRCERR) 1327177050Syongari sc->vr_stat.rx_crc_errors++; 1328110131Ssilby if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1329177050Syongari sc->vr_stat.rx_alignment++; 1330110131Ssilby if (rxstat & VR_RXSTAT_FIFOOFLOW) 1331177050Syongari sc->vr_stat.rx_fifo_overflows++; 1332110131Ssilby if (rxstat & VR_RXSTAT_GIANT) 1333177050Syongari sc->vr_stat.rx_giants++; 1334110131Ssilby if (rxstat & VR_RXSTAT_RUNT) 1335177050Syongari sc->vr_stat.rx_runts++; 1336110131Ssilby if (rxstat & VR_RXSTAT_BUFFERR) 1337177050Syongari sc->vr_stat.rx_no_buffers++; 1338177050Syongari#ifdef VR_SHOW_ERRORS 1339177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1340177050Syongari __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1341177050Syongari#endif 1342177050Syongari vr_discard_rxbuf(rxd); 134341502Swpaul continue; 134441502Swpaul } 134541502Swpaul 1346177050Syongari if (vr_newbuf(sc, cons) != 0) { 1347177050Syongari ifp->if_iqdrops++; 1348177050Syongari sc->vr_stat.rx_errors++; 1349177050Syongari sc->vr_stat.rx_no_mbufs++; 1350177050Syongari vr_discard_rxbuf(rxd); 1351177050Syongari continue; 1352168827Sphk } 135341502Swpaul 135441502Swpaul /* 135542048Swpaul * XXX The VIA Rhine chip includes the CRC with every 135642048Swpaul * received frame, and there's no way to turn this 135742048Swpaul * behavior off (at least, I can't find anything in 1358131503Sbms * the manual that explains how to do it) so we have 135942048Swpaul * to trim off the CRC manually. 136042048Swpaul */ 1361177050Syongari total_len = VR_RXBYTES(rxstat); 136242048Swpaul total_len -= ETHER_CRC_LEN; 1363177050Syongari m->m_pkthdr.len = m->m_len = total_len; 1364177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1365177050Syongari /* 1366177050Syongari * RX buffers must be 32-bit aligned. 1367177050Syongari * Ignore the alignment problems on the non-strict alignment 1368177050Syongari * platform. The performance hit incurred due to unaligned 1369177050Syongari * accesses is much smaller than the hit produced by forcing 1370177050Syongari * buffer copies all the time. 1371177050Syongari */ 1372177050Syongari vr_fixup_rx(m); 1373177050Syongari#endif 1374177050Syongari m->m_pkthdr.rcvif = ifp; 1375177050Syongari ifp->if_ipackets++; 1376177050Syongari sc->vr_stat.rx_ok++; 1377177050Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1378177050Syongari (rxstat & VR_RXSTAT_FRAG) == 0 && 1379177050Syongari (rxctl & VR_RXCTL_IP) != 0) { 1380177050Syongari /* Checksum is valid for non-fragmented IP packets. */ 1381177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1382177050Syongari if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1383177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1384177050Syongari if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1385177050Syongari m->m_pkthdr.csum_flags |= 1386177050Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1387177050Syongari if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1388177050Syongari m->m_pkthdr.csum_data = 0xffff; 1389177050Syongari } 1390177050Syongari } 139141502Swpaul } 1392122689Ssam VR_UNLOCK(sc); 1393106936Ssam (*ifp->if_input)(ifp, m); 1394122689Ssam VR_LOCK(sc); 1395193096Sattilio rx_npkts++; 139641502Swpaul } 139741502Swpaul 1398177050Syongari if (prog > 0) { 1399177050Syongari sc->vr_cdata.vr_rx_cons = cons; 1400177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1401177050Syongari sc->vr_cdata.vr_rx_ring_map, 1402177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1403131503Sbms } 1404193096Sattilio return (rx_npkts); 140541502Swpaul} 140641502Swpaul 140741502Swpaul/* 140841502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 140941502Swpaul * the list buffers. 141041502Swpaul */ 1411102336Salfredstatic void 1412131503Sbmsvr_txeof(struct vr_softc *sc) 141341502Swpaul{ 1414177050Syongari struct vr_txdesc *txd; 1415168952Sphk struct vr_desc *cur_tx; 1416177050Syongari struct ifnet *ifp; 1417177050Syongari uint32_t txctl, txstat; 1418177050Syongari int cons, prod; 141941502Swpaul 1420131518Sbms VR_LOCK_ASSERT(sc); 142141502Swpaul 1422177050Syongari cons = sc->vr_cdata.vr_tx_cons; 1423177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1424177050Syongari if (cons == prod) 1425177050Syongari return; 1426177050Syongari 1427177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1428177050Syongari sc->vr_cdata.vr_tx_ring_map, 1429177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1430177050Syongari 1431177050Syongari ifp = sc->vr_ifp; 143241502Swpaul /* 143341502Swpaul * Go through our tx list and free mbufs for those 143441502Swpaul * frames that have been transmitted. 143541502Swpaul */ 1436177050Syongari for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1437177050Syongari cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1438177050Syongari txctl = le32toh(cur_tx->vr_ctl); 1439177050Syongari txstat = le32toh(cur_tx->vr_status); 1440177050Syongari if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1441177050Syongari break; 144241502Swpaul 1443177050Syongari sc->vr_cdata.vr_tx_cnt--; 1444177050Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1445177050Syongari /* Only the first descriptor in the chain is valid. */ 1446177050Syongari if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1447177050Syongari continue; 144841502Swpaul 1449177050Syongari txd = &sc->vr_cdata.vr_txdesc[cons]; 1450177050Syongari KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1451177050Syongari __func__)); 1452177050Syongari 1453177050Syongari if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1454177050Syongari ifp->if_oerrors++; 1455177050Syongari sc->vr_stat.tx_errors++; 1456177050Syongari if ((txstat & VR_TXSTAT_ABRT) != 0) { 1457177050Syongari /* Give up and restart Tx. */ 1458177050Syongari sc->vr_stat.tx_abort++; 1459177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1460177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1461177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1462177050Syongari txd->tx_dmamap); 1463177050Syongari m_freem(txd->tx_m); 1464177050Syongari txd->tx_m = NULL; 1465177050Syongari VR_INC(cons, VR_TX_RING_CNT); 1466177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1467177050Syongari if (vr_tx_stop(sc) != 0) { 1468177050Syongari device_printf(sc->vr_dev, 1469177050Syongari "%s: Tx shutdown error -- " 1470177050Syongari "resetting\n", __func__); 1471177050Syongari sc->vr_flags |= VR_F_RESTART; 1472177050Syongari return; 1473177050Syongari } 1474177050Syongari vr_tx_start(sc); 1475110131Ssilby break; 1476110131Ssilby } 1477177050Syongari if ((sc->vr_revid < REV_ID_VT3071_A && 1478177050Syongari (txstat & VR_TXSTAT_UNDERRUN)) || 1479177050Syongari (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1480177050Syongari sc->vr_stat.tx_underrun++; 1481177050Syongari /* Retry and restart Tx. */ 1482177050Syongari sc->vr_cdata.vr_tx_cnt++; 1483177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1484177050Syongari cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1485177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1486177050Syongari sc->vr_cdata.vr_tx_ring_map, 1487177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1488177050Syongari vr_tx_underrun(sc); 1489177050Syongari return; 1490177050Syongari } 1491177050Syongari if ((txstat & VR_TXSTAT_DEFER) != 0) { 149241502Swpaul ifp->if_collisions++; 1493177050Syongari sc->vr_stat.tx_collisions++; 1494177050Syongari } 1495177050Syongari if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 149641502Swpaul ifp->if_collisions++; 1497177050Syongari sc->vr_stat.tx_late_collisions++; 1498177050Syongari } 1499177050Syongari } else { 1500177050Syongari sc->vr_stat.tx_ok++; 1501177050Syongari ifp->if_opackets++; 150241502Swpaul } 150341502Swpaul 1504177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1505177050Syongari BUS_DMASYNC_POSTWRITE); 1506177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1507177050Syongari if (sc->vr_revid < REV_ID_VT3071_A) { 1508177050Syongari ifp->if_collisions += 1509177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1510177050Syongari sc->vr_stat.tx_collisions += 1511177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1512177050Syongari } else { 1513177050Syongari ifp->if_collisions += (txstat & 0x0f); 1514177050Syongari sc->vr_stat.tx_collisions += (txstat & 0x0f); 1515177050Syongari } 1516177050Syongari m_freem(txd->tx_m); 1517177050Syongari txd->tx_m = NULL; 1518177050Syongari } 151941502Swpaul 1520177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1521177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 1522177050Syongari sc->vr_watchdog_timer = 0; 152341502Swpaul} 152441502Swpaul 1525102336Salfredstatic void 1526131503Sbmsvr_tick(void *xsc) 152751432Swpaul{ 1528177050Syongari struct vr_softc *sc; 152951432Swpaul struct mii_data *mii; 153051432Swpaul 1531177050Syongari sc = (struct vr_softc *)xsc; 1532177050Syongari 1533151911Sjhb VR_LOCK_ASSERT(sc); 1534131517Sbms 1535177050Syongari if ((sc->vr_flags & VR_F_RESTART) != 0) { 1536162315Sglebius device_printf(sc->vr_dev, "restarting\n"); 1537177050Syongari sc->vr_stat.num_restart++; 1538211765Syongari sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1539131844Sbms vr_init_locked(sc); 1540110131Ssilby sc->vr_flags &= ~VR_F_RESTART; 1541110131Ssilby } 1542110131Ssilby 154351432Swpaul mii = device_get_softc(sc->vr_miibus); 154451432Swpaul mii_tick(mii); 1545223405Syongari if (sc->vr_link == 0) 1546223405Syongari vr_miibus_statchg(sc->vr_dev); 1547177050Syongari vr_watchdog(sc); 1548151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 154951432Swpaul} 155051432Swpaul 1551127901Sru#ifdef DEVICE_POLLING 1552127901Srustatic poll_handler_t vr_poll; 1553131844Sbmsstatic poll_handler_t vr_poll_locked; 1554127901Sru 1555193096Sattiliostatic int 1556127901Sruvr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1557127901Sru{ 1558177050Syongari struct vr_softc *sc; 1559193096Sattilio int rx_npkts; 1560127901Sru 1561177050Syongari sc = ifp->if_softc; 1562193096Sattilio rx_npkts = 0; 1563177050Syongari 1564127901Sru VR_LOCK(sc); 1565177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1566193096Sattilio rx_npkts = vr_poll_locked(ifp, cmd, count); 1567131844Sbms VR_UNLOCK(sc); 1568193096Sattilio return (rx_npkts); 1569131844Sbms} 1570131517Sbms 1571193096Sattiliostatic int 1572131844Sbmsvr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1573131844Sbms{ 1574177050Syongari struct vr_softc *sc; 1575193096Sattilio int rx_npkts; 1576131844Sbms 1577177050Syongari sc = ifp->if_softc; 1578177050Syongari 1579131844Sbms VR_LOCK_ASSERT(sc); 1580131844Sbms 1581127901Sru sc->rxcycles = count; 1582193096Sattilio rx_npkts = vr_rxeof(sc); 1583127901Sru vr_txeof(sc); 1584133006Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1585131844Sbms vr_start_locked(ifp); 1586127901Sru 1587131503Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1588131503Sbms uint16_t status; 1589127901Sru 1590131503Sbms /* Also check status register. */ 1591127901Sru status = CSR_READ_2(sc, VR_ISR); 1592127901Sru if (status) 1593127901Sru CSR_WRITE_2(sc, VR_ISR, status); 1594127901Sru 1595127901Sru if ((status & VR_INTRS) == 0) 1596193096Sattilio return (rx_npkts); 1597127901Sru 1598177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1599177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1600177050Syongari if (vr_error(sc, status) != 0) 1601193096Sattilio return (rx_npkts); 1602127901Sru } 1603177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1604177050Syongari#ifdef VR_SHOW_ERRORS 1605177050Syongari device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1606177050Syongari __func__, status, VR_ISR_ERR_BITS); 1607177050Syongari#endif 1608177050Syongari vr_rx_start(sc); 1609127901Sru } 1610177050Syongari } 1611193096Sattilio return (rx_npkts); 1612177050Syongari} 1613177050Syongari#endif /* DEVICE_POLLING */ 1614127901Sru 1615177050Syongari/* Back off the transmit threshold. */ 1616177050Syongaristatic void 1617177050Syongarivr_tx_underrun(struct vr_softc *sc) 1618177050Syongari{ 1619177050Syongari int thresh; 1620127901Sru 1621177050Syongari device_printf(sc->vr_dev, "Tx underrun -- "); 1622177050Syongari if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1623177050Syongari thresh = sc->vr_txthresh; 1624177050Syongari sc->vr_txthresh++; 1625177050Syongari if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1626177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 1627177050Syongari printf("using store and forward mode\n"); 1628177050Syongari } else 1629177050Syongari printf("increasing Tx threshold(%d -> %d)\n", 1630177050Syongari vr_tx_threshold_tables[thresh].value, 1631177050Syongari vr_tx_threshold_tables[thresh + 1].value); 1632177050Syongari } else 1633177050Syongari printf("\n"); 1634177050Syongari sc->vr_stat.tx_underrun++; 1635177050Syongari if (vr_tx_stop(sc) != 0) { 1636177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1637177050Syongari "resetting\n", __func__); 1638177050Syongari sc->vr_flags |= VR_F_RESTART; 1639177050Syongari return; 1640127901Sru } 1641177050Syongari vr_tx_start(sc); 1642127901Sru} 1643127901Sru 1644127901Srustatic void 1645131503Sbmsvr_intr(void *arg) 164641502Swpaul{ 1647177050Syongari struct vr_softc *sc; 1648177050Syongari struct ifnet *ifp; 1649131503Sbms uint16_t status; 165041502Swpaul 1651177050Syongari sc = (struct vr_softc *)arg; 1652177050Syongari 165367087Swpaul VR_LOCK(sc); 1654131844Sbms 1655177050Syongari if (sc->vr_suspended != 0) 1656131844Sbms goto done_locked; 1657131844Sbms 1658177050Syongari status = CSR_READ_2(sc, VR_ISR); 1659177050Syongari if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1660177050Syongari goto done_locked; 1661177050Syongari 1662177050Syongari ifp = sc->vr_ifp; 1663127901Sru#ifdef DEVICE_POLLING 1664177050Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1665131844Sbms goto done_locked; 1666150789Sglebius#endif 1667131844Sbms 1668131844Sbms /* Suppress unwanted interrupts. */ 1669177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1670177050Syongari (sc->vr_flags & VR_F_RESTART) != 0) { 1671177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1672177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1673131844Sbms goto done_locked; 167441502Swpaul } 167541502Swpaul 167641502Swpaul /* Disable interrupts. */ 167741502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 167841502Swpaul 1679177050Syongari for (; (status & VR_INTRS) != 0;) { 1680177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1681177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1682177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1683177050Syongari if (vr_error(sc, status) != 0) { 1684177050Syongari VR_UNLOCK(sc); 1685177050Syongari return; 1686177050Syongari } 1687177050Syongari } 1688177050Syongari vr_rxeof(sc); 1689177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1690177050Syongari#ifdef VR_SHOW_ERRORS 1691177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1692177050Syongari __func__, status, VR_ISR_ERR_BITS); 1693177050Syongari#endif 1694177050Syongari /* Restart Rx if RxDMA SM was stopped. */ 1695177050Syongari vr_rx_start(sc); 1696177050Syongari } 1697177050Syongari vr_txeof(sc); 169841502Swpaul status = CSR_READ_2(sc, VR_ISR); 1699177050Syongari } 1700168813Sphk 1701177050Syongari /* Re-enable interrupts. */ 1702177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 170341502Swpaul 1704177050Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1705177050Syongari vr_start_locked(ifp); 170641502Swpaul 1707177050Syongaridone_locked: 1708177050Syongari VR_UNLOCK(sc); 1709177050Syongari} 171041502Swpaul 1711177050Syongaristatic int 1712177050Syongarivr_error(struct vr_softc *sc, uint16_t status) 1713177050Syongari{ 1714177050Syongari uint16_t pcis; 1715110131Ssilby 1716177050Syongari status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1717177050Syongari if ((status & VR_ISR_BUSERR) != 0) { 1718177050Syongari status &= ~VR_ISR_BUSERR; 1719177050Syongari sc->vr_stat.bus_errors++; 1720177050Syongari /* Disable further interrupts. */ 1721177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1722177050Syongari pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1723177050Syongari device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1724177050Syongari "resetting\n", pcis); 1725177050Syongari pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1726177050Syongari sc->vr_flags |= VR_F_RESTART; 1727177050Syongari return (EAGAIN); 1728177050Syongari } 1729177050Syongari if ((status & VR_ISR_LINKSTAT2) != 0) { 1730177050Syongari /* Link state change, duplex changes etc. */ 1731177050Syongari status &= ~VR_ISR_LINKSTAT2; 1732177050Syongari } 1733177050Syongari if ((status & VR_ISR_STATSOFLOW) != 0) { 1734177050Syongari status &= ~VR_ISR_STATSOFLOW; 1735177050Syongari if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1736177050Syongari /* Update MIB counters. */ 173741502Swpaul } 1738177050Syongari } 173941502Swpaul 1740177050Syongari if (status != 0) 1741177050Syongari device_printf(sc->vr_dev, 1742177050Syongari "unhandled interrupt, status = 0x%04x\n", status); 1743177050Syongari return (0); 1744177050Syongari} 1745177050Syongari 1746177050Syongari/* 1747177050Syongari * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1748177050Syongari * pointers to the fragment pointers. 1749177050Syongari */ 1750177050Syongaristatic int 1751177050Syongarivr_encap(struct vr_softc *sc, struct mbuf **m_head) 1752177050Syongari{ 1753177050Syongari struct vr_txdesc *txd; 1754177050Syongari struct vr_desc *desc; 1755177050Syongari struct mbuf *m; 1756177050Syongari bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1757177050Syongari uint32_t csum_flags, txctl; 1758177050Syongari int error, i, nsegs, prod, si; 1759177050Syongari int padlen; 1760177050Syongari 1761177050Syongari VR_LOCK_ASSERT(sc); 1762177050Syongari 1763177050Syongari M_ASSERTPKTHDR((*m_head)); 1764177050Syongari 1765177050Syongari /* 1766177050Syongari * Some VIA Rhine wants packet buffers to be longword 1767177050Syongari * aligned, but very often our mbufs aren't. Rather than 1768177050Syongari * waste time trying to decide when to copy and when not 1769177050Syongari * to copy, just do it all the time. 1770177050Syongari */ 1771177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1772177050Syongari m = m_defrag(*m_head, M_DONTWAIT); 1773177050Syongari if (m == NULL) { 1774177050Syongari m_freem(*m_head); 1775177050Syongari *m_head = NULL; 1776177050Syongari return (ENOBUFS); 177741502Swpaul } 1778177050Syongari *m_head = m; 1779177050Syongari } 178041502Swpaul 1781177050Syongari /* 1782177050Syongari * The Rhine chip doesn't auto-pad, so we have to make 1783177050Syongari * sure to pad short frames out to the minimum frame length 1784177050Syongari * ourselves. 1785177050Syongari */ 1786177050Syongari if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1787177050Syongari m = *m_head; 1788177050Syongari padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1789177050Syongari if (M_WRITABLE(m) == 0) { 1790177050Syongari /* Get a writable copy. */ 1791177050Syongari m = m_dup(*m_head, M_DONTWAIT); 1792177050Syongari m_freem(*m_head); 1793177050Syongari if (m == NULL) { 1794177050Syongari *m_head = NULL; 1795177050Syongari return (ENOBUFS); 1796127901Sru } 1797177050Syongari *m_head = m; 179841502Swpaul } 1799177050Syongari if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1800177050Syongari m = m_defrag(m, M_DONTWAIT); 1801177050Syongari if (m == NULL) { 1802177050Syongari m_freem(*m_head); 1803177050Syongari *m_head = NULL; 1804177050Syongari return (ENOBUFS); 1805177050Syongari } 1806177050Syongari } 1807177050Syongari /* 1808177050Syongari * Manually pad short frames, and zero the pad space 1809177050Syongari * to avoid leaking data. 1810177050Syongari */ 1811177050Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1812177050Syongari m->m_pkthdr.len += padlen; 1813177050Syongari m->m_len = m->m_pkthdr.len; 1814177050Syongari *m_head = m; 181541502Swpaul } 181641502Swpaul 1817177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1818177050Syongari txd = &sc->vr_cdata.vr_txdesc[prod]; 1819177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1820177050Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1821177050Syongari if (error == EFBIG) { 1822177050Syongari m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1823177050Syongari if (m == NULL) { 1824177050Syongari m_freem(*m_head); 1825177050Syongari *m_head = NULL; 1826177050Syongari return (ENOBUFS); 1827177050Syongari } 1828177050Syongari *m_head = m; 1829177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1830177050Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1831177050Syongari if (error != 0) { 1832177050Syongari m_freem(*m_head); 1833177050Syongari *m_head = NULL; 1834177050Syongari return (error); 1835177050Syongari } 1836177050Syongari } else if (error != 0) 1837177050Syongari return (error); 1838177050Syongari if (nsegs == 0) { 1839177050Syongari m_freem(*m_head); 1840177050Syongari *m_head = NULL; 1841177050Syongari return (EIO); 1842177050Syongari } 184341502Swpaul 1844177050Syongari /* Check number of available descriptors. */ 1845177050Syongari if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1846177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1847177050Syongari return (ENOBUFS); 1848177050Syongari } 1849131844Sbms 1850177050Syongari txd->tx_m = *m_head; 1851177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1852177050Syongari BUS_DMASYNC_PREWRITE); 1853177050Syongari 1854177050Syongari /* Set checksum offload. */ 1855177050Syongari csum_flags = 0; 1856177050Syongari if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1857177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1858177050Syongari csum_flags |= VR_TXCTL_IPCSUM; 1859177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1860177050Syongari csum_flags |= VR_TXCTL_TCPCSUM; 1861177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1862177050Syongari csum_flags |= VR_TXCTL_UDPCSUM; 1863177050Syongari } 1864177050Syongari 1865177050Syongari /* 1866177050Syongari * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1867177050Syongari * is required for all descriptors regardless of single or 1868177050Syongari * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1869177050Syongari * the first descriptor for a multi-fragmented frames. Without 1870177050Syongari * that VIA Rhine chip generates Tx underrun interrupts and can't 1871177050Syongari * send any frames. 1872177050Syongari */ 1873177050Syongari si = prod; 1874177050Syongari for (i = 0; i < nsegs; i++) { 1875177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1876177050Syongari desc->vr_status = 0; 1877177050Syongari txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1878177050Syongari if (i == 0) 1879177050Syongari txctl |= VR_TXCTL_FIRSTFRAG; 1880177050Syongari desc->vr_ctl = htole32(txctl); 1881177050Syongari desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1882177050Syongari sc->vr_cdata.vr_tx_cnt++; 1883177050Syongari VR_INC(prod, VR_TX_RING_CNT); 1884177050Syongari } 1885177050Syongari /* Update producer index. */ 1886177050Syongari sc->vr_cdata.vr_tx_prod = prod; 1887177050Syongari 1888177050Syongari prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1889177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1890177050Syongari 1891177050Syongari /* 1892177050Syongari * Set EOP on the last desciptor and reuqest Tx completion 1893177050Syongari * interrupt for every VR_TX_INTR_THRESH-th frames. 1894177050Syongari */ 1895177050Syongari VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1896177050Syongari if (sc->vr_cdata.vr_tx_pkts == 0) 1897177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1898177050Syongari else 1899177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1900177050Syongari 1901177050Syongari /* Lastly turn the first descriptor ownership to hardware. */ 1902177050Syongari desc = &sc->vr_rdata.vr_tx_ring[si]; 1903177050Syongari desc->vr_status |= htole32(VR_TXSTAT_OWN); 1904177050Syongari 1905177050Syongari /* Sync descriptors. */ 1906177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1907177050Syongari sc->vr_cdata.vr_tx_ring_map, 1908177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1909177050Syongari 1910177050Syongari return (0); 191141502Swpaul} 191241502Swpaul 1913102336Salfredstatic void 1914131503Sbmsvr_start(struct ifnet *ifp) 191541502Swpaul{ 1916177050Syongari struct vr_softc *sc; 1917131844Sbms 1918177050Syongari sc = ifp->if_softc; 1919131844Sbms VR_LOCK(sc); 1920131844Sbms vr_start_locked(ifp); 1921131844Sbms VR_UNLOCK(sc); 1922131844Sbms} 1923131844Sbms 1924131844Sbmsstatic void 1925131844Sbmsvr_start_locked(struct ifnet *ifp) 1926131844Sbms{ 1927177050Syongari struct vr_softc *sc; 1928177050Syongari struct mbuf *m_head; 1929177050Syongari int enq; 193041502Swpaul 1931177050Syongari sc = ifp->if_softc; 1932177050Syongari 1933177050Syongari VR_LOCK_ASSERT(sc); 1934177050Syongari 1935177050Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1936177050Syongari IFF_DRV_RUNNING || sc->vr_link == 0) 1937127901Sru return; 1938127901Sru 1939177050Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1940177050Syongari sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1941177050Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 194241502Swpaul if (m_head == NULL) 194341502Swpaul break; 1944168813Sphk /* 1945177050Syongari * Pack the data into the transmit ring. If we 1946177050Syongari * don't have room, set the OACTIVE flag and wait 1947177050Syongari * for the NIC to drain the ring. 1948168813Sphk */ 1949177050Syongari if (vr_encap(sc, &m_head)) { 1950177050Syongari if (m_head == NULL) 1951168813Sphk break; 1952177050Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1953177050Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1954177050Syongari break; 1955168813Sphk } 195651583Swpaul 1957177050Syongari enq++; 1958168813Sphk /* 1959168813Sphk * If there's a BPF listener, bounce a copy of this frame 1960168813Sphk * to him. 1961168813Sphk */ 1962177050Syongari ETHER_BPF_MTAP(ifp, m_head); 1963127901Sru } 1964177050Syongari 1965177050Syongari if (enq > 0) { 1966177050Syongari /* Tell the chip to start transmitting. */ 1967177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1968177050Syongari /* Set a timeout in case the chip goes out to lunch. */ 1969177050Syongari sc->vr_watchdog_timer = 5; 1970177050Syongari } 1971131844Sbms} 197241502Swpaul 1973131844Sbmsstatic void 1974131844Sbmsvr_init(void *xsc) 1975131844Sbms{ 1976177050Syongari struct vr_softc *sc; 1977131844Sbms 1978177050Syongari sc = (struct vr_softc *)xsc; 1979131844Sbms VR_LOCK(sc); 1980131844Sbms vr_init_locked(sc); 198167087Swpaul VR_UNLOCK(sc); 198241502Swpaul} 198341502Swpaul 1984102336Salfredstatic void 1985131844Sbmsvr_init_locked(struct vr_softc *sc) 198641502Swpaul{ 1987177050Syongari struct ifnet *ifp; 198851432Swpaul struct mii_data *mii; 1989177050Syongari bus_addr_t addr; 199073963Swpaul int i; 199141502Swpaul 1992131844Sbms VR_LOCK_ASSERT(sc); 199341502Swpaul 1994177050Syongari ifp = sc->vr_ifp; 199551432Swpaul mii = device_get_softc(sc->vr_miibus); 199641502Swpaul 1997211765Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1998211765Syongari return; 1999211765Syongari 2000131503Sbms /* Cancel pending I/O and free all RX/TX buffers. */ 200141502Swpaul vr_stop(sc); 200241502Swpaul vr_reset(sc); 200341502Swpaul 2004131503Sbms /* Set our station address. */ 200573963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 2006152315Sru CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2007131503Sbms 2008131503Sbms /* Set DMA size. */ 2009101375Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2010101375Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 201173963Swpaul 2012131503Sbms /* 2013101375Ssilby * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2014101108Ssilby * so we must set both. 2015101108Ssilby */ 2016101108Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2017110131Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2018101108Ssilby 2019101108Ssilby VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2020177050Syongari VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2021101108Ssilby 202241502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2023110131Ssilby VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 202441502Swpaul 202541502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2026177050Syongari VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 202741502Swpaul 202841502Swpaul /* Init circular RX list. */ 2029177050Syongari if (vr_rx_ring_init(sc) != 0) { 2030162315Sglebius device_printf(sc->vr_dev, 2031151773Sjhb "initialization failed: no memory for rx buffers\n"); 203241502Swpaul vr_stop(sc); 203341502Swpaul return; 203441502Swpaul } 203541502Swpaul 2036131503Sbms /* Init tx descriptors. */ 2037177050Syongari vr_tx_ring_init(sc); 203841502Swpaul 2039177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2040180552Syongari uint8_t vcam[2] = { 0, 0 }; 2041180552Syongari 2042180552Syongari /* Disable VLAN hardware tag insertion/stripping. */ 2043180552Syongari VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2044180552Syongari /* Disable VLAN hardware filtering. */ 2045180552Syongari VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2046180552Syongari /* Disable all CAM entries. */ 2047180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, 0); 2048180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 0); 2049180552Syongari /* Enable the first VLAN CAM. */ 2050180552Syongari vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2051180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 1); 2052177050Syongari } 205341502Swpaul 205441502Swpaul /* 2055177050Syongari * Set up receive filter. 205641502Swpaul */ 2057177050Syongari vr_set_filter(sc); 205841502Swpaul 205941502Swpaul /* 2060177050Syongari * Load the address of the RX ring. 206141502Swpaul */ 2062177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 2063177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2064177050Syongari /* 2065177050Syongari * Load the address of the TX ring. 2066177050Syongari */ 2067177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 2068177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2069177050Syongari /* Default : full-duplex, no Tx poll. */ 2070177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 207141502Swpaul 2072177050Syongari /* Set flow-control parameters for Rhine III. */ 2073177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 2074177050Syongari /* Rx buffer count available for incoming packet. */ 2075177050Syongari CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT); 2076177050Syongari /* 2077177050Syongari * Tx pause low threshold : 16 free receive buffers 2078177050Syongari * Tx pause XON high threshold : 48 free receive buffers 2079177050Syongari */ 2080177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, 2081177050Syongari VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF); 2082177050Syongari /* Set Tx pause timer. */ 2083177050Syongari CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2084177050Syongari } 2085177050Syongari 208641502Swpaul /* Enable receiver and transmitter. */ 2087177050Syongari CSR_WRITE_1(sc, VR_CR0, 2088177050Syongari VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 208941502Swpaul 2090127901Sru CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2091127901Sru#ifdef DEVICE_POLLING 209241502Swpaul /* 2093127901Sru * Disable interrupts if we are polling. 2094127901Sru */ 2095150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 2096127901Sru CSR_WRITE_2(sc, VR_IMR, 0); 2097131503Sbms else 2098150789Sglebius#endif 2099127901Sru /* 2100177050Syongari * Enable interrupts and disable MII intrs. 210141502Swpaul */ 210241502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2103177050Syongari if (sc->vr_revid > REV_ID_VT6102_A) 2104177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 210541502Swpaul 2106177050Syongari sc->vr_link = 0; 210751432Swpaul mii_mediachg(mii); 210841502Swpaul 2109148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2110148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 211141502Swpaul 2112151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 211341502Swpaul} 211441502Swpaul 211541502Swpaul/* 211641502Swpaul * Set media options. 211741502Swpaul */ 2118102336Salfredstatic int 2119131503Sbmsvr_ifmedia_upd(struct ifnet *ifp) 212041502Swpaul{ 2121177050Syongari struct vr_softc *sc; 2122177050Syongari struct mii_data *mii; 2123177050Syongari struct mii_softc *miisc; 2124177050Syongari int error; 212541502Swpaul 2126177050Syongari sc = ifp->if_softc; 2127177050Syongari VR_LOCK(sc); 2128177050Syongari mii = device_get_softc(sc->vr_miibus); 2129221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2130221407Smarius PHY_RESET(miisc); 2131177050Syongari error = mii_mediachg(mii); 2132177050Syongari VR_UNLOCK(sc); 213341502Swpaul 2134177050Syongari return (error); 213541502Swpaul} 213641502Swpaul 213741502Swpaul/* 213841502Swpaul * Report current media status. 213941502Swpaul */ 2140102336Salfredstatic void 2141131503Sbmsvr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 214241502Swpaul{ 2143177050Syongari struct vr_softc *sc; 214451432Swpaul struct mii_data *mii; 214541502Swpaul 2146177050Syongari sc = ifp->if_softc; 214751432Swpaul mii = device_get_softc(sc->vr_miibus); 2148133468Sscottl VR_LOCK(sc); 2149223405Syongari if ((ifp->if_flags & IFF_UP) == 0) { 2150223405Syongari VR_UNLOCK(sc); 2151223405Syongari return; 2152223405Syongari } 215351432Swpaul mii_pollstat(mii); 215451432Swpaul ifmr->ifm_active = mii->mii_media_active; 215551432Swpaul ifmr->ifm_status = mii->mii_media_status; 2156226478Syongari VR_UNLOCK(sc); 215741502Swpaul} 215841502Swpaul 2159102336Salfredstatic int 2160131503Sbmsvr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 216141502Swpaul{ 2162177050Syongari struct vr_softc *sc; 2163177050Syongari struct ifreq *ifr; 216451432Swpaul struct mii_data *mii; 2165177050Syongari int error, mask; 216641502Swpaul 2167177050Syongari sc = ifp->if_softc; 2168177050Syongari ifr = (struct ifreq *)data; 2169177050Syongari error = 0; 2170177050Syongari 2171131503Sbms switch (command) { 217241502Swpaul case SIOCSIFFLAGS: 2173131844Sbms VR_LOCK(sc); 217441502Swpaul if (ifp->if_flags & IFF_UP) { 2175177050Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2176177050Syongari if ((ifp->if_flags ^ sc->vr_if_flags) & 2177177050Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2178177050Syongari vr_set_filter(sc); 2179177050Syongari } else { 2180177050Syongari if (sc->vr_detach == 0) 2181177050Syongari vr_init_locked(sc); 2182177050Syongari } 218341502Swpaul } else { 2184148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 218541502Swpaul vr_stop(sc); 218641502Swpaul } 2187177050Syongari sc->vr_if_flags = ifp->if_flags; 2188131844Sbms VR_UNLOCK(sc); 218941502Swpaul break; 219041502Swpaul case SIOCADDMULTI: 219141502Swpaul case SIOCDELMULTI: 2192131518Sbms VR_LOCK(sc); 2193177050Syongari vr_set_filter(sc); 2194131518Sbms VR_UNLOCK(sc); 219541502Swpaul break; 219641502Swpaul case SIOCGIFMEDIA: 219741502Swpaul case SIOCSIFMEDIA: 219851432Swpaul mii = device_get_softc(sc->vr_miibus); 219951432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 220041502Swpaul break; 2201128118Sru case SIOCSIFCAP: 2202177050Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2203150789Sglebius#ifdef DEVICE_POLLING 2204177050Syongari if (mask & IFCAP_POLLING) { 2205177050Syongari if (ifr->ifr_reqcap & IFCAP_POLLING) { 2206177050Syongari error = ether_poll_register(vr_poll, ifp); 2207177050Syongari if (error != 0) 2208177050Syongari break; 2209177050Syongari VR_LOCK(sc); 2210177050Syongari /* Disable interrupts. */ 2211177050Syongari CSR_WRITE_2(sc, VR_IMR, 0x0000); 2212177050Syongari ifp->if_capenable |= IFCAP_POLLING; 2213177050Syongari VR_UNLOCK(sc); 2214177050Syongari } else { 2215177050Syongari error = ether_poll_deregister(ifp); 2216177050Syongari /* Enable interrupts. */ 2217177050Syongari VR_LOCK(sc); 2218177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2219177050Syongari ifp->if_capenable &= ~IFCAP_POLLING; 2220177050Syongari VR_UNLOCK(sc); 2221177050Syongari } 2222150789Sglebius } 2223177050Syongari#endif /* DEVICE_POLLING */ 2224177050Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2225177050Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2226177050Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2227177050Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2228177050Syongari ifp->if_hwassist |= VR_CSUM_FEATURES; 2229177050Syongari else 2230177050Syongari ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2231150789Sglebius } 2232177050Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2233177050Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2234177050Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2235177050Syongari if ((mask & IFCAP_WOL_UCAST) != 0 && 2236177050Syongari (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2237177050Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2238177050Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2239177050Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2240177050Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2241128118Sru break; 224241502Swpaul default: 2243106936Ssam error = ether_ioctl(ifp, command, data); 224441502Swpaul break; 224541502Swpaul } 224641502Swpaul 2247131503Sbms return (error); 224841502Swpaul} 224941502Swpaul 2250102336Salfredstatic void 2251177050Syongarivr_watchdog(struct vr_softc *sc) 225241502Swpaul{ 2253177050Syongari struct ifnet *ifp; 225441502Swpaul 2255177050Syongari VR_LOCK_ASSERT(sc); 2256131844Sbms 2257177050Syongari if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2258177050Syongari return; 2259177050Syongari 2260177050Syongari ifp = sc->vr_ifp; 2261177050Syongari /* 2262177050Syongari * Reclaim first as we don't request interrupt for every packets. 2263177050Syongari */ 2264177050Syongari vr_txeof(sc); 2265177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 2266177050Syongari return; 2267177050Syongari 2268177050Syongari if (sc->vr_link == 0) { 2269177050Syongari if (bootverbose) 2270177050Syongari if_printf(sc->vr_ifp, "watchdog timeout " 2271177050Syongari "(missed link)\n"); 2272177050Syongari ifp->if_oerrors++; 2273211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2274177050Syongari vr_init_locked(sc); 2275177050Syongari return; 2276177050Syongari } 2277177050Syongari 227841502Swpaul ifp->if_oerrors++; 2279151773Sjhb if_printf(ifp, "watchdog timeout\n"); 228041502Swpaul 2281211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2282131844Sbms vr_init_locked(sc); 2283131518Sbms 2284132986Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2285131844Sbms vr_start_locked(ifp); 2286177050Syongari} 2287131844Sbms 2288177050Syongaristatic void 2289177050Syongarivr_tx_start(struct vr_softc *sc) 2290177050Syongari{ 2291177050Syongari bus_addr_t addr; 2292177050Syongari uint8_t cmd; 2293177050Syongari 2294177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2295177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) { 2296177050Syongari addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2297177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2298177050Syongari cmd |= VR_CR0_TX_ON; 2299177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2300177050Syongari } 2301177050Syongari if (sc->vr_cdata.vr_tx_cnt != 0) { 2302177050Syongari sc->vr_watchdog_timer = 5; 2303177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2304177050Syongari } 230541502Swpaul} 230641502Swpaul 2307177050Syongaristatic void 2308177050Syongarivr_rx_start(struct vr_softc *sc) 2309177050Syongari{ 2310177050Syongari bus_addr_t addr; 2311177050Syongari uint8_t cmd; 2312177050Syongari 2313177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2314177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) { 2315177050Syongari addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2316177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2317177050Syongari cmd |= VR_CR0_RX_ON; 2318177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2319177050Syongari } 2320177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2321177050Syongari} 2322177050Syongari 2323177050Syongaristatic int 2324177050Syongarivr_tx_stop(struct vr_softc *sc) 2325177050Syongari{ 2326177050Syongari int i; 2327177050Syongari uint8_t cmd; 2328177050Syongari 2329177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2330177050Syongari if ((cmd & VR_CR0_TX_ON) != 0) { 2331177050Syongari cmd &= ~VR_CR0_TX_ON; 2332177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2333177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2334177050Syongari DELAY(5); 2335177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2336177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) 2337177050Syongari break; 2338177050Syongari } 2339177050Syongari if (i == 0) 2340177050Syongari return (ETIMEDOUT); 2341177050Syongari } 2342177050Syongari return (0); 2343177050Syongari} 2344177050Syongari 2345177050Syongaristatic int 2346177050Syongarivr_rx_stop(struct vr_softc *sc) 2347177050Syongari{ 2348177050Syongari int i; 2349177050Syongari uint8_t cmd; 2350177050Syongari 2351177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2352177050Syongari if ((cmd & VR_CR0_RX_ON) != 0) { 2353177050Syongari cmd &= ~VR_CR0_RX_ON; 2354177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2355177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2356177050Syongari DELAY(5); 2357177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2358177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) 2359177050Syongari break; 2360177050Syongari } 2361177050Syongari if (i == 0) 2362177050Syongari return (ETIMEDOUT); 2363177050Syongari } 2364177050Syongari return (0); 2365177050Syongari} 2366177050Syongari 236741502Swpaul/* 236841502Swpaul * Stop the adapter and free any mbufs allocated to the 236941502Swpaul * RX and TX lists. 237041502Swpaul */ 2371102336Salfredstatic void 2372131503Sbmsvr_stop(struct vr_softc *sc) 237341502Swpaul{ 2374177050Syongari struct vr_txdesc *txd; 2375177050Syongari struct vr_rxdesc *rxd; 2376177050Syongari struct ifnet *ifp; 2377177050Syongari int i; 237841502Swpaul 2379131518Sbms VR_LOCK_ASSERT(sc); 238067087Swpaul 2381147256Sbrooks ifp = sc->vr_ifp; 2382177050Syongari sc->vr_watchdog_timer = 0; 238341502Swpaul 2384151911Sjhb callout_stop(&sc->vr_stat_callout); 2385148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 238651432Swpaul 2387177050Syongari CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2388177050Syongari if (vr_rx_stop(sc) != 0) 2389177050Syongari device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2390177050Syongari if (vr_tx_stop(sc) != 0) 2391177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2392177050Syongari /* Clear pending interrupts. */ 2393177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 239441502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 239541502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 239641502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 239741502Swpaul 239841502Swpaul /* 2399177050Syongari * Free RX and TX mbufs still in the queues. 240041502Swpaul */ 2401177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 2402177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 2403177050Syongari if (rxd->rx_m != NULL) { 2404177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2405177050Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2406177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2407177050Syongari rxd->rx_dmamap); 2408177050Syongari m_freem(rxd->rx_m); 2409177050Syongari rxd->rx_m = NULL; 2410177050Syongari } 2411177050Syongari } 2412177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 2413177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 2414177050Syongari if (txd->tx_m != NULL) { 2415177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2416177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2417177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2418177050Syongari txd->tx_dmamap); 2419177050Syongari m_freem(txd->tx_m); 2420177050Syongari txd->tx_m = NULL; 2421177050Syongari } 2422177050Syongari } 242341502Swpaul} 242441502Swpaul 242541502Swpaul/* 242641502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 242741502Swpaul * get confused by errant DMAs when rebooting. 242841502Swpaul */ 2429173839Syongaristatic int 2430131503Sbmsvr_shutdown(device_t dev) 243141502Swpaul{ 243241502Swpaul 2433177050Syongari return (vr_suspend(dev)); 2434177050Syongari} 2435173839Syongari 2436177050Syongaristatic int 2437177050Syongarivr_suspend(device_t dev) 2438177050Syongari{ 2439177050Syongari struct vr_softc *sc; 2440177050Syongari 2441177050Syongari sc = device_get_softc(dev); 2442177050Syongari 2443177050Syongari VR_LOCK(sc); 2444177050Syongari vr_stop(sc); 2445177050Syongari vr_setwol(sc); 2446177050Syongari sc->vr_suspended = 1; 2447177050Syongari VR_UNLOCK(sc); 2448177050Syongari 2449173839Syongari return (0); 245041502Swpaul} 2451177050Syongari 2452177050Syongaristatic int 2453177050Syongarivr_resume(device_t dev) 2454177050Syongari{ 2455177050Syongari struct vr_softc *sc; 2456177050Syongari struct ifnet *ifp; 2457177050Syongari 2458177050Syongari sc = device_get_softc(dev); 2459177050Syongari 2460177050Syongari VR_LOCK(sc); 2461177050Syongari ifp = sc->vr_ifp; 2462177050Syongari vr_clrwol(sc); 2463177050Syongari vr_reset(sc); 2464177050Syongari if (ifp->if_flags & IFF_UP) 2465177050Syongari vr_init_locked(sc); 2466177050Syongari 2467177050Syongari sc->vr_suspended = 0; 2468177050Syongari VR_UNLOCK(sc); 2469177050Syongari 2470177050Syongari return (0); 2471177050Syongari} 2472177050Syongari 2473177050Syongaristatic void 2474177050Syongarivr_setwol(struct vr_softc *sc) 2475177050Syongari{ 2476177050Syongari struct ifnet *ifp; 2477177050Syongari int pmc; 2478177050Syongari uint16_t pmstat; 2479177050Syongari uint8_t v; 2480177050Syongari 2481177050Syongari VR_LOCK_ASSERT(sc); 2482177050Syongari 2483177050Syongari if (sc->vr_revid < REV_ID_VT6102_A || 2484219902Sjhb pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2485177050Syongari return; 2486177050Syongari 2487177050Syongari ifp = sc->vr_ifp; 2488177050Syongari 2489177050Syongari /* Clear WOL configuration. */ 2490177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2491177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2492177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2493177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2494177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2495177050Syongari /* Newer Rhine III supports two additional patterns. */ 2496177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2497177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2498177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2499177050Syongari } 2500177050Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2501177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2502177050Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2503177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2504177050Syongari /* 2505177050Syongari * It seems that multicast wakeup frames require programming pattern 2506177050Syongari * registers and valid CRC as well as pattern mask for each pattern. 2507177050Syongari * While it's possible to setup such a pattern it would complicate 2508177050Syongari * WOL configuration so ignore multicast wakeup frames. 2509177050Syongari */ 2510177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2511177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2512177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2513177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2514177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2515177050Syongari } 2516177050Syongari 2517177050Syongari /* Put hardware into sleep. */ 2518177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2519177050Syongari v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2520177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2521177050Syongari 2522177050Syongari /* Request PME if WOL is requested. */ 2523177050Syongari pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2524177050Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2525177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2526177050Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2527177050Syongari pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2528177050Syongari} 2529177050Syongari 2530177050Syongaristatic void 2531177050Syongarivr_clrwol(struct vr_softc *sc) 2532177050Syongari{ 2533177050Syongari uint8_t v; 2534177050Syongari 2535177050Syongari VR_LOCK_ASSERT(sc); 2536177050Syongari 2537177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 2538177050Syongari return; 2539177050Syongari 2540177050Syongari /* Take hardware out of sleep. */ 2541177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2542177050Syongari v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2543177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2544177050Syongari 2545177050Syongari /* Clear WOL configuration as WOL may interfere normal operation. */ 2546177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2547177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2548177050Syongari VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2549177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2550177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2551177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2552177050Syongari /* Newer Rhine III supports two additional patterns. */ 2553177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2554177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2555177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2556177050Syongari } 2557177050Syongari} 2558177050Syongari 2559177050Syongaristatic int 2560177050Syongarivr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2561177050Syongari{ 2562177050Syongari struct vr_softc *sc; 2563177050Syongari struct vr_statistics *stat; 2564177050Syongari int error; 2565177050Syongari int result; 2566177050Syongari 2567177050Syongari result = -1; 2568177050Syongari error = sysctl_handle_int(oidp, &result, 0, req); 2569177050Syongari 2570177050Syongari if (error != 0 || req->newptr == NULL) 2571177050Syongari return (error); 2572177050Syongari 2573177050Syongari if (result == 1) { 2574177050Syongari sc = (struct vr_softc *)arg1; 2575177050Syongari stat = &sc->vr_stat; 2576177050Syongari 2577177050Syongari printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2578177050Syongari printf("Outbound good frames : %ju\n", 2579177050Syongari (uintmax_t)stat->tx_ok); 2580177050Syongari printf("Inbound good frames : %ju\n", 2581177050Syongari (uintmax_t)stat->rx_ok); 2582177050Syongari printf("Outbound errors : %u\n", stat->tx_errors); 2583177050Syongari printf("Inbound errors : %u\n", stat->rx_errors); 2584177050Syongari printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2585177050Syongari printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2586177050Syongari printf("Inbound FIFO overflows : %d\n", 2587177050Syongari stat->rx_fifo_overflows); 2588177050Syongari printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2589177050Syongari printf("Inbound frame alignment errors : %u\n", 2590177050Syongari stat->rx_alignment); 2591177050Syongari printf("Inbound giant frames : %u\n", stat->rx_giants); 2592177050Syongari printf("Inbound runt frames : %u\n", stat->rx_runts); 2593177050Syongari printf("Outbound aborted with excessive collisions : %u\n", 2594177050Syongari stat->tx_abort); 2595177050Syongari printf("Outbound collisions : %u\n", stat->tx_collisions); 2596177050Syongari printf("Outbound late collisions : %u\n", 2597177050Syongari stat->tx_late_collisions); 2598177050Syongari printf("Outbound underrun : %u\n", stat->tx_underrun); 2599177050Syongari printf("PCI bus errors : %u\n", stat->bus_errors); 2600177050Syongari printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2601177050Syongari stat->num_restart); 2602177050Syongari } 2603177050Syongari 2604177050Syongari return (error); 2605177050Syongari} 2606