if_vr.c revision 226478
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 226478 2011-10-17 19:49:00Z yongari $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various network adapters based on the VIA Rhine 4041502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4141502Swpaul * Datasheets are available at http://www.via.com.tw. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 47131503Sbms 4841502Swpaul/* 4941502Swpaul * The VIA Rhine controllers are similar in some respects to the 5041502Swpaul * the DEC tulip chips, except less complicated. The controller 5141502Swpaul * uses an MII bus and an external physical layer interface. The 5241502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5341502Swpaul * multicast filter. Transmit and receive descriptors are similar 5441502Swpaul * to the tulip. 5541502Swpaul * 56168953Sphk * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 5741502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5841502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5941502Swpaul * at longword boundaries, so we have to do a buffer copy before 6041502Swpaul * transmission. 6141502Swpaul */ 6241502Swpaul 63150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 64150968Sglebius#include "opt_device_polling.h" 65150968Sglebius#endif 66150968Sglebius 6741502Swpaul#include <sys/param.h> 6841502Swpaul#include <sys/systm.h> 69177050Syongari#include <sys/bus.h> 70177050Syongari#include <sys/endian.h> 71177050Syongari#include <sys/kernel.h> 72177050Syongari#include <sys/malloc.h> 7341502Swpaul#include <sys/mbuf.h> 74129878Sphk#include <sys/module.h> 75177050Syongari#include <sys/rman.h> 7641502Swpaul#include <sys/socket.h> 77177050Syongari#include <sys/sockio.h> 78177050Syongari#include <sys/sysctl.h> 79177050Syongari#include <sys/taskqueue.h> 8041502Swpaul 81177050Syongari#include <net/bpf.h> 8241502Swpaul#include <net/if.h> 8341502Swpaul#include <net/ethernet.h> 8441502Swpaul#include <net/if_dl.h> 8541502Swpaul#include <net/if_media.h> 86147256Sbrooks#include <net/if_types.h> 87177050Syongari#include <net/if_vlan_var.h> 8841502Swpaul 89177050Syongari#include <dev/mii/mii.h> 9051432Swpaul#include <dev/mii/miivar.h> 9151432Swpaul 92172555Syongari#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9441502Swpaul 95177050Syongari#include <machine/bus.h> 9641502Swpaul 97177047Syongari#include <dev/vr/if_vrreg.h> 9841502Swpaul 99177050Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 100177050Syongari#include "miibus_if.h" 101177050Syongari 102113506SmdoddMODULE_DEPEND(vr, pci, 1, 1, 1); 103113506SmdoddMODULE_DEPEND(vr, ether, 1, 1, 1); 10459758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 10559758Speter 106177050Syongari/* Define to show Rx/Tx error status. */ 107177050Syongari#undef VR_SHOW_ERRORS 108177050Syongari#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 10951432Swpaul 11041502Swpaul/* 111177050Syongari * Various supported device vendors/types, their names & quirks. 11241502Swpaul */ 113168952Sphk#define VR_Q_NEEDALIGN (1<<0) 114168952Sphk#define VR_Q_CSUM (1<<1) 115177050Syongari#define VR_Q_CAM (1<<2) 116168952Sphk 117226171Smariusstatic const struct vr_type { 118168952Sphk u_int16_t vr_vid; 119168952Sphk u_int16_t vr_did; 120168952Sphk int vr_quirks; 121226171Smarius const char *vr_name; 122226171Smarius} const vr_devs[] = { 123168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE, 124168827Sphk VR_Q_NEEDALIGN, 125168827Sphk "VIA VT3043 Rhine I 10/100BaseTX" }, 126168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127168827Sphk VR_Q_NEEDALIGN, 128168827Sphk "VIA VT86C100A Rhine II 10/100BaseTX" }, 129168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130168827Sphk 0, 131168827Sphk "VIA VT6102 Rhine II 10/100BaseTX" }, 132168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133168827Sphk 0, 134168827Sphk "VIA VT6105 Rhine III 10/100BaseTX" }, 135168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136185962Syongari VR_Q_CSUM, 137168827Sphk "VIA VT6105M Rhine III 10/100BaseTX" }, 138168827Sphk { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139168827Sphk VR_Q_NEEDALIGN, 140168827Sphk "Delta Electronics Rhine II 10/100BaseTX" }, 141168827Sphk { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142168827Sphk VR_Q_NEEDALIGN, 143168827Sphk "Addtron Technology Rhine II 10/100BaseTX" }, 144168813Sphk { 0, 0, 0, NULL } 14541502Swpaul}; 14641502Swpaul 147142407Simpstatic int vr_probe(device_t); 148142407Simpstatic int vr_attach(device_t); 149142407Simpstatic int vr_detach(device_t); 150177050Syongaristatic int vr_shutdown(device_t); 151177050Syongaristatic int vr_suspend(device_t); 152177050Syongaristatic int vr_resume(device_t); 15341502Swpaul 154177050Syongaristatic void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155177050Syongaristatic int vr_dma_alloc(struct vr_softc *); 156177050Syongaristatic void vr_dma_free(struct vr_softc *); 157177050Syongaristatic __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158177050Syongaristatic int vr_newbuf(struct vr_softc *, int); 15941502Swpaul 160177050Syongari#ifndef __NO_STRICT_ALIGNMENT 161177050Syongaristatic __inline void vr_fixup_rx(struct mbuf *); 162177050Syongari#endif 163193096Sattiliostatic int vr_rxeof(struct vr_softc *); 164142407Simpstatic void vr_txeof(struct vr_softc *); 165142407Simpstatic void vr_tick(void *); 166177050Syongaristatic int vr_error(struct vr_softc *, uint16_t); 167177050Syongaristatic void vr_tx_underrun(struct vr_softc *); 168142407Simpstatic void vr_intr(void *); 169142407Simpstatic void vr_start(struct ifnet *); 170142407Simpstatic void vr_start_locked(struct ifnet *); 171177050Syongaristatic int vr_encap(struct vr_softc *, struct mbuf **); 172142407Simpstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 173142407Simpstatic void vr_init(void *); 174142407Simpstatic void vr_init_locked(struct vr_softc *); 175177050Syongaristatic void vr_tx_start(struct vr_softc *); 176177050Syongaristatic void vr_rx_start(struct vr_softc *); 177177050Syongaristatic int vr_tx_stop(struct vr_softc *); 178177050Syongaristatic int vr_rx_stop(struct vr_softc *); 179142407Simpstatic void vr_stop(struct vr_softc *); 180177050Syongaristatic void vr_watchdog(struct vr_softc *); 181142407Simpstatic int vr_ifmedia_upd(struct ifnet *); 182142407Simpstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 18341502Swpaul 184177050Syongaristatic int vr_miibus_readreg(device_t, int, int); 185177050Syongaristatic int vr_miibus_writereg(device_t, int, int, int); 186142407Simpstatic void vr_miibus_statchg(device_t); 18741502Swpaul 188180552Syongaristatic void vr_cam_mask(struct vr_softc *, uint32_t, int); 189180552Syongaristatic int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 190177050Syongaristatic void vr_set_filter(struct vr_softc *); 191168946Sphkstatic void vr_reset(const struct vr_softc *); 192177050Syongaristatic int vr_tx_ring_init(struct vr_softc *); 193177050Syongaristatic int vr_rx_ring_init(struct vr_softc *); 194177050Syongaristatic void vr_setwol(struct vr_softc *); 195177050Syongaristatic void vr_clrwol(struct vr_softc *); 196177050Syongaristatic int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 19741502Swpaul 198226171Smariusstatic const struct vr_tx_threshold_table { 199177050Syongari int tx_cfg; 200177050Syongari int bcr_cfg; 201177050Syongari int value; 202226171Smarius} const vr_tx_threshold_tables[] = { 203177050Syongari { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 204177050Syongari { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 205177050Syongari { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 206177050Syongari { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 207177050Syongari { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 208177050Syongari { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 209177050Syongari}; 21049610Swpaul 21149610Swpaulstatic device_method_t vr_methods[] = { 21249610Swpaul /* Device interface */ 21349610Swpaul DEVMETHOD(device_probe, vr_probe), 21449610Swpaul DEVMETHOD(device_attach, vr_attach), 21549610Swpaul DEVMETHOD(device_detach, vr_detach), 21649610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 217177050Syongari DEVMETHOD(device_suspend, vr_suspend), 218177050Syongari DEVMETHOD(device_resume, vr_resume), 21951432Swpaul 22051432Swpaul /* bus interface */ 22151432Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22251432Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22351432Swpaul 22451432Swpaul /* MII interface */ 22551432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 22651432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 22751432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 22851432Swpaul 229177050Syongari { NULL, NULL } 23049610Swpaul}; 23149610Swpaul 23249610Swpaulstatic driver_t vr_driver = { 23351455Swpaul "vr", 23449610Swpaul vr_methods, 23549610Swpaul sizeof(struct vr_softc) 23649610Swpaul}; 23749610Swpaul 23849610Swpaulstatic devclass_t vr_devclass; 23949610Swpaul 240113506SmdoddDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 24151473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 24249610Swpaul 243102336Salfredstatic int 244177050Syongarivr_miibus_readreg(device_t dev, int phy, int reg) 24541502Swpaul{ 246177050Syongari struct vr_softc *sc; 247177050Syongari int i; 24841502Swpaul 249177050Syongari sc = device_get_softc(dev); 250110168Ssilby 251131503Sbms /* Set the register address. */ 252177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 253110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 254131503Sbms 255177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 256177050Syongari DELAY(1); 257110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 258110168Ssilby break; 259110168Ssilby } 260177050Syongari if (i == VR_MII_TIMEOUT) 261177050Syongari device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 262110168Ssilby 263177050Syongari return (CSR_READ_2(sc, VR_MIIDATA)); 264110168Ssilby} 265110168Ssilby 266102336Salfredstatic int 267177050Syongarivr_miibus_writereg(device_t dev, int phy, int reg, int data) 26841502Swpaul{ 269177050Syongari struct vr_softc *sc; 270177050Syongari int i; 27141502Swpaul 272177050Syongari sc = device_get_softc(dev); 273110168Ssilby 274131503Sbms /* Set the register address and data to write. */ 275177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 276177050Syongari CSR_WRITE_2(sc, VR_MIIDATA, data); 277110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 278110168Ssilby 279177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 280177050Syongari DELAY(1); 281110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 282110168Ssilby break; 283110168Ssilby } 284177050Syongari if (i == VR_MII_TIMEOUT) 285177050Syongari device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 286177050Syongari reg); 287110168Ssilby 288131503Sbms return (0); 289110168Ssilby} 290110168Ssilby 291177050Syongari/* 292177050Syongari * In order to fiddle with the 293177050Syongari * 'full-duplex' and '100Mbps' bits in the netconfig register, we 294177050Syongari * first have to put the transmit and/or receive logic in the idle state. 295177050Syongari */ 296177050Syongaristatic void 297223405Syongarivr_miibus_statchg(device_t dev) 29851432Swpaul{ 299177050Syongari struct vr_softc *sc; 300177050Syongari struct mii_data *mii; 301177050Syongari struct ifnet *ifp; 302177050Syongari int lfdx, mfdx; 303177050Syongari uint8_t cr0, cr1, fc; 30441502Swpaul 305223405Syongari sc = device_get_softc(dev); 306177050Syongari mii = device_get_softc(sc->vr_miibus); 307177050Syongari ifp = sc->vr_ifp; 308177050Syongari if (mii == NULL || ifp == NULL || 309223405Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 310177050Syongari return; 31141502Swpaul 312223405Syongari sc->vr_link = 0; 313223405Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 314223405Syongari (IFM_ACTIVE | IFM_AVALID)) { 315223405Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 316223405Syongari case IFM_10_T: 317223405Syongari case IFM_100_TX: 318177050Syongari sc->vr_link = 1; 319223405Syongari break; 320223405Syongari default: 321223405Syongari break; 322223405Syongari } 323223405Syongari } 324177050Syongari 325177050Syongari if (sc->vr_link != 0) { 326177050Syongari cr0 = CSR_READ_1(sc, VR_CR0); 327177050Syongari cr1 = CSR_READ_1(sc, VR_CR1); 328177050Syongari mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 329177050Syongari lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 330177050Syongari if (mfdx != lfdx) { 331177050Syongari if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 332177050Syongari if (vr_tx_stop(sc) != 0 || 333177050Syongari vr_rx_stop(sc) != 0) { 334177050Syongari device_printf(sc->vr_dev, 335177050Syongari "%s: Tx/Rx shutdown error -- " 336177050Syongari "resetting\n", __func__); 337177050Syongari sc->vr_flags |= VR_F_RESTART; 338177050Syongari VR_UNLOCK(sc); 339177050Syongari return; 340177050Syongari } 341177050Syongari } 342177050Syongari if (lfdx) 343177050Syongari cr1 |= VR_CR1_FULLDUPLEX; 344177050Syongari else 345177050Syongari cr1 &= ~VR_CR1_FULLDUPLEX; 346177050Syongari CSR_WRITE_1(sc, VR_CR1, cr1); 347177050Syongari } 348177050Syongari fc = 0; 349177050Syongari#ifdef notyet 350177050Syongari /* Configure flow-control. */ 351177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 352177050Syongari fc = CSR_READ_1(sc, VR_FLOWCR1); 353177050Syongari fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 354177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 355177050Syongari IFM_ETH_RXPAUSE) != 0) 356177050Syongari fc |= VR_FLOWCR1_RXPAUSE; 357177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 358177050Syongari IFM_ETH_TXPAUSE) != 0) 359177050Syongari fc |= VR_FLOWCR1_TXPAUSE; 360177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, fc); 361177050Syongari } else if (sc->vr_revid >= REV_ID_VT6102_A) { 362177050Syongari /* No Tx puase capability available for Rhine II. */ 363177050Syongari fc = CSR_READ_1(sc, VR_MISC_CR0); 364177050Syongari fc &= ~VR_MISCCR0_RXPAUSE; 365177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 366177050Syongari IFM_ETH_RXPAUSE) != 0) 367177050Syongari fc |= VR_MISCCR0_RXPAUSE; 368177050Syongari CSR_WRITE_1(sc, VR_MISC_CR0, fc); 369177050Syongari } 370177050Syongari#endif 371177050Syongari vr_rx_start(sc); 372177050Syongari vr_tx_start(sc); 373177050Syongari } else { 374177050Syongari if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 375177050Syongari device_printf(sc->vr_dev, 376177050Syongari "%s: Tx/Rx shutdown error -- resetting\n", 377177050Syongari __func__); 378177050Syongari sc->vr_flags |= VR_F_RESTART; 379177050Syongari } 380177050Syongari } 38151432Swpaul} 38251432Swpaul 383180552Syongari 384180552Syongaristatic void 385180552Syongarivr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 386180552Syongari{ 387180552Syongari 388180552Syongari if (type == VR_MCAST_CAM) 389180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 390180552Syongari else 391180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 392180552Syongari CSR_WRITE_4(sc, VR_CAMMASK, mask); 393180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 394180552Syongari} 395180552Syongari 396177050Syongaristatic int 397180552Syongarivr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 39851432Swpaul{ 399177050Syongari int i; 40051432Swpaul 401180552Syongari if (type == VR_MCAST_CAM) { 402180552Syongari if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 403180552Syongari return (EINVAL); 404180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 405180552Syongari } else 406180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 407177050Syongari 408177050Syongari /* Set CAM entry address. */ 409177050Syongari CSR_WRITE_1(sc, VR_CAMADDR, idx); 410177050Syongari /* Set CAM entry data. */ 411180552Syongari if (type == VR_MCAST_CAM) { 412180552Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) 413180552Syongari CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 414180552Syongari } else { 415180552Syongari CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 416180552Syongari CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 417180552Syongari } 418180552Syongari DELAY(10); 419177050Syongari /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 420180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 421177050Syongari for (i = 0; i < VR_TIMEOUT; i++) { 422177050Syongari DELAY(1); 423177050Syongari if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 424177050Syongari break; 425177050Syongari } 426177050Syongari 427177050Syongari if (i == VR_TIMEOUT) 428177050Syongari device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 429177050Syongari __func__); 430180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 431177050Syongari 432177050Syongari return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 43341502Swpaul} 43441502Swpaul 43541502Swpaul/* 43641502Swpaul * Program the 64-bit multicast hash filter. 43741502Swpaul */ 438102336Salfredstatic void 439177050Syongarivr_set_filter(struct vr_softc *sc) 44041502Swpaul{ 441177050Syongari struct ifnet *ifp; 442177050Syongari int h; 443131503Sbms uint32_t hashes[2] = { 0, 0 }; 44441502Swpaul struct ifmultiaddr *ifma; 445131503Sbms uint8_t rxfilt; 446177050Syongari int error, mcnt; 447177050Syongari uint32_t cam_mask; 44841502Swpaul 449131518Sbms VR_LOCK_ASSERT(sc); 45041502Swpaul 451177050Syongari ifp = sc->vr_ifp; 45241502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 453185014Syongari rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 454185014Syongari VR_RXCFG_RX_MULTI); 455177050Syongari if (ifp->if_flags & IFF_BROADCAST) 456177050Syongari rxfilt |= VR_RXCFG_RX_BROAD; 45741502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 45841502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 459177050Syongari if (ifp->if_flags & IFF_PROMISC) 460177050Syongari rxfilt |= VR_RXCFG_RX_PROMISC; 46141502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 46241502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 46341502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 46441502Swpaul return; 46541502Swpaul } 46641502Swpaul 467131503Sbms /* Now program new ones. */ 468177050Syongari error = 0; 469180552Syongari mcnt = 0; 470195049Srwatson if_maddr_rlock(ifp); 471177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 472177050Syongari /* 473177050Syongari * For hardwares that have CAM capability, use 474177050Syongari * 32 entries multicast perfect filter. 475177050Syongari */ 476177050Syongari cam_mask = 0; 477177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 478177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 479177050Syongari continue; 480180552Syongari error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 481177050Syongari LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 482177050Syongari if (error != 0) { 483177050Syongari cam_mask = 0; 484177050Syongari break; 485177050Syongari } 486177050Syongari cam_mask |= 1 << mcnt; 487177050Syongari mcnt++; 488177050Syongari } 489180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 49041502Swpaul } 491177050Syongari 492177050Syongari if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 493177050Syongari /* 494177050Syongari * If there are too many multicast addresses or 495177050Syongari * setting multicast CAM filter failed, use hash 496177050Syongari * table based filtering. 497177050Syongari */ 498180552Syongari mcnt = 0; 499177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 500177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 501177050Syongari continue; 502177050Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 503177050Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 504177050Syongari if (h < 32) 505177050Syongari hashes[0] |= (1 << h); 506177050Syongari else 507177050Syongari hashes[1] |= (1 << (h - 32)); 508177050Syongari mcnt++; 509177050Syongari } 510177050Syongari } 511195049Srwatson if_maddr_runlock(ifp); 51241502Swpaul 513177050Syongari if (mcnt > 0) 51441502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 51541502Swpaul 51641502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 51741502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 51841502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 51941502Swpaul} 52041502Swpaul 521102336Salfredstatic void 522168946Sphkvr_reset(const struct vr_softc *sc) 52341502Swpaul{ 524177050Syongari int i; 52541502Swpaul 526151773Sjhb /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 527131518Sbms 528177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 529177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 530177050Syongari /* VT86C100A needs more delay after reset. */ 531177050Syongari DELAY(100); 532177050Syongari } 53341502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 53441502Swpaul DELAY(10); 535177050Syongari if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 53641502Swpaul break; 53741502Swpaul } 538107220Ssilby if (i == VR_TIMEOUT) { 539177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 540162315Sglebius device_printf(sc->vr_dev, "reset never completed!\n"); 541107220Ssilby else { 542177050Syongari /* Use newer force reset command. */ 543177050Syongari device_printf(sc->vr_dev, 544177050Syongari "Using force reset command.\n"); 545107220Ssilby VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 546177050Syongari /* 547177050Syongari * Wait a little while for the chip to get its brains 548177050Syongari * in order. 549177050Syongari */ 550177050Syongari DELAY(2000); 551107220Ssilby } 552107220Ssilby } 55341502Swpaul 55441502Swpaul} 55541502Swpaul 55641502Swpaul/* 55741502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 558168813Sphk * IDs against our list and return a match or NULL 559168813Sphk */ 560226171Smariusstatic const struct vr_type * 561168813Sphkvr_match(device_t dev) 562168813Sphk{ 563226171Smarius const struct vr_type *t = vr_devs; 564168813Sphk 565168813Sphk for (t = vr_devs; t->vr_name != NULL; t++) 566168813Sphk if ((pci_get_vendor(dev) == t->vr_vid) && 567168813Sphk (pci_get_device(dev) == t->vr_did)) 568168813Sphk return (t); 569168813Sphk return (NULL); 570168813Sphk} 571168813Sphk 572168813Sphk/* 573168813Sphk * Probe for a VIA Rhine chip. Check the PCI vendor and device 57441502Swpaul * IDs against our list and return a device name if we find a match. 57541502Swpaul */ 576102336Salfredstatic int 577131503Sbmsvr_probe(device_t dev) 57841502Swpaul{ 579226171Smarius const struct vr_type *t; 58041502Swpaul 581168813Sphk t = vr_match(dev); 582168813Sphk if (t != NULL) { 583168813Sphk device_set_desc(dev, t->vr_name); 584168813Sphk return (BUS_PROBE_DEFAULT); 58541502Swpaul } 586131503Sbms return (ENXIO); 58741502Swpaul} 58841502Swpaul 58941502Swpaul/* 59041502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 59141502Swpaul * setup and ethernet/BPF attach. 59241502Swpaul */ 593102336Salfredstatic int 594168946Sphkvr_attach(device_t dev) 59541502Swpaul{ 59641502Swpaul struct vr_softc *sc; 59741502Swpaul struct ifnet *ifp; 598226171Smarius const struct vr_type *t; 599177050Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 600177050Syongari int error, rid; 601213893Smarius int i, phy, pmc; 60241502Swpaul 60349610Swpaul sc = device_get_softc(dev); 604162315Sglebius sc->vr_dev = dev; 605168813Sphk t = vr_match(dev); 606168813Sphk KASSERT(t != NULL, ("Lost if_vr device match")); 607168813Sphk sc->vr_quirks = t->vr_quirks; 608168813Sphk device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 60941502Swpaul 61093818Sjhb mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 611131518Sbms MTX_DEF); 612151911Sjhb callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 613177050Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 614177050Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 615177050Syongari OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 616177050Syongari vr_sysctl_stats, "I", "Statistics"); 617151911Sjhb 618177050Syongari error = 0; 619177050Syongari 62041502Swpaul /* 62141502Swpaul * Map control/status registers. 62241502Swpaul */ 62372813Swpaul pci_enable_busmaster(dev); 624177050Syongari sc->vr_revid = pci_get_revid(dev); 625177050Syongari device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 62641502Swpaul 627177050Syongari sc->vr_res_id = PCIR_BAR(0); 628177050Syongari sc->vr_res_type = SYS_RES_IOPORT; 629177050Syongari sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 630177050Syongari &sc->vr_res_id, RF_ACTIVE); 63149610Swpaul if (sc->vr_res == NULL) { 632177050Syongari device_printf(dev, "couldn't map ports\n"); 63349610Swpaul error = ENXIO; 63441502Swpaul goto fail; 63541502Swpaul } 63641502Swpaul 637177050Syongari /* Allocate interrupt. */ 63849610Swpaul rid = 0; 639127135Snjl sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 64049610Swpaul RF_SHAREABLE | RF_ACTIVE); 64149610Swpaul 64249610Swpaul if (sc->vr_irq == NULL) { 643151773Sjhb device_printf(dev, "couldn't map interrupt\n"); 64449610Swpaul error = ENXIO; 64541502Swpaul goto fail; 64641502Swpaul } 64741502Swpaul 648151773Sjhb /* Allocate ifnet structure. */ 649151773Sjhb ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 650151773Sjhb if (ifp == NULL) { 651177050Syongari device_printf(dev, "couldn't allocate ifnet structure\n"); 652151773Sjhb error = ENOSPC; 653151773Sjhb goto fail; 654151773Sjhb } 655151773Sjhb ifp->if_softc = sc; 656151773Sjhb if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 657151773Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658151773Sjhb ifp->if_ioctl = vr_ioctl; 659151773Sjhb ifp->if_start = vr_start; 660151773Sjhb ifp->if_init = vr_init; 661177050Syongari IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 662177050Syongari ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 663151773Sjhb IFQ_SET_READY(&ifp->if_snd); 664168827Sphk 665177050Syongari /* Configure Tx FIFO threshold. */ 666177050Syongari sc->vr_txthresh = VR_TXTHRESH_MIN; 667177050Syongari if (sc->vr_revid < REV_ID_VT6105_A0) { 668177050Syongari /* 669177050Syongari * Use store and forward mode for Rhine I/II. 670177050Syongari * Otherwise they produce a lot of Tx underruns and 671177050Syongari * it would take a while to get working FIFO threshold 672177050Syongari * value. 673177050Syongari */ 674177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 675177050Syongari } 676177050Syongari if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 677177050Syongari ifp->if_hwassist = VR_CSUM_FEATURES; 678168827Sphk ifp->if_capabilities |= IFCAP_HWCSUM; 679177050Syongari /* 680177050Syongari * To update checksum field the hardware may need to 681177050Syongari * store entire frames into FIFO before transmitting. 682177050Syongari */ 683177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 684168827Sphk } 685168827Sphk 686177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A && 687219902Sjhb pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 688177050Syongari ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 689177050Syongari 690177050Syongari /* Rhine supports oversized VLAN frame. */ 691168973Sphk ifp->if_capabilities |= IFCAP_VLAN_MTU; 692151773Sjhb ifp->if_capenable = ifp->if_capabilities; 693151773Sjhb#ifdef DEVICE_POLLING 694151773Sjhb ifp->if_capabilities |= IFCAP_POLLING; 695151773Sjhb#endif 696151773Sjhb 69776586Swpaul /* 69876586Swpaul * Windows may put the chip in suspend mode when it 69976586Swpaul * shuts down. Be sure to kick it in the head to wake it 70076586Swpaul * up again. 70176586Swpaul */ 702219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 703172555Syongari VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 70476586Swpaul 705131503Sbms /* 70641502Swpaul * Get station address. The way the Rhine chips work, 70741502Swpaul * you're not allowed to directly access the EEPROM once 70841502Swpaul * they've been programmed a special way. Consequently, 70941502Swpaul * we need to read the node address from the PAR0 and PAR1 71041502Swpaul * registers. 711177050Syongari * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 712177050Syongari * VR_CFGC and VR_CFGD such that memory mapped IO configured 713177050Syongari * by driver is reset to default state. 71441502Swpaul */ 71541502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 716177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 717177050Syongari DELAY(1); 718177050Syongari if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 719177050Syongari break; 720177050Syongari } 721177050Syongari if (i == 0) 722177050Syongari device_printf(dev, "Reloading EEPROM timeout!\n"); 72341502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 72441502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 72541502Swpaul 726177050Syongari /* Reset the adapter. */ 727177050Syongari vr_reset(sc); 728177050Syongari /* Ack intr & disable further interrupts. */ 729177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 730177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 731177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A) 732177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 73351432Swpaul 734177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 735177050Syongari pci_write_config(dev, VR_PCI_MODE2, 736177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 737177050Syongari VR_MODE2_MODE10T, 1); 738177050Syongari } else { 739177050Syongari /* Report error instead of retrying forever. */ 740177050Syongari pci_write_config(dev, VR_PCI_MODE2, 741177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 742177050Syongari VR_MODE2_PCEROPT, 1); 743177050Syongari /* Detect MII coding error. */ 744177050Syongari pci_write_config(dev, VR_PCI_MODE3, 745177050Syongari pci_read_config(dev, VR_PCI_MODE3, 1) | 746177050Syongari VR_MODE3_MIION, 1); 747177050Syongari if (sc->vr_revid >= REV_ID_VT6105_LOM && 748177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 749177050Syongari pci_write_config(dev, VR_PCI_MODE2, 750177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 751177050Syongari VR_MODE2_MODE10T, 1); 752177050Syongari /* Enable Memory-Read-Multiple. */ 753177050Syongari if (sc->vr_revid >= REV_ID_VT6107_A1 && 754177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 755177050Syongari pci_write_config(dev, VR_PCI_MODE2, 756177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 757177050Syongari VR_MODE2_MRDPL, 1); 758177050Syongari } 759177050Syongari /* Disable MII AUTOPOLL. */ 760177050Syongari VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 761177050Syongari 762177050Syongari if (vr_dma_alloc(sc) != 0) { 76349610Swpaul error = ENXIO; 76449610Swpaul goto fail; 76541502Swpaul } 76641502Swpaul 767213893Smarius /* Do MII setup. */ 768177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) 769213893Smarius phy = 1; 770177050Syongari else 771213893Smarius phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 772213893Smarius error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 773213893Smarius vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 774213893Smarius if (error != 0) { 775213893Smarius device_printf(dev, "attaching PHYs failed\n"); 77641502Swpaul goto fail; 77741502Swpaul } 77841502Swpaul 779131503Sbms /* Call MI attach routine. */ 780106936Ssam ether_ifattach(ifp, eaddr); 781177050Syongari /* 782177050Syongari * Tell the upper layer(s) we support long frames. 783177050Syongari * Must appear after the call to ether_ifattach() because 784177050Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 785177050Syongari */ 786177050Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 78741502Swpaul 788177050Syongari /* Hook interrupt last to avoid having to lock softc. */ 789131518Sbms error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 790166901Spiso NULL, vr_intr, sc, &sc->vr_intrhand); 791112872Snjl 792112872Snjl if (error) { 793151773Sjhb device_printf(dev, "couldn't set up irq\n"); 794113609Snjl ether_ifdetach(ifp); 795112872Snjl goto fail; 796112872Snjl } 797112872Snjl 79841502Swpaulfail: 799112872Snjl if (error) 800112872Snjl vr_detach(dev); 80167087Swpaul 802131503Sbms return (error); 80341502Swpaul} 80441502Swpaul 805113609Snjl/* 806113609Snjl * Shutdown hardware and free up resources. This can be called any 807113609Snjl * time after the mutex has been initialized. It is called in both 808113609Snjl * the error case in attach and the normal detach case so it needs 809113609Snjl * to be careful about only freeing resources that have actually been 810113609Snjl * allocated. 811113609Snjl */ 812102336Salfredstatic int 813131503Sbmsvr_detach(device_t dev) 81449610Swpaul{ 815131503Sbms struct vr_softc *sc = device_get_softc(dev); 816147256Sbrooks struct ifnet *ifp = sc->vr_ifp; 81749610Swpaul 818112880Sjhb KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 819131518Sbms 820150789Sglebius#ifdef DEVICE_POLLING 821177050Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 822150789Sglebius ether_poll_deregister(ifp); 823150789Sglebius#endif 824150789Sglebius 825177050Syongari /* These should only be active if attach succeeded. */ 826113812Simp if (device_is_attached(dev)) { 827151911Sjhb VR_LOCK(sc); 828177050Syongari sc->vr_detach = 1; 829113609Snjl vr_stop(sc); 830151911Sjhb VR_UNLOCK(sc); 831151911Sjhb callout_drain(&sc->vr_stat_callout); 832112872Snjl ether_ifdetach(ifp); 833113609Snjl } 834113609Snjl if (sc->vr_miibus) 835112872Snjl device_delete_child(dev, sc->vr_miibus); 836113609Snjl bus_generic_detach(dev); 83749610Swpaul 838112872Snjl if (sc->vr_intrhand) 839112872Snjl bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 840112872Snjl if (sc->vr_irq) 841112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 842112872Snjl if (sc->vr_res) 843177050Syongari bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 844177050Syongari sc->vr_res); 84551432Swpaul 846151297Sru if (ifp) 847151297Sru if_free(ifp); 848151297Sru 849177050Syongari vr_dma_free(sc); 85049610Swpaul 85167087Swpaul mtx_destroy(&sc->vr_mtx); 85249610Swpaul 853131503Sbms return (0); 85449610Swpaul} 85549610Swpaul 856177050Syongaristruct vr_dmamap_arg { 857177050Syongari bus_addr_t vr_busaddr; 858177050Syongari}; 859177050Syongari 860177050Syongaristatic void 861177050Syongarivr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 862177050Syongari{ 863177050Syongari struct vr_dmamap_arg *ctx; 864177050Syongari 865177050Syongari if (error != 0) 866177050Syongari return; 867177050Syongari ctx = arg; 868177050Syongari ctx->vr_busaddr = segs[0].ds_addr; 869177050Syongari} 870177050Syongari 871177050Syongaristatic int 872177050Syongarivr_dma_alloc(struct vr_softc *sc) 873177050Syongari{ 874177050Syongari struct vr_dmamap_arg ctx; 875177050Syongari struct vr_txdesc *txd; 876177050Syongari struct vr_rxdesc *rxd; 877177050Syongari bus_size_t tx_alignment; 878177050Syongari int error, i; 879177050Syongari 880177050Syongari /* Create parent DMA tag. */ 881177050Syongari error = bus_dma_tag_create( 882177050Syongari bus_get_dma_tag(sc->vr_dev), /* parent */ 883177050Syongari 1, 0, /* alignment, boundary */ 884177050Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 885177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 886177050Syongari NULL, NULL, /* filter, filterarg */ 887177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 888177050Syongari 0, /* nsegments */ 889177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 890177050Syongari 0, /* flags */ 891177050Syongari NULL, NULL, /* lockfunc, lockarg */ 892177050Syongari &sc->vr_cdata.vr_parent_tag); 893177050Syongari if (error != 0) { 894177050Syongari device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 895177050Syongari goto fail; 896177050Syongari } 897177050Syongari /* Create tag for Tx ring. */ 898177050Syongari error = bus_dma_tag_create( 899177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 900177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 901177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 902177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 903177050Syongari NULL, NULL, /* filter, filterarg */ 904177050Syongari VR_TX_RING_SIZE, /* maxsize */ 905177050Syongari 1, /* nsegments */ 906177050Syongari VR_TX_RING_SIZE, /* maxsegsize */ 907177050Syongari 0, /* flags */ 908177050Syongari NULL, NULL, /* lockfunc, lockarg */ 909177050Syongari &sc->vr_cdata.vr_tx_ring_tag); 910177050Syongari if (error != 0) { 911177050Syongari device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 912177050Syongari goto fail; 913177050Syongari } 914177050Syongari 915177050Syongari /* Create tag for Rx ring. */ 916177050Syongari error = bus_dma_tag_create( 917177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 918177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 919177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 920177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 921177050Syongari NULL, NULL, /* filter, filterarg */ 922177050Syongari VR_RX_RING_SIZE, /* maxsize */ 923177050Syongari 1, /* nsegments */ 924177050Syongari VR_RX_RING_SIZE, /* maxsegsize */ 925177050Syongari 0, /* flags */ 926177050Syongari NULL, NULL, /* lockfunc, lockarg */ 927177050Syongari &sc->vr_cdata.vr_rx_ring_tag); 928177050Syongari if (error != 0) { 929177050Syongari device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 930177050Syongari goto fail; 931177050Syongari } 932177050Syongari 933177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 934177050Syongari tx_alignment = sizeof(uint32_t); 935177050Syongari else 936177050Syongari tx_alignment = 1; 937177050Syongari /* Create tag for Tx buffers. */ 938177050Syongari error = bus_dma_tag_create( 939177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 940177050Syongari tx_alignment, 0, /* alignment, boundary */ 941177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 942177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 943177050Syongari NULL, NULL, /* filter, filterarg */ 944177050Syongari MCLBYTES * VR_MAXFRAGS, /* maxsize */ 945177050Syongari VR_MAXFRAGS, /* nsegments */ 946177050Syongari MCLBYTES, /* maxsegsize */ 947177050Syongari 0, /* flags */ 948177050Syongari NULL, NULL, /* lockfunc, lockarg */ 949177050Syongari &sc->vr_cdata.vr_tx_tag); 950177050Syongari if (error != 0) { 951177050Syongari device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 952177050Syongari goto fail; 953177050Syongari } 954177050Syongari 955177050Syongari /* Create tag for Rx buffers. */ 956177050Syongari error = bus_dma_tag_create( 957177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 958177050Syongari VR_RX_ALIGN, 0, /* alignment, boundary */ 959177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 960177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 961177050Syongari NULL, NULL, /* filter, filterarg */ 962177050Syongari MCLBYTES, /* maxsize */ 963177050Syongari 1, /* nsegments */ 964177050Syongari MCLBYTES, /* maxsegsize */ 965177050Syongari 0, /* flags */ 966177050Syongari NULL, NULL, /* lockfunc, lockarg */ 967177050Syongari &sc->vr_cdata.vr_rx_tag); 968177050Syongari if (error != 0) { 969177050Syongari device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 970177050Syongari goto fail; 971177050Syongari } 972177050Syongari 973177050Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 974177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 975177050Syongari (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 976177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 977177050Syongari if (error != 0) { 978177050Syongari device_printf(sc->vr_dev, 979177050Syongari "failed to allocate DMA'able memory for Tx ring\n"); 980177050Syongari goto fail; 981177050Syongari } 982177050Syongari 983177050Syongari ctx.vr_busaddr = 0; 984177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 985177050Syongari sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 986177050Syongari VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 987177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 988177050Syongari device_printf(sc->vr_dev, 989177050Syongari "failed to load DMA'able memory for Tx ring\n"); 990177050Syongari goto fail; 991177050Syongari } 992177050Syongari sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 993177050Syongari 994177050Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 995177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 996177050Syongari (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 997177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 998177050Syongari if (error != 0) { 999177050Syongari device_printf(sc->vr_dev, 1000177050Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1001177050Syongari goto fail; 1002177050Syongari } 1003177050Syongari 1004177050Syongari ctx.vr_busaddr = 0; 1005177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1006177050Syongari sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1007177050Syongari VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1008177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1009177050Syongari device_printf(sc->vr_dev, 1010177050Syongari "failed to load DMA'able memory for Rx ring\n"); 1011177050Syongari goto fail; 1012177050Syongari } 1013177050Syongari sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1014177050Syongari 1015177050Syongari /* Create DMA maps for Tx buffers. */ 1016177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1017177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1018177050Syongari txd->tx_m = NULL; 1019177050Syongari txd->tx_dmamap = NULL; 1020177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1021177050Syongari &txd->tx_dmamap); 1022177050Syongari if (error != 0) { 1023177050Syongari device_printf(sc->vr_dev, 1024177050Syongari "failed to create Tx dmamap\n"); 1025177050Syongari goto fail; 1026177050Syongari } 1027177050Syongari } 1028177050Syongari /* Create DMA maps for Rx buffers. */ 1029177050Syongari if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1030177050Syongari &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1031177050Syongari device_printf(sc->vr_dev, 1032177050Syongari "failed to create spare Rx dmamap\n"); 1033177050Syongari goto fail; 1034177050Syongari } 1035177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1036177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1037177050Syongari rxd->rx_m = NULL; 1038177050Syongari rxd->rx_dmamap = NULL; 1039177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1040177050Syongari &rxd->rx_dmamap); 1041177050Syongari if (error != 0) { 1042177050Syongari device_printf(sc->vr_dev, 1043177050Syongari "failed to create Rx dmamap\n"); 1044177050Syongari goto fail; 1045177050Syongari } 1046177050Syongari } 1047177050Syongari 1048177050Syongarifail: 1049177050Syongari return (error); 1050177050Syongari} 1051177050Syongari 1052177050Syongaristatic void 1053177050Syongarivr_dma_free(struct vr_softc *sc) 1054177050Syongari{ 1055177050Syongari struct vr_txdesc *txd; 1056177050Syongari struct vr_rxdesc *rxd; 1057177050Syongari int i; 1058177050Syongari 1059177050Syongari /* Tx ring. */ 1060177050Syongari if (sc->vr_cdata.vr_tx_ring_tag) { 1061177050Syongari if (sc->vr_cdata.vr_tx_ring_map) 1062177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1063177050Syongari sc->vr_cdata.vr_tx_ring_map); 1064177050Syongari if (sc->vr_cdata.vr_tx_ring_map && 1065177050Syongari sc->vr_rdata.vr_tx_ring) 1066177050Syongari bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1067177050Syongari sc->vr_rdata.vr_tx_ring, 1068177050Syongari sc->vr_cdata.vr_tx_ring_map); 1069177050Syongari sc->vr_rdata.vr_tx_ring = NULL; 1070177050Syongari sc->vr_cdata.vr_tx_ring_map = NULL; 1071177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1072177050Syongari sc->vr_cdata.vr_tx_ring_tag = NULL; 1073177050Syongari } 1074177050Syongari /* Rx ring. */ 1075177050Syongari if (sc->vr_cdata.vr_rx_ring_tag) { 1076177050Syongari if (sc->vr_cdata.vr_rx_ring_map) 1077177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1078177050Syongari sc->vr_cdata.vr_rx_ring_map); 1079177050Syongari if (sc->vr_cdata.vr_rx_ring_map && 1080177050Syongari sc->vr_rdata.vr_rx_ring) 1081177050Syongari bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1082177050Syongari sc->vr_rdata.vr_rx_ring, 1083177050Syongari sc->vr_cdata.vr_rx_ring_map); 1084177050Syongari sc->vr_rdata.vr_rx_ring = NULL; 1085177050Syongari sc->vr_cdata.vr_rx_ring_map = NULL; 1086177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1087177050Syongari sc->vr_cdata.vr_rx_ring_tag = NULL; 1088177050Syongari } 1089177050Syongari /* Tx buffers. */ 1090177050Syongari if (sc->vr_cdata.vr_tx_tag) { 1091177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1092177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1093177050Syongari if (txd->tx_dmamap) { 1094177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1095177050Syongari txd->tx_dmamap); 1096177050Syongari txd->tx_dmamap = NULL; 1097177050Syongari } 1098177050Syongari } 1099177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1100177050Syongari sc->vr_cdata.vr_tx_tag = NULL; 1101177050Syongari } 1102177050Syongari /* Rx buffers. */ 1103177050Syongari if (sc->vr_cdata.vr_rx_tag) { 1104177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1105177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1106177050Syongari if (rxd->rx_dmamap) { 1107177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1108177050Syongari rxd->rx_dmamap); 1109177050Syongari rxd->rx_dmamap = NULL; 1110177050Syongari } 1111177050Syongari } 1112177050Syongari if (sc->vr_cdata.vr_rx_sparemap) { 1113177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1114177050Syongari sc->vr_cdata.vr_rx_sparemap); 1115177050Syongari sc->vr_cdata.vr_rx_sparemap = 0; 1116177050Syongari } 1117177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1118177050Syongari sc->vr_cdata.vr_rx_tag = NULL; 1119177050Syongari } 1120177050Syongari 1121177050Syongari if (sc->vr_cdata.vr_parent_tag) { 1122177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1123177050Syongari sc->vr_cdata.vr_parent_tag = NULL; 1124177050Syongari } 1125177050Syongari} 1126177050Syongari 112741502Swpaul/* 112841502Swpaul * Initialize the transmit descriptors. 112941502Swpaul */ 1130102336Salfredstatic int 1131177050Syongarivr_tx_ring_init(struct vr_softc *sc) 113241502Swpaul{ 1133177050Syongari struct vr_ring_data *rd; 1134177050Syongari struct vr_txdesc *txd; 1135177050Syongari bus_addr_t addr; 113641502Swpaul int i; 113741502Swpaul 1138177050Syongari sc->vr_cdata.vr_tx_prod = 0; 1139177050Syongari sc->vr_cdata.vr_tx_cons = 0; 1140177050Syongari sc->vr_cdata.vr_tx_cnt = 0; 1141177050Syongari sc->vr_cdata.vr_tx_pkts = 0; 1142177050Syongari 1143177050Syongari rd = &sc->vr_rdata; 1144177050Syongari bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1145177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1146177050Syongari if (i == VR_TX_RING_CNT - 1) 1147177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 1148177050Syongari else 1149177050Syongari addr = VR_TX_RING_ADDR(sc, i + 1); 1150177050Syongari rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1151177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1152177050Syongari txd->tx_m = NULL; 115341502Swpaul } 115441502Swpaul 1155177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1156177050Syongari sc->vr_cdata.vr_tx_ring_map, 1157177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1158177050Syongari 1159131503Sbms return (0); 116041502Swpaul} 116141502Swpaul 116241502Swpaul/* 116341502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 116441502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 116541502Swpaul * points back to the first. 116641502Swpaul */ 1167102336Salfredstatic int 1168177050Syongarivr_rx_ring_init(struct vr_softc *sc) 116941502Swpaul{ 1170177050Syongari struct vr_ring_data *rd; 1171177050Syongari struct vr_rxdesc *rxd; 1172177050Syongari bus_addr_t addr; 117341502Swpaul int i; 117441502Swpaul 1175177050Syongari sc->vr_cdata.vr_rx_cons = 0; 1176131518Sbms 1177177050Syongari rd = &sc->vr_rdata; 1178177050Syongari bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1179177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1180177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1181177050Syongari rxd->rx_m = NULL; 1182177050Syongari rxd->desc = &rd->vr_rx_ring[i]; 1183177050Syongari if (i == VR_RX_RING_CNT - 1) 1184177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 1185177050Syongari else 1186177050Syongari addr = VR_RX_RING_ADDR(sc, i + 1); 1187177050Syongari rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1188177050Syongari if (vr_newbuf(sc, i) != 0) 1189131503Sbms return (ENOBUFS); 119041502Swpaul } 119141502Swpaul 1192177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1193177050Syongari sc->vr_cdata.vr_rx_ring_map, 1194177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 119541502Swpaul 1196131503Sbms return (0); 119741502Swpaul} 119841502Swpaul 1199177050Syongaristatic __inline void 1200177050Syongarivr_discard_rxbuf(struct vr_rxdesc *rxd) 1201177050Syongari{ 1202177050Syongari struct vr_desc *desc; 1203177050Syongari 1204177050Syongari desc = rxd->desc; 1205177050Syongari desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1206177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 1207177050Syongari} 1208177050Syongari 120941502Swpaul/* 121041502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 121141502Swpaul * Note: the length fields are only 11 bits wide, which means the 121241502Swpaul * largest size we can specify is 2047. This is important because 121341502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 121441502Swpaul * overflow the field and make a mess. 121541502Swpaul */ 1216102336Salfredstatic int 1217177050Syongarivr_newbuf(struct vr_softc *sc, int idx) 121841502Swpaul{ 1219177050Syongari struct vr_desc *desc; 1220177050Syongari struct vr_rxdesc *rxd; 1221177050Syongari struct mbuf *m; 1222177050Syongari bus_dma_segment_t segs[1]; 1223177050Syongari bus_dmamap_t map; 1224177050Syongari int nsegs; 122541502Swpaul 1226177050Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1227177050Syongari if (m == NULL) 1228177050Syongari return (ENOBUFS); 1229177050Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 1230177050Syongari m_adj(m, sizeof(uint64_t)); 1231177050Syongari 1232177050Syongari if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1233177050Syongari sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1234177050Syongari m_freem(m); 1235177050Syongari return (ENOBUFS); 123641502Swpaul } 1237177050Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 123841502Swpaul 1239177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1240177050Syongari if (rxd->rx_m != NULL) { 1241177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1242177050Syongari BUS_DMASYNC_POSTREAD); 1243177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1244177050Syongari } 1245177050Syongari map = rxd->rx_dmamap; 1246177050Syongari rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1247177050Syongari sc->vr_cdata.vr_rx_sparemap = map; 1248177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1249177050Syongari BUS_DMASYNC_PREREAD); 1250177050Syongari rxd->rx_m = m; 1251177050Syongari desc = rxd->desc; 1252177050Syongari desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1253177050Syongari desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1254177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 125549610Swpaul 1256131503Sbms return (0); 125741502Swpaul} 125841502Swpaul 1259177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1260177050Syongaristatic __inline void 1261177050Syongarivr_fixup_rx(struct mbuf *m) 1262177050Syongari{ 1263177050Syongari uint16_t *src, *dst; 1264177050Syongari int i; 1265177050Syongari 1266177050Syongari src = mtod(m, uint16_t *); 1267177050Syongari dst = src - 1; 1268177050Syongari 1269177050Syongari for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1270177050Syongari *dst++ = *src++; 1271177050Syongari 1272177050Syongari m->m_data -= ETHER_ALIGN; 1273177050Syongari} 1274177050Syongari#endif 1275177050Syongari 127641502Swpaul/* 127741502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 127841502Swpaul * the higher level protocols. 127941502Swpaul */ 1280193096Sattiliostatic int 1281131503Sbmsvr_rxeof(struct vr_softc *sc) 128241502Swpaul{ 1283177050Syongari struct vr_rxdesc *rxd; 1284177050Syongari struct mbuf *m; 1285131503Sbms struct ifnet *ifp; 1286168952Sphk struct vr_desc *cur_rx; 1287193096Sattilio int cons, prog, total_len, rx_npkts; 1288168827Sphk uint32_t rxstat, rxctl; 128941502Swpaul 1290122689Ssam VR_LOCK_ASSERT(sc); 1291147256Sbrooks ifp = sc->vr_ifp; 1292177050Syongari cons = sc->vr_cdata.vr_rx_cons; 1293193096Sattilio rx_npkts = 0; 129441502Swpaul 1295177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1296177050Syongari sc->vr_cdata.vr_rx_ring_map, 1297177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1298177050Syongari 1299177050Syongari for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1300127901Sru#ifdef DEVICE_POLLING 1301150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1302127901Sru if (sc->rxcycles <= 0) 1303127901Sru break; 1304127901Sru sc->rxcycles--; 1305127901Sru } 1306150789Sglebius#endif 1307177050Syongari cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1308177050Syongari rxstat = le32toh(cur_rx->vr_status); 1309177050Syongari rxctl = le32toh(cur_rx->vr_ctl); 1310177050Syongari if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1311177050Syongari break; 131241502Swpaul 1313177050Syongari prog++; 1314177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1315177050Syongari m = rxd->rx_m; 1316177050Syongari 131741502Swpaul /* 131841502Swpaul * If an error occurs, update stats, clear the 131941502Swpaul * status word and leave the mbuf cluster in place: 132041502Swpaul * it should simply get re-used next time this descriptor 1321131503Sbms * comes up in the ring. 1322177050Syongari * We don't support SG in Rx path yet, so discard 1323177050Syongari * partial frame. 132441502Swpaul */ 1325180551Syongari if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1326180551Syongari (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1327177050Syongari (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 132841502Swpaul ifp->if_ierrors++; 1329177050Syongari sc->vr_stat.rx_errors++; 1330110131Ssilby if (rxstat & VR_RXSTAT_CRCERR) 1331177050Syongari sc->vr_stat.rx_crc_errors++; 1332110131Ssilby if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1333177050Syongari sc->vr_stat.rx_alignment++; 1334110131Ssilby if (rxstat & VR_RXSTAT_FIFOOFLOW) 1335177050Syongari sc->vr_stat.rx_fifo_overflows++; 1336110131Ssilby if (rxstat & VR_RXSTAT_GIANT) 1337177050Syongari sc->vr_stat.rx_giants++; 1338110131Ssilby if (rxstat & VR_RXSTAT_RUNT) 1339177050Syongari sc->vr_stat.rx_runts++; 1340110131Ssilby if (rxstat & VR_RXSTAT_BUFFERR) 1341177050Syongari sc->vr_stat.rx_no_buffers++; 1342177050Syongari#ifdef VR_SHOW_ERRORS 1343177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1344177050Syongari __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1345177050Syongari#endif 1346177050Syongari vr_discard_rxbuf(rxd); 134741502Swpaul continue; 134841502Swpaul } 134941502Swpaul 1350177050Syongari if (vr_newbuf(sc, cons) != 0) { 1351177050Syongari ifp->if_iqdrops++; 1352177050Syongari sc->vr_stat.rx_errors++; 1353177050Syongari sc->vr_stat.rx_no_mbufs++; 1354177050Syongari vr_discard_rxbuf(rxd); 1355177050Syongari continue; 1356168827Sphk } 135741502Swpaul 135841502Swpaul /* 135942048Swpaul * XXX The VIA Rhine chip includes the CRC with every 136042048Swpaul * received frame, and there's no way to turn this 136142048Swpaul * behavior off (at least, I can't find anything in 1362131503Sbms * the manual that explains how to do it) so we have 136342048Swpaul * to trim off the CRC manually. 136442048Swpaul */ 1365177050Syongari total_len = VR_RXBYTES(rxstat); 136642048Swpaul total_len -= ETHER_CRC_LEN; 1367177050Syongari m->m_pkthdr.len = m->m_len = total_len; 1368177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1369177050Syongari /* 1370177050Syongari * RX buffers must be 32-bit aligned. 1371177050Syongari * Ignore the alignment problems on the non-strict alignment 1372177050Syongari * platform. The performance hit incurred due to unaligned 1373177050Syongari * accesses is much smaller than the hit produced by forcing 1374177050Syongari * buffer copies all the time. 1375177050Syongari */ 1376177050Syongari vr_fixup_rx(m); 1377177050Syongari#endif 1378177050Syongari m->m_pkthdr.rcvif = ifp; 1379177050Syongari ifp->if_ipackets++; 1380177050Syongari sc->vr_stat.rx_ok++; 1381177050Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1382177050Syongari (rxstat & VR_RXSTAT_FRAG) == 0 && 1383177050Syongari (rxctl & VR_RXCTL_IP) != 0) { 1384177050Syongari /* Checksum is valid for non-fragmented IP packets. */ 1385177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1386177050Syongari if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1387177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1388177050Syongari if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1389177050Syongari m->m_pkthdr.csum_flags |= 1390177050Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1391177050Syongari if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1392177050Syongari m->m_pkthdr.csum_data = 0xffff; 1393177050Syongari } 1394177050Syongari } 139541502Swpaul } 1396122689Ssam VR_UNLOCK(sc); 1397106936Ssam (*ifp->if_input)(ifp, m); 1398122689Ssam VR_LOCK(sc); 1399193096Sattilio rx_npkts++; 140041502Swpaul } 140141502Swpaul 1402177050Syongari if (prog > 0) { 1403177050Syongari sc->vr_cdata.vr_rx_cons = cons; 1404177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1405177050Syongari sc->vr_cdata.vr_rx_ring_map, 1406177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1407131503Sbms } 1408193096Sattilio return (rx_npkts); 140941502Swpaul} 141041502Swpaul 141141502Swpaul/* 141241502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 141341502Swpaul * the list buffers. 141441502Swpaul */ 1415102336Salfredstatic void 1416131503Sbmsvr_txeof(struct vr_softc *sc) 141741502Swpaul{ 1418177050Syongari struct vr_txdesc *txd; 1419168952Sphk struct vr_desc *cur_tx; 1420177050Syongari struct ifnet *ifp; 1421177050Syongari uint32_t txctl, txstat; 1422177050Syongari int cons, prod; 142341502Swpaul 1424131518Sbms VR_LOCK_ASSERT(sc); 142541502Swpaul 1426177050Syongari cons = sc->vr_cdata.vr_tx_cons; 1427177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1428177050Syongari if (cons == prod) 1429177050Syongari return; 1430177050Syongari 1431177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1432177050Syongari sc->vr_cdata.vr_tx_ring_map, 1433177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1434177050Syongari 1435177050Syongari ifp = sc->vr_ifp; 143641502Swpaul /* 143741502Swpaul * Go through our tx list and free mbufs for those 143841502Swpaul * frames that have been transmitted. 143941502Swpaul */ 1440177050Syongari for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1441177050Syongari cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1442177050Syongari txctl = le32toh(cur_tx->vr_ctl); 1443177050Syongari txstat = le32toh(cur_tx->vr_status); 1444177050Syongari if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1445177050Syongari break; 144641502Swpaul 1447177050Syongari sc->vr_cdata.vr_tx_cnt--; 1448177050Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1449177050Syongari /* Only the first descriptor in the chain is valid. */ 1450177050Syongari if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1451177050Syongari continue; 145241502Swpaul 1453177050Syongari txd = &sc->vr_cdata.vr_txdesc[cons]; 1454177050Syongari KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1455177050Syongari __func__)); 1456177050Syongari 1457177050Syongari if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1458177050Syongari ifp->if_oerrors++; 1459177050Syongari sc->vr_stat.tx_errors++; 1460177050Syongari if ((txstat & VR_TXSTAT_ABRT) != 0) { 1461177050Syongari /* Give up and restart Tx. */ 1462177050Syongari sc->vr_stat.tx_abort++; 1463177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1464177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1465177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1466177050Syongari txd->tx_dmamap); 1467177050Syongari m_freem(txd->tx_m); 1468177050Syongari txd->tx_m = NULL; 1469177050Syongari VR_INC(cons, VR_TX_RING_CNT); 1470177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1471177050Syongari if (vr_tx_stop(sc) != 0) { 1472177050Syongari device_printf(sc->vr_dev, 1473177050Syongari "%s: Tx shutdown error -- " 1474177050Syongari "resetting\n", __func__); 1475177050Syongari sc->vr_flags |= VR_F_RESTART; 1476177050Syongari return; 1477177050Syongari } 1478177050Syongari vr_tx_start(sc); 1479110131Ssilby break; 1480110131Ssilby } 1481177050Syongari if ((sc->vr_revid < REV_ID_VT3071_A && 1482177050Syongari (txstat & VR_TXSTAT_UNDERRUN)) || 1483177050Syongari (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1484177050Syongari sc->vr_stat.tx_underrun++; 1485177050Syongari /* Retry and restart Tx. */ 1486177050Syongari sc->vr_cdata.vr_tx_cnt++; 1487177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1488177050Syongari cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1489177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1490177050Syongari sc->vr_cdata.vr_tx_ring_map, 1491177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1492177050Syongari vr_tx_underrun(sc); 1493177050Syongari return; 1494177050Syongari } 1495177050Syongari if ((txstat & VR_TXSTAT_DEFER) != 0) { 149641502Swpaul ifp->if_collisions++; 1497177050Syongari sc->vr_stat.tx_collisions++; 1498177050Syongari } 1499177050Syongari if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 150041502Swpaul ifp->if_collisions++; 1501177050Syongari sc->vr_stat.tx_late_collisions++; 1502177050Syongari } 1503177050Syongari } else { 1504177050Syongari sc->vr_stat.tx_ok++; 1505177050Syongari ifp->if_opackets++; 150641502Swpaul } 150741502Swpaul 1508177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1509177050Syongari BUS_DMASYNC_POSTWRITE); 1510177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1511177050Syongari if (sc->vr_revid < REV_ID_VT3071_A) { 1512177050Syongari ifp->if_collisions += 1513177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1514177050Syongari sc->vr_stat.tx_collisions += 1515177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1516177050Syongari } else { 1517177050Syongari ifp->if_collisions += (txstat & 0x0f); 1518177050Syongari sc->vr_stat.tx_collisions += (txstat & 0x0f); 1519177050Syongari } 1520177050Syongari m_freem(txd->tx_m); 1521177050Syongari txd->tx_m = NULL; 1522177050Syongari } 152341502Swpaul 1524177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1525177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 1526177050Syongari sc->vr_watchdog_timer = 0; 152741502Swpaul} 152841502Swpaul 1529102336Salfredstatic void 1530131503Sbmsvr_tick(void *xsc) 153151432Swpaul{ 1532177050Syongari struct vr_softc *sc; 153351432Swpaul struct mii_data *mii; 153451432Swpaul 1535177050Syongari sc = (struct vr_softc *)xsc; 1536177050Syongari 1537151911Sjhb VR_LOCK_ASSERT(sc); 1538131517Sbms 1539177050Syongari if ((sc->vr_flags & VR_F_RESTART) != 0) { 1540162315Sglebius device_printf(sc->vr_dev, "restarting\n"); 1541177050Syongari sc->vr_stat.num_restart++; 1542211765Syongari sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1543131844Sbms vr_init_locked(sc); 1544110131Ssilby sc->vr_flags &= ~VR_F_RESTART; 1545110131Ssilby } 1546110131Ssilby 154751432Swpaul mii = device_get_softc(sc->vr_miibus); 154851432Swpaul mii_tick(mii); 1549223405Syongari if (sc->vr_link == 0) 1550223405Syongari vr_miibus_statchg(sc->vr_dev); 1551177050Syongari vr_watchdog(sc); 1552151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 155351432Swpaul} 155451432Swpaul 1555127901Sru#ifdef DEVICE_POLLING 1556127901Srustatic poll_handler_t vr_poll; 1557131844Sbmsstatic poll_handler_t vr_poll_locked; 1558127901Sru 1559193096Sattiliostatic int 1560127901Sruvr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1561127901Sru{ 1562177050Syongari struct vr_softc *sc; 1563193096Sattilio int rx_npkts; 1564127901Sru 1565177050Syongari sc = ifp->if_softc; 1566193096Sattilio rx_npkts = 0; 1567177050Syongari 1568127901Sru VR_LOCK(sc); 1569177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1570193096Sattilio rx_npkts = vr_poll_locked(ifp, cmd, count); 1571131844Sbms VR_UNLOCK(sc); 1572193096Sattilio return (rx_npkts); 1573131844Sbms} 1574131517Sbms 1575193096Sattiliostatic int 1576131844Sbmsvr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1577131844Sbms{ 1578177050Syongari struct vr_softc *sc; 1579193096Sattilio int rx_npkts; 1580131844Sbms 1581177050Syongari sc = ifp->if_softc; 1582177050Syongari 1583131844Sbms VR_LOCK_ASSERT(sc); 1584131844Sbms 1585127901Sru sc->rxcycles = count; 1586193096Sattilio rx_npkts = vr_rxeof(sc); 1587127901Sru vr_txeof(sc); 1588133006Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1589131844Sbms vr_start_locked(ifp); 1590127901Sru 1591131503Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1592131503Sbms uint16_t status; 1593127901Sru 1594131503Sbms /* Also check status register. */ 1595127901Sru status = CSR_READ_2(sc, VR_ISR); 1596127901Sru if (status) 1597127901Sru CSR_WRITE_2(sc, VR_ISR, status); 1598127901Sru 1599127901Sru if ((status & VR_INTRS) == 0) 1600193096Sattilio return (rx_npkts); 1601127901Sru 1602177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1603177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1604177050Syongari if (vr_error(sc, status) != 0) 1605193096Sattilio return (rx_npkts); 1606127901Sru } 1607177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1608177050Syongari#ifdef VR_SHOW_ERRORS 1609177050Syongari device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1610177050Syongari __func__, status, VR_ISR_ERR_BITS); 1611177050Syongari#endif 1612177050Syongari vr_rx_start(sc); 1613127901Sru } 1614177050Syongari } 1615193096Sattilio return (rx_npkts); 1616177050Syongari} 1617177050Syongari#endif /* DEVICE_POLLING */ 1618127901Sru 1619177050Syongari/* Back off the transmit threshold. */ 1620177050Syongaristatic void 1621177050Syongarivr_tx_underrun(struct vr_softc *sc) 1622177050Syongari{ 1623177050Syongari int thresh; 1624127901Sru 1625177050Syongari device_printf(sc->vr_dev, "Tx underrun -- "); 1626177050Syongari if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1627177050Syongari thresh = sc->vr_txthresh; 1628177050Syongari sc->vr_txthresh++; 1629177050Syongari if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1630177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 1631177050Syongari printf("using store and forward mode\n"); 1632177050Syongari } else 1633177050Syongari printf("increasing Tx threshold(%d -> %d)\n", 1634177050Syongari vr_tx_threshold_tables[thresh].value, 1635177050Syongari vr_tx_threshold_tables[thresh + 1].value); 1636177050Syongari } else 1637177050Syongari printf("\n"); 1638177050Syongari sc->vr_stat.tx_underrun++; 1639177050Syongari if (vr_tx_stop(sc) != 0) { 1640177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1641177050Syongari "resetting\n", __func__); 1642177050Syongari sc->vr_flags |= VR_F_RESTART; 1643177050Syongari return; 1644127901Sru } 1645177050Syongari vr_tx_start(sc); 1646127901Sru} 1647127901Sru 1648127901Srustatic void 1649131503Sbmsvr_intr(void *arg) 165041502Swpaul{ 1651177050Syongari struct vr_softc *sc; 1652177050Syongari struct ifnet *ifp; 1653131503Sbms uint16_t status; 165441502Swpaul 1655177050Syongari sc = (struct vr_softc *)arg; 1656177050Syongari 165767087Swpaul VR_LOCK(sc); 1658131844Sbms 1659177050Syongari if (sc->vr_suspended != 0) 1660131844Sbms goto done_locked; 1661131844Sbms 1662177050Syongari status = CSR_READ_2(sc, VR_ISR); 1663177050Syongari if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1664177050Syongari goto done_locked; 1665177050Syongari 1666177050Syongari ifp = sc->vr_ifp; 1667127901Sru#ifdef DEVICE_POLLING 1668177050Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1669131844Sbms goto done_locked; 1670150789Sglebius#endif 1671131844Sbms 1672131844Sbms /* Suppress unwanted interrupts. */ 1673177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1674177050Syongari (sc->vr_flags & VR_F_RESTART) != 0) { 1675177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1676177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1677131844Sbms goto done_locked; 167841502Swpaul } 167941502Swpaul 168041502Swpaul /* Disable interrupts. */ 168141502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 168241502Swpaul 1683177050Syongari for (; (status & VR_INTRS) != 0;) { 1684177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1685177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1686177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1687177050Syongari if (vr_error(sc, status) != 0) { 1688177050Syongari VR_UNLOCK(sc); 1689177050Syongari return; 1690177050Syongari } 1691177050Syongari } 1692177050Syongari vr_rxeof(sc); 1693177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1694177050Syongari#ifdef VR_SHOW_ERRORS 1695177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1696177050Syongari __func__, status, VR_ISR_ERR_BITS); 1697177050Syongari#endif 1698177050Syongari /* Restart Rx if RxDMA SM was stopped. */ 1699177050Syongari vr_rx_start(sc); 1700177050Syongari } 1701177050Syongari vr_txeof(sc); 170241502Swpaul status = CSR_READ_2(sc, VR_ISR); 1703177050Syongari } 1704168813Sphk 1705177050Syongari /* Re-enable interrupts. */ 1706177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 170741502Swpaul 1708177050Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1709177050Syongari vr_start_locked(ifp); 171041502Swpaul 1711177050Syongaridone_locked: 1712177050Syongari VR_UNLOCK(sc); 1713177050Syongari} 171441502Swpaul 1715177050Syongaristatic int 1716177050Syongarivr_error(struct vr_softc *sc, uint16_t status) 1717177050Syongari{ 1718177050Syongari uint16_t pcis; 1719110131Ssilby 1720177050Syongari status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1721177050Syongari if ((status & VR_ISR_BUSERR) != 0) { 1722177050Syongari status &= ~VR_ISR_BUSERR; 1723177050Syongari sc->vr_stat.bus_errors++; 1724177050Syongari /* Disable further interrupts. */ 1725177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1726177050Syongari pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1727177050Syongari device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1728177050Syongari "resetting\n", pcis); 1729177050Syongari pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1730177050Syongari sc->vr_flags |= VR_F_RESTART; 1731177050Syongari return (EAGAIN); 1732177050Syongari } 1733177050Syongari if ((status & VR_ISR_LINKSTAT2) != 0) { 1734177050Syongari /* Link state change, duplex changes etc. */ 1735177050Syongari status &= ~VR_ISR_LINKSTAT2; 1736177050Syongari } 1737177050Syongari if ((status & VR_ISR_STATSOFLOW) != 0) { 1738177050Syongari status &= ~VR_ISR_STATSOFLOW; 1739177050Syongari if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1740177050Syongari /* Update MIB counters. */ 174141502Swpaul } 1742177050Syongari } 174341502Swpaul 1744177050Syongari if (status != 0) 1745177050Syongari device_printf(sc->vr_dev, 1746177050Syongari "unhandled interrupt, status = 0x%04x\n", status); 1747177050Syongari return (0); 1748177050Syongari} 1749177050Syongari 1750177050Syongari/* 1751177050Syongari * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1752177050Syongari * pointers to the fragment pointers. 1753177050Syongari */ 1754177050Syongaristatic int 1755177050Syongarivr_encap(struct vr_softc *sc, struct mbuf **m_head) 1756177050Syongari{ 1757177050Syongari struct vr_txdesc *txd; 1758177050Syongari struct vr_desc *desc; 1759177050Syongari struct mbuf *m; 1760177050Syongari bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1761177050Syongari uint32_t csum_flags, txctl; 1762177050Syongari int error, i, nsegs, prod, si; 1763177050Syongari int padlen; 1764177050Syongari 1765177050Syongari VR_LOCK_ASSERT(sc); 1766177050Syongari 1767177050Syongari M_ASSERTPKTHDR((*m_head)); 1768177050Syongari 1769177050Syongari /* 1770177050Syongari * Some VIA Rhine wants packet buffers to be longword 1771177050Syongari * aligned, but very often our mbufs aren't. Rather than 1772177050Syongari * waste time trying to decide when to copy and when not 1773177050Syongari * to copy, just do it all the time. 1774177050Syongari */ 1775177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1776177050Syongari m = m_defrag(*m_head, M_DONTWAIT); 1777177050Syongari if (m == NULL) { 1778177050Syongari m_freem(*m_head); 1779177050Syongari *m_head = NULL; 1780177050Syongari return (ENOBUFS); 178141502Swpaul } 1782177050Syongari *m_head = m; 1783177050Syongari } 178441502Swpaul 1785177050Syongari /* 1786177050Syongari * The Rhine chip doesn't auto-pad, so we have to make 1787177050Syongari * sure to pad short frames out to the minimum frame length 1788177050Syongari * ourselves. 1789177050Syongari */ 1790177050Syongari if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1791177050Syongari m = *m_head; 1792177050Syongari padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1793177050Syongari if (M_WRITABLE(m) == 0) { 1794177050Syongari /* Get a writable copy. */ 1795177050Syongari m = m_dup(*m_head, M_DONTWAIT); 1796177050Syongari m_freem(*m_head); 1797177050Syongari if (m == NULL) { 1798177050Syongari *m_head = NULL; 1799177050Syongari return (ENOBUFS); 1800127901Sru } 1801177050Syongari *m_head = m; 180241502Swpaul } 1803177050Syongari if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1804177050Syongari m = m_defrag(m, M_DONTWAIT); 1805177050Syongari if (m == NULL) { 1806177050Syongari m_freem(*m_head); 1807177050Syongari *m_head = NULL; 1808177050Syongari return (ENOBUFS); 1809177050Syongari } 1810177050Syongari } 1811177050Syongari /* 1812177050Syongari * Manually pad short frames, and zero the pad space 1813177050Syongari * to avoid leaking data. 1814177050Syongari */ 1815177050Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1816177050Syongari m->m_pkthdr.len += padlen; 1817177050Syongari m->m_len = m->m_pkthdr.len; 1818177050Syongari *m_head = m; 181941502Swpaul } 182041502Swpaul 1821177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1822177050Syongari txd = &sc->vr_cdata.vr_txdesc[prod]; 1823177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1824177050Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1825177050Syongari if (error == EFBIG) { 1826177050Syongari m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1827177050Syongari if (m == NULL) { 1828177050Syongari m_freem(*m_head); 1829177050Syongari *m_head = NULL; 1830177050Syongari return (ENOBUFS); 1831177050Syongari } 1832177050Syongari *m_head = m; 1833177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1834177050Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1835177050Syongari if (error != 0) { 1836177050Syongari m_freem(*m_head); 1837177050Syongari *m_head = NULL; 1838177050Syongari return (error); 1839177050Syongari } 1840177050Syongari } else if (error != 0) 1841177050Syongari return (error); 1842177050Syongari if (nsegs == 0) { 1843177050Syongari m_freem(*m_head); 1844177050Syongari *m_head = NULL; 1845177050Syongari return (EIO); 1846177050Syongari } 184741502Swpaul 1848177050Syongari /* Check number of available descriptors. */ 1849177050Syongari if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1850177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1851177050Syongari return (ENOBUFS); 1852177050Syongari } 1853131844Sbms 1854177050Syongari txd->tx_m = *m_head; 1855177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1856177050Syongari BUS_DMASYNC_PREWRITE); 1857177050Syongari 1858177050Syongari /* Set checksum offload. */ 1859177050Syongari csum_flags = 0; 1860177050Syongari if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1861177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1862177050Syongari csum_flags |= VR_TXCTL_IPCSUM; 1863177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1864177050Syongari csum_flags |= VR_TXCTL_TCPCSUM; 1865177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1866177050Syongari csum_flags |= VR_TXCTL_UDPCSUM; 1867177050Syongari } 1868177050Syongari 1869177050Syongari /* 1870177050Syongari * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1871177050Syongari * is required for all descriptors regardless of single or 1872177050Syongari * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1873177050Syongari * the first descriptor for a multi-fragmented frames. Without 1874177050Syongari * that VIA Rhine chip generates Tx underrun interrupts and can't 1875177050Syongari * send any frames. 1876177050Syongari */ 1877177050Syongari si = prod; 1878177050Syongari for (i = 0; i < nsegs; i++) { 1879177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1880177050Syongari desc->vr_status = 0; 1881177050Syongari txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1882177050Syongari if (i == 0) 1883177050Syongari txctl |= VR_TXCTL_FIRSTFRAG; 1884177050Syongari desc->vr_ctl = htole32(txctl); 1885177050Syongari desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1886177050Syongari sc->vr_cdata.vr_tx_cnt++; 1887177050Syongari VR_INC(prod, VR_TX_RING_CNT); 1888177050Syongari } 1889177050Syongari /* Update producer index. */ 1890177050Syongari sc->vr_cdata.vr_tx_prod = prod; 1891177050Syongari 1892177050Syongari prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1893177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1894177050Syongari 1895177050Syongari /* 1896177050Syongari * Set EOP on the last desciptor and reuqest Tx completion 1897177050Syongari * interrupt for every VR_TX_INTR_THRESH-th frames. 1898177050Syongari */ 1899177050Syongari VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1900177050Syongari if (sc->vr_cdata.vr_tx_pkts == 0) 1901177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1902177050Syongari else 1903177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1904177050Syongari 1905177050Syongari /* Lastly turn the first descriptor ownership to hardware. */ 1906177050Syongari desc = &sc->vr_rdata.vr_tx_ring[si]; 1907177050Syongari desc->vr_status |= htole32(VR_TXSTAT_OWN); 1908177050Syongari 1909177050Syongari /* Sync descriptors. */ 1910177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1911177050Syongari sc->vr_cdata.vr_tx_ring_map, 1912177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1913177050Syongari 1914177050Syongari return (0); 191541502Swpaul} 191641502Swpaul 1917102336Salfredstatic void 1918131503Sbmsvr_start(struct ifnet *ifp) 191941502Swpaul{ 1920177050Syongari struct vr_softc *sc; 1921131844Sbms 1922177050Syongari sc = ifp->if_softc; 1923131844Sbms VR_LOCK(sc); 1924131844Sbms vr_start_locked(ifp); 1925131844Sbms VR_UNLOCK(sc); 1926131844Sbms} 1927131844Sbms 1928131844Sbmsstatic void 1929131844Sbmsvr_start_locked(struct ifnet *ifp) 1930131844Sbms{ 1931177050Syongari struct vr_softc *sc; 1932177050Syongari struct mbuf *m_head; 1933177050Syongari int enq; 193441502Swpaul 1935177050Syongari sc = ifp->if_softc; 1936177050Syongari 1937177050Syongari VR_LOCK_ASSERT(sc); 1938177050Syongari 1939177050Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1940177050Syongari IFF_DRV_RUNNING || sc->vr_link == 0) 1941127901Sru return; 1942127901Sru 1943177050Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1944177050Syongari sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1945177050Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 194641502Swpaul if (m_head == NULL) 194741502Swpaul break; 1948168813Sphk /* 1949177050Syongari * Pack the data into the transmit ring. If we 1950177050Syongari * don't have room, set the OACTIVE flag and wait 1951177050Syongari * for the NIC to drain the ring. 1952168813Sphk */ 1953177050Syongari if (vr_encap(sc, &m_head)) { 1954177050Syongari if (m_head == NULL) 1955168813Sphk break; 1956177050Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1957177050Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1958177050Syongari break; 1959168813Sphk } 196051583Swpaul 1961177050Syongari enq++; 1962168813Sphk /* 1963168813Sphk * If there's a BPF listener, bounce a copy of this frame 1964168813Sphk * to him. 1965168813Sphk */ 1966177050Syongari ETHER_BPF_MTAP(ifp, m_head); 1967127901Sru } 1968177050Syongari 1969177050Syongari if (enq > 0) { 1970177050Syongari /* Tell the chip to start transmitting. */ 1971177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1972177050Syongari /* Set a timeout in case the chip goes out to lunch. */ 1973177050Syongari sc->vr_watchdog_timer = 5; 1974177050Syongari } 1975131844Sbms} 197641502Swpaul 1977131844Sbmsstatic void 1978131844Sbmsvr_init(void *xsc) 1979131844Sbms{ 1980177050Syongari struct vr_softc *sc; 1981131844Sbms 1982177050Syongari sc = (struct vr_softc *)xsc; 1983131844Sbms VR_LOCK(sc); 1984131844Sbms vr_init_locked(sc); 198567087Swpaul VR_UNLOCK(sc); 198641502Swpaul} 198741502Swpaul 1988102336Salfredstatic void 1989131844Sbmsvr_init_locked(struct vr_softc *sc) 199041502Swpaul{ 1991177050Syongari struct ifnet *ifp; 199251432Swpaul struct mii_data *mii; 1993177050Syongari bus_addr_t addr; 199473963Swpaul int i; 199541502Swpaul 1996131844Sbms VR_LOCK_ASSERT(sc); 199741502Swpaul 1998177050Syongari ifp = sc->vr_ifp; 199951432Swpaul mii = device_get_softc(sc->vr_miibus); 200041502Swpaul 2001211765Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2002211765Syongari return; 2003211765Syongari 2004131503Sbms /* Cancel pending I/O and free all RX/TX buffers. */ 200541502Swpaul vr_stop(sc); 200641502Swpaul vr_reset(sc); 200741502Swpaul 2008131503Sbms /* Set our station address. */ 200973963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 2010152315Sru CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2011131503Sbms 2012131503Sbms /* Set DMA size. */ 2013101375Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2014101375Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 201573963Swpaul 2016131503Sbms /* 2017101375Ssilby * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2018101108Ssilby * so we must set both. 2019101108Ssilby */ 2020101108Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2021110131Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2022101108Ssilby 2023101108Ssilby VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2024177050Syongari VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2025101108Ssilby 202641502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2027110131Ssilby VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 202841502Swpaul 202941502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2030177050Syongari VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 203141502Swpaul 203241502Swpaul /* Init circular RX list. */ 2033177050Syongari if (vr_rx_ring_init(sc) != 0) { 2034162315Sglebius device_printf(sc->vr_dev, 2035151773Sjhb "initialization failed: no memory for rx buffers\n"); 203641502Swpaul vr_stop(sc); 203741502Swpaul return; 203841502Swpaul } 203941502Swpaul 2040131503Sbms /* Init tx descriptors. */ 2041177050Syongari vr_tx_ring_init(sc); 204241502Swpaul 2043177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2044180552Syongari uint8_t vcam[2] = { 0, 0 }; 2045180552Syongari 2046180552Syongari /* Disable VLAN hardware tag insertion/stripping. */ 2047180552Syongari VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2048180552Syongari /* Disable VLAN hardware filtering. */ 2049180552Syongari VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2050180552Syongari /* Disable all CAM entries. */ 2051180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, 0); 2052180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 0); 2053180552Syongari /* Enable the first VLAN CAM. */ 2054180552Syongari vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2055180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 1); 2056177050Syongari } 205741502Swpaul 205841502Swpaul /* 2059177050Syongari * Set up receive filter. 206041502Swpaul */ 2061177050Syongari vr_set_filter(sc); 206241502Swpaul 206341502Swpaul /* 2064177050Syongari * Load the address of the RX ring. 206541502Swpaul */ 2066177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 2067177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2068177050Syongari /* 2069177050Syongari * Load the address of the TX ring. 2070177050Syongari */ 2071177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 2072177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2073177050Syongari /* Default : full-duplex, no Tx poll. */ 2074177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 207541502Swpaul 2076177050Syongari /* Set flow-control parameters for Rhine III. */ 2077177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 2078177050Syongari /* Rx buffer count available for incoming packet. */ 2079177050Syongari CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT); 2080177050Syongari /* 2081177050Syongari * Tx pause low threshold : 16 free receive buffers 2082177050Syongari * Tx pause XON high threshold : 48 free receive buffers 2083177050Syongari */ 2084177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, 2085177050Syongari VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF); 2086177050Syongari /* Set Tx pause timer. */ 2087177050Syongari CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2088177050Syongari } 2089177050Syongari 209041502Swpaul /* Enable receiver and transmitter. */ 2091177050Syongari CSR_WRITE_1(sc, VR_CR0, 2092177050Syongari VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 209341502Swpaul 2094127901Sru CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2095127901Sru#ifdef DEVICE_POLLING 209641502Swpaul /* 2097127901Sru * Disable interrupts if we are polling. 2098127901Sru */ 2099150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 2100127901Sru CSR_WRITE_2(sc, VR_IMR, 0); 2101131503Sbms else 2102150789Sglebius#endif 2103127901Sru /* 2104177050Syongari * Enable interrupts and disable MII intrs. 210541502Swpaul */ 210641502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2107177050Syongari if (sc->vr_revid > REV_ID_VT6102_A) 2108177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 210941502Swpaul 2110177050Syongari sc->vr_link = 0; 211151432Swpaul mii_mediachg(mii); 211241502Swpaul 2113148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2114148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 211541502Swpaul 2116151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 211741502Swpaul} 211841502Swpaul 211941502Swpaul/* 212041502Swpaul * Set media options. 212141502Swpaul */ 2122102336Salfredstatic int 2123131503Sbmsvr_ifmedia_upd(struct ifnet *ifp) 212441502Swpaul{ 2125177050Syongari struct vr_softc *sc; 2126177050Syongari struct mii_data *mii; 2127177050Syongari struct mii_softc *miisc; 2128177050Syongari int error; 212941502Swpaul 2130177050Syongari sc = ifp->if_softc; 2131177050Syongari VR_LOCK(sc); 2132177050Syongari mii = device_get_softc(sc->vr_miibus); 2133221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2134221407Smarius PHY_RESET(miisc); 2135177050Syongari error = mii_mediachg(mii); 2136177050Syongari VR_UNLOCK(sc); 213741502Swpaul 2138177050Syongari return (error); 213941502Swpaul} 214041502Swpaul 214141502Swpaul/* 214241502Swpaul * Report current media status. 214341502Swpaul */ 2144102336Salfredstatic void 2145131503Sbmsvr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 214641502Swpaul{ 2147177050Syongari struct vr_softc *sc; 214851432Swpaul struct mii_data *mii; 214941502Swpaul 2150177050Syongari sc = ifp->if_softc; 215151432Swpaul mii = device_get_softc(sc->vr_miibus); 2152133468Sscottl VR_LOCK(sc); 2153223405Syongari if ((ifp->if_flags & IFF_UP) == 0) { 2154223405Syongari VR_UNLOCK(sc); 2155223405Syongari return; 2156223405Syongari } 215751432Swpaul mii_pollstat(mii); 215851432Swpaul ifmr->ifm_active = mii->mii_media_active; 215951432Swpaul ifmr->ifm_status = mii->mii_media_status; 2160226478Syongari VR_UNLOCK(sc); 216141502Swpaul} 216241502Swpaul 2163102336Salfredstatic int 2164131503Sbmsvr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 216541502Swpaul{ 2166177050Syongari struct vr_softc *sc; 2167177050Syongari struct ifreq *ifr; 216851432Swpaul struct mii_data *mii; 2169177050Syongari int error, mask; 217041502Swpaul 2171177050Syongari sc = ifp->if_softc; 2172177050Syongari ifr = (struct ifreq *)data; 2173177050Syongari error = 0; 2174177050Syongari 2175131503Sbms switch (command) { 217641502Swpaul case SIOCSIFFLAGS: 2177131844Sbms VR_LOCK(sc); 217841502Swpaul if (ifp->if_flags & IFF_UP) { 2179177050Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2180177050Syongari if ((ifp->if_flags ^ sc->vr_if_flags) & 2181177050Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2182177050Syongari vr_set_filter(sc); 2183177050Syongari } else { 2184177050Syongari if (sc->vr_detach == 0) 2185177050Syongari vr_init_locked(sc); 2186177050Syongari } 218741502Swpaul } else { 2188148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 218941502Swpaul vr_stop(sc); 219041502Swpaul } 2191177050Syongari sc->vr_if_flags = ifp->if_flags; 2192131844Sbms VR_UNLOCK(sc); 219341502Swpaul break; 219441502Swpaul case SIOCADDMULTI: 219541502Swpaul case SIOCDELMULTI: 2196131518Sbms VR_LOCK(sc); 2197177050Syongari vr_set_filter(sc); 2198131518Sbms VR_UNLOCK(sc); 219941502Swpaul break; 220041502Swpaul case SIOCGIFMEDIA: 220141502Swpaul case SIOCSIFMEDIA: 220251432Swpaul mii = device_get_softc(sc->vr_miibus); 220351432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 220441502Swpaul break; 2205128118Sru case SIOCSIFCAP: 2206177050Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2207150789Sglebius#ifdef DEVICE_POLLING 2208177050Syongari if (mask & IFCAP_POLLING) { 2209177050Syongari if (ifr->ifr_reqcap & IFCAP_POLLING) { 2210177050Syongari error = ether_poll_register(vr_poll, ifp); 2211177050Syongari if (error != 0) 2212177050Syongari break; 2213177050Syongari VR_LOCK(sc); 2214177050Syongari /* Disable interrupts. */ 2215177050Syongari CSR_WRITE_2(sc, VR_IMR, 0x0000); 2216177050Syongari ifp->if_capenable |= IFCAP_POLLING; 2217177050Syongari VR_UNLOCK(sc); 2218177050Syongari } else { 2219177050Syongari error = ether_poll_deregister(ifp); 2220177050Syongari /* Enable interrupts. */ 2221177050Syongari VR_LOCK(sc); 2222177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2223177050Syongari ifp->if_capenable &= ~IFCAP_POLLING; 2224177050Syongari VR_UNLOCK(sc); 2225177050Syongari } 2226150789Sglebius } 2227177050Syongari#endif /* DEVICE_POLLING */ 2228177050Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2229177050Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2230177050Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2231177050Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2232177050Syongari ifp->if_hwassist |= VR_CSUM_FEATURES; 2233177050Syongari else 2234177050Syongari ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2235150789Sglebius } 2236177050Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2237177050Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2238177050Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2239177050Syongari if ((mask & IFCAP_WOL_UCAST) != 0 && 2240177050Syongari (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2241177050Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2242177050Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2243177050Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2244177050Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2245128118Sru break; 224641502Swpaul default: 2247106936Ssam error = ether_ioctl(ifp, command, data); 224841502Swpaul break; 224941502Swpaul } 225041502Swpaul 2251131503Sbms return (error); 225241502Swpaul} 225341502Swpaul 2254102336Salfredstatic void 2255177050Syongarivr_watchdog(struct vr_softc *sc) 225641502Swpaul{ 2257177050Syongari struct ifnet *ifp; 225841502Swpaul 2259177050Syongari VR_LOCK_ASSERT(sc); 2260131844Sbms 2261177050Syongari if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2262177050Syongari return; 2263177050Syongari 2264177050Syongari ifp = sc->vr_ifp; 2265177050Syongari /* 2266177050Syongari * Reclaim first as we don't request interrupt for every packets. 2267177050Syongari */ 2268177050Syongari vr_txeof(sc); 2269177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 2270177050Syongari return; 2271177050Syongari 2272177050Syongari if (sc->vr_link == 0) { 2273177050Syongari if (bootverbose) 2274177050Syongari if_printf(sc->vr_ifp, "watchdog timeout " 2275177050Syongari "(missed link)\n"); 2276177050Syongari ifp->if_oerrors++; 2277211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2278177050Syongari vr_init_locked(sc); 2279177050Syongari return; 2280177050Syongari } 2281177050Syongari 228241502Swpaul ifp->if_oerrors++; 2283151773Sjhb if_printf(ifp, "watchdog timeout\n"); 228441502Swpaul 2285211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2286131844Sbms vr_init_locked(sc); 2287131518Sbms 2288132986Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2289131844Sbms vr_start_locked(ifp); 2290177050Syongari} 2291131844Sbms 2292177050Syongaristatic void 2293177050Syongarivr_tx_start(struct vr_softc *sc) 2294177050Syongari{ 2295177050Syongari bus_addr_t addr; 2296177050Syongari uint8_t cmd; 2297177050Syongari 2298177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2299177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) { 2300177050Syongari addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2301177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2302177050Syongari cmd |= VR_CR0_TX_ON; 2303177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2304177050Syongari } 2305177050Syongari if (sc->vr_cdata.vr_tx_cnt != 0) { 2306177050Syongari sc->vr_watchdog_timer = 5; 2307177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2308177050Syongari } 230941502Swpaul} 231041502Swpaul 2311177050Syongaristatic void 2312177050Syongarivr_rx_start(struct vr_softc *sc) 2313177050Syongari{ 2314177050Syongari bus_addr_t addr; 2315177050Syongari uint8_t cmd; 2316177050Syongari 2317177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2318177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) { 2319177050Syongari addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2320177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2321177050Syongari cmd |= VR_CR0_RX_ON; 2322177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2323177050Syongari } 2324177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2325177050Syongari} 2326177050Syongari 2327177050Syongaristatic int 2328177050Syongarivr_tx_stop(struct vr_softc *sc) 2329177050Syongari{ 2330177050Syongari int i; 2331177050Syongari uint8_t cmd; 2332177050Syongari 2333177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2334177050Syongari if ((cmd & VR_CR0_TX_ON) != 0) { 2335177050Syongari cmd &= ~VR_CR0_TX_ON; 2336177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2337177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2338177050Syongari DELAY(5); 2339177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2340177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) 2341177050Syongari break; 2342177050Syongari } 2343177050Syongari if (i == 0) 2344177050Syongari return (ETIMEDOUT); 2345177050Syongari } 2346177050Syongari return (0); 2347177050Syongari} 2348177050Syongari 2349177050Syongaristatic int 2350177050Syongarivr_rx_stop(struct vr_softc *sc) 2351177050Syongari{ 2352177050Syongari int i; 2353177050Syongari uint8_t cmd; 2354177050Syongari 2355177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2356177050Syongari if ((cmd & VR_CR0_RX_ON) != 0) { 2357177050Syongari cmd &= ~VR_CR0_RX_ON; 2358177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2359177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2360177050Syongari DELAY(5); 2361177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2362177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) 2363177050Syongari break; 2364177050Syongari } 2365177050Syongari if (i == 0) 2366177050Syongari return (ETIMEDOUT); 2367177050Syongari } 2368177050Syongari return (0); 2369177050Syongari} 2370177050Syongari 237141502Swpaul/* 237241502Swpaul * Stop the adapter and free any mbufs allocated to the 237341502Swpaul * RX and TX lists. 237441502Swpaul */ 2375102336Salfredstatic void 2376131503Sbmsvr_stop(struct vr_softc *sc) 237741502Swpaul{ 2378177050Syongari struct vr_txdesc *txd; 2379177050Syongari struct vr_rxdesc *rxd; 2380177050Syongari struct ifnet *ifp; 2381177050Syongari int i; 238241502Swpaul 2383131518Sbms VR_LOCK_ASSERT(sc); 238467087Swpaul 2385147256Sbrooks ifp = sc->vr_ifp; 2386177050Syongari sc->vr_watchdog_timer = 0; 238741502Swpaul 2388151911Sjhb callout_stop(&sc->vr_stat_callout); 2389148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 239051432Swpaul 2391177050Syongari CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2392177050Syongari if (vr_rx_stop(sc) != 0) 2393177050Syongari device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2394177050Syongari if (vr_tx_stop(sc) != 0) 2395177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2396177050Syongari /* Clear pending interrupts. */ 2397177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 239841502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 239941502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 240041502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 240141502Swpaul 240241502Swpaul /* 2403177050Syongari * Free RX and TX mbufs still in the queues. 240441502Swpaul */ 2405177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 2406177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 2407177050Syongari if (rxd->rx_m != NULL) { 2408177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2409177050Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2410177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2411177050Syongari rxd->rx_dmamap); 2412177050Syongari m_freem(rxd->rx_m); 2413177050Syongari rxd->rx_m = NULL; 2414177050Syongari } 2415177050Syongari } 2416177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 2417177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 2418177050Syongari if (txd->tx_m != NULL) { 2419177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2420177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2421177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2422177050Syongari txd->tx_dmamap); 2423177050Syongari m_freem(txd->tx_m); 2424177050Syongari txd->tx_m = NULL; 2425177050Syongari } 2426177050Syongari } 242741502Swpaul} 242841502Swpaul 242941502Swpaul/* 243041502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 243141502Swpaul * get confused by errant DMAs when rebooting. 243241502Swpaul */ 2433173839Syongaristatic int 2434131503Sbmsvr_shutdown(device_t dev) 243541502Swpaul{ 243641502Swpaul 2437177050Syongari return (vr_suspend(dev)); 2438177050Syongari} 2439173839Syongari 2440177050Syongaristatic int 2441177050Syongarivr_suspend(device_t dev) 2442177050Syongari{ 2443177050Syongari struct vr_softc *sc; 2444177050Syongari 2445177050Syongari sc = device_get_softc(dev); 2446177050Syongari 2447177050Syongari VR_LOCK(sc); 2448177050Syongari vr_stop(sc); 2449177050Syongari vr_setwol(sc); 2450177050Syongari sc->vr_suspended = 1; 2451177050Syongari VR_UNLOCK(sc); 2452177050Syongari 2453173839Syongari return (0); 245441502Swpaul} 2455177050Syongari 2456177050Syongaristatic int 2457177050Syongarivr_resume(device_t dev) 2458177050Syongari{ 2459177050Syongari struct vr_softc *sc; 2460177050Syongari struct ifnet *ifp; 2461177050Syongari 2462177050Syongari sc = device_get_softc(dev); 2463177050Syongari 2464177050Syongari VR_LOCK(sc); 2465177050Syongari ifp = sc->vr_ifp; 2466177050Syongari vr_clrwol(sc); 2467177050Syongari vr_reset(sc); 2468177050Syongari if (ifp->if_flags & IFF_UP) 2469177050Syongari vr_init_locked(sc); 2470177050Syongari 2471177050Syongari sc->vr_suspended = 0; 2472177050Syongari VR_UNLOCK(sc); 2473177050Syongari 2474177050Syongari return (0); 2475177050Syongari} 2476177050Syongari 2477177050Syongaristatic void 2478177050Syongarivr_setwol(struct vr_softc *sc) 2479177050Syongari{ 2480177050Syongari struct ifnet *ifp; 2481177050Syongari int pmc; 2482177050Syongari uint16_t pmstat; 2483177050Syongari uint8_t v; 2484177050Syongari 2485177050Syongari VR_LOCK_ASSERT(sc); 2486177050Syongari 2487177050Syongari if (sc->vr_revid < REV_ID_VT6102_A || 2488219902Sjhb pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2489177050Syongari return; 2490177050Syongari 2491177050Syongari ifp = sc->vr_ifp; 2492177050Syongari 2493177050Syongari /* Clear WOL configuration. */ 2494177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2495177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2496177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2497177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2498177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2499177050Syongari /* Newer Rhine III supports two additional patterns. */ 2500177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2501177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2502177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2503177050Syongari } 2504177050Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2505177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2506177050Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2507177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2508177050Syongari /* 2509177050Syongari * It seems that multicast wakeup frames require programming pattern 2510177050Syongari * registers and valid CRC as well as pattern mask for each pattern. 2511177050Syongari * While it's possible to setup such a pattern it would complicate 2512177050Syongari * WOL configuration so ignore multicast wakeup frames. 2513177050Syongari */ 2514177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2515177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2516177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2517177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2518177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2519177050Syongari } 2520177050Syongari 2521177050Syongari /* Put hardware into sleep. */ 2522177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2523177050Syongari v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2524177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2525177050Syongari 2526177050Syongari /* Request PME if WOL is requested. */ 2527177050Syongari pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2528177050Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2529177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2530177050Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2531177050Syongari pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2532177050Syongari} 2533177050Syongari 2534177050Syongaristatic void 2535177050Syongarivr_clrwol(struct vr_softc *sc) 2536177050Syongari{ 2537177050Syongari uint8_t v; 2538177050Syongari 2539177050Syongari VR_LOCK_ASSERT(sc); 2540177050Syongari 2541177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 2542177050Syongari return; 2543177050Syongari 2544177050Syongari /* Take hardware out of sleep. */ 2545177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2546177050Syongari v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2547177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2548177050Syongari 2549177050Syongari /* Clear WOL configuration as WOL may interfere normal operation. */ 2550177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2551177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2552177050Syongari VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2553177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2554177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2555177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2556177050Syongari /* Newer Rhine III supports two additional patterns. */ 2557177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2558177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2559177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2560177050Syongari } 2561177050Syongari} 2562177050Syongari 2563177050Syongaristatic int 2564177050Syongarivr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2565177050Syongari{ 2566177050Syongari struct vr_softc *sc; 2567177050Syongari struct vr_statistics *stat; 2568177050Syongari int error; 2569177050Syongari int result; 2570177050Syongari 2571177050Syongari result = -1; 2572177050Syongari error = sysctl_handle_int(oidp, &result, 0, req); 2573177050Syongari 2574177050Syongari if (error != 0 || req->newptr == NULL) 2575177050Syongari return (error); 2576177050Syongari 2577177050Syongari if (result == 1) { 2578177050Syongari sc = (struct vr_softc *)arg1; 2579177050Syongari stat = &sc->vr_stat; 2580177050Syongari 2581177050Syongari printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2582177050Syongari printf("Outbound good frames : %ju\n", 2583177050Syongari (uintmax_t)stat->tx_ok); 2584177050Syongari printf("Inbound good frames : %ju\n", 2585177050Syongari (uintmax_t)stat->rx_ok); 2586177050Syongari printf("Outbound errors : %u\n", stat->tx_errors); 2587177050Syongari printf("Inbound errors : %u\n", stat->rx_errors); 2588177050Syongari printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2589177050Syongari printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2590177050Syongari printf("Inbound FIFO overflows : %d\n", 2591177050Syongari stat->rx_fifo_overflows); 2592177050Syongari printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2593177050Syongari printf("Inbound frame alignment errors : %u\n", 2594177050Syongari stat->rx_alignment); 2595177050Syongari printf("Inbound giant frames : %u\n", stat->rx_giants); 2596177050Syongari printf("Inbound runt frames : %u\n", stat->rx_runts); 2597177050Syongari printf("Outbound aborted with excessive collisions : %u\n", 2598177050Syongari stat->tx_abort); 2599177050Syongari printf("Outbound collisions : %u\n", stat->tx_collisions); 2600177050Syongari printf("Outbound late collisions : %u\n", 2601177050Syongari stat->tx_late_collisions); 2602177050Syongari printf("Outbound underrun : %u\n", stat->tx_underrun); 2603177050Syongari printf("PCI bus errors : %u\n", stat->bus_errors); 2604177050Syongari printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2605177050Syongari stat->num_restart); 2606177050Syongari } 2607177050Syongari 2608177050Syongari return (error); 2609177050Syongari} 2610