if_vr.c revision 219902
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 219902 2011-03-23 13:10:15Z jhb $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various network adapters based on the VIA Rhine 4041502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4141502Swpaul * Datasheets are available at http://www.via.com.tw. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 47131503Sbms 4841502Swpaul/* 4941502Swpaul * The VIA Rhine controllers are similar in some respects to the 5041502Swpaul * the DEC tulip chips, except less complicated. The controller 5141502Swpaul * uses an MII bus and an external physical layer interface. The 5241502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5341502Swpaul * multicast filter. Transmit and receive descriptors are similar 5441502Swpaul * to the tulip. 5541502Swpaul * 56168953Sphk * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 5741502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5841502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5941502Swpaul * at longword boundaries, so we have to do a buffer copy before 6041502Swpaul * transmission. 6141502Swpaul */ 6241502Swpaul 63150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 64150968Sglebius#include "opt_device_polling.h" 65150968Sglebius#endif 66150968Sglebius 6741502Swpaul#include <sys/param.h> 6841502Swpaul#include <sys/systm.h> 69177050Syongari#include <sys/bus.h> 70177050Syongari#include <sys/endian.h> 71177050Syongari#include <sys/kernel.h> 72177050Syongari#include <sys/malloc.h> 7341502Swpaul#include <sys/mbuf.h> 74129878Sphk#include <sys/module.h> 75177050Syongari#include <sys/rman.h> 7641502Swpaul#include <sys/socket.h> 77177050Syongari#include <sys/sockio.h> 78177050Syongari#include <sys/sysctl.h> 79177050Syongari#include <sys/taskqueue.h> 8041502Swpaul 81177050Syongari#include <net/bpf.h> 8241502Swpaul#include <net/if.h> 8341502Swpaul#include <net/ethernet.h> 8441502Swpaul#include <net/if_dl.h> 8541502Swpaul#include <net/if_media.h> 86147256Sbrooks#include <net/if_types.h> 87177050Syongari#include <net/if_vlan_var.h> 8841502Swpaul 89177050Syongari#include <dev/mii/mii.h> 9051432Swpaul#include <dev/mii/miivar.h> 9151432Swpaul 92172555Syongari#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9441502Swpaul 95177050Syongari#include <machine/bus.h> 9641502Swpaul 97177047Syongari#include <dev/vr/if_vrreg.h> 9841502Swpaul 99177050Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 100177050Syongari#include "miibus_if.h" 101177050Syongari 102113506SmdoddMODULE_DEPEND(vr, pci, 1, 1, 1); 103113506SmdoddMODULE_DEPEND(vr, ether, 1, 1, 1); 10459758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 10559758Speter 106177050Syongari/* Define to show Rx/Tx error status. */ 107177050Syongari#undef VR_SHOW_ERRORS 108177050Syongari#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 10951432Swpaul 11041502Swpaul/* 111177050Syongari * Various supported device vendors/types, their names & quirks. 11241502Swpaul */ 113168952Sphk#define VR_Q_NEEDALIGN (1<<0) 114168952Sphk#define VR_Q_CSUM (1<<1) 115177050Syongari#define VR_Q_CAM (1<<2) 116168952Sphk 117168952Sphkstatic struct vr_type { 118168952Sphk u_int16_t vr_vid; 119168952Sphk u_int16_t vr_did; 120168952Sphk int vr_quirks; 121168952Sphk char *vr_name; 122168952Sphk} vr_devs[] = { 123168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE, 124168827Sphk VR_Q_NEEDALIGN, 125168827Sphk "VIA VT3043 Rhine I 10/100BaseTX" }, 126168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127168827Sphk VR_Q_NEEDALIGN, 128168827Sphk "VIA VT86C100A Rhine II 10/100BaseTX" }, 129168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130168827Sphk 0, 131168827Sphk "VIA VT6102 Rhine II 10/100BaseTX" }, 132168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133168827Sphk 0, 134168827Sphk "VIA VT6105 Rhine III 10/100BaseTX" }, 135168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136185962Syongari VR_Q_CSUM, 137168827Sphk "VIA VT6105M Rhine III 10/100BaseTX" }, 138168827Sphk { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139168827Sphk VR_Q_NEEDALIGN, 140168827Sphk "Delta Electronics Rhine II 10/100BaseTX" }, 141168827Sphk { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142168827Sphk VR_Q_NEEDALIGN, 143168827Sphk "Addtron Technology Rhine II 10/100BaseTX" }, 144168813Sphk { 0, 0, 0, NULL } 14541502Swpaul}; 14641502Swpaul 147142407Simpstatic int vr_probe(device_t); 148142407Simpstatic int vr_attach(device_t); 149142407Simpstatic int vr_detach(device_t); 150177050Syongaristatic int vr_shutdown(device_t); 151177050Syongaristatic int vr_suspend(device_t); 152177050Syongaristatic int vr_resume(device_t); 15341502Swpaul 154177050Syongaristatic void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155177050Syongaristatic int vr_dma_alloc(struct vr_softc *); 156177050Syongaristatic void vr_dma_free(struct vr_softc *); 157177050Syongaristatic __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158177050Syongaristatic int vr_newbuf(struct vr_softc *, int); 15941502Swpaul 160177050Syongari#ifndef __NO_STRICT_ALIGNMENT 161177050Syongaristatic __inline void vr_fixup_rx(struct mbuf *); 162177050Syongari#endif 163193096Sattiliostatic int vr_rxeof(struct vr_softc *); 164142407Simpstatic void vr_txeof(struct vr_softc *); 165142407Simpstatic void vr_tick(void *); 166177050Syongaristatic int vr_error(struct vr_softc *, uint16_t); 167177050Syongaristatic void vr_tx_underrun(struct vr_softc *); 168142407Simpstatic void vr_intr(void *); 169142407Simpstatic void vr_start(struct ifnet *); 170142407Simpstatic void vr_start_locked(struct ifnet *); 171177050Syongaristatic int vr_encap(struct vr_softc *, struct mbuf **); 172142407Simpstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 173142407Simpstatic void vr_init(void *); 174142407Simpstatic void vr_init_locked(struct vr_softc *); 175177050Syongaristatic void vr_tx_start(struct vr_softc *); 176177050Syongaristatic void vr_rx_start(struct vr_softc *); 177177050Syongaristatic int vr_tx_stop(struct vr_softc *); 178177050Syongaristatic int vr_rx_stop(struct vr_softc *); 179142407Simpstatic void vr_stop(struct vr_softc *); 180177050Syongaristatic void vr_watchdog(struct vr_softc *); 181142407Simpstatic int vr_ifmedia_upd(struct ifnet *); 182142407Simpstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 18341502Swpaul 184177050Syongaristatic int vr_miibus_readreg(device_t, int, int); 185177050Syongaristatic int vr_miibus_writereg(device_t, int, int, int); 186142407Simpstatic void vr_miibus_statchg(device_t); 18741502Swpaul 188177050Syongaristatic void vr_link_task(void *, int); 189180552Syongaristatic void vr_cam_mask(struct vr_softc *, uint32_t, int); 190180552Syongaristatic int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 191177050Syongaristatic void vr_set_filter(struct vr_softc *); 192168946Sphkstatic void vr_reset(const struct vr_softc *); 193177050Syongaristatic int vr_tx_ring_init(struct vr_softc *); 194177050Syongaristatic int vr_rx_ring_init(struct vr_softc *); 195177050Syongaristatic void vr_setwol(struct vr_softc *); 196177050Syongaristatic void vr_clrwol(struct vr_softc *); 197177050Syongaristatic int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 19841502Swpaul 199177050Syongaristatic struct vr_tx_threshold_table { 200177050Syongari int tx_cfg; 201177050Syongari int bcr_cfg; 202177050Syongari int value; 203177050Syongari} vr_tx_threshold_tables[] = { 204177050Syongari { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 205177050Syongari { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 206177050Syongari { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 207177050Syongari { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 208177050Syongari { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 209177050Syongari { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 210177050Syongari}; 21149610Swpaul 21249610Swpaulstatic device_method_t vr_methods[] = { 21349610Swpaul /* Device interface */ 21449610Swpaul DEVMETHOD(device_probe, vr_probe), 21549610Swpaul DEVMETHOD(device_attach, vr_attach), 21649610Swpaul DEVMETHOD(device_detach, vr_detach), 21749610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 218177050Syongari DEVMETHOD(device_suspend, vr_suspend), 219177050Syongari DEVMETHOD(device_resume, vr_resume), 22051432Swpaul 22151432Swpaul /* bus interface */ 22251432Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22351432Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22451432Swpaul 22551432Swpaul /* MII interface */ 22651432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 22751432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 22851432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 229177050Syongari DEVMETHOD(miibus_linkchg, vr_miibus_statchg), 23051432Swpaul 231177050Syongari { NULL, NULL } 23249610Swpaul}; 23349610Swpaul 23449610Swpaulstatic driver_t vr_driver = { 23551455Swpaul "vr", 23649610Swpaul vr_methods, 23749610Swpaul sizeof(struct vr_softc) 23849610Swpaul}; 23949610Swpaul 24049610Swpaulstatic devclass_t vr_devclass; 24149610Swpaul 242113506SmdoddDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 24351473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 24449610Swpaul 245102336Salfredstatic int 246177050Syongarivr_miibus_readreg(device_t dev, int phy, int reg) 24741502Swpaul{ 248177050Syongari struct vr_softc *sc; 249177050Syongari int i; 25041502Swpaul 251177050Syongari sc = device_get_softc(dev); 252110168Ssilby 253131503Sbms /* Set the register address. */ 254177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 255110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 256131503Sbms 257177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 258177050Syongari DELAY(1); 259110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 260110168Ssilby break; 261110168Ssilby } 262177050Syongari if (i == VR_MII_TIMEOUT) 263177050Syongari device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 264110168Ssilby 265177050Syongari return (CSR_READ_2(sc, VR_MIIDATA)); 266110168Ssilby} 267110168Ssilby 268102336Salfredstatic int 269177050Syongarivr_miibus_writereg(device_t dev, int phy, int reg, int data) 27041502Swpaul{ 271177050Syongari struct vr_softc *sc; 272177050Syongari int i; 27341502Swpaul 274177050Syongari sc = device_get_softc(dev); 275110168Ssilby 276131503Sbms /* Set the register address and data to write. */ 277177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 278177050Syongari CSR_WRITE_2(sc, VR_MIIDATA, data); 279110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 280110168Ssilby 281177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 282177050Syongari DELAY(1); 283110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 284110168Ssilby break; 285110168Ssilby } 286177050Syongari if (i == VR_MII_TIMEOUT) 287177050Syongari device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 288177050Syongari reg); 289110168Ssilby 290131503Sbms return (0); 291110168Ssilby} 292110168Ssilby 293177050Syongaristatic void 294177050Syongarivr_miibus_statchg(device_t dev) 29551432Swpaul{ 296177050Syongari struct vr_softc *sc; 29741502Swpaul 298177050Syongari sc = device_get_softc(dev); 299177050Syongari taskqueue_enqueue(taskqueue_swi, &sc->vr_link_task); 30041502Swpaul} 30141502Swpaul 302177050Syongari/* 303177050Syongari * In order to fiddle with the 304177050Syongari * 'full-duplex' and '100Mbps' bits in the netconfig register, we 305177050Syongari * first have to put the transmit and/or receive logic in the idle state. 306177050Syongari */ 307177050Syongaristatic void 308177050Syongarivr_link_task(void *arg, int pending) 30951432Swpaul{ 310177050Syongari struct vr_softc *sc; 311177050Syongari struct mii_data *mii; 312177050Syongari struct ifnet *ifp; 313177050Syongari int lfdx, mfdx; 314177050Syongari uint8_t cr0, cr1, fc; 31541502Swpaul 316177050Syongari sc = (struct vr_softc *)arg; 317110168Ssilby 318177050Syongari VR_LOCK(sc); 319177050Syongari mii = device_get_softc(sc->vr_miibus); 320177050Syongari ifp = sc->vr_ifp; 321177050Syongari if (mii == NULL || ifp == NULL || 322177050Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 323177050Syongari VR_UNLOCK(sc); 324177050Syongari return; 325177050Syongari } 32641502Swpaul 327177050Syongari if (mii->mii_media_status & IFM_ACTIVE) { 328177050Syongari if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 329177050Syongari sc->vr_link = 1; 330177050Syongari } else 331177050Syongari sc->vr_link = 0; 332177050Syongari 333177050Syongari if (sc->vr_link != 0) { 334177050Syongari cr0 = CSR_READ_1(sc, VR_CR0); 335177050Syongari cr1 = CSR_READ_1(sc, VR_CR1); 336177050Syongari mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 337177050Syongari lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 338177050Syongari if (mfdx != lfdx) { 339177050Syongari if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 340177050Syongari if (vr_tx_stop(sc) != 0 || 341177050Syongari vr_rx_stop(sc) != 0) { 342177050Syongari device_printf(sc->vr_dev, 343177050Syongari "%s: Tx/Rx shutdown error -- " 344177050Syongari "resetting\n", __func__); 345177050Syongari sc->vr_flags |= VR_F_RESTART; 346177050Syongari VR_UNLOCK(sc); 347177050Syongari return; 348177050Syongari } 349177050Syongari } 350177050Syongari if (lfdx) 351177050Syongari cr1 |= VR_CR1_FULLDUPLEX; 352177050Syongari else 353177050Syongari cr1 &= ~VR_CR1_FULLDUPLEX; 354177050Syongari CSR_WRITE_1(sc, VR_CR1, cr1); 355177050Syongari } 356177050Syongari fc = 0; 357177050Syongari#ifdef notyet 358177050Syongari /* Configure flow-control. */ 359177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 360177050Syongari fc = CSR_READ_1(sc, VR_FLOWCR1); 361177050Syongari fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 362177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 363177050Syongari IFM_ETH_RXPAUSE) != 0) 364177050Syongari fc |= VR_FLOWCR1_RXPAUSE; 365177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 366177050Syongari IFM_ETH_TXPAUSE) != 0) 367177050Syongari fc |= VR_FLOWCR1_TXPAUSE; 368177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, fc); 369177050Syongari } else if (sc->vr_revid >= REV_ID_VT6102_A) { 370177050Syongari /* No Tx puase capability available for Rhine II. */ 371177050Syongari fc = CSR_READ_1(sc, VR_MISC_CR0); 372177050Syongari fc &= ~VR_MISCCR0_RXPAUSE; 373177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 374177050Syongari IFM_ETH_RXPAUSE) != 0) 375177050Syongari fc |= VR_MISCCR0_RXPAUSE; 376177050Syongari CSR_WRITE_1(sc, VR_MISC_CR0, fc); 377177050Syongari } 378177050Syongari#endif 379177050Syongari vr_rx_start(sc); 380177050Syongari vr_tx_start(sc); 381177050Syongari } else { 382177050Syongari if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 383177050Syongari device_printf(sc->vr_dev, 384177050Syongari "%s: Tx/Rx shutdown error -- resetting\n", 385177050Syongari __func__); 386177050Syongari sc->vr_flags |= VR_F_RESTART; 387177050Syongari VR_UNLOCK(sc); 388177050Syongari return; 389177050Syongari } 390177050Syongari } 391177050Syongari VR_UNLOCK(sc); 39251432Swpaul} 39351432Swpaul 394180552Syongari 395180552Syongaristatic void 396180552Syongarivr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 397180552Syongari{ 398180552Syongari 399180552Syongari if (type == VR_MCAST_CAM) 400180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 401180552Syongari else 402180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 403180552Syongari CSR_WRITE_4(sc, VR_CAMMASK, mask); 404180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 405180552Syongari} 406180552Syongari 407177050Syongaristatic int 408180552Syongarivr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 40951432Swpaul{ 410177050Syongari int i; 41151432Swpaul 412180552Syongari if (type == VR_MCAST_CAM) { 413180552Syongari if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 414180552Syongari return (EINVAL); 415180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 416180552Syongari } else 417180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 418177050Syongari 419177050Syongari /* Set CAM entry address. */ 420177050Syongari CSR_WRITE_1(sc, VR_CAMADDR, idx); 421177050Syongari /* Set CAM entry data. */ 422180552Syongari if (type == VR_MCAST_CAM) { 423180552Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) 424180552Syongari CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 425180552Syongari } else { 426180552Syongari CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 427180552Syongari CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 428180552Syongari } 429180552Syongari DELAY(10); 430177050Syongari /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 431180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 432177050Syongari for (i = 0; i < VR_TIMEOUT; i++) { 433177050Syongari DELAY(1); 434177050Syongari if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 435177050Syongari break; 436177050Syongari } 437177050Syongari 438177050Syongari if (i == VR_TIMEOUT) 439177050Syongari device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 440177050Syongari __func__); 441180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 442177050Syongari 443177050Syongari return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 44441502Swpaul} 44541502Swpaul 44641502Swpaul/* 44741502Swpaul * Program the 64-bit multicast hash filter. 44841502Swpaul */ 449102336Salfredstatic void 450177050Syongarivr_set_filter(struct vr_softc *sc) 45141502Swpaul{ 452177050Syongari struct ifnet *ifp; 453177050Syongari int h; 454131503Sbms uint32_t hashes[2] = { 0, 0 }; 45541502Swpaul struct ifmultiaddr *ifma; 456131503Sbms uint8_t rxfilt; 457177050Syongari int error, mcnt; 458177050Syongari uint32_t cam_mask; 45941502Swpaul 460131518Sbms VR_LOCK_ASSERT(sc); 46141502Swpaul 462177050Syongari ifp = sc->vr_ifp; 46341502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 464185014Syongari rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 465185014Syongari VR_RXCFG_RX_MULTI); 466177050Syongari if (ifp->if_flags & IFF_BROADCAST) 467177050Syongari rxfilt |= VR_RXCFG_RX_BROAD; 46841502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 46941502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 470177050Syongari if (ifp->if_flags & IFF_PROMISC) 471177050Syongari rxfilt |= VR_RXCFG_RX_PROMISC; 47241502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 47341502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 47441502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 47541502Swpaul return; 47641502Swpaul } 47741502Swpaul 478131503Sbms /* Now program new ones. */ 479177050Syongari error = 0; 480180552Syongari mcnt = 0; 481195049Srwatson if_maddr_rlock(ifp); 482177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 483177050Syongari /* 484177050Syongari * For hardwares that have CAM capability, use 485177050Syongari * 32 entries multicast perfect filter. 486177050Syongari */ 487177050Syongari cam_mask = 0; 488177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 489177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 490177050Syongari continue; 491180552Syongari error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 492177050Syongari LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 493177050Syongari if (error != 0) { 494177050Syongari cam_mask = 0; 495177050Syongari break; 496177050Syongari } 497177050Syongari cam_mask |= 1 << mcnt; 498177050Syongari mcnt++; 499177050Syongari } 500180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 50141502Swpaul } 502177050Syongari 503177050Syongari if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 504177050Syongari /* 505177050Syongari * If there are too many multicast addresses or 506177050Syongari * setting multicast CAM filter failed, use hash 507177050Syongari * table based filtering. 508177050Syongari */ 509180552Syongari mcnt = 0; 510177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 511177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 512177050Syongari continue; 513177050Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 514177050Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 515177050Syongari if (h < 32) 516177050Syongari hashes[0] |= (1 << h); 517177050Syongari else 518177050Syongari hashes[1] |= (1 << (h - 32)); 519177050Syongari mcnt++; 520177050Syongari } 521177050Syongari } 522195049Srwatson if_maddr_runlock(ifp); 52341502Swpaul 524177050Syongari if (mcnt > 0) 52541502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 52641502Swpaul 52741502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 52841502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 52941502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 53041502Swpaul} 53141502Swpaul 532102336Salfredstatic void 533168946Sphkvr_reset(const struct vr_softc *sc) 53441502Swpaul{ 535177050Syongari int i; 53641502Swpaul 537151773Sjhb /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 538131518Sbms 539177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 540177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 541177050Syongari /* VT86C100A needs more delay after reset. */ 542177050Syongari DELAY(100); 543177050Syongari } 54441502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 54541502Swpaul DELAY(10); 546177050Syongari if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 54741502Swpaul break; 54841502Swpaul } 549107220Ssilby if (i == VR_TIMEOUT) { 550177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 551162315Sglebius device_printf(sc->vr_dev, "reset never completed!\n"); 552107220Ssilby else { 553177050Syongari /* Use newer force reset command. */ 554177050Syongari device_printf(sc->vr_dev, 555177050Syongari "Using force reset command.\n"); 556107220Ssilby VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 557177050Syongari /* 558177050Syongari * Wait a little while for the chip to get its brains 559177050Syongari * in order. 560177050Syongari */ 561177050Syongari DELAY(2000); 562107220Ssilby } 563107220Ssilby } 56441502Swpaul 56541502Swpaul} 56641502Swpaul 56741502Swpaul/* 56841502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 569168813Sphk * IDs against our list and return a match or NULL 570168813Sphk */ 571168813Sphkstatic struct vr_type * 572168813Sphkvr_match(device_t dev) 573168813Sphk{ 574168813Sphk struct vr_type *t = vr_devs; 575168813Sphk 576168813Sphk for (t = vr_devs; t->vr_name != NULL; t++) 577168813Sphk if ((pci_get_vendor(dev) == t->vr_vid) && 578168813Sphk (pci_get_device(dev) == t->vr_did)) 579168813Sphk return (t); 580168813Sphk return (NULL); 581168813Sphk} 582168813Sphk 583168813Sphk/* 584168813Sphk * Probe for a VIA Rhine chip. Check the PCI vendor and device 58541502Swpaul * IDs against our list and return a device name if we find a match. 58641502Swpaul */ 587102336Salfredstatic int 588131503Sbmsvr_probe(device_t dev) 58941502Swpaul{ 590168813Sphk struct vr_type *t; 59141502Swpaul 592168813Sphk t = vr_match(dev); 593168813Sphk if (t != NULL) { 594168813Sphk device_set_desc(dev, t->vr_name); 595168813Sphk return (BUS_PROBE_DEFAULT); 59641502Swpaul } 597131503Sbms return (ENXIO); 59841502Swpaul} 59941502Swpaul 60041502Swpaul/* 60141502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 60241502Swpaul * setup and ethernet/BPF attach. 60341502Swpaul */ 604102336Salfredstatic int 605168946Sphkvr_attach(device_t dev) 60641502Swpaul{ 60741502Swpaul struct vr_softc *sc; 60841502Swpaul struct ifnet *ifp; 609168813Sphk struct vr_type *t; 610177050Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 611177050Syongari int error, rid; 612213893Smarius int i, phy, pmc; 61341502Swpaul 61449610Swpaul sc = device_get_softc(dev); 615162315Sglebius sc->vr_dev = dev; 616168813Sphk t = vr_match(dev); 617168813Sphk KASSERT(t != NULL, ("Lost if_vr device match")); 618168813Sphk sc->vr_quirks = t->vr_quirks; 619168813Sphk device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 62041502Swpaul 62193818Sjhb mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 622131518Sbms MTX_DEF); 623151911Sjhb callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 624177050Syongari TASK_INIT(&sc->vr_link_task, 0, vr_link_task, sc); 625177050Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 626177050Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 627177050Syongari OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 628177050Syongari vr_sysctl_stats, "I", "Statistics"); 629151911Sjhb 630177050Syongari error = 0; 631177050Syongari 63241502Swpaul /* 63341502Swpaul * Map control/status registers. 63441502Swpaul */ 63572813Swpaul pci_enable_busmaster(dev); 636177050Syongari sc->vr_revid = pci_get_revid(dev); 637177050Syongari device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 63841502Swpaul 639177050Syongari sc->vr_res_id = PCIR_BAR(0); 640177050Syongari sc->vr_res_type = SYS_RES_IOPORT; 641177050Syongari sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 642177050Syongari &sc->vr_res_id, RF_ACTIVE); 64349610Swpaul if (sc->vr_res == NULL) { 644177050Syongari device_printf(dev, "couldn't map ports\n"); 64549610Swpaul error = ENXIO; 64641502Swpaul goto fail; 64741502Swpaul } 64841502Swpaul 649177050Syongari /* Allocate interrupt. */ 65049610Swpaul rid = 0; 651127135Snjl sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 65249610Swpaul RF_SHAREABLE | RF_ACTIVE); 65349610Swpaul 65449610Swpaul if (sc->vr_irq == NULL) { 655151773Sjhb device_printf(dev, "couldn't map interrupt\n"); 65649610Swpaul error = ENXIO; 65741502Swpaul goto fail; 65841502Swpaul } 65941502Swpaul 660151773Sjhb /* Allocate ifnet structure. */ 661151773Sjhb ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 662151773Sjhb if (ifp == NULL) { 663177050Syongari device_printf(dev, "couldn't allocate ifnet structure\n"); 664151773Sjhb error = ENOSPC; 665151773Sjhb goto fail; 666151773Sjhb } 667151773Sjhb ifp->if_softc = sc; 668151773Sjhb if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 669151773Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 670151773Sjhb ifp->if_ioctl = vr_ioctl; 671151773Sjhb ifp->if_start = vr_start; 672151773Sjhb ifp->if_init = vr_init; 673177050Syongari IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 674177050Syongari ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 675151773Sjhb IFQ_SET_READY(&ifp->if_snd); 676168827Sphk 677177050Syongari /* Configure Tx FIFO threshold. */ 678177050Syongari sc->vr_txthresh = VR_TXTHRESH_MIN; 679177050Syongari if (sc->vr_revid < REV_ID_VT6105_A0) { 680177050Syongari /* 681177050Syongari * Use store and forward mode for Rhine I/II. 682177050Syongari * Otherwise they produce a lot of Tx underruns and 683177050Syongari * it would take a while to get working FIFO threshold 684177050Syongari * value. 685177050Syongari */ 686177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 687177050Syongari } 688177050Syongari if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 689177050Syongari ifp->if_hwassist = VR_CSUM_FEATURES; 690168827Sphk ifp->if_capabilities |= IFCAP_HWCSUM; 691177050Syongari /* 692177050Syongari * To update checksum field the hardware may need to 693177050Syongari * store entire frames into FIFO before transmitting. 694177050Syongari */ 695177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 696168827Sphk } 697168827Sphk 698177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A && 699219902Sjhb pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 700177050Syongari ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 701177050Syongari 702177050Syongari /* Rhine supports oversized VLAN frame. */ 703168973Sphk ifp->if_capabilities |= IFCAP_VLAN_MTU; 704151773Sjhb ifp->if_capenable = ifp->if_capabilities; 705151773Sjhb#ifdef DEVICE_POLLING 706151773Sjhb ifp->if_capabilities |= IFCAP_POLLING; 707151773Sjhb#endif 708151773Sjhb 70976586Swpaul /* 71076586Swpaul * Windows may put the chip in suspend mode when it 71176586Swpaul * shuts down. Be sure to kick it in the head to wake it 71276586Swpaul * up again. 71376586Swpaul */ 714219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 715172555Syongari VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 71676586Swpaul 717131503Sbms /* 71841502Swpaul * Get station address. The way the Rhine chips work, 71941502Swpaul * you're not allowed to directly access the EEPROM once 72041502Swpaul * they've been programmed a special way. Consequently, 72141502Swpaul * we need to read the node address from the PAR0 and PAR1 72241502Swpaul * registers. 723177050Syongari * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 724177050Syongari * VR_CFGC and VR_CFGD such that memory mapped IO configured 725177050Syongari * by driver is reset to default state. 72641502Swpaul */ 72741502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 728177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 729177050Syongari DELAY(1); 730177050Syongari if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 731177050Syongari break; 732177050Syongari } 733177050Syongari if (i == 0) 734177050Syongari device_printf(dev, "Reloading EEPROM timeout!\n"); 73541502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 73641502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 73741502Swpaul 738177050Syongari /* Reset the adapter. */ 739177050Syongari vr_reset(sc); 740177050Syongari /* Ack intr & disable further interrupts. */ 741177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 742177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 743177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A) 744177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 74551432Swpaul 746177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 747177050Syongari pci_write_config(dev, VR_PCI_MODE2, 748177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 749177050Syongari VR_MODE2_MODE10T, 1); 750177050Syongari } else { 751177050Syongari /* Report error instead of retrying forever. */ 752177050Syongari pci_write_config(dev, VR_PCI_MODE2, 753177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 754177050Syongari VR_MODE2_PCEROPT, 1); 755177050Syongari /* Detect MII coding error. */ 756177050Syongari pci_write_config(dev, VR_PCI_MODE3, 757177050Syongari pci_read_config(dev, VR_PCI_MODE3, 1) | 758177050Syongari VR_MODE3_MIION, 1); 759177050Syongari if (sc->vr_revid >= REV_ID_VT6105_LOM && 760177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 761177050Syongari pci_write_config(dev, VR_PCI_MODE2, 762177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 763177050Syongari VR_MODE2_MODE10T, 1); 764177050Syongari /* Enable Memory-Read-Multiple. */ 765177050Syongari if (sc->vr_revid >= REV_ID_VT6107_A1 && 766177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 767177050Syongari pci_write_config(dev, VR_PCI_MODE2, 768177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 769177050Syongari VR_MODE2_MRDPL, 1); 770177050Syongari } 771177050Syongari /* Disable MII AUTOPOLL. */ 772177050Syongari VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 773177050Syongari 774177050Syongari if (vr_dma_alloc(sc) != 0) { 77549610Swpaul error = ENXIO; 77649610Swpaul goto fail; 77741502Swpaul } 77841502Swpaul 779213893Smarius /* Do MII setup. */ 780177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) 781213893Smarius phy = 1; 782177050Syongari else 783213893Smarius phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 784213893Smarius error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 785213893Smarius vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 786213893Smarius if (error != 0) { 787213893Smarius device_printf(dev, "attaching PHYs failed\n"); 78841502Swpaul goto fail; 78941502Swpaul } 79041502Swpaul 791131503Sbms /* Call MI attach routine. */ 792106936Ssam ether_ifattach(ifp, eaddr); 793177050Syongari /* 794177050Syongari * Tell the upper layer(s) we support long frames. 795177050Syongari * Must appear after the call to ether_ifattach() because 796177050Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 797177050Syongari */ 798177050Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 79941502Swpaul 800177050Syongari /* Hook interrupt last to avoid having to lock softc. */ 801131518Sbms error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 802166901Spiso NULL, vr_intr, sc, &sc->vr_intrhand); 803112872Snjl 804112872Snjl if (error) { 805151773Sjhb device_printf(dev, "couldn't set up irq\n"); 806113609Snjl ether_ifdetach(ifp); 807112872Snjl goto fail; 808112872Snjl } 809112872Snjl 81041502Swpaulfail: 811112872Snjl if (error) 812112872Snjl vr_detach(dev); 81367087Swpaul 814131503Sbms return (error); 81541502Swpaul} 81641502Swpaul 817113609Snjl/* 818113609Snjl * Shutdown hardware and free up resources. This can be called any 819113609Snjl * time after the mutex has been initialized. It is called in both 820113609Snjl * the error case in attach and the normal detach case so it needs 821113609Snjl * to be careful about only freeing resources that have actually been 822113609Snjl * allocated. 823113609Snjl */ 824102336Salfredstatic int 825131503Sbmsvr_detach(device_t dev) 82649610Swpaul{ 827131503Sbms struct vr_softc *sc = device_get_softc(dev); 828147256Sbrooks struct ifnet *ifp = sc->vr_ifp; 82949610Swpaul 830112880Sjhb KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 831131518Sbms 832150789Sglebius#ifdef DEVICE_POLLING 833177050Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 834150789Sglebius ether_poll_deregister(ifp); 835150789Sglebius#endif 836150789Sglebius 837177050Syongari /* These should only be active if attach succeeded. */ 838113812Simp if (device_is_attached(dev)) { 839151911Sjhb VR_LOCK(sc); 840177050Syongari sc->vr_detach = 1; 841113609Snjl vr_stop(sc); 842151911Sjhb VR_UNLOCK(sc); 843151911Sjhb callout_drain(&sc->vr_stat_callout); 844177050Syongari taskqueue_drain(taskqueue_swi, &sc->vr_link_task); 845112872Snjl ether_ifdetach(ifp); 846113609Snjl } 847113609Snjl if (sc->vr_miibus) 848112872Snjl device_delete_child(dev, sc->vr_miibus); 849113609Snjl bus_generic_detach(dev); 85049610Swpaul 851112872Snjl if (sc->vr_intrhand) 852112872Snjl bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 853112872Snjl if (sc->vr_irq) 854112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 855112872Snjl if (sc->vr_res) 856177050Syongari bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 857177050Syongari sc->vr_res); 85851432Swpaul 859151297Sru if (ifp) 860151297Sru if_free(ifp); 861151297Sru 862177050Syongari vr_dma_free(sc); 86349610Swpaul 86467087Swpaul mtx_destroy(&sc->vr_mtx); 86549610Swpaul 866131503Sbms return (0); 86749610Swpaul} 86849610Swpaul 869177050Syongaristruct vr_dmamap_arg { 870177050Syongari bus_addr_t vr_busaddr; 871177050Syongari}; 872177050Syongari 873177050Syongaristatic void 874177050Syongarivr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 875177050Syongari{ 876177050Syongari struct vr_dmamap_arg *ctx; 877177050Syongari 878177050Syongari if (error != 0) 879177050Syongari return; 880177050Syongari ctx = arg; 881177050Syongari ctx->vr_busaddr = segs[0].ds_addr; 882177050Syongari} 883177050Syongari 884177050Syongaristatic int 885177050Syongarivr_dma_alloc(struct vr_softc *sc) 886177050Syongari{ 887177050Syongari struct vr_dmamap_arg ctx; 888177050Syongari struct vr_txdesc *txd; 889177050Syongari struct vr_rxdesc *rxd; 890177050Syongari bus_size_t tx_alignment; 891177050Syongari int error, i; 892177050Syongari 893177050Syongari /* Create parent DMA tag. */ 894177050Syongari error = bus_dma_tag_create( 895177050Syongari bus_get_dma_tag(sc->vr_dev), /* parent */ 896177050Syongari 1, 0, /* alignment, boundary */ 897177050Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 898177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 899177050Syongari NULL, NULL, /* filter, filterarg */ 900177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 901177050Syongari 0, /* nsegments */ 902177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 903177050Syongari 0, /* flags */ 904177050Syongari NULL, NULL, /* lockfunc, lockarg */ 905177050Syongari &sc->vr_cdata.vr_parent_tag); 906177050Syongari if (error != 0) { 907177050Syongari device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 908177050Syongari goto fail; 909177050Syongari } 910177050Syongari /* Create tag for Tx ring. */ 911177050Syongari error = bus_dma_tag_create( 912177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 913177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 914177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 915177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 916177050Syongari NULL, NULL, /* filter, filterarg */ 917177050Syongari VR_TX_RING_SIZE, /* maxsize */ 918177050Syongari 1, /* nsegments */ 919177050Syongari VR_TX_RING_SIZE, /* maxsegsize */ 920177050Syongari 0, /* flags */ 921177050Syongari NULL, NULL, /* lockfunc, lockarg */ 922177050Syongari &sc->vr_cdata.vr_tx_ring_tag); 923177050Syongari if (error != 0) { 924177050Syongari device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 925177050Syongari goto fail; 926177050Syongari } 927177050Syongari 928177050Syongari /* Create tag for Rx ring. */ 929177050Syongari error = bus_dma_tag_create( 930177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 931177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 932177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 933177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 934177050Syongari NULL, NULL, /* filter, filterarg */ 935177050Syongari VR_RX_RING_SIZE, /* maxsize */ 936177050Syongari 1, /* nsegments */ 937177050Syongari VR_RX_RING_SIZE, /* maxsegsize */ 938177050Syongari 0, /* flags */ 939177050Syongari NULL, NULL, /* lockfunc, lockarg */ 940177050Syongari &sc->vr_cdata.vr_rx_ring_tag); 941177050Syongari if (error != 0) { 942177050Syongari device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 943177050Syongari goto fail; 944177050Syongari } 945177050Syongari 946177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 947177050Syongari tx_alignment = sizeof(uint32_t); 948177050Syongari else 949177050Syongari tx_alignment = 1; 950177050Syongari /* Create tag for Tx buffers. */ 951177050Syongari error = bus_dma_tag_create( 952177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 953177050Syongari tx_alignment, 0, /* alignment, boundary */ 954177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 955177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 956177050Syongari NULL, NULL, /* filter, filterarg */ 957177050Syongari MCLBYTES * VR_MAXFRAGS, /* maxsize */ 958177050Syongari VR_MAXFRAGS, /* nsegments */ 959177050Syongari MCLBYTES, /* maxsegsize */ 960177050Syongari 0, /* flags */ 961177050Syongari NULL, NULL, /* lockfunc, lockarg */ 962177050Syongari &sc->vr_cdata.vr_tx_tag); 963177050Syongari if (error != 0) { 964177050Syongari device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 965177050Syongari goto fail; 966177050Syongari } 967177050Syongari 968177050Syongari /* Create tag for Rx buffers. */ 969177050Syongari error = bus_dma_tag_create( 970177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 971177050Syongari VR_RX_ALIGN, 0, /* alignment, boundary */ 972177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 973177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 974177050Syongari NULL, NULL, /* filter, filterarg */ 975177050Syongari MCLBYTES, /* maxsize */ 976177050Syongari 1, /* nsegments */ 977177050Syongari MCLBYTES, /* maxsegsize */ 978177050Syongari 0, /* flags */ 979177050Syongari NULL, NULL, /* lockfunc, lockarg */ 980177050Syongari &sc->vr_cdata.vr_rx_tag); 981177050Syongari if (error != 0) { 982177050Syongari device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 983177050Syongari goto fail; 984177050Syongari } 985177050Syongari 986177050Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 987177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 988177050Syongari (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 989177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 990177050Syongari if (error != 0) { 991177050Syongari device_printf(sc->vr_dev, 992177050Syongari "failed to allocate DMA'able memory for Tx ring\n"); 993177050Syongari goto fail; 994177050Syongari } 995177050Syongari 996177050Syongari ctx.vr_busaddr = 0; 997177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 998177050Syongari sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 999177050Syongari VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1000177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1001177050Syongari device_printf(sc->vr_dev, 1002177050Syongari "failed to load DMA'able memory for Tx ring\n"); 1003177050Syongari goto fail; 1004177050Syongari } 1005177050Syongari sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 1006177050Syongari 1007177050Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1008177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 1009177050Syongari (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 1010177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 1011177050Syongari if (error != 0) { 1012177050Syongari device_printf(sc->vr_dev, 1013177050Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1014177050Syongari goto fail; 1015177050Syongari } 1016177050Syongari 1017177050Syongari ctx.vr_busaddr = 0; 1018177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1019177050Syongari sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1020177050Syongari VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1021177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1022177050Syongari device_printf(sc->vr_dev, 1023177050Syongari "failed to load DMA'able memory for Rx ring\n"); 1024177050Syongari goto fail; 1025177050Syongari } 1026177050Syongari sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1027177050Syongari 1028177050Syongari /* Create DMA maps for Tx buffers. */ 1029177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1030177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1031177050Syongari txd->tx_m = NULL; 1032177050Syongari txd->tx_dmamap = NULL; 1033177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1034177050Syongari &txd->tx_dmamap); 1035177050Syongari if (error != 0) { 1036177050Syongari device_printf(sc->vr_dev, 1037177050Syongari "failed to create Tx dmamap\n"); 1038177050Syongari goto fail; 1039177050Syongari } 1040177050Syongari } 1041177050Syongari /* Create DMA maps for Rx buffers. */ 1042177050Syongari if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1043177050Syongari &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1044177050Syongari device_printf(sc->vr_dev, 1045177050Syongari "failed to create spare Rx dmamap\n"); 1046177050Syongari goto fail; 1047177050Syongari } 1048177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1049177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1050177050Syongari rxd->rx_m = NULL; 1051177050Syongari rxd->rx_dmamap = NULL; 1052177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1053177050Syongari &rxd->rx_dmamap); 1054177050Syongari if (error != 0) { 1055177050Syongari device_printf(sc->vr_dev, 1056177050Syongari "failed to create Rx dmamap\n"); 1057177050Syongari goto fail; 1058177050Syongari } 1059177050Syongari } 1060177050Syongari 1061177050Syongarifail: 1062177050Syongari return (error); 1063177050Syongari} 1064177050Syongari 1065177050Syongaristatic void 1066177050Syongarivr_dma_free(struct vr_softc *sc) 1067177050Syongari{ 1068177050Syongari struct vr_txdesc *txd; 1069177050Syongari struct vr_rxdesc *rxd; 1070177050Syongari int i; 1071177050Syongari 1072177050Syongari /* Tx ring. */ 1073177050Syongari if (sc->vr_cdata.vr_tx_ring_tag) { 1074177050Syongari if (sc->vr_cdata.vr_tx_ring_map) 1075177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1076177050Syongari sc->vr_cdata.vr_tx_ring_map); 1077177050Syongari if (sc->vr_cdata.vr_tx_ring_map && 1078177050Syongari sc->vr_rdata.vr_tx_ring) 1079177050Syongari bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1080177050Syongari sc->vr_rdata.vr_tx_ring, 1081177050Syongari sc->vr_cdata.vr_tx_ring_map); 1082177050Syongari sc->vr_rdata.vr_tx_ring = NULL; 1083177050Syongari sc->vr_cdata.vr_tx_ring_map = NULL; 1084177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1085177050Syongari sc->vr_cdata.vr_tx_ring_tag = NULL; 1086177050Syongari } 1087177050Syongari /* Rx ring. */ 1088177050Syongari if (sc->vr_cdata.vr_rx_ring_tag) { 1089177050Syongari if (sc->vr_cdata.vr_rx_ring_map) 1090177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1091177050Syongari sc->vr_cdata.vr_rx_ring_map); 1092177050Syongari if (sc->vr_cdata.vr_rx_ring_map && 1093177050Syongari sc->vr_rdata.vr_rx_ring) 1094177050Syongari bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1095177050Syongari sc->vr_rdata.vr_rx_ring, 1096177050Syongari sc->vr_cdata.vr_rx_ring_map); 1097177050Syongari sc->vr_rdata.vr_rx_ring = NULL; 1098177050Syongari sc->vr_cdata.vr_rx_ring_map = NULL; 1099177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1100177050Syongari sc->vr_cdata.vr_rx_ring_tag = NULL; 1101177050Syongari } 1102177050Syongari /* Tx buffers. */ 1103177050Syongari if (sc->vr_cdata.vr_tx_tag) { 1104177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1105177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1106177050Syongari if (txd->tx_dmamap) { 1107177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1108177050Syongari txd->tx_dmamap); 1109177050Syongari txd->tx_dmamap = NULL; 1110177050Syongari } 1111177050Syongari } 1112177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1113177050Syongari sc->vr_cdata.vr_tx_tag = NULL; 1114177050Syongari } 1115177050Syongari /* Rx buffers. */ 1116177050Syongari if (sc->vr_cdata.vr_rx_tag) { 1117177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1118177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1119177050Syongari if (rxd->rx_dmamap) { 1120177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1121177050Syongari rxd->rx_dmamap); 1122177050Syongari rxd->rx_dmamap = NULL; 1123177050Syongari } 1124177050Syongari } 1125177050Syongari if (sc->vr_cdata.vr_rx_sparemap) { 1126177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1127177050Syongari sc->vr_cdata.vr_rx_sparemap); 1128177050Syongari sc->vr_cdata.vr_rx_sparemap = 0; 1129177050Syongari } 1130177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1131177050Syongari sc->vr_cdata.vr_rx_tag = NULL; 1132177050Syongari } 1133177050Syongari 1134177050Syongari if (sc->vr_cdata.vr_parent_tag) { 1135177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1136177050Syongari sc->vr_cdata.vr_parent_tag = NULL; 1137177050Syongari } 1138177050Syongari} 1139177050Syongari 114041502Swpaul/* 114141502Swpaul * Initialize the transmit descriptors. 114241502Swpaul */ 1143102336Salfredstatic int 1144177050Syongarivr_tx_ring_init(struct vr_softc *sc) 114541502Swpaul{ 1146177050Syongari struct vr_ring_data *rd; 1147177050Syongari struct vr_txdesc *txd; 1148177050Syongari bus_addr_t addr; 114941502Swpaul int i; 115041502Swpaul 1151177050Syongari sc->vr_cdata.vr_tx_prod = 0; 1152177050Syongari sc->vr_cdata.vr_tx_cons = 0; 1153177050Syongari sc->vr_cdata.vr_tx_cnt = 0; 1154177050Syongari sc->vr_cdata.vr_tx_pkts = 0; 1155177050Syongari 1156177050Syongari rd = &sc->vr_rdata; 1157177050Syongari bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1158177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1159177050Syongari if (i == VR_TX_RING_CNT - 1) 1160177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 1161177050Syongari else 1162177050Syongari addr = VR_TX_RING_ADDR(sc, i + 1); 1163177050Syongari rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1164177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1165177050Syongari txd->tx_m = NULL; 116641502Swpaul } 116741502Swpaul 1168177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1169177050Syongari sc->vr_cdata.vr_tx_ring_map, 1170177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1171177050Syongari 1172131503Sbms return (0); 117341502Swpaul} 117441502Swpaul 117541502Swpaul/* 117641502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 117741502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 117841502Swpaul * points back to the first. 117941502Swpaul */ 1180102336Salfredstatic int 1181177050Syongarivr_rx_ring_init(struct vr_softc *sc) 118241502Swpaul{ 1183177050Syongari struct vr_ring_data *rd; 1184177050Syongari struct vr_rxdesc *rxd; 1185177050Syongari bus_addr_t addr; 118641502Swpaul int i; 118741502Swpaul 1188177050Syongari sc->vr_cdata.vr_rx_cons = 0; 1189131518Sbms 1190177050Syongari rd = &sc->vr_rdata; 1191177050Syongari bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1192177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1193177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1194177050Syongari rxd->rx_m = NULL; 1195177050Syongari rxd->desc = &rd->vr_rx_ring[i]; 1196177050Syongari if (i == VR_RX_RING_CNT - 1) 1197177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 1198177050Syongari else 1199177050Syongari addr = VR_RX_RING_ADDR(sc, i + 1); 1200177050Syongari rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1201177050Syongari if (vr_newbuf(sc, i) != 0) 1202131503Sbms return (ENOBUFS); 120341502Swpaul } 120441502Swpaul 1205177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1206177050Syongari sc->vr_cdata.vr_rx_ring_map, 1207177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 120841502Swpaul 1209131503Sbms return (0); 121041502Swpaul} 121141502Swpaul 1212177050Syongaristatic __inline void 1213177050Syongarivr_discard_rxbuf(struct vr_rxdesc *rxd) 1214177050Syongari{ 1215177050Syongari struct vr_desc *desc; 1216177050Syongari 1217177050Syongari desc = rxd->desc; 1218177050Syongari desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1219177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 1220177050Syongari} 1221177050Syongari 122241502Swpaul/* 122341502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 122441502Swpaul * Note: the length fields are only 11 bits wide, which means the 122541502Swpaul * largest size we can specify is 2047. This is important because 122641502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 122741502Swpaul * overflow the field and make a mess. 122841502Swpaul */ 1229102336Salfredstatic int 1230177050Syongarivr_newbuf(struct vr_softc *sc, int idx) 123141502Swpaul{ 1232177050Syongari struct vr_desc *desc; 1233177050Syongari struct vr_rxdesc *rxd; 1234177050Syongari struct mbuf *m; 1235177050Syongari bus_dma_segment_t segs[1]; 1236177050Syongari bus_dmamap_t map; 1237177050Syongari int nsegs; 123841502Swpaul 1239177050Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1240177050Syongari if (m == NULL) 1241177050Syongari return (ENOBUFS); 1242177050Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 1243177050Syongari m_adj(m, sizeof(uint64_t)); 1244177050Syongari 1245177050Syongari if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1246177050Syongari sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1247177050Syongari m_freem(m); 1248177050Syongari return (ENOBUFS); 124941502Swpaul } 1250177050Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 125141502Swpaul 1252177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1253177050Syongari if (rxd->rx_m != NULL) { 1254177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1255177050Syongari BUS_DMASYNC_POSTREAD); 1256177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1257177050Syongari } 1258177050Syongari map = rxd->rx_dmamap; 1259177050Syongari rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1260177050Syongari sc->vr_cdata.vr_rx_sparemap = map; 1261177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1262177050Syongari BUS_DMASYNC_PREREAD); 1263177050Syongari rxd->rx_m = m; 1264177050Syongari desc = rxd->desc; 1265177050Syongari desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1266177050Syongari desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1267177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 126849610Swpaul 1269131503Sbms return (0); 127041502Swpaul} 127141502Swpaul 1272177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1273177050Syongaristatic __inline void 1274177050Syongarivr_fixup_rx(struct mbuf *m) 1275177050Syongari{ 1276177050Syongari uint16_t *src, *dst; 1277177050Syongari int i; 1278177050Syongari 1279177050Syongari src = mtod(m, uint16_t *); 1280177050Syongari dst = src - 1; 1281177050Syongari 1282177050Syongari for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1283177050Syongari *dst++ = *src++; 1284177050Syongari 1285177050Syongari m->m_data -= ETHER_ALIGN; 1286177050Syongari} 1287177050Syongari#endif 1288177050Syongari 128941502Swpaul/* 129041502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 129141502Swpaul * the higher level protocols. 129241502Swpaul */ 1293193096Sattiliostatic int 1294131503Sbmsvr_rxeof(struct vr_softc *sc) 129541502Swpaul{ 1296177050Syongari struct vr_rxdesc *rxd; 1297177050Syongari struct mbuf *m; 1298131503Sbms struct ifnet *ifp; 1299168952Sphk struct vr_desc *cur_rx; 1300193096Sattilio int cons, prog, total_len, rx_npkts; 1301168827Sphk uint32_t rxstat, rxctl; 130241502Swpaul 1303122689Ssam VR_LOCK_ASSERT(sc); 1304147256Sbrooks ifp = sc->vr_ifp; 1305177050Syongari cons = sc->vr_cdata.vr_rx_cons; 1306193096Sattilio rx_npkts = 0; 130741502Swpaul 1308177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1309177050Syongari sc->vr_cdata.vr_rx_ring_map, 1310177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1311177050Syongari 1312177050Syongari for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1313127901Sru#ifdef DEVICE_POLLING 1314150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1315127901Sru if (sc->rxcycles <= 0) 1316127901Sru break; 1317127901Sru sc->rxcycles--; 1318127901Sru } 1319150789Sglebius#endif 1320177050Syongari cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1321177050Syongari rxstat = le32toh(cur_rx->vr_status); 1322177050Syongari rxctl = le32toh(cur_rx->vr_ctl); 1323177050Syongari if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1324177050Syongari break; 132541502Swpaul 1326177050Syongari prog++; 1327177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1328177050Syongari m = rxd->rx_m; 1329177050Syongari 133041502Swpaul /* 133141502Swpaul * If an error occurs, update stats, clear the 133241502Swpaul * status word and leave the mbuf cluster in place: 133341502Swpaul * it should simply get re-used next time this descriptor 1334131503Sbms * comes up in the ring. 1335177050Syongari * We don't support SG in Rx path yet, so discard 1336177050Syongari * partial frame. 133741502Swpaul */ 1338180551Syongari if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1339180551Syongari (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1340177050Syongari (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 134141502Swpaul ifp->if_ierrors++; 1342177050Syongari sc->vr_stat.rx_errors++; 1343110131Ssilby if (rxstat & VR_RXSTAT_CRCERR) 1344177050Syongari sc->vr_stat.rx_crc_errors++; 1345110131Ssilby if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1346177050Syongari sc->vr_stat.rx_alignment++; 1347110131Ssilby if (rxstat & VR_RXSTAT_FIFOOFLOW) 1348177050Syongari sc->vr_stat.rx_fifo_overflows++; 1349110131Ssilby if (rxstat & VR_RXSTAT_GIANT) 1350177050Syongari sc->vr_stat.rx_giants++; 1351110131Ssilby if (rxstat & VR_RXSTAT_RUNT) 1352177050Syongari sc->vr_stat.rx_runts++; 1353110131Ssilby if (rxstat & VR_RXSTAT_BUFFERR) 1354177050Syongari sc->vr_stat.rx_no_buffers++; 1355177050Syongari#ifdef VR_SHOW_ERRORS 1356177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1357177050Syongari __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1358177050Syongari#endif 1359177050Syongari vr_discard_rxbuf(rxd); 136041502Swpaul continue; 136141502Swpaul } 136241502Swpaul 1363177050Syongari if (vr_newbuf(sc, cons) != 0) { 1364177050Syongari ifp->if_iqdrops++; 1365177050Syongari sc->vr_stat.rx_errors++; 1366177050Syongari sc->vr_stat.rx_no_mbufs++; 1367177050Syongari vr_discard_rxbuf(rxd); 1368177050Syongari continue; 1369168827Sphk } 137041502Swpaul 137141502Swpaul /* 137242048Swpaul * XXX The VIA Rhine chip includes the CRC with every 137342048Swpaul * received frame, and there's no way to turn this 137442048Swpaul * behavior off (at least, I can't find anything in 1375131503Sbms * the manual that explains how to do it) so we have 137642048Swpaul * to trim off the CRC manually. 137742048Swpaul */ 1378177050Syongari total_len = VR_RXBYTES(rxstat); 137942048Swpaul total_len -= ETHER_CRC_LEN; 1380177050Syongari m->m_pkthdr.len = m->m_len = total_len; 1381177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1382177050Syongari /* 1383177050Syongari * RX buffers must be 32-bit aligned. 1384177050Syongari * Ignore the alignment problems on the non-strict alignment 1385177050Syongari * platform. The performance hit incurred due to unaligned 1386177050Syongari * accesses is much smaller than the hit produced by forcing 1387177050Syongari * buffer copies all the time. 1388177050Syongari */ 1389177050Syongari vr_fixup_rx(m); 1390177050Syongari#endif 1391177050Syongari m->m_pkthdr.rcvif = ifp; 1392177050Syongari ifp->if_ipackets++; 1393177050Syongari sc->vr_stat.rx_ok++; 1394177050Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1395177050Syongari (rxstat & VR_RXSTAT_FRAG) == 0 && 1396177050Syongari (rxctl & VR_RXCTL_IP) != 0) { 1397177050Syongari /* Checksum is valid for non-fragmented IP packets. */ 1398177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1399177050Syongari if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1400177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1401177050Syongari if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1402177050Syongari m->m_pkthdr.csum_flags |= 1403177050Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1404177050Syongari if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1405177050Syongari m->m_pkthdr.csum_data = 0xffff; 1406177050Syongari } 1407177050Syongari } 140841502Swpaul } 1409122689Ssam VR_UNLOCK(sc); 1410106936Ssam (*ifp->if_input)(ifp, m); 1411122689Ssam VR_LOCK(sc); 1412193096Sattilio rx_npkts++; 141341502Swpaul } 141441502Swpaul 1415177050Syongari if (prog > 0) { 1416177050Syongari sc->vr_cdata.vr_rx_cons = cons; 1417177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1418177050Syongari sc->vr_cdata.vr_rx_ring_map, 1419177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1420131503Sbms } 1421193096Sattilio return (rx_npkts); 142241502Swpaul} 142341502Swpaul 142441502Swpaul/* 142541502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 142641502Swpaul * the list buffers. 142741502Swpaul */ 1428102336Salfredstatic void 1429131503Sbmsvr_txeof(struct vr_softc *sc) 143041502Swpaul{ 1431177050Syongari struct vr_txdesc *txd; 1432168952Sphk struct vr_desc *cur_tx; 1433177050Syongari struct ifnet *ifp; 1434177050Syongari uint32_t txctl, txstat; 1435177050Syongari int cons, prod; 143641502Swpaul 1437131518Sbms VR_LOCK_ASSERT(sc); 143841502Swpaul 1439177050Syongari cons = sc->vr_cdata.vr_tx_cons; 1440177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1441177050Syongari if (cons == prod) 1442177050Syongari return; 1443177050Syongari 1444177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1445177050Syongari sc->vr_cdata.vr_tx_ring_map, 1446177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1447177050Syongari 1448177050Syongari ifp = sc->vr_ifp; 144941502Swpaul /* 145041502Swpaul * Go through our tx list and free mbufs for those 145141502Swpaul * frames that have been transmitted. 145241502Swpaul */ 1453177050Syongari for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1454177050Syongari cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1455177050Syongari txctl = le32toh(cur_tx->vr_ctl); 1456177050Syongari txstat = le32toh(cur_tx->vr_status); 1457177050Syongari if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1458177050Syongari break; 145941502Swpaul 1460177050Syongari sc->vr_cdata.vr_tx_cnt--; 1461177050Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1462177050Syongari /* Only the first descriptor in the chain is valid. */ 1463177050Syongari if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1464177050Syongari continue; 146541502Swpaul 1466177050Syongari txd = &sc->vr_cdata.vr_txdesc[cons]; 1467177050Syongari KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1468177050Syongari __func__)); 1469177050Syongari 1470177050Syongari if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1471177050Syongari ifp->if_oerrors++; 1472177050Syongari sc->vr_stat.tx_errors++; 1473177050Syongari if ((txstat & VR_TXSTAT_ABRT) != 0) { 1474177050Syongari /* Give up and restart Tx. */ 1475177050Syongari sc->vr_stat.tx_abort++; 1476177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1477177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1478177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1479177050Syongari txd->tx_dmamap); 1480177050Syongari m_freem(txd->tx_m); 1481177050Syongari txd->tx_m = NULL; 1482177050Syongari VR_INC(cons, VR_TX_RING_CNT); 1483177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1484177050Syongari if (vr_tx_stop(sc) != 0) { 1485177050Syongari device_printf(sc->vr_dev, 1486177050Syongari "%s: Tx shutdown error -- " 1487177050Syongari "resetting\n", __func__); 1488177050Syongari sc->vr_flags |= VR_F_RESTART; 1489177050Syongari return; 1490177050Syongari } 1491177050Syongari vr_tx_start(sc); 1492110131Ssilby break; 1493110131Ssilby } 1494177050Syongari if ((sc->vr_revid < REV_ID_VT3071_A && 1495177050Syongari (txstat & VR_TXSTAT_UNDERRUN)) || 1496177050Syongari (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1497177050Syongari sc->vr_stat.tx_underrun++; 1498177050Syongari /* Retry and restart Tx. */ 1499177050Syongari sc->vr_cdata.vr_tx_cnt++; 1500177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1501177050Syongari cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1502177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1503177050Syongari sc->vr_cdata.vr_tx_ring_map, 1504177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1505177050Syongari vr_tx_underrun(sc); 1506177050Syongari return; 1507177050Syongari } 1508177050Syongari if ((txstat & VR_TXSTAT_DEFER) != 0) { 150941502Swpaul ifp->if_collisions++; 1510177050Syongari sc->vr_stat.tx_collisions++; 1511177050Syongari } 1512177050Syongari if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 151341502Swpaul ifp->if_collisions++; 1514177050Syongari sc->vr_stat.tx_late_collisions++; 1515177050Syongari } 1516177050Syongari } else { 1517177050Syongari sc->vr_stat.tx_ok++; 1518177050Syongari ifp->if_opackets++; 151941502Swpaul } 152041502Swpaul 1521177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1522177050Syongari BUS_DMASYNC_POSTWRITE); 1523177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1524177050Syongari if (sc->vr_revid < REV_ID_VT3071_A) { 1525177050Syongari ifp->if_collisions += 1526177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1527177050Syongari sc->vr_stat.tx_collisions += 1528177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1529177050Syongari } else { 1530177050Syongari ifp->if_collisions += (txstat & 0x0f); 1531177050Syongari sc->vr_stat.tx_collisions += (txstat & 0x0f); 1532177050Syongari } 1533177050Syongari m_freem(txd->tx_m); 1534177050Syongari txd->tx_m = NULL; 1535177050Syongari } 153641502Swpaul 1537177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1538177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 1539177050Syongari sc->vr_watchdog_timer = 0; 154041502Swpaul} 154141502Swpaul 1542102336Salfredstatic void 1543131503Sbmsvr_tick(void *xsc) 154451432Swpaul{ 1545177050Syongari struct vr_softc *sc; 154651432Swpaul struct mii_data *mii; 154751432Swpaul 1548177050Syongari sc = (struct vr_softc *)xsc; 1549177050Syongari 1550151911Sjhb VR_LOCK_ASSERT(sc); 1551131517Sbms 1552177050Syongari if ((sc->vr_flags & VR_F_RESTART) != 0) { 1553162315Sglebius device_printf(sc->vr_dev, "restarting\n"); 1554177050Syongari sc->vr_stat.num_restart++; 1555211765Syongari sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1556131844Sbms vr_init_locked(sc); 1557110131Ssilby sc->vr_flags &= ~VR_F_RESTART; 1558110131Ssilby } 1559110131Ssilby 156051432Swpaul mii = device_get_softc(sc->vr_miibus); 156151432Swpaul mii_tick(mii); 1562177050Syongari vr_watchdog(sc); 1563151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 156451432Swpaul} 156551432Swpaul 1566127901Sru#ifdef DEVICE_POLLING 1567127901Srustatic poll_handler_t vr_poll; 1568131844Sbmsstatic poll_handler_t vr_poll_locked; 1569127901Sru 1570193096Sattiliostatic int 1571127901Sruvr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1572127901Sru{ 1573177050Syongari struct vr_softc *sc; 1574193096Sattilio int rx_npkts; 1575127901Sru 1576177050Syongari sc = ifp->if_softc; 1577193096Sattilio rx_npkts = 0; 1578177050Syongari 1579127901Sru VR_LOCK(sc); 1580177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1581193096Sattilio rx_npkts = vr_poll_locked(ifp, cmd, count); 1582131844Sbms VR_UNLOCK(sc); 1583193096Sattilio return (rx_npkts); 1584131844Sbms} 1585131517Sbms 1586193096Sattiliostatic int 1587131844Sbmsvr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1588131844Sbms{ 1589177050Syongari struct vr_softc *sc; 1590193096Sattilio int rx_npkts; 1591131844Sbms 1592177050Syongari sc = ifp->if_softc; 1593177050Syongari 1594131844Sbms VR_LOCK_ASSERT(sc); 1595131844Sbms 1596127901Sru sc->rxcycles = count; 1597193096Sattilio rx_npkts = vr_rxeof(sc); 1598127901Sru vr_txeof(sc); 1599133006Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1600131844Sbms vr_start_locked(ifp); 1601127901Sru 1602131503Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1603131503Sbms uint16_t status; 1604127901Sru 1605131503Sbms /* Also check status register. */ 1606127901Sru status = CSR_READ_2(sc, VR_ISR); 1607127901Sru if (status) 1608127901Sru CSR_WRITE_2(sc, VR_ISR, status); 1609127901Sru 1610127901Sru if ((status & VR_INTRS) == 0) 1611193096Sattilio return (rx_npkts); 1612127901Sru 1613177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1614177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1615177050Syongari if (vr_error(sc, status) != 0) 1616193096Sattilio return (rx_npkts); 1617127901Sru } 1618177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1619177050Syongari#ifdef VR_SHOW_ERRORS 1620177050Syongari device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1621177050Syongari __func__, status, VR_ISR_ERR_BITS); 1622177050Syongari#endif 1623177050Syongari vr_rx_start(sc); 1624127901Sru } 1625177050Syongari } 1626193096Sattilio return (rx_npkts); 1627177050Syongari} 1628177050Syongari#endif /* DEVICE_POLLING */ 1629127901Sru 1630177050Syongari/* Back off the transmit threshold. */ 1631177050Syongaristatic void 1632177050Syongarivr_tx_underrun(struct vr_softc *sc) 1633177050Syongari{ 1634177050Syongari int thresh; 1635127901Sru 1636177050Syongari device_printf(sc->vr_dev, "Tx underrun -- "); 1637177050Syongari if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1638177050Syongari thresh = sc->vr_txthresh; 1639177050Syongari sc->vr_txthresh++; 1640177050Syongari if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1641177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 1642177050Syongari printf("using store and forward mode\n"); 1643177050Syongari } else 1644177050Syongari printf("increasing Tx threshold(%d -> %d)\n", 1645177050Syongari vr_tx_threshold_tables[thresh].value, 1646177050Syongari vr_tx_threshold_tables[thresh + 1].value); 1647177050Syongari } else 1648177050Syongari printf("\n"); 1649177050Syongari sc->vr_stat.tx_underrun++; 1650177050Syongari if (vr_tx_stop(sc) != 0) { 1651177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1652177050Syongari "resetting\n", __func__); 1653177050Syongari sc->vr_flags |= VR_F_RESTART; 1654177050Syongari return; 1655127901Sru } 1656177050Syongari vr_tx_start(sc); 1657127901Sru} 1658127901Sru 1659127901Srustatic void 1660131503Sbmsvr_intr(void *arg) 166141502Swpaul{ 1662177050Syongari struct vr_softc *sc; 1663177050Syongari struct ifnet *ifp; 1664131503Sbms uint16_t status; 166541502Swpaul 1666177050Syongari sc = (struct vr_softc *)arg; 1667177050Syongari 166867087Swpaul VR_LOCK(sc); 1669131844Sbms 1670177050Syongari if (sc->vr_suspended != 0) 1671131844Sbms goto done_locked; 1672131844Sbms 1673177050Syongari status = CSR_READ_2(sc, VR_ISR); 1674177050Syongari if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1675177050Syongari goto done_locked; 1676177050Syongari 1677177050Syongari ifp = sc->vr_ifp; 1678127901Sru#ifdef DEVICE_POLLING 1679177050Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1680131844Sbms goto done_locked; 1681150789Sglebius#endif 1682131844Sbms 1683131844Sbms /* Suppress unwanted interrupts. */ 1684177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1685177050Syongari (sc->vr_flags & VR_F_RESTART) != 0) { 1686177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1687177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1688131844Sbms goto done_locked; 168941502Swpaul } 169041502Swpaul 169141502Swpaul /* Disable interrupts. */ 169241502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 169341502Swpaul 1694177050Syongari for (; (status & VR_INTRS) != 0;) { 1695177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1696177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1697177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1698177050Syongari if (vr_error(sc, status) != 0) { 1699177050Syongari VR_UNLOCK(sc); 1700177050Syongari return; 1701177050Syongari } 1702177050Syongari } 1703177050Syongari vr_rxeof(sc); 1704177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1705177050Syongari#ifdef VR_SHOW_ERRORS 1706177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1707177050Syongari __func__, status, VR_ISR_ERR_BITS); 1708177050Syongari#endif 1709177050Syongari /* Restart Rx if RxDMA SM was stopped. */ 1710177050Syongari vr_rx_start(sc); 1711177050Syongari } 1712177050Syongari vr_txeof(sc); 171341502Swpaul status = CSR_READ_2(sc, VR_ISR); 1714177050Syongari } 1715168813Sphk 1716177050Syongari /* Re-enable interrupts. */ 1717177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 171841502Swpaul 1719177050Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1720177050Syongari vr_start_locked(ifp); 172141502Swpaul 1722177050Syongaridone_locked: 1723177050Syongari VR_UNLOCK(sc); 1724177050Syongari} 172541502Swpaul 1726177050Syongaristatic int 1727177050Syongarivr_error(struct vr_softc *sc, uint16_t status) 1728177050Syongari{ 1729177050Syongari uint16_t pcis; 1730110131Ssilby 1731177050Syongari status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1732177050Syongari if ((status & VR_ISR_BUSERR) != 0) { 1733177050Syongari status &= ~VR_ISR_BUSERR; 1734177050Syongari sc->vr_stat.bus_errors++; 1735177050Syongari /* Disable further interrupts. */ 1736177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1737177050Syongari pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1738177050Syongari device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1739177050Syongari "resetting\n", pcis); 1740177050Syongari pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1741177050Syongari sc->vr_flags |= VR_F_RESTART; 1742177050Syongari return (EAGAIN); 1743177050Syongari } 1744177050Syongari if ((status & VR_ISR_LINKSTAT2) != 0) { 1745177050Syongari /* Link state change, duplex changes etc. */ 1746177050Syongari status &= ~VR_ISR_LINKSTAT2; 1747177050Syongari } 1748177050Syongari if ((status & VR_ISR_STATSOFLOW) != 0) { 1749177050Syongari status &= ~VR_ISR_STATSOFLOW; 1750177050Syongari if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1751177050Syongari /* Update MIB counters. */ 175241502Swpaul } 1753177050Syongari } 175441502Swpaul 1755177050Syongari if (status != 0) 1756177050Syongari device_printf(sc->vr_dev, 1757177050Syongari "unhandled interrupt, status = 0x%04x\n", status); 1758177050Syongari return (0); 1759177050Syongari} 1760177050Syongari 1761177050Syongari/* 1762177050Syongari * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1763177050Syongari * pointers to the fragment pointers. 1764177050Syongari */ 1765177050Syongaristatic int 1766177050Syongarivr_encap(struct vr_softc *sc, struct mbuf **m_head) 1767177050Syongari{ 1768177050Syongari struct vr_txdesc *txd; 1769177050Syongari struct vr_desc *desc; 1770177050Syongari struct mbuf *m; 1771177050Syongari bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1772177050Syongari uint32_t csum_flags, txctl; 1773177050Syongari int error, i, nsegs, prod, si; 1774177050Syongari int padlen; 1775177050Syongari 1776177050Syongari VR_LOCK_ASSERT(sc); 1777177050Syongari 1778177050Syongari M_ASSERTPKTHDR((*m_head)); 1779177050Syongari 1780177050Syongari /* 1781177050Syongari * Some VIA Rhine wants packet buffers to be longword 1782177050Syongari * aligned, but very often our mbufs aren't. Rather than 1783177050Syongari * waste time trying to decide when to copy and when not 1784177050Syongari * to copy, just do it all the time. 1785177050Syongari */ 1786177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1787177050Syongari m = m_defrag(*m_head, M_DONTWAIT); 1788177050Syongari if (m == NULL) { 1789177050Syongari m_freem(*m_head); 1790177050Syongari *m_head = NULL; 1791177050Syongari return (ENOBUFS); 179241502Swpaul } 1793177050Syongari *m_head = m; 1794177050Syongari } 179541502Swpaul 1796177050Syongari /* 1797177050Syongari * The Rhine chip doesn't auto-pad, so we have to make 1798177050Syongari * sure to pad short frames out to the minimum frame length 1799177050Syongari * ourselves. 1800177050Syongari */ 1801177050Syongari if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1802177050Syongari m = *m_head; 1803177050Syongari padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1804177050Syongari if (M_WRITABLE(m) == 0) { 1805177050Syongari /* Get a writable copy. */ 1806177050Syongari m = m_dup(*m_head, M_DONTWAIT); 1807177050Syongari m_freem(*m_head); 1808177050Syongari if (m == NULL) { 1809177050Syongari *m_head = NULL; 1810177050Syongari return (ENOBUFS); 1811127901Sru } 1812177050Syongari *m_head = m; 181341502Swpaul } 1814177050Syongari if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1815177050Syongari m = m_defrag(m, M_DONTWAIT); 1816177050Syongari if (m == NULL) { 1817177050Syongari m_freem(*m_head); 1818177050Syongari *m_head = NULL; 1819177050Syongari return (ENOBUFS); 1820177050Syongari } 1821177050Syongari } 1822177050Syongari /* 1823177050Syongari * Manually pad short frames, and zero the pad space 1824177050Syongari * to avoid leaking data. 1825177050Syongari */ 1826177050Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1827177050Syongari m->m_pkthdr.len += padlen; 1828177050Syongari m->m_len = m->m_pkthdr.len; 1829177050Syongari *m_head = m; 183041502Swpaul } 183141502Swpaul 1832177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1833177050Syongari txd = &sc->vr_cdata.vr_txdesc[prod]; 1834177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1835177050Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1836177050Syongari if (error == EFBIG) { 1837177050Syongari m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1838177050Syongari if (m == NULL) { 1839177050Syongari m_freem(*m_head); 1840177050Syongari *m_head = NULL; 1841177050Syongari return (ENOBUFS); 1842177050Syongari } 1843177050Syongari *m_head = m; 1844177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1845177050Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1846177050Syongari if (error != 0) { 1847177050Syongari m_freem(*m_head); 1848177050Syongari *m_head = NULL; 1849177050Syongari return (error); 1850177050Syongari } 1851177050Syongari } else if (error != 0) 1852177050Syongari return (error); 1853177050Syongari if (nsegs == 0) { 1854177050Syongari m_freem(*m_head); 1855177050Syongari *m_head = NULL; 1856177050Syongari return (EIO); 1857177050Syongari } 185841502Swpaul 1859177050Syongari /* Check number of available descriptors. */ 1860177050Syongari if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1861177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1862177050Syongari return (ENOBUFS); 1863177050Syongari } 1864131844Sbms 1865177050Syongari txd->tx_m = *m_head; 1866177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1867177050Syongari BUS_DMASYNC_PREWRITE); 1868177050Syongari 1869177050Syongari /* Set checksum offload. */ 1870177050Syongari csum_flags = 0; 1871177050Syongari if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1872177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1873177050Syongari csum_flags |= VR_TXCTL_IPCSUM; 1874177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1875177050Syongari csum_flags |= VR_TXCTL_TCPCSUM; 1876177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1877177050Syongari csum_flags |= VR_TXCTL_UDPCSUM; 1878177050Syongari } 1879177050Syongari 1880177050Syongari /* 1881177050Syongari * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1882177050Syongari * is required for all descriptors regardless of single or 1883177050Syongari * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1884177050Syongari * the first descriptor for a multi-fragmented frames. Without 1885177050Syongari * that VIA Rhine chip generates Tx underrun interrupts and can't 1886177050Syongari * send any frames. 1887177050Syongari */ 1888177050Syongari si = prod; 1889177050Syongari for (i = 0; i < nsegs; i++) { 1890177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1891177050Syongari desc->vr_status = 0; 1892177050Syongari txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1893177050Syongari if (i == 0) 1894177050Syongari txctl |= VR_TXCTL_FIRSTFRAG; 1895177050Syongari desc->vr_ctl = htole32(txctl); 1896177050Syongari desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1897177050Syongari sc->vr_cdata.vr_tx_cnt++; 1898177050Syongari VR_INC(prod, VR_TX_RING_CNT); 1899177050Syongari } 1900177050Syongari /* Update producer index. */ 1901177050Syongari sc->vr_cdata.vr_tx_prod = prod; 1902177050Syongari 1903177050Syongari prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1904177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1905177050Syongari 1906177050Syongari /* 1907177050Syongari * Set EOP on the last desciptor and reuqest Tx completion 1908177050Syongari * interrupt for every VR_TX_INTR_THRESH-th frames. 1909177050Syongari */ 1910177050Syongari VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1911177050Syongari if (sc->vr_cdata.vr_tx_pkts == 0) 1912177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1913177050Syongari else 1914177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1915177050Syongari 1916177050Syongari /* Lastly turn the first descriptor ownership to hardware. */ 1917177050Syongari desc = &sc->vr_rdata.vr_tx_ring[si]; 1918177050Syongari desc->vr_status |= htole32(VR_TXSTAT_OWN); 1919177050Syongari 1920177050Syongari /* Sync descriptors. */ 1921177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1922177050Syongari sc->vr_cdata.vr_tx_ring_map, 1923177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1924177050Syongari 1925177050Syongari return (0); 192641502Swpaul} 192741502Swpaul 1928102336Salfredstatic void 1929131503Sbmsvr_start(struct ifnet *ifp) 193041502Swpaul{ 1931177050Syongari struct vr_softc *sc; 1932131844Sbms 1933177050Syongari sc = ifp->if_softc; 1934131844Sbms VR_LOCK(sc); 1935131844Sbms vr_start_locked(ifp); 1936131844Sbms VR_UNLOCK(sc); 1937131844Sbms} 1938131844Sbms 1939131844Sbmsstatic void 1940131844Sbmsvr_start_locked(struct ifnet *ifp) 1941131844Sbms{ 1942177050Syongari struct vr_softc *sc; 1943177050Syongari struct mbuf *m_head; 1944177050Syongari int enq; 194541502Swpaul 1946177050Syongari sc = ifp->if_softc; 1947177050Syongari 1948177050Syongari VR_LOCK_ASSERT(sc); 1949177050Syongari 1950177050Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1951177050Syongari IFF_DRV_RUNNING || sc->vr_link == 0) 1952127901Sru return; 1953127901Sru 1954177050Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1955177050Syongari sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1956177050Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 195741502Swpaul if (m_head == NULL) 195841502Swpaul break; 1959168813Sphk /* 1960177050Syongari * Pack the data into the transmit ring. If we 1961177050Syongari * don't have room, set the OACTIVE flag and wait 1962177050Syongari * for the NIC to drain the ring. 1963168813Sphk */ 1964177050Syongari if (vr_encap(sc, &m_head)) { 1965177050Syongari if (m_head == NULL) 1966168813Sphk break; 1967177050Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1968177050Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1969177050Syongari break; 1970168813Sphk } 197151583Swpaul 1972177050Syongari enq++; 1973168813Sphk /* 1974168813Sphk * If there's a BPF listener, bounce a copy of this frame 1975168813Sphk * to him. 1976168813Sphk */ 1977177050Syongari ETHER_BPF_MTAP(ifp, m_head); 1978127901Sru } 1979177050Syongari 1980177050Syongari if (enq > 0) { 1981177050Syongari /* Tell the chip to start transmitting. */ 1982177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1983177050Syongari /* Set a timeout in case the chip goes out to lunch. */ 1984177050Syongari sc->vr_watchdog_timer = 5; 1985177050Syongari } 1986131844Sbms} 198741502Swpaul 1988131844Sbmsstatic void 1989131844Sbmsvr_init(void *xsc) 1990131844Sbms{ 1991177050Syongari struct vr_softc *sc; 1992131844Sbms 1993177050Syongari sc = (struct vr_softc *)xsc; 1994131844Sbms VR_LOCK(sc); 1995131844Sbms vr_init_locked(sc); 199667087Swpaul VR_UNLOCK(sc); 199741502Swpaul} 199841502Swpaul 1999102336Salfredstatic void 2000131844Sbmsvr_init_locked(struct vr_softc *sc) 200141502Swpaul{ 2002177050Syongari struct ifnet *ifp; 200351432Swpaul struct mii_data *mii; 2004177050Syongari bus_addr_t addr; 200573963Swpaul int i; 200641502Swpaul 2007131844Sbms VR_LOCK_ASSERT(sc); 200841502Swpaul 2009177050Syongari ifp = sc->vr_ifp; 201051432Swpaul mii = device_get_softc(sc->vr_miibus); 201141502Swpaul 2012211765Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2013211765Syongari return; 2014211765Syongari 2015131503Sbms /* Cancel pending I/O and free all RX/TX buffers. */ 201641502Swpaul vr_stop(sc); 201741502Swpaul vr_reset(sc); 201841502Swpaul 2019131503Sbms /* Set our station address. */ 202073963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 2021152315Sru CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2022131503Sbms 2023131503Sbms /* Set DMA size. */ 2024101375Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2025101375Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 202673963Swpaul 2027131503Sbms /* 2028101375Ssilby * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2029101108Ssilby * so we must set both. 2030101108Ssilby */ 2031101108Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2032110131Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2033101108Ssilby 2034101108Ssilby VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2035177050Syongari VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2036101108Ssilby 203741502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2038110131Ssilby VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 203941502Swpaul 204041502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2041177050Syongari VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 204241502Swpaul 204341502Swpaul /* Init circular RX list. */ 2044177050Syongari if (vr_rx_ring_init(sc) != 0) { 2045162315Sglebius device_printf(sc->vr_dev, 2046151773Sjhb "initialization failed: no memory for rx buffers\n"); 204741502Swpaul vr_stop(sc); 204841502Swpaul return; 204941502Swpaul } 205041502Swpaul 2051131503Sbms /* Init tx descriptors. */ 2052177050Syongari vr_tx_ring_init(sc); 205341502Swpaul 2054177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2055180552Syongari uint8_t vcam[2] = { 0, 0 }; 2056180552Syongari 2057180552Syongari /* Disable VLAN hardware tag insertion/stripping. */ 2058180552Syongari VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2059180552Syongari /* Disable VLAN hardware filtering. */ 2060180552Syongari VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2061180552Syongari /* Disable all CAM entries. */ 2062180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, 0); 2063180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 0); 2064180552Syongari /* Enable the first VLAN CAM. */ 2065180552Syongari vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2066180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 1); 2067177050Syongari } 206841502Swpaul 206941502Swpaul /* 2070177050Syongari * Set up receive filter. 207141502Swpaul */ 2072177050Syongari vr_set_filter(sc); 207341502Swpaul 207441502Swpaul /* 2075177050Syongari * Load the address of the RX ring. 207641502Swpaul */ 2077177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 2078177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2079177050Syongari /* 2080177050Syongari * Load the address of the TX ring. 2081177050Syongari */ 2082177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 2083177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2084177050Syongari /* Default : full-duplex, no Tx poll. */ 2085177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 208641502Swpaul 2087177050Syongari /* Set flow-control parameters for Rhine III. */ 2088177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 2089177050Syongari /* Rx buffer count available for incoming packet. */ 2090177050Syongari CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT); 2091177050Syongari /* 2092177050Syongari * Tx pause low threshold : 16 free receive buffers 2093177050Syongari * Tx pause XON high threshold : 48 free receive buffers 2094177050Syongari */ 2095177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, 2096177050Syongari VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF); 2097177050Syongari /* Set Tx pause timer. */ 2098177050Syongari CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2099177050Syongari } 2100177050Syongari 210141502Swpaul /* Enable receiver and transmitter. */ 2102177050Syongari CSR_WRITE_1(sc, VR_CR0, 2103177050Syongari VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 210441502Swpaul 2105127901Sru CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2106127901Sru#ifdef DEVICE_POLLING 210741502Swpaul /* 2108127901Sru * Disable interrupts if we are polling. 2109127901Sru */ 2110150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 2111127901Sru CSR_WRITE_2(sc, VR_IMR, 0); 2112131503Sbms else 2113150789Sglebius#endif 2114127901Sru /* 2115177050Syongari * Enable interrupts and disable MII intrs. 211641502Swpaul */ 211741502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2118177050Syongari if (sc->vr_revid > REV_ID_VT6102_A) 2119177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 212041502Swpaul 2121177050Syongari sc->vr_link = 0; 212251432Swpaul mii_mediachg(mii); 212341502Swpaul 2124148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2125148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 212641502Swpaul 2127151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 212841502Swpaul} 212941502Swpaul 213041502Swpaul/* 213141502Swpaul * Set media options. 213241502Swpaul */ 2133102336Salfredstatic int 2134131503Sbmsvr_ifmedia_upd(struct ifnet *ifp) 213541502Swpaul{ 2136177050Syongari struct vr_softc *sc; 2137177050Syongari struct mii_data *mii; 2138177050Syongari struct mii_softc *miisc; 2139177050Syongari int error; 214041502Swpaul 2141177050Syongari sc = ifp->if_softc; 2142177050Syongari VR_LOCK(sc); 2143177050Syongari mii = device_get_softc(sc->vr_miibus); 2144177050Syongari if (mii->mii_instance) { 2145177050Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2146177050Syongari mii_phy_reset(miisc); 2147177050Syongari } 2148177050Syongari error = mii_mediachg(mii); 2149177050Syongari VR_UNLOCK(sc); 215041502Swpaul 2151177050Syongari return (error); 215241502Swpaul} 215341502Swpaul 215441502Swpaul/* 215541502Swpaul * Report current media status. 215641502Swpaul */ 2157102336Salfredstatic void 2158131503Sbmsvr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 215941502Swpaul{ 2160177050Syongari struct vr_softc *sc; 216151432Swpaul struct mii_data *mii; 216241502Swpaul 2163177050Syongari sc = ifp->if_softc; 216451432Swpaul mii = device_get_softc(sc->vr_miibus); 2165133468Sscottl VR_LOCK(sc); 216651432Swpaul mii_pollstat(mii); 2167133468Sscottl VR_UNLOCK(sc); 216851432Swpaul ifmr->ifm_active = mii->mii_media_active; 216951432Swpaul ifmr->ifm_status = mii->mii_media_status; 217041502Swpaul} 217141502Swpaul 2172102336Salfredstatic int 2173131503Sbmsvr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 217441502Swpaul{ 2175177050Syongari struct vr_softc *sc; 2176177050Syongari struct ifreq *ifr; 217751432Swpaul struct mii_data *mii; 2178177050Syongari int error, mask; 217941502Swpaul 2180177050Syongari sc = ifp->if_softc; 2181177050Syongari ifr = (struct ifreq *)data; 2182177050Syongari error = 0; 2183177050Syongari 2184131503Sbms switch (command) { 218541502Swpaul case SIOCSIFFLAGS: 2186131844Sbms VR_LOCK(sc); 218741502Swpaul if (ifp->if_flags & IFF_UP) { 2188177050Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2189177050Syongari if ((ifp->if_flags ^ sc->vr_if_flags) & 2190177050Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2191177050Syongari vr_set_filter(sc); 2192177050Syongari } else { 2193177050Syongari if (sc->vr_detach == 0) 2194177050Syongari vr_init_locked(sc); 2195177050Syongari } 219641502Swpaul } else { 2197148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 219841502Swpaul vr_stop(sc); 219941502Swpaul } 2200177050Syongari sc->vr_if_flags = ifp->if_flags; 2201131844Sbms VR_UNLOCK(sc); 220241502Swpaul break; 220341502Swpaul case SIOCADDMULTI: 220441502Swpaul case SIOCDELMULTI: 2205131518Sbms VR_LOCK(sc); 2206177050Syongari vr_set_filter(sc); 2207131518Sbms VR_UNLOCK(sc); 220841502Swpaul break; 220941502Swpaul case SIOCGIFMEDIA: 221041502Swpaul case SIOCSIFMEDIA: 221151432Swpaul mii = device_get_softc(sc->vr_miibus); 221251432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 221341502Swpaul break; 2214128118Sru case SIOCSIFCAP: 2215177050Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2216150789Sglebius#ifdef DEVICE_POLLING 2217177050Syongari if (mask & IFCAP_POLLING) { 2218177050Syongari if (ifr->ifr_reqcap & IFCAP_POLLING) { 2219177050Syongari error = ether_poll_register(vr_poll, ifp); 2220177050Syongari if (error != 0) 2221177050Syongari break; 2222177050Syongari VR_LOCK(sc); 2223177050Syongari /* Disable interrupts. */ 2224177050Syongari CSR_WRITE_2(sc, VR_IMR, 0x0000); 2225177050Syongari ifp->if_capenable |= IFCAP_POLLING; 2226177050Syongari VR_UNLOCK(sc); 2227177050Syongari } else { 2228177050Syongari error = ether_poll_deregister(ifp); 2229177050Syongari /* Enable interrupts. */ 2230177050Syongari VR_LOCK(sc); 2231177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2232177050Syongari ifp->if_capenable &= ~IFCAP_POLLING; 2233177050Syongari VR_UNLOCK(sc); 2234177050Syongari } 2235150789Sglebius } 2236177050Syongari#endif /* DEVICE_POLLING */ 2237177050Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2238177050Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2239177050Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2240177050Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2241177050Syongari ifp->if_hwassist |= VR_CSUM_FEATURES; 2242177050Syongari else 2243177050Syongari ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2244150789Sglebius } 2245177050Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2246177050Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2247177050Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2248177050Syongari if ((mask & IFCAP_WOL_UCAST) != 0 && 2249177050Syongari (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2250177050Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2251177050Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2252177050Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2253177050Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2254128118Sru break; 225541502Swpaul default: 2256106936Ssam error = ether_ioctl(ifp, command, data); 225741502Swpaul break; 225841502Swpaul } 225941502Swpaul 2260131503Sbms return (error); 226141502Swpaul} 226241502Swpaul 2263102336Salfredstatic void 2264177050Syongarivr_watchdog(struct vr_softc *sc) 226541502Swpaul{ 2266177050Syongari struct ifnet *ifp; 226741502Swpaul 2268177050Syongari VR_LOCK_ASSERT(sc); 2269131844Sbms 2270177050Syongari if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2271177050Syongari return; 2272177050Syongari 2273177050Syongari ifp = sc->vr_ifp; 2274177050Syongari /* 2275177050Syongari * Reclaim first as we don't request interrupt for every packets. 2276177050Syongari */ 2277177050Syongari vr_txeof(sc); 2278177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 2279177050Syongari return; 2280177050Syongari 2281177050Syongari if (sc->vr_link == 0) { 2282177050Syongari if (bootverbose) 2283177050Syongari if_printf(sc->vr_ifp, "watchdog timeout " 2284177050Syongari "(missed link)\n"); 2285177050Syongari ifp->if_oerrors++; 2286211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2287177050Syongari vr_init_locked(sc); 2288177050Syongari return; 2289177050Syongari } 2290177050Syongari 229141502Swpaul ifp->if_oerrors++; 2292151773Sjhb if_printf(ifp, "watchdog timeout\n"); 229341502Swpaul 2294211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2295131844Sbms vr_init_locked(sc); 2296131518Sbms 2297132986Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2298131844Sbms vr_start_locked(ifp); 2299177050Syongari} 2300131844Sbms 2301177050Syongaristatic void 2302177050Syongarivr_tx_start(struct vr_softc *sc) 2303177050Syongari{ 2304177050Syongari bus_addr_t addr; 2305177050Syongari uint8_t cmd; 2306177050Syongari 2307177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2308177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) { 2309177050Syongari addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2310177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2311177050Syongari cmd |= VR_CR0_TX_ON; 2312177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2313177050Syongari } 2314177050Syongari if (sc->vr_cdata.vr_tx_cnt != 0) { 2315177050Syongari sc->vr_watchdog_timer = 5; 2316177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2317177050Syongari } 231841502Swpaul} 231941502Swpaul 2320177050Syongaristatic void 2321177050Syongarivr_rx_start(struct vr_softc *sc) 2322177050Syongari{ 2323177050Syongari bus_addr_t addr; 2324177050Syongari uint8_t cmd; 2325177050Syongari 2326177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2327177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) { 2328177050Syongari addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2329177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2330177050Syongari cmd |= VR_CR0_RX_ON; 2331177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2332177050Syongari } 2333177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2334177050Syongari} 2335177050Syongari 2336177050Syongaristatic int 2337177050Syongarivr_tx_stop(struct vr_softc *sc) 2338177050Syongari{ 2339177050Syongari int i; 2340177050Syongari uint8_t cmd; 2341177050Syongari 2342177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2343177050Syongari if ((cmd & VR_CR0_TX_ON) != 0) { 2344177050Syongari cmd &= ~VR_CR0_TX_ON; 2345177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2346177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2347177050Syongari DELAY(5); 2348177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2349177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) 2350177050Syongari break; 2351177050Syongari } 2352177050Syongari if (i == 0) 2353177050Syongari return (ETIMEDOUT); 2354177050Syongari } 2355177050Syongari return (0); 2356177050Syongari} 2357177050Syongari 2358177050Syongaristatic int 2359177050Syongarivr_rx_stop(struct vr_softc *sc) 2360177050Syongari{ 2361177050Syongari int i; 2362177050Syongari uint8_t cmd; 2363177050Syongari 2364177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2365177050Syongari if ((cmd & VR_CR0_RX_ON) != 0) { 2366177050Syongari cmd &= ~VR_CR0_RX_ON; 2367177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2368177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2369177050Syongari DELAY(5); 2370177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2371177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) 2372177050Syongari break; 2373177050Syongari } 2374177050Syongari if (i == 0) 2375177050Syongari return (ETIMEDOUT); 2376177050Syongari } 2377177050Syongari return (0); 2378177050Syongari} 2379177050Syongari 238041502Swpaul/* 238141502Swpaul * Stop the adapter and free any mbufs allocated to the 238241502Swpaul * RX and TX lists. 238341502Swpaul */ 2384102336Salfredstatic void 2385131503Sbmsvr_stop(struct vr_softc *sc) 238641502Swpaul{ 2387177050Syongari struct vr_txdesc *txd; 2388177050Syongari struct vr_rxdesc *rxd; 2389177050Syongari struct ifnet *ifp; 2390177050Syongari int i; 239141502Swpaul 2392131518Sbms VR_LOCK_ASSERT(sc); 239367087Swpaul 2394147256Sbrooks ifp = sc->vr_ifp; 2395177050Syongari sc->vr_watchdog_timer = 0; 239641502Swpaul 2397151911Sjhb callout_stop(&sc->vr_stat_callout); 2398148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 239951432Swpaul 2400177050Syongari CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2401177050Syongari if (vr_rx_stop(sc) != 0) 2402177050Syongari device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2403177050Syongari if (vr_tx_stop(sc) != 0) 2404177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2405177050Syongari /* Clear pending interrupts. */ 2406177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 240741502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 240841502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 240941502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 241041502Swpaul 241141502Swpaul /* 2412177050Syongari * Free RX and TX mbufs still in the queues. 241341502Swpaul */ 2414177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 2415177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 2416177050Syongari if (rxd->rx_m != NULL) { 2417177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2418177050Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2419177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2420177050Syongari rxd->rx_dmamap); 2421177050Syongari m_freem(rxd->rx_m); 2422177050Syongari rxd->rx_m = NULL; 2423177050Syongari } 2424177050Syongari } 2425177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 2426177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 2427177050Syongari if (txd->tx_m != NULL) { 2428177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2429177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2430177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2431177050Syongari txd->tx_dmamap); 2432177050Syongari m_freem(txd->tx_m); 2433177050Syongari txd->tx_m = NULL; 2434177050Syongari } 2435177050Syongari } 243641502Swpaul} 243741502Swpaul 243841502Swpaul/* 243941502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 244041502Swpaul * get confused by errant DMAs when rebooting. 244141502Swpaul */ 2442173839Syongaristatic int 2443131503Sbmsvr_shutdown(device_t dev) 244441502Swpaul{ 244541502Swpaul 2446177050Syongari return (vr_suspend(dev)); 2447177050Syongari} 2448173839Syongari 2449177050Syongaristatic int 2450177050Syongarivr_suspend(device_t dev) 2451177050Syongari{ 2452177050Syongari struct vr_softc *sc; 2453177050Syongari 2454177050Syongari sc = device_get_softc(dev); 2455177050Syongari 2456177050Syongari VR_LOCK(sc); 2457177050Syongari vr_stop(sc); 2458177050Syongari vr_setwol(sc); 2459177050Syongari sc->vr_suspended = 1; 2460177050Syongari VR_UNLOCK(sc); 2461177050Syongari 2462173839Syongari return (0); 246341502Swpaul} 2464177050Syongari 2465177050Syongaristatic int 2466177050Syongarivr_resume(device_t dev) 2467177050Syongari{ 2468177050Syongari struct vr_softc *sc; 2469177050Syongari struct ifnet *ifp; 2470177050Syongari 2471177050Syongari sc = device_get_softc(dev); 2472177050Syongari 2473177050Syongari VR_LOCK(sc); 2474177050Syongari ifp = sc->vr_ifp; 2475177050Syongari vr_clrwol(sc); 2476177050Syongari vr_reset(sc); 2477177050Syongari if (ifp->if_flags & IFF_UP) 2478177050Syongari vr_init_locked(sc); 2479177050Syongari 2480177050Syongari sc->vr_suspended = 0; 2481177050Syongari VR_UNLOCK(sc); 2482177050Syongari 2483177050Syongari return (0); 2484177050Syongari} 2485177050Syongari 2486177050Syongaristatic void 2487177050Syongarivr_setwol(struct vr_softc *sc) 2488177050Syongari{ 2489177050Syongari struct ifnet *ifp; 2490177050Syongari int pmc; 2491177050Syongari uint16_t pmstat; 2492177050Syongari uint8_t v; 2493177050Syongari 2494177050Syongari VR_LOCK_ASSERT(sc); 2495177050Syongari 2496177050Syongari if (sc->vr_revid < REV_ID_VT6102_A || 2497219902Sjhb pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2498177050Syongari return; 2499177050Syongari 2500177050Syongari ifp = sc->vr_ifp; 2501177050Syongari 2502177050Syongari /* Clear WOL configuration. */ 2503177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2504177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2505177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2506177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2507177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2508177050Syongari /* Newer Rhine III supports two additional patterns. */ 2509177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2510177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2511177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2512177050Syongari } 2513177050Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2514177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2515177050Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2516177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2517177050Syongari /* 2518177050Syongari * It seems that multicast wakeup frames require programming pattern 2519177050Syongari * registers and valid CRC as well as pattern mask for each pattern. 2520177050Syongari * While it's possible to setup such a pattern it would complicate 2521177050Syongari * WOL configuration so ignore multicast wakeup frames. 2522177050Syongari */ 2523177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2524177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2525177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2526177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2527177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2528177050Syongari } 2529177050Syongari 2530177050Syongari /* Put hardware into sleep. */ 2531177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2532177050Syongari v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2533177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2534177050Syongari 2535177050Syongari /* Request PME if WOL is requested. */ 2536177050Syongari pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2537177050Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2538177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2539177050Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2540177050Syongari pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2541177050Syongari} 2542177050Syongari 2543177050Syongaristatic void 2544177050Syongarivr_clrwol(struct vr_softc *sc) 2545177050Syongari{ 2546177050Syongari uint8_t v; 2547177050Syongari 2548177050Syongari VR_LOCK_ASSERT(sc); 2549177050Syongari 2550177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 2551177050Syongari return; 2552177050Syongari 2553177050Syongari /* Take hardware out of sleep. */ 2554177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2555177050Syongari v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2556177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2557177050Syongari 2558177050Syongari /* Clear WOL configuration as WOL may interfere normal operation. */ 2559177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2560177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2561177050Syongari VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2562177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2563177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2564177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2565177050Syongari /* Newer Rhine III supports two additional patterns. */ 2566177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2567177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2568177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2569177050Syongari } 2570177050Syongari} 2571177050Syongari 2572177050Syongaristatic int 2573177050Syongarivr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2574177050Syongari{ 2575177050Syongari struct vr_softc *sc; 2576177050Syongari struct vr_statistics *stat; 2577177050Syongari int error; 2578177050Syongari int result; 2579177050Syongari 2580177050Syongari result = -1; 2581177050Syongari error = sysctl_handle_int(oidp, &result, 0, req); 2582177050Syongari 2583177050Syongari if (error != 0 || req->newptr == NULL) 2584177050Syongari return (error); 2585177050Syongari 2586177050Syongari if (result == 1) { 2587177050Syongari sc = (struct vr_softc *)arg1; 2588177050Syongari stat = &sc->vr_stat; 2589177050Syongari 2590177050Syongari printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2591177050Syongari printf("Outbound good frames : %ju\n", 2592177050Syongari (uintmax_t)stat->tx_ok); 2593177050Syongari printf("Inbound good frames : %ju\n", 2594177050Syongari (uintmax_t)stat->rx_ok); 2595177050Syongari printf("Outbound errors : %u\n", stat->tx_errors); 2596177050Syongari printf("Inbound errors : %u\n", stat->rx_errors); 2597177050Syongari printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2598177050Syongari printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2599177050Syongari printf("Inbound FIFO overflows : %d\n", 2600177050Syongari stat->rx_fifo_overflows); 2601177050Syongari printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2602177050Syongari printf("Inbound frame alignment errors : %u\n", 2603177050Syongari stat->rx_alignment); 2604177050Syongari printf("Inbound giant frames : %u\n", stat->rx_giants); 2605177050Syongari printf("Inbound runt frames : %u\n", stat->rx_runts); 2606177050Syongari printf("Outbound aborted with excessive collisions : %u\n", 2607177050Syongari stat->tx_abort); 2608177050Syongari printf("Outbound collisions : %u\n", stat->tx_collisions); 2609177050Syongari printf("Outbound late collisions : %u\n", 2610177050Syongari stat->tx_late_collisions); 2611177050Syongari printf("Outbound underrun : %u\n", stat->tx_underrun); 2612177050Syongari printf("PCI bus errors : %u\n", stat->bus_errors); 2613177050Syongari printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2614177050Syongari stat->num_restart); 2615177050Syongari } 2616177050Syongari 2617177050Syongari return (error); 2618177050Syongari} 2619