if_vr.c revision 185962
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 185962 2008-12-12 01:26:11Z yongari $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various network adapters based on the VIA Rhine 4041502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4141502Swpaul * Datasheets are available at http://www.via.com.tw. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 47131503Sbms 4841502Swpaul/* 4941502Swpaul * The VIA Rhine controllers are similar in some respects to the 5041502Swpaul * the DEC tulip chips, except less complicated. The controller 5141502Swpaul * uses an MII bus and an external physical layer interface. The 5241502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5341502Swpaul * multicast filter. Transmit and receive descriptors are similar 5441502Swpaul * to the tulip. 5541502Swpaul * 56168953Sphk * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 5741502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5841502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5941502Swpaul * at longword boundaries, so we have to do a buffer copy before 6041502Swpaul * transmission. 6141502Swpaul */ 6241502Swpaul 63150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 64150968Sglebius#include "opt_device_polling.h" 65150968Sglebius#endif 66150968Sglebius 6741502Swpaul#include <sys/param.h> 6841502Swpaul#include <sys/systm.h> 69177050Syongari#include <sys/bus.h> 70177050Syongari#include <sys/endian.h> 71177050Syongari#include <sys/kernel.h> 72177050Syongari#include <sys/malloc.h> 7341502Swpaul#include <sys/mbuf.h> 74129878Sphk#include <sys/module.h> 75177050Syongari#include <sys/rman.h> 7641502Swpaul#include <sys/socket.h> 77177050Syongari#include <sys/sockio.h> 78177050Syongari#include <sys/sysctl.h> 79177050Syongari#include <sys/taskqueue.h> 8041502Swpaul 81177050Syongari#include <net/bpf.h> 8241502Swpaul#include <net/if.h> 8341502Swpaul#include <net/ethernet.h> 8441502Swpaul#include <net/if_dl.h> 8541502Swpaul#include <net/if_media.h> 86147256Sbrooks#include <net/if_types.h> 87177050Syongari#include <net/if_vlan_var.h> 8841502Swpaul 89177050Syongari#include <dev/mii/mii.h> 9051432Swpaul#include <dev/mii/miivar.h> 9151432Swpaul 92172555Syongari#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9441502Swpaul 95177050Syongari#include <machine/bus.h> 9641502Swpaul 97177047Syongari#include <dev/vr/if_vrreg.h> 9841502Swpaul 99177050Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 100177050Syongari#include "miibus_if.h" 101177050Syongari 102113506SmdoddMODULE_DEPEND(vr, pci, 1, 1, 1); 103113506SmdoddMODULE_DEPEND(vr, ether, 1, 1, 1); 10459758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 10559758Speter 106177050Syongari/* Define to show Rx/Tx error status. */ 107177050Syongari#undef VR_SHOW_ERRORS 108177050Syongari#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 10951432Swpaul 11041502Swpaul/* 111177050Syongari * Various supported device vendors/types, their names & quirks. 11241502Swpaul */ 113168952Sphk#define VR_Q_NEEDALIGN (1<<0) 114168952Sphk#define VR_Q_CSUM (1<<1) 115177050Syongari#define VR_Q_CAM (1<<2) 116168952Sphk 117168952Sphkstatic struct vr_type { 118168952Sphk u_int16_t vr_vid; 119168952Sphk u_int16_t vr_did; 120168952Sphk int vr_quirks; 121168952Sphk char *vr_name; 122168952Sphk} vr_devs[] = { 123168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE, 124168827Sphk VR_Q_NEEDALIGN, 125168827Sphk "VIA VT3043 Rhine I 10/100BaseTX" }, 126168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127168827Sphk VR_Q_NEEDALIGN, 128168827Sphk "VIA VT86C100A Rhine II 10/100BaseTX" }, 129168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130168827Sphk 0, 131168827Sphk "VIA VT6102 Rhine II 10/100BaseTX" }, 132168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133168827Sphk 0, 134168827Sphk "VIA VT6105 Rhine III 10/100BaseTX" }, 135168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136185962Syongari VR_Q_CSUM, 137168827Sphk "VIA VT6105M Rhine III 10/100BaseTX" }, 138168827Sphk { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139168827Sphk VR_Q_NEEDALIGN, 140168827Sphk "Delta Electronics Rhine II 10/100BaseTX" }, 141168827Sphk { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142168827Sphk VR_Q_NEEDALIGN, 143168827Sphk "Addtron Technology Rhine II 10/100BaseTX" }, 144168813Sphk { 0, 0, 0, NULL } 14541502Swpaul}; 14641502Swpaul 147142407Simpstatic int vr_probe(device_t); 148142407Simpstatic int vr_attach(device_t); 149142407Simpstatic int vr_detach(device_t); 150177050Syongaristatic int vr_shutdown(device_t); 151177050Syongaristatic int vr_suspend(device_t); 152177050Syongaristatic int vr_resume(device_t); 15341502Swpaul 154177050Syongaristatic void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155177050Syongaristatic int vr_dma_alloc(struct vr_softc *); 156177050Syongaristatic void vr_dma_free(struct vr_softc *); 157177050Syongaristatic __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158177050Syongaristatic int vr_newbuf(struct vr_softc *, int); 15941502Swpaul 160177050Syongari#ifndef __NO_STRICT_ALIGNMENT 161177050Syongaristatic __inline void vr_fixup_rx(struct mbuf *); 162177050Syongari#endif 163142407Simpstatic void vr_rxeof(struct vr_softc *); 164142407Simpstatic void vr_txeof(struct vr_softc *); 165142407Simpstatic void vr_tick(void *); 166177050Syongaristatic int vr_error(struct vr_softc *, uint16_t); 167177050Syongaristatic void vr_tx_underrun(struct vr_softc *); 168142407Simpstatic void vr_intr(void *); 169142407Simpstatic void vr_start(struct ifnet *); 170142407Simpstatic void vr_start_locked(struct ifnet *); 171177050Syongaristatic int vr_encap(struct vr_softc *, struct mbuf **); 172142407Simpstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 173142407Simpstatic void vr_init(void *); 174142407Simpstatic void vr_init_locked(struct vr_softc *); 175177050Syongaristatic void vr_tx_start(struct vr_softc *); 176177050Syongaristatic void vr_rx_start(struct vr_softc *); 177177050Syongaristatic int vr_tx_stop(struct vr_softc *); 178177050Syongaristatic int vr_rx_stop(struct vr_softc *); 179142407Simpstatic void vr_stop(struct vr_softc *); 180177050Syongaristatic void vr_watchdog(struct vr_softc *); 181142407Simpstatic int vr_ifmedia_upd(struct ifnet *); 182142407Simpstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 18341502Swpaul 184177050Syongaristatic int vr_miibus_readreg(device_t, int, int); 185177050Syongaristatic int vr_miibus_writereg(device_t, int, int, int); 186142407Simpstatic void vr_miibus_statchg(device_t); 18741502Swpaul 188177050Syongaristatic void vr_link_task(void *, int); 189180552Syongaristatic void vr_cam_mask(struct vr_softc *, uint32_t, int); 190180552Syongaristatic int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 191177050Syongaristatic void vr_set_filter(struct vr_softc *); 192168946Sphkstatic void vr_reset(const struct vr_softc *); 193177050Syongaristatic int vr_tx_ring_init(struct vr_softc *); 194177050Syongaristatic int vr_rx_ring_init(struct vr_softc *); 195177050Syongaristatic void vr_setwol(struct vr_softc *); 196177050Syongaristatic void vr_clrwol(struct vr_softc *); 197177050Syongaristatic int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 19841502Swpaul 199177050Syongaristatic struct vr_tx_threshold_table { 200177050Syongari int tx_cfg; 201177050Syongari int bcr_cfg; 202177050Syongari int value; 203177050Syongari} vr_tx_threshold_tables[] = { 204177050Syongari { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 205177050Syongari { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 206177050Syongari { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 207177050Syongari { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 208177050Syongari { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 209177050Syongari { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 210177050Syongari}; 21149610Swpaul 21249610Swpaulstatic device_method_t vr_methods[] = { 21349610Swpaul /* Device interface */ 21449610Swpaul DEVMETHOD(device_probe, vr_probe), 21549610Swpaul DEVMETHOD(device_attach, vr_attach), 21649610Swpaul DEVMETHOD(device_detach, vr_detach), 21749610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 218177050Syongari DEVMETHOD(device_suspend, vr_suspend), 219177050Syongari DEVMETHOD(device_resume, vr_resume), 22051432Swpaul 22151432Swpaul /* bus interface */ 22251432Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22351432Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22451432Swpaul 22551432Swpaul /* MII interface */ 22651432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 22751432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 22851432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 229177050Syongari DEVMETHOD(miibus_linkchg, vr_miibus_statchg), 23051432Swpaul 231177050Syongari { NULL, NULL } 23249610Swpaul}; 23349610Swpaul 23449610Swpaulstatic driver_t vr_driver = { 23551455Swpaul "vr", 23649610Swpaul vr_methods, 23749610Swpaul sizeof(struct vr_softc) 23849610Swpaul}; 23949610Swpaul 24049610Swpaulstatic devclass_t vr_devclass; 24149610Swpaul 242113506SmdoddDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 24351473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 24449610Swpaul 245102336Salfredstatic int 246177050Syongarivr_miibus_readreg(device_t dev, int phy, int reg) 24741502Swpaul{ 248177050Syongari struct vr_softc *sc; 249177050Syongari int i; 25041502Swpaul 251177050Syongari sc = device_get_softc(dev); 252177050Syongari if (sc->vr_phyaddr != phy) 253177050Syongari return (0); 254110168Ssilby 255131503Sbms /* Set the register address. */ 256177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 257110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 258131503Sbms 259177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 260177050Syongari DELAY(1); 261110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 262110168Ssilby break; 263110168Ssilby } 264177050Syongari if (i == VR_MII_TIMEOUT) 265177050Syongari device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 266110168Ssilby 267177050Syongari return (CSR_READ_2(sc, VR_MIIDATA)); 268110168Ssilby} 269110168Ssilby 270102336Salfredstatic int 271177050Syongarivr_miibus_writereg(device_t dev, int phy, int reg, int data) 27241502Swpaul{ 273177050Syongari struct vr_softc *sc; 274177050Syongari int i; 27541502Swpaul 276177050Syongari sc = device_get_softc(dev); 277177050Syongari if (sc->vr_phyaddr != phy) 278177050Syongari return (0); 279110168Ssilby 280131503Sbms /* Set the register address and data to write. */ 281177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 282177050Syongari CSR_WRITE_2(sc, VR_MIIDATA, data); 283110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 284110168Ssilby 285177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 286177050Syongari DELAY(1); 287110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 288110168Ssilby break; 289110168Ssilby } 290177050Syongari if (i == VR_MII_TIMEOUT) 291177050Syongari device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 292177050Syongari reg); 293110168Ssilby 294131503Sbms return (0); 295110168Ssilby} 296110168Ssilby 297177050Syongaristatic void 298177050Syongarivr_miibus_statchg(device_t dev) 29951432Swpaul{ 300177050Syongari struct vr_softc *sc; 30141502Swpaul 302177050Syongari sc = device_get_softc(dev); 303177050Syongari taskqueue_enqueue(taskqueue_swi, &sc->vr_link_task); 30441502Swpaul} 30541502Swpaul 306177050Syongari/* 307177050Syongari * In order to fiddle with the 308177050Syongari * 'full-duplex' and '100Mbps' bits in the netconfig register, we 309177050Syongari * first have to put the transmit and/or receive logic in the idle state. 310177050Syongari */ 311177050Syongaristatic void 312177050Syongarivr_link_task(void *arg, int pending) 31351432Swpaul{ 314177050Syongari struct vr_softc *sc; 315177050Syongari struct mii_data *mii; 316177050Syongari struct ifnet *ifp; 317177050Syongari int lfdx, mfdx; 318177050Syongari uint8_t cr0, cr1, fc; 31941502Swpaul 320177050Syongari sc = (struct vr_softc *)arg; 321110168Ssilby 322177050Syongari VR_LOCK(sc); 323177050Syongari mii = device_get_softc(sc->vr_miibus); 324177050Syongari ifp = sc->vr_ifp; 325177050Syongari if (mii == NULL || ifp == NULL || 326177050Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 327177050Syongari VR_UNLOCK(sc); 328177050Syongari return; 329177050Syongari } 33041502Swpaul 331177050Syongari if (mii->mii_media_status & IFM_ACTIVE) { 332177050Syongari if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 333177050Syongari sc->vr_link = 1; 334177050Syongari } else 335177050Syongari sc->vr_link = 0; 336177050Syongari 337177050Syongari if (sc->vr_link != 0) { 338177050Syongari cr0 = CSR_READ_1(sc, VR_CR0); 339177050Syongari cr1 = CSR_READ_1(sc, VR_CR1); 340177050Syongari mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 341177050Syongari lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 342177050Syongari if (mfdx != lfdx) { 343177050Syongari if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 344177050Syongari if (vr_tx_stop(sc) != 0 || 345177050Syongari vr_rx_stop(sc) != 0) { 346177050Syongari device_printf(sc->vr_dev, 347177050Syongari "%s: Tx/Rx shutdown error -- " 348177050Syongari "resetting\n", __func__); 349177050Syongari sc->vr_flags |= VR_F_RESTART; 350177050Syongari VR_UNLOCK(sc); 351177050Syongari return; 352177050Syongari } 353177050Syongari } 354177050Syongari if (lfdx) 355177050Syongari cr1 |= VR_CR1_FULLDUPLEX; 356177050Syongari else 357177050Syongari cr1 &= ~VR_CR1_FULLDUPLEX; 358177050Syongari CSR_WRITE_1(sc, VR_CR1, cr1); 359177050Syongari } 360177050Syongari fc = 0; 361177050Syongari#ifdef notyet 362177050Syongari /* Configure flow-control. */ 363177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 364177050Syongari fc = CSR_READ_1(sc, VR_FLOWCR1); 365177050Syongari fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 366177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 367177050Syongari IFM_ETH_RXPAUSE) != 0) 368177050Syongari fc |= VR_FLOWCR1_RXPAUSE; 369177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 370177050Syongari IFM_ETH_TXPAUSE) != 0) 371177050Syongari fc |= VR_FLOWCR1_TXPAUSE; 372177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, fc); 373177050Syongari } else if (sc->vr_revid >= REV_ID_VT6102_A) { 374177050Syongari /* No Tx puase capability available for Rhine II. */ 375177050Syongari fc = CSR_READ_1(sc, VR_MISC_CR0); 376177050Syongari fc &= ~VR_MISCCR0_RXPAUSE; 377177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 378177050Syongari IFM_ETH_RXPAUSE) != 0) 379177050Syongari fc |= VR_MISCCR0_RXPAUSE; 380177050Syongari CSR_WRITE_1(sc, VR_MISC_CR0, fc); 381177050Syongari } 382177050Syongari#endif 383177050Syongari vr_rx_start(sc); 384177050Syongari vr_tx_start(sc); 385177050Syongari } else { 386177050Syongari if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 387177050Syongari device_printf(sc->vr_dev, 388177050Syongari "%s: Tx/Rx shutdown error -- resetting\n", 389177050Syongari __func__); 390177050Syongari sc->vr_flags |= VR_F_RESTART; 391177050Syongari VR_UNLOCK(sc); 392177050Syongari return; 393177050Syongari } 394177050Syongari } 395177050Syongari VR_UNLOCK(sc); 39651432Swpaul} 39751432Swpaul 398180552Syongari 399180552Syongaristatic void 400180552Syongarivr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 401180552Syongari{ 402180552Syongari 403180552Syongari if (type == VR_MCAST_CAM) 404180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 405180552Syongari else 406180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 407180552Syongari CSR_WRITE_4(sc, VR_CAMMASK, mask); 408180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 409180552Syongari} 410180552Syongari 411177050Syongaristatic int 412180552Syongarivr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 41351432Swpaul{ 414177050Syongari int i; 41551432Swpaul 416180552Syongari if (type == VR_MCAST_CAM) { 417180552Syongari if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 418180552Syongari return (EINVAL); 419180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 420180552Syongari } else 421180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 422177050Syongari 423177050Syongari /* Set CAM entry address. */ 424177050Syongari CSR_WRITE_1(sc, VR_CAMADDR, idx); 425177050Syongari /* Set CAM entry data. */ 426180552Syongari if (type == VR_MCAST_CAM) { 427180552Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) 428180552Syongari CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 429180552Syongari } else { 430180552Syongari CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 431180552Syongari CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 432180552Syongari } 433180552Syongari DELAY(10); 434177050Syongari /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 435180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 436177050Syongari for (i = 0; i < VR_TIMEOUT; i++) { 437177050Syongari DELAY(1); 438177050Syongari if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 439177050Syongari break; 440177050Syongari } 441177050Syongari 442177050Syongari if (i == VR_TIMEOUT) 443177050Syongari device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 444177050Syongari __func__); 445180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 446177050Syongari 447177050Syongari return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 44841502Swpaul} 44941502Swpaul 45041502Swpaul/* 45141502Swpaul * Program the 64-bit multicast hash filter. 45241502Swpaul */ 453102336Salfredstatic void 454177050Syongarivr_set_filter(struct vr_softc *sc) 45541502Swpaul{ 456177050Syongari struct ifnet *ifp; 457177050Syongari int h; 458131503Sbms uint32_t hashes[2] = { 0, 0 }; 45941502Swpaul struct ifmultiaddr *ifma; 460131503Sbms uint8_t rxfilt; 461177050Syongari int error, mcnt; 462177050Syongari uint32_t cam_mask; 46341502Swpaul 464131518Sbms VR_LOCK_ASSERT(sc); 46541502Swpaul 466177050Syongari ifp = sc->vr_ifp; 46741502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 468185014Syongari rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 469185014Syongari VR_RXCFG_RX_MULTI); 470177050Syongari if (ifp->if_flags & IFF_BROADCAST) 471177050Syongari rxfilt |= VR_RXCFG_RX_BROAD; 47241502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 47341502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 474177050Syongari if (ifp->if_flags & IFF_PROMISC) 475177050Syongari rxfilt |= VR_RXCFG_RX_PROMISC; 47641502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 47741502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 47841502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 47941502Swpaul return; 48041502Swpaul } 48141502Swpaul 482131503Sbms /* Now program new ones. */ 483177050Syongari error = 0; 484180552Syongari mcnt = 0; 485148654Srwatson IF_ADDR_LOCK(ifp); 486177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 487177050Syongari /* 488177050Syongari * For hardwares that have CAM capability, use 489177050Syongari * 32 entries multicast perfect filter. 490177050Syongari */ 491177050Syongari cam_mask = 0; 492177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 493177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 494177050Syongari continue; 495180552Syongari error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 496177050Syongari LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 497177050Syongari if (error != 0) { 498177050Syongari cam_mask = 0; 499177050Syongari break; 500177050Syongari } 501177050Syongari cam_mask |= 1 << mcnt; 502177050Syongari mcnt++; 503177050Syongari } 504180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 50541502Swpaul } 506177050Syongari 507177050Syongari if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 508177050Syongari /* 509177050Syongari * If there are too many multicast addresses or 510177050Syongari * setting multicast CAM filter failed, use hash 511177050Syongari * table based filtering. 512177050Syongari */ 513180552Syongari mcnt = 0; 514177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 515177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 516177050Syongari continue; 517177050Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 518177050Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 519177050Syongari if (h < 32) 520177050Syongari hashes[0] |= (1 << h); 521177050Syongari else 522177050Syongari hashes[1] |= (1 << (h - 32)); 523177050Syongari mcnt++; 524177050Syongari } 525177050Syongari } 526148654Srwatson IF_ADDR_UNLOCK(ifp); 52741502Swpaul 528177050Syongari if (mcnt > 0) 52941502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 53041502Swpaul 53141502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 53241502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 53341502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 53441502Swpaul} 53541502Swpaul 536102336Salfredstatic void 537168946Sphkvr_reset(const struct vr_softc *sc) 53841502Swpaul{ 539177050Syongari int i; 54041502Swpaul 541151773Sjhb /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 542131518Sbms 543177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 544177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 545177050Syongari /* VT86C100A needs more delay after reset. */ 546177050Syongari DELAY(100); 547177050Syongari } 54841502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 54941502Swpaul DELAY(10); 550177050Syongari if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 55141502Swpaul break; 55241502Swpaul } 553107220Ssilby if (i == VR_TIMEOUT) { 554177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 555162315Sglebius device_printf(sc->vr_dev, "reset never completed!\n"); 556107220Ssilby else { 557177050Syongari /* Use newer force reset command. */ 558177050Syongari device_printf(sc->vr_dev, 559177050Syongari "Using force reset command.\n"); 560107220Ssilby VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 561177050Syongari /* 562177050Syongari * Wait a little while for the chip to get its brains 563177050Syongari * in order. 564177050Syongari */ 565177050Syongari DELAY(2000); 566107220Ssilby } 567107220Ssilby } 56841502Swpaul 56941502Swpaul} 57041502Swpaul 57141502Swpaul/* 57241502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 573168813Sphk * IDs against our list and return a match or NULL 574168813Sphk */ 575168813Sphkstatic struct vr_type * 576168813Sphkvr_match(device_t dev) 577168813Sphk{ 578168813Sphk struct vr_type *t = vr_devs; 579168813Sphk 580168813Sphk for (t = vr_devs; t->vr_name != NULL; t++) 581168813Sphk if ((pci_get_vendor(dev) == t->vr_vid) && 582168813Sphk (pci_get_device(dev) == t->vr_did)) 583168813Sphk return (t); 584168813Sphk return (NULL); 585168813Sphk} 586168813Sphk 587168813Sphk/* 588168813Sphk * Probe for a VIA Rhine chip. Check the PCI vendor and device 58941502Swpaul * IDs against our list and return a device name if we find a match. 59041502Swpaul */ 591102336Salfredstatic int 592131503Sbmsvr_probe(device_t dev) 59341502Swpaul{ 594168813Sphk struct vr_type *t; 59541502Swpaul 596168813Sphk t = vr_match(dev); 597168813Sphk if (t != NULL) { 598168813Sphk device_set_desc(dev, t->vr_name); 599168813Sphk return (BUS_PROBE_DEFAULT); 60041502Swpaul } 601131503Sbms return (ENXIO); 60241502Swpaul} 60341502Swpaul 60441502Swpaul/* 60541502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 60641502Swpaul * setup and ethernet/BPF attach. 60741502Swpaul */ 608102336Salfredstatic int 609168946Sphkvr_attach(device_t dev) 61041502Swpaul{ 61141502Swpaul struct vr_softc *sc; 61241502Swpaul struct ifnet *ifp; 613168813Sphk struct vr_type *t; 614177050Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 615177050Syongari int error, rid; 616177050Syongari int i, pmc; 61741502Swpaul 61849610Swpaul sc = device_get_softc(dev); 619162315Sglebius sc->vr_dev = dev; 620168813Sphk t = vr_match(dev); 621168813Sphk KASSERT(t != NULL, ("Lost if_vr device match")); 622168813Sphk sc->vr_quirks = t->vr_quirks; 623168813Sphk device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 62441502Swpaul 62593818Sjhb mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 626131518Sbms MTX_DEF); 627151911Sjhb callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 628177050Syongari TASK_INIT(&sc->vr_link_task, 0, vr_link_task, sc); 629177050Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 630177050Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 631177050Syongari OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 632177050Syongari vr_sysctl_stats, "I", "Statistics"); 633151911Sjhb 634177050Syongari error = 0; 635177050Syongari 63641502Swpaul /* 63741502Swpaul * Map control/status registers. 63841502Swpaul */ 63972813Swpaul pci_enable_busmaster(dev); 640177050Syongari sc->vr_revid = pci_get_revid(dev); 641177050Syongari device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 64241502Swpaul 643177050Syongari sc->vr_res_id = PCIR_BAR(0); 644177050Syongari sc->vr_res_type = SYS_RES_IOPORT; 645177050Syongari sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 646177050Syongari &sc->vr_res_id, RF_ACTIVE); 64749610Swpaul if (sc->vr_res == NULL) { 648177050Syongari device_printf(dev, "couldn't map ports\n"); 64949610Swpaul error = ENXIO; 65041502Swpaul goto fail; 65141502Swpaul } 65241502Swpaul 653177050Syongari /* Allocate interrupt. */ 65449610Swpaul rid = 0; 655127135Snjl sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 65649610Swpaul RF_SHAREABLE | RF_ACTIVE); 65749610Swpaul 65849610Swpaul if (sc->vr_irq == NULL) { 659151773Sjhb device_printf(dev, "couldn't map interrupt\n"); 66049610Swpaul error = ENXIO; 66141502Swpaul goto fail; 66241502Swpaul } 66341502Swpaul 664151773Sjhb /* Allocate ifnet structure. */ 665151773Sjhb ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 666151773Sjhb if (ifp == NULL) { 667177050Syongari device_printf(dev, "couldn't allocate ifnet structure\n"); 668151773Sjhb error = ENOSPC; 669151773Sjhb goto fail; 670151773Sjhb } 671151773Sjhb ifp->if_softc = sc; 672151773Sjhb if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 673151773Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 674151773Sjhb ifp->if_ioctl = vr_ioctl; 675151773Sjhb ifp->if_start = vr_start; 676151773Sjhb ifp->if_init = vr_init; 677177050Syongari IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 678177050Syongari ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 679151773Sjhb IFQ_SET_READY(&ifp->if_snd); 680168827Sphk 681177050Syongari /* Configure Tx FIFO threshold. */ 682177050Syongari sc->vr_txthresh = VR_TXTHRESH_MIN; 683177050Syongari if (sc->vr_revid < REV_ID_VT6105_A0) { 684177050Syongari /* 685177050Syongari * Use store and forward mode for Rhine I/II. 686177050Syongari * Otherwise they produce a lot of Tx underruns and 687177050Syongari * it would take a while to get working FIFO threshold 688177050Syongari * value. 689177050Syongari */ 690177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 691177050Syongari } 692177050Syongari if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 693177050Syongari ifp->if_hwassist = VR_CSUM_FEATURES; 694168827Sphk ifp->if_capabilities |= IFCAP_HWCSUM; 695177050Syongari /* 696177050Syongari * To update checksum field the hardware may need to 697177050Syongari * store entire frames into FIFO before transmitting. 698177050Syongari */ 699177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 700168827Sphk } 701168827Sphk 702177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A && 703177050Syongari pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 704177050Syongari ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 705177050Syongari 706177050Syongari /* Rhine supports oversized VLAN frame. */ 707168973Sphk ifp->if_capabilities |= IFCAP_VLAN_MTU; 708151773Sjhb ifp->if_capenable = ifp->if_capabilities; 709151773Sjhb#ifdef DEVICE_POLLING 710151773Sjhb ifp->if_capabilities |= IFCAP_POLLING; 711151773Sjhb#endif 712151773Sjhb 71376586Swpaul /* 71476586Swpaul * Windows may put the chip in suspend mode when it 71576586Swpaul * shuts down. Be sure to kick it in the head to wake it 71676586Swpaul * up again. 71776586Swpaul */ 718172555Syongari if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 719172555Syongari VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 72076586Swpaul 721131503Sbms /* 72241502Swpaul * Get station address. The way the Rhine chips work, 72341502Swpaul * you're not allowed to directly access the EEPROM once 72441502Swpaul * they've been programmed a special way. Consequently, 72541502Swpaul * we need to read the node address from the PAR0 and PAR1 72641502Swpaul * registers. 727177050Syongari * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 728177050Syongari * VR_CFGC and VR_CFGD such that memory mapped IO configured 729177050Syongari * by driver is reset to default state. 73041502Swpaul */ 73141502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 732177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 733177050Syongari DELAY(1); 734177050Syongari if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 735177050Syongari break; 736177050Syongari } 737177050Syongari if (i == 0) 738177050Syongari device_printf(dev, "Reloading EEPROM timeout!\n"); 73941502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 74041502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 74141502Swpaul 742177050Syongari /* Reset the adapter. */ 743177050Syongari vr_reset(sc); 744177050Syongari /* Ack intr & disable further interrupts. */ 745177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 746177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 747177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A) 748177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 74951432Swpaul 750177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 751177050Syongari pci_write_config(dev, VR_PCI_MODE2, 752177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 753177050Syongari VR_MODE2_MODE10T, 1); 754177050Syongari } else { 755177050Syongari /* Report error instead of retrying forever. */ 756177050Syongari pci_write_config(dev, VR_PCI_MODE2, 757177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 758177050Syongari VR_MODE2_PCEROPT, 1); 759177050Syongari /* Detect MII coding error. */ 760177050Syongari pci_write_config(dev, VR_PCI_MODE3, 761177050Syongari pci_read_config(dev, VR_PCI_MODE3, 1) | 762177050Syongari VR_MODE3_MIION, 1); 763177050Syongari if (sc->vr_revid >= REV_ID_VT6105_LOM && 764177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 765177050Syongari pci_write_config(dev, VR_PCI_MODE2, 766177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 767177050Syongari VR_MODE2_MODE10T, 1); 768177050Syongari /* Enable Memory-Read-Multiple. */ 769177050Syongari if (sc->vr_revid >= REV_ID_VT6107_A1 && 770177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 771177050Syongari pci_write_config(dev, VR_PCI_MODE2, 772177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 773177050Syongari VR_MODE2_MRDPL, 1); 774177050Syongari } 775177050Syongari /* Disable MII AUTOPOLL. */ 776177050Syongari VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 777177050Syongari 778177050Syongari if (vr_dma_alloc(sc) != 0) { 77949610Swpaul error = ENXIO; 78049610Swpaul goto fail; 78141502Swpaul } 78241502Swpaul 783177050Syongari /* Save PHY address. */ 784177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) 785177050Syongari sc->vr_phyaddr = 1; 786177050Syongari else 787177050Syongari sc->vr_phyaddr = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 788177050Syongari 789131503Sbms /* Do MII setup. */ 79051432Swpaul if (mii_phy_probe(dev, &sc->vr_miibus, 79151432Swpaul vr_ifmedia_upd, vr_ifmedia_sts)) { 792151773Sjhb device_printf(dev, "MII without any phy!\n"); 79349610Swpaul error = ENXIO; 79441502Swpaul goto fail; 79541502Swpaul } 79641502Swpaul 797131503Sbms /* Call MI attach routine. */ 798106936Ssam ether_ifattach(ifp, eaddr); 799177050Syongari /* 800177050Syongari * Tell the upper layer(s) we support long frames. 801177050Syongari * Must appear after the call to ether_ifattach() because 802177050Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 803177050Syongari */ 804177050Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 80541502Swpaul 806177050Syongari /* Hook interrupt last to avoid having to lock softc. */ 807131518Sbms error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 808166901Spiso NULL, vr_intr, sc, &sc->vr_intrhand); 809112872Snjl 810112872Snjl if (error) { 811151773Sjhb device_printf(dev, "couldn't set up irq\n"); 812113609Snjl ether_ifdetach(ifp); 813112872Snjl goto fail; 814112872Snjl } 815112872Snjl 81641502Swpaulfail: 817112872Snjl if (error) 818112872Snjl vr_detach(dev); 81967087Swpaul 820131503Sbms return (error); 82141502Swpaul} 82241502Swpaul 823113609Snjl/* 824113609Snjl * Shutdown hardware and free up resources. This can be called any 825113609Snjl * time after the mutex has been initialized. It is called in both 826113609Snjl * the error case in attach and the normal detach case so it needs 827113609Snjl * to be careful about only freeing resources that have actually been 828113609Snjl * allocated. 829113609Snjl */ 830102336Salfredstatic int 831131503Sbmsvr_detach(device_t dev) 83249610Swpaul{ 833131503Sbms struct vr_softc *sc = device_get_softc(dev); 834147256Sbrooks struct ifnet *ifp = sc->vr_ifp; 83549610Swpaul 836112880Sjhb KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 837131518Sbms 838150789Sglebius#ifdef DEVICE_POLLING 839177050Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 840150789Sglebius ether_poll_deregister(ifp); 841150789Sglebius#endif 842150789Sglebius 843177050Syongari /* These should only be active if attach succeeded. */ 844113812Simp if (device_is_attached(dev)) { 845151911Sjhb VR_LOCK(sc); 846177050Syongari sc->vr_detach = 1; 847113609Snjl vr_stop(sc); 848151911Sjhb VR_UNLOCK(sc); 849151911Sjhb callout_drain(&sc->vr_stat_callout); 850177050Syongari taskqueue_drain(taskqueue_swi, &sc->vr_link_task); 851112872Snjl ether_ifdetach(ifp); 852113609Snjl } 853113609Snjl if (sc->vr_miibus) 854112872Snjl device_delete_child(dev, sc->vr_miibus); 855113609Snjl bus_generic_detach(dev); 85649610Swpaul 857112872Snjl if (sc->vr_intrhand) 858112872Snjl bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 859112872Snjl if (sc->vr_irq) 860112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 861112872Snjl if (sc->vr_res) 862177050Syongari bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 863177050Syongari sc->vr_res); 86451432Swpaul 865151297Sru if (ifp) 866151297Sru if_free(ifp); 867151297Sru 868177050Syongari vr_dma_free(sc); 86949610Swpaul 87067087Swpaul mtx_destroy(&sc->vr_mtx); 87149610Swpaul 872131503Sbms return (0); 87349610Swpaul} 87449610Swpaul 875177050Syongaristruct vr_dmamap_arg { 876177050Syongari bus_addr_t vr_busaddr; 877177050Syongari}; 878177050Syongari 879177050Syongaristatic void 880177050Syongarivr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 881177050Syongari{ 882177050Syongari struct vr_dmamap_arg *ctx; 883177050Syongari 884177050Syongari if (error != 0) 885177050Syongari return; 886177050Syongari ctx = arg; 887177050Syongari ctx->vr_busaddr = segs[0].ds_addr; 888177050Syongari} 889177050Syongari 890177050Syongaristatic int 891177050Syongarivr_dma_alloc(struct vr_softc *sc) 892177050Syongari{ 893177050Syongari struct vr_dmamap_arg ctx; 894177050Syongari struct vr_txdesc *txd; 895177050Syongari struct vr_rxdesc *rxd; 896177050Syongari bus_size_t tx_alignment; 897177050Syongari int error, i; 898177050Syongari 899177050Syongari /* Create parent DMA tag. */ 900177050Syongari error = bus_dma_tag_create( 901177050Syongari bus_get_dma_tag(sc->vr_dev), /* parent */ 902177050Syongari 1, 0, /* alignment, boundary */ 903177050Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 904177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 905177050Syongari NULL, NULL, /* filter, filterarg */ 906177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 907177050Syongari 0, /* nsegments */ 908177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 909177050Syongari 0, /* flags */ 910177050Syongari NULL, NULL, /* lockfunc, lockarg */ 911177050Syongari &sc->vr_cdata.vr_parent_tag); 912177050Syongari if (error != 0) { 913177050Syongari device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 914177050Syongari goto fail; 915177050Syongari } 916177050Syongari /* Create tag for Tx ring. */ 917177050Syongari error = bus_dma_tag_create( 918177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 919177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 920177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 921177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 922177050Syongari NULL, NULL, /* filter, filterarg */ 923177050Syongari VR_TX_RING_SIZE, /* maxsize */ 924177050Syongari 1, /* nsegments */ 925177050Syongari VR_TX_RING_SIZE, /* maxsegsize */ 926177050Syongari 0, /* flags */ 927177050Syongari NULL, NULL, /* lockfunc, lockarg */ 928177050Syongari &sc->vr_cdata.vr_tx_ring_tag); 929177050Syongari if (error != 0) { 930177050Syongari device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 931177050Syongari goto fail; 932177050Syongari } 933177050Syongari 934177050Syongari /* Create tag for Rx ring. */ 935177050Syongari error = bus_dma_tag_create( 936177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 937177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 938177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 939177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 940177050Syongari NULL, NULL, /* filter, filterarg */ 941177050Syongari VR_RX_RING_SIZE, /* maxsize */ 942177050Syongari 1, /* nsegments */ 943177050Syongari VR_RX_RING_SIZE, /* maxsegsize */ 944177050Syongari 0, /* flags */ 945177050Syongari NULL, NULL, /* lockfunc, lockarg */ 946177050Syongari &sc->vr_cdata.vr_rx_ring_tag); 947177050Syongari if (error != 0) { 948177050Syongari device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 949177050Syongari goto fail; 950177050Syongari } 951177050Syongari 952177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 953177050Syongari tx_alignment = sizeof(uint32_t); 954177050Syongari else 955177050Syongari tx_alignment = 1; 956177050Syongari /* Create tag for Tx buffers. */ 957177050Syongari error = bus_dma_tag_create( 958177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 959177050Syongari tx_alignment, 0, /* alignment, boundary */ 960177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 961177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 962177050Syongari NULL, NULL, /* filter, filterarg */ 963177050Syongari MCLBYTES * VR_MAXFRAGS, /* maxsize */ 964177050Syongari VR_MAXFRAGS, /* nsegments */ 965177050Syongari MCLBYTES, /* maxsegsize */ 966177050Syongari 0, /* flags */ 967177050Syongari NULL, NULL, /* lockfunc, lockarg */ 968177050Syongari &sc->vr_cdata.vr_tx_tag); 969177050Syongari if (error != 0) { 970177050Syongari device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 971177050Syongari goto fail; 972177050Syongari } 973177050Syongari 974177050Syongari /* Create tag for Rx buffers. */ 975177050Syongari error = bus_dma_tag_create( 976177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 977177050Syongari VR_RX_ALIGN, 0, /* alignment, boundary */ 978177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 979177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 980177050Syongari NULL, NULL, /* filter, filterarg */ 981177050Syongari MCLBYTES, /* maxsize */ 982177050Syongari 1, /* nsegments */ 983177050Syongari MCLBYTES, /* maxsegsize */ 984177050Syongari 0, /* flags */ 985177050Syongari NULL, NULL, /* lockfunc, lockarg */ 986177050Syongari &sc->vr_cdata.vr_rx_tag); 987177050Syongari if (error != 0) { 988177050Syongari device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 989177050Syongari goto fail; 990177050Syongari } 991177050Syongari 992177050Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 993177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 994177050Syongari (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 995177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 996177050Syongari if (error != 0) { 997177050Syongari device_printf(sc->vr_dev, 998177050Syongari "failed to allocate DMA'able memory for Tx ring\n"); 999177050Syongari goto fail; 1000177050Syongari } 1001177050Syongari 1002177050Syongari ctx.vr_busaddr = 0; 1003177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 1004177050Syongari sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 1005177050Syongari VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1006177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1007177050Syongari device_printf(sc->vr_dev, 1008177050Syongari "failed to load DMA'able memory for Tx ring\n"); 1009177050Syongari goto fail; 1010177050Syongari } 1011177050Syongari sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 1012177050Syongari 1013177050Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1014177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 1015177050Syongari (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 1016177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 1017177050Syongari if (error != 0) { 1018177050Syongari device_printf(sc->vr_dev, 1019177050Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1020177050Syongari goto fail; 1021177050Syongari } 1022177050Syongari 1023177050Syongari ctx.vr_busaddr = 0; 1024177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1025177050Syongari sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1026177050Syongari VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1027177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1028177050Syongari device_printf(sc->vr_dev, 1029177050Syongari "failed to load DMA'able memory for Rx ring\n"); 1030177050Syongari goto fail; 1031177050Syongari } 1032177050Syongari sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1033177050Syongari 1034177050Syongari /* Create DMA maps for Tx buffers. */ 1035177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1036177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1037177050Syongari txd->tx_m = NULL; 1038177050Syongari txd->tx_dmamap = NULL; 1039177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1040177050Syongari &txd->tx_dmamap); 1041177050Syongari if (error != 0) { 1042177050Syongari device_printf(sc->vr_dev, 1043177050Syongari "failed to create Tx dmamap\n"); 1044177050Syongari goto fail; 1045177050Syongari } 1046177050Syongari } 1047177050Syongari /* Create DMA maps for Rx buffers. */ 1048177050Syongari if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1049177050Syongari &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1050177050Syongari device_printf(sc->vr_dev, 1051177050Syongari "failed to create spare Rx dmamap\n"); 1052177050Syongari goto fail; 1053177050Syongari } 1054177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1055177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1056177050Syongari rxd->rx_m = NULL; 1057177050Syongari rxd->rx_dmamap = NULL; 1058177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1059177050Syongari &rxd->rx_dmamap); 1060177050Syongari if (error != 0) { 1061177050Syongari device_printf(sc->vr_dev, 1062177050Syongari "failed to create Rx dmamap\n"); 1063177050Syongari goto fail; 1064177050Syongari } 1065177050Syongari } 1066177050Syongari 1067177050Syongarifail: 1068177050Syongari return (error); 1069177050Syongari} 1070177050Syongari 1071177050Syongaristatic void 1072177050Syongarivr_dma_free(struct vr_softc *sc) 1073177050Syongari{ 1074177050Syongari struct vr_txdesc *txd; 1075177050Syongari struct vr_rxdesc *rxd; 1076177050Syongari int i; 1077177050Syongari 1078177050Syongari /* Tx ring. */ 1079177050Syongari if (sc->vr_cdata.vr_tx_ring_tag) { 1080177050Syongari if (sc->vr_cdata.vr_tx_ring_map) 1081177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1082177050Syongari sc->vr_cdata.vr_tx_ring_map); 1083177050Syongari if (sc->vr_cdata.vr_tx_ring_map && 1084177050Syongari sc->vr_rdata.vr_tx_ring) 1085177050Syongari bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1086177050Syongari sc->vr_rdata.vr_tx_ring, 1087177050Syongari sc->vr_cdata.vr_tx_ring_map); 1088177050Syongari sc->vr_rdata.vr_tx_ring = NULL; 1089177050Syongari sc->vr_cdata.vr_tx_ring_map = NULL; 1090177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1091177050Syongari sc->vr_cdata.vr_tx_ring_tag = NULL; 1092177050Syongari } 1093177050Syongari /* Rx ring. */ 1094177050Syongari if (sc->vr_cdata.vr_rx_ring_tag) { 1095177050Syongari if (sc->vr_cdata.vr_rx_ring_map) 1096177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1097177050Syongari sc->vr_cdata.vr_rx_ring_map); 1098177050Syongari if (sc->vr_cdata.vr_rx_ring_map && 1099177050Syongari sc->vr_rdata.vr_rx_ring) 1100177050Syongari bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1101177050Syongari sc->vr_rdata.vr_rx_ring, 1102177050Syongari sc->vr_cdata.vr_rx_ring_map); 1103177050Syongari sc->vr_rdata.vr_rx_ring = NULL; 1104177050Syongari sc->vr_cdata.vr_rx_ring_map = NULL; 1105177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1106177050Syongari sc->vr_cdata.vr_rx_ring_tag = NULL; 1107177050Syongari } 1108177050Syongari /* Tx buffers. */ 1109177050Syongari if (sc->vr_cdata.vr_tx_tag) { 1110177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1111177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1112177050Syongari if (txd->tx_dmamap) { 1113177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1114177050Syongari txd->tx_dmamap); 1115177050Syongari txd->tx_dmamap = NULL; 1116177050Syongari } 1117177050Syongari } 1118177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1119177050Syongari sc->vr_cdata.vr_tx_tag = NULL; 1120177050Syongari } 1121177050Syongari /* Rx buffers. */ 1122177050Syongari if (sc->vr_cdata.vr_rx_tag) { 1123177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1124177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1125177050Syongari if (rxd->rx_dmamap) { 1126177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1127177050Syongari rxd->rx_dmamap); 1128177050Syongari rxd->rx_dmamap = NULL; 1129177050Syongari } 1130177050Syongari } 1131177050Syongari if (sc->vr_cdata.vr_rx_sparemap) { 1132177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1133177050Syongari sc->vr_cdata.vr_rx_sparemap); 1134177050Syongari sc->vr_cdata.vr_rx_sparemap = 0; 1135177050Syongari } 1136177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1137177050Syongari sc->vr_cdata.vr_rx_tag = NULL; 1138177050Syongari } 1139177050Syongari 1140177050Syongari if (sc->vr_cdata.vr_parent_tag) { 1141177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1142177050Syongari sc->vr_cdata.vr_parent_tag = NULL; 1143177050Syongari } 1144177050Syongari} 1145177050Syongari 114641502Swpaul/* 114741502Swpaul * Initialize the transmit descriptors. 114841502Swpaul */ 1149102336Salfredstatic int 1150177050Syongarivr_tx_ring_init(struct vr_softc *sc) 115141502Swpaul{ 1152177050Syongari struct vr_ring_data *rd; 1153177050Syongari struct vr_txdesc *txd; 1154177050Syongari bus_addr_t addr; 115541502Swpaul int i; 115641502Swpaul 1157177050Syongari sc->vr_cdata.vr_tx_prod = 0; 1158177050Syongari sc->vr_cdata.vr_tx_cons = 0; 1159177050Syongari sc->vr_cdata.vr_tx_cnt = 0; 1160177050Syongari sc->vr_cdata.vr_tx_pkts = 0; 1161177050Syongari 1162177050Syongari rd = &sc->vr_rdata; 1163177050Syongari bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1164177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1165177050Syongari if (i == VR_TX_RING_CNT - 1) 1166177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 1167177050Syongari else 1168177050Syongari addr = VR_TX_RING_ADDR(sc, i + 1); 1169177050Syongari rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1170177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1171177050Syongari txd->tx_m = NULL; 117241502Swpaul } 117341502Swpaul 1174177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1175177050Syongari sc->vr_cdata.vr_tx_ring_map, 1176177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1177177050Syongari 1178131503Sbms return (0); 117941502Swpaul} 118041502Swpaul 118141502Swpaul/* 118241502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 118341502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 118441502Swpaul * points back to the first. 118541502Swpaul */ 1186102336Salfredstatic int 1187177050Syongarivr_rx_ring_init(struct vr_softc *sc) 118841502Swpaul{ 1189177050Syongari struct vr_ring_data *rd; 1190177050Syongari struct vr_rxdesc *rxd; 1191177050Syongari bus_addr_t addr; 119241502Swpaul int i; 119341502Swpaul 1194177050Syongari sc->vr_cdata.vr_rx_cons = 0; 1195131518Sbms 1196177050Syongari rd = &sc->vr_rdata; 1197177050Syongari bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1198177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1199177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1200177050Syongari rxd->rx_m = NULL; 1201177050Syongari rxd->desc = &rd->vr_rx_ring[i]; 1202177050Syongari if (i == VR_RX_RING_CNT - 1) 1203177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 1204177050Syongari else 1205177050Syongari addr = VR_RX_RING_ADDR(sc, i + 1); 1206177050Syongari rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1207177050Syongari if (vr_newbuf(sc, i) != 0) 1208131503Sbms return (ENOBUFS); 120941502Swpaul } 121041502Swpaul 1211177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1212177050Syongari sc->vr_cdata.vr_rx_ring_map, 1213177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 121441502Swpaul 1215131503Sbms return (0); 121641502Swpaul} 121741502Swpaul 1218177050Syongaristatic __inline void 1219177050Syongarivr_discard_rxbuf(struct vr_rxdesc *rxd) 1220177050Syongari{ 1221177050Syongari struct vr_desc *desc; 1222177050Syongari 1223177050Syongari desc = rxd->desc; 1224177050Syongari desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1225177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 1226177050Syongari} 1227177050Syongari 122841502Swpaul/* 122941502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 123041502Swpaul * Note: the length fields are only 11 bits wide, which means the 123141502Swpaul * largest size we can specify is 2047. This is important because 123241502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 123341502Swpaul * overflow the field and make a mess. 123441502Swpaul */ 1235102336Salfredstatic int 1236177050Syongarivr_newbuf(struct vr_softc *sc, int idx) 123741502Swpaul{ 1238177050Syongari struct vr_desc *desc; 1239177050Syongari struct vr_rxdesc *rxd; 1240177050Syongari struct mbuf *m; 1241177050Syongari bus_dma_segment_t segs[1]; 1242177050Syongari bus_dmamap_t map; 1243177050Syongari int nsegs; 124441502Swpaul 1245177050Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1246177050Syongari if (m == NULL) 1247177050Syongari return (ENOBUFS); 1248177050Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 1249177050Syongari m_adj(m, sizeof(uint64_t)); 1250177050Syongari 1251177050Syongari if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1252177050Syongari sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1253177050Syongari m_freem(m); 1254177050Syongari return (ENOBUFS); 125541502Swpaul } 1256177050Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 125741502Swpaul 1258177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1259177050Syongari if (rxd->rx_m != NULL) { 1260177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1261177050Syongari BUS_DMASYNC_POSTREAD); 1262177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1263177050Syongari } 1264177050Syongari map = rxd->rx_dmamap; 1265177050Syongari rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1266177050Syongari sc->vr_cdata.vr_rx_sparemap = map; 1267177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1268177050Syongari BUS_DMASYNC_PREREAD); 1269177050Syongari rxd->rx_m = m; 1270177050Syongari desc = rxd->desc; 1271177050Syongari desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1272177050Syongari desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1273177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 127449610Swpaul 1275131503Sbms return (0); 127641502Swpaul} 127741502Swpaul 1278177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1279177050Syongaristatic __inline void 1280177050Syongarivr_fixup_rx(struct mbuf *m) 1281177050Syongari{ 1282177050Syongari uint16_t *src, *dst; 1283177050Syongari int i; 1284177050Syongari 1285177050Syongari src = mtod(m, uint16_t *); 1286177050Syongari dst = src - 1; 1287177050Syongari 1288177050Syongari for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1289177050Syongari *dst++ = *src++; 1290177050Syongari 1291177050Syongari m->m_data -= ETHER_ALIGN; 1292177050Syongari} 1293177050Syongari#endif 1294177050Syongari 129541502Swpaul/* 129641502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 129741502Swpaul * the higher level protocols. 129841502Swpaul */ 1299102336Salfredstatic void 1300131503Sbmsvr_rxeof(struct vr_softc *sc) 130141502Swpaul{ 1302177050Syongari struct vr_rxdesc *rxd; 1303177050Syongari struct mbuf *m; 1304131503Sbms struct ifnet *ifp; 1305168952Sphk struct vr_desc *cur_rx; 1306177050Syongari int cons, prog, total_len; 1307168827Sphk uint32_t rxstat, rxctl; 130841502Swpaul 1309122689Ssam VR_LOCK_ASSERT(sc); 1310147256Sbrooks ifp = sc->vr_ifp; 1311177050Syongari cons = sc->vr_cdata.vr_rx_cons; 131241502Swpaul 1313177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1314177050Syongari sc->vr_cdata.vr_rx_ring_map, 1315177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1316177050Syongari 1317177050Syongari for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1318127901Sru#ifdef DEVICE_POLLING 1319150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1320127901Sru if (sc->rxcycles <= 0) 1321127901Sru break; 1322127901Sru sc->rxcycles--; 1323127901Sru } 1324150789Sglebius#endif 1325177050Syongari cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1326177050Syongari rxstat = le32toh(cur_rx->vr_status); 1327177050Syongari rxctl = le32toh(cur_rx->vr_ctl); 1328177050Syongari if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1329177050Syongari break; 133041502Swpaul 1331177050Syongari prog++; 1332177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1333177050Syongari m = rxd->rx_m; 1334177050Syongari 133541502Swpaul /* 133641502Swpaul * If an error occurs, update stats, clear the 133741502Swpaul * status word and leave the mbuf cluster in place: 133841502Swpaul * it should simply get re-used next time this descriptor 1339131503Sbms * comes up in the ring. 1340177050Syongari * We don't support SG in Rx path yet, so discard 1341177050Syongari * partial frame. 134241502Swpaul */ 1343180551Syongari if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1344180551Syongari (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1345177050Syongari (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 134641502Swpaul ifp->if_ierrors++; 1347177050Syongari sc->vr_stat.rx_errors++; 1348110131Ssilby if (rxstat & VR_RXSTAT_CRCERR) 1349177050Syongari sc->vr_stat.rx_crc_errors++; 1350110131Ssilby if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1351177050Syongari sc->vr_stat.rx_alignment++; 1352110131Ssilby if (rxstat & VR_RXSTAT_FIFOOFLOW) 1353177050Syongari sc->vr_stat.rx_fifo_overflows++; 1354110131Ssilby if (rxstat & VR_RXSTAT_GIANT) 1355177050Syongari sc->vr_stat.rx_giants++; 1356110131Ssilby if (rxstat & VR_RXSTAT_RUNT) 1357177050Syongari sc->vr_stat.rx_runts++; 1358110131Ssilby if (rxstat & VR_RXSTAT_BUFFERR) 1359177050Syongari sc->vr_stat.rx_no_buffers++; 1360177050Syongari#ifdef VR_SHOW_ERRORS 1361177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1362177050Syongari __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1363177050Syongari#endif 1364177050Syongari vr_discard_rxbuf(rxd); 136541502Swpaul continue; 136641502Swpaul } 136741502Swpaul 1368177050Syongari if (vr_newbuf(sc, cons) != 0) { 1369177050Syongari ifp->if_iqdrops++; 1370177050Syongari sc->vr_stat.rx_errors++; 1371177050Syongari sc->vr_stat.rx_no_mbufs++; 1372177050Syongari vr_discard_rxbuf(rxd); 1373177050Syongari continue; 1374168827Sphk } 137541502Swpaul 137641502Swpaul /* 137742048Swpaul * XXX The VIA Rhine chip includes the CRC with every 137842048Swpaul * received frame, and there's no way to turn this 137942048Swpaul * behavior off (at least, I can't find anything in 1380131503Sbms * the manual that explains how to do it) so we have 138142048Swpaul * to trim off the CRC manually. 138242048Swpaul */ 1383177050Syongari total_len = VR_RXBYTES(rxstat); 138442048Swpaul total_len -= ETHER_CRC_LEN; 1385177050Syongari m->m_pkthdr.len = m->m_len = total_len; 1386177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1387177050Syongari /* 1388177050Syongari * RX buffers must be 32-bit aligned. 1389177050Syongari * Ignore the alignment problems on the non-strict alignment 1390177050Syongari * platform. The performance hit incurred due to unaligned 1391177050Syongari * accesses is much smaller than the hit produced by forcing 1392177050Syongari * buffer copies all the time. 1393177050Syongari */ 1394177050Syongari vr_fixup_rx(m); 1395177050Syongari#endif 1396177050Syongari m->m_pkthdr.rcvif = ifp; 1397177050Syongari ifp->if_ipackets++; 1398177050Syongari sc->vr_stat.rx_ok++; 1399177050Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1400177050Syongari (rxstat & VR_RXSTAT_FRAG) == 0 && 1401177050Syongari (rxctl & VR_RXCTL_IP) != 0) { 1402177050Syongari /* Checksum is valid for non-fragmented IP packets. */ 1403177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1404177050Syongari if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1405177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1406177050Syongari if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1407177050Syongari m->m_pkthdr.csum_flags |= 1408177050Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1409177050Syongari if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1410177050Syongari m->m_pkthdr.csum_data = 0xffff; 1411177050Syongari } 1412177050Syongari } 141341502Swpaul } 1414122689Ssam VR_UNLOCK(sc); 1415106936Ssam (*ifp->if_input)(ifp, m); 1416122689Ssam VR_LOCK(sc); 141741502Swpaul } 141841502Swpaul 1419177050Syongari if (prog > 0) { 1420177050Syongari sc->vr_cdata.vr_rx_cons = cons; 1421177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1422177050Syongari sc->vr_cdata.vr_rx_ring_map, 1423177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1424131503Sbms } 142541502Swpaul} 142641502Swpaul 142741502Swpaul/* 142841502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 142941502Swpaul * the list buffers. 143041502Swpaul */ 1431102336Salfredstatic void 1432131503Sbmsvr_txeof(struct vr_softc *sc) 143341502Swpaul{ 1434177050Syongari struct vr_txdesc *txd; 1435168952Sphk struct vr_desc *cur_tx; 1436177050Syongari struct ifnet *ifp; 1437177050Syongari uint32_t txctl, txstat; 1438177050Syongari int cons, prod; 143941502Swpaul 1440131518Sbms VR_LOCK_ASSERT(sc); 144141502Swpaul 1442177050Syongari cons = sc->vr_cdata.vr_tx_cons; 1443177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1444177050Syongari if (cons == prod) 1445177050Syongari return; 1446177050Syongari 1447177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1448177050Syongari sc->vr_cdata.vr_tx_ring_map, 1449177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1450177050Syongari 1451177050Syongari ifp = sc->vr_ifp; 145241502Swpaul /* 145341502Swpaul * Go through our tx list and free mbufs for those 145441502Swpaul * frames that have been transmitted. 145541502Swpaul */ 1456177050Syongari for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1457177050Syongari cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1458177050Syongari txctl = le32toh(cur_tx->vr_ctl); 1459177050Syongari txstat = le32toh(cur_tx->vr_status); 1460177050Syongari if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1461177050Syongari break; 146241502Swpaul 1463177050Syongari sc->vr_cdata.vr_tx_cnt--; 1464177050Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1465177050Syongari /* Only the first descriptor in the chain is valid. */ 1466177050Syongari if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1467177050Syongari continue; 146841502Swpaul 1469177050Syongari txd = &sc->vr_cdata.vr_txdesc[cons]; 1470177050Syongari KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1471177050Syongari __func__)); 1472177050Syongari 1473177050Syongari if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1474177050Syongari ifp->if_oerrors++; 1475177050Syongari sc->vr_stat.tx_errors++; 1476177050Syongari if ((txstat & VR_TXSTAT_ABRT) != 0) { 1477177050Syongari /* Give up and restart Tx. */ 1478177050Syongari sc->vr_stat.tx_abort++; 1479177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1480177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1481177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1482177050Syongari txd->tx_dmamap); 1483177050Syongari m_freem(txd->tx_m); 1484177050Syongari txd->tx_m = NULL; 1485177050Syongari VR_INC(cons, VR_TX_RING_CNT); 1486177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1487177050Syongari if (vr_tx_stop(sc) != 0) { 1488177050Syongari device_printf(sc->vr_dev, 1489177050Syongari "%s: Tx shutdown error -- " 1490177050Syongari "resetting\n", __func__); 1491177050Syongari sc->vr_flags |= VR_F_RESTART; 1492177050Syongari return; 1493177050Syongari } 1494177050Syongari vr_tx_start(sc); 1495110131Ssilby break; 1496110131Ssilby } 1497177050Syongari if ((sc->vr_revid < REV_ID_VT3071_A && 1498177050Syongari (txstat & VR_TXSTAT_UNDERRUN)) || 1499177050Syongari (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1500177050Syongari sc->vr_stat.tx_underrun++; 1501177050Syongari /* Retry and restart Tx. */ 1502177050Syongari sc->vr_cdata.vr_tx_cnt++; 1503177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1504177050Syongari cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1505177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1506177050Syongari sc->vr_cdata.vr_tx_ring_map, 1507177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1508177050Syongari vr_tx_underrun(sc); 1509177050Syongari return; 1510177050Syongari } 1511177050Syongari if ((txstat & VR_TXSTAT_DEFER) != 0) { 151241502Swpaul ifp->if_collisions++; 1513177050Syongari sc->vr_stat.tx_collisions++; 1514177050Syongari } 1515177050Syongari if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 151641502Swpaul ifp->if_collisions++; 1517177050Syongari sc->vr_stat.tx_late_collisions++; 1518177050Syongari } 1519177050Syongari } else { 1520177050Syongari sc->vr_stat.tx_ok++; 1521177050Syongari ifp->if_opackets++; 152241502Swpaul } 152341502Swpaul 1524177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1525177050Syongari BUS_DMASYNC_POSTWRITE); 1526177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1527177050Syongari if (sc->vr_revid < REV_ID_VT3071_A) { 1528177050Syongari ifp->if_collisions += 1529177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1530177050Syongari sc->vr_stat.tx_collisions += 1531177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1532177050Syongari } else { 1533177050Syongari ifp->if_collisions += (txstat & 0x0f); 1534177050Syongari sc->vr_stat.tx_collisions += (txstat & 0x0f); 1535177050Syongari } 1536177050Syongari m_freem(txd->tx_m); 1537177050Syongari txd->tx_m = NULL; 1538177050Syongari } 153941502Swpaul 1540177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1541177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 1542177050Syongari sc->vr_watchdog_timer = 0; 154341502Swpaul} 154441502Swpaul 1545102336Salfredstatic void 1546131503Sbmsvr_tick(void *xsc) 154751432Swpaul{ 1548177050Syongari struct vr_softc *sc; 154951432Swpaul struct mii_data *mii; 155051432Swpaul 1551177050Syongari sc = (struct vr_softc *)xsc; 1552177050Syongari 1553151911Sjhb VR_LOCK_ASSERT(sc); 1554131517Sbms 1555177050Syongari if ((sc->vr_flags & VR_F_RESTART) != 0) { 1556162315Sglebius device_printf(sc->vr_dev, "restarting\n"); 1557177050Syongari sc->vr_stat.num_restart++; 1558110131Ssilby vr_stop(sc); 1559110131Ssilby vr_reset(sc); 1560131844Sbms vr_init_locked(sc); 1561110131Ssilby sc->vr_flags &= ~VR_F_RESTART; 1562110131Ssilby } 1563110131Ssilby 156451432Swpaul mii = device_get_softc(sc->vr_miibus); 156551432Swpaul mii_tick(mii); 1566177050Syongari vr_watchdog(sc); 1567151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 156851432Swpaul} 156951432Swpaul 1570127901Sru#ifdef DEVICE_POLLING 1571127901Srustatic poll_handler_t vr_poll; 1572131844Sbmsstatic poll_handler_t vr_poll_locked; 1573127901Sru 1574102336Salfredstatic void 1575127901Sruvr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1576127901Sru{ 1577177050Syongari struct vr_softc *sc; 1578127901Sru 1579177050Syongari sc = ifp->if_softc; 1580177050Syongari 1581127901Sru VR_LOCK(sc); 1582177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1583150789Sglebius vr_poll_locked(ifp, cmd, count); 1584131844Sbms VR_UNLOCK(sc); 1585131844Sbms} 1586131517Sbms 1587131844Sbmsstatic void 1588131844Sbmsvr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1589131844Sbms{ 1590177050Syongari struct vr_softc *sc; 1591131844Sbms 1592177050Syongari sc = ifp->if_softc; 1593177050Syongari 1594131844Sbms VR_LOCK_ASSERT(sc); 1595131844Sbms 1596127901Sru sc->rxcycles = count; 1597127901Sru vr_rxeof(sc); 1598127901Sru vr_txeof(sc); 1599133006Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1600131844Sbms vr_start_locked(ifp); 1601127901Sru 1602131503Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1603131503Sbms uint16_t status; 1604127901Sru 1605131503Sbms /* Also check status register. */ 1606127901Sru status = CSR_READ_2(sc, VR_ISR); 1607127901Sru if (status) 1608127901Sru CSR_WRITE_2(sc, VR_ISR, status); 1609127901Sru 1610127901Sru if ((status & VR_INTRS) == 0) 1611131844Sbms return; 1612127901Sru 1613177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1614177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1615177050Syongari if (vr_error(sc, status) != 0) 1616177050Syongari return; 1617127901Sru } 1618177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1619177050Syongari#ifdef VR_SHOW_ERRORS 1620177050Syongari device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1621177050Syongari __func__, status, VR_ISR_ERR_BITS); 1622177050Syongari#endif 1623177050Syongari vr_rx_start(sc); 1624127901Sru } 1625177050Syongari } 1626177050Syongari} 1627177050Syongari#endif /* DEVICE_POLLING */ 1628127901Sru 1629177050Syongari/* Back off the transmit threshold. */ 1630177050Syongaristatic void 1631177050Syongarivr_tx_underrun(struct vr_softc *sc) 1632177050Syongari{ 1633177050Syongari int thresh; 1634127901Sru 1635177050Syongari device_printf(sc->vr_dev, "Tx underrun -- "); 1636177050Syongari if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1637177050Syongari thresh = sc->vr_txthresh; 1638177050Syongari sc->vr_txthresh++; 1639177050Syongari if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1640177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 1641177050Syongari printf("using store and forward mode\n"); 1642177050Syongari } else 1643177050Syongari printf("increasing Tx threshold(%d -> %d)\n", 1644177050Syongari vr_tx_threshold_tables[thresh].value, 1645177050Syongari vr_tx_threshold_tables[thresh + 1].value); 1646177050Syongari } else 1647177050Syongari printf("\n"); 1648177050Syongari sc->vr_stat.tx_underrun++; 1649177050Syongari if (vr_tx_stop(sc) != 0) { 1650177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1651177050Syongari "resetting\n", __func__); 1652177050Syongari sc->vr_flags |= VR_F_RESTART; 1653177050Syongari return; 1654127901Sru } 1655177050Syongari vr_tx_start(sc); 1656127901Sru} 1657127901Sru 1658127901Srustatic void 1659131503Sbmsvr_intr(void *arg) 166041502Swpaul{ 1661177050Syongari struct vr_softc *sc; 1662177050Syongari struct ifnet *ifp; 1663131503Sbms uint16_t status; 166441502Swpaul 1665177050Syongari sc = (struct vr_softc *)arg; 1666177050Syongari 166767087Swpaul VR_LOCK(sc); 1668131844Sbms 1669177050Syongari if (sc->vr_suspended != 0) 1670131844Sbms goto done_locked; 1671131844Sbms 1672177050Syongari status = CSR_READ_2(sc, VR_ISR); 1673177050Syongari if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1674177050Syongari goto done_locked; 1675177050Syongari 1676177050Syongari ifp = sc->vr_ifp; 1677127901Sru#ifdef DEVICE_POLLING 1678177050Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1679131844Sbms goto done_locked; 1680150789Sglebius#endif 1681131844Sbms 1682131844Sbms /* Suppress unwanted interrupts. */ 1683177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1684177050Syongari (sc->vr_flags & VR_F_RESTART) != 0) { 1685177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1686177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1687131844Sbms goto done_locked; 168841502Swpaul } 168941502Swpaul 169041502Swpaul /* Disable interrupts. */ 169141502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 169241502Swpaul 1693177050Syongari for (; (status & VR_INTRS) != 0;) { 1694177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1695177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1696177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1697177050Syongari if (vr_error(sc, status) != 0) { 1698177050Syongari VR_UNLOCK(sc); 1699177050Syongari return; 1700177050Syongari } 1701177050Syongari } 1702177050Syongari vr_rxeof(sc); 1703177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1704177050Syongari#ifdef VR_SHOW_ERRORS 1705177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1706177050Syongari __func__, status, VR_ISR_ERR_BITS); 1707177050Syongari#endif 1708177050Syongari /* Restart Rx if RxDMA SM was stopped. */ 1709177050Syongari vr_rx_start(sc); 1710177050Syongari } 1711177050Syongari vr_txeof(sc); 171241502Swpaul status = CSR_READ_2(sc, VR_ISR); 1713177050Syongari } 1714168813Sphk 1715177050Syongari /* Re-enable interrupts. */ 1716177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 171741502Swpaul 1718177050Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1719177050Syongari vr_start_locked(ifp); 172041502Swpaul 1721177050Syongaridone_locked: 1722177050Syongari VR_UNLOCK(sc); 1723177050Syongari} 172441502Swpaul 1725177050Syongaristatic int 1726177050Syongarivr_error(struct vr_softc *sc, uint16_t status) 1727177050Syongari{ 1728177050Syongari uint16_t pcis; 1729110131Ssilby 1730177050Syongari status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1731177050Syongari if ((status & VR_ISR_BUSERR) != 0) { 1732177050Syongari status &= ~VR_ISR_BUSERR; 1733177050Syongari sc->vr_stat.bus_errors++; 1734177050Syongari /* Disable further interrupts. */ 1735177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1736177050Syongari pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1737177050Syongari device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1738177050Syongari "resetting\n", pcis); 1739177050Syongari pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1740177050Syongari sc->vr_flags |= VR_F_RESTART; 1741177050Syongari return (EAGAIN); 1742177050Syongari } 1743177050Syongari if ((status & VR_ISR_LINKSTAT2) != 0) { 1744177050Syongari /* Link state change, duplex changes etc. */ 1745177050Syongari status &= ~VR_ISR_LINKSTAT2; 1746177050Syongari } 1747177050Syongari if ((status & VR_ISR_STATSOFLOW) != 0) { 1748177050Syongari status &= ~VR_ISR_STATSOFLOW; 1749177050Syongari if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1750177050Syongari /* Update MIB counters. */ 175141502Swpaul } 1752177050Syongari } 175341502Swpaul 1754177050Syongari if (status != 0) 1755177050Syongari device_printf(sc->vr_dev, 1756177050Syongari "unhandled interrupt, status = 0x%04x\n", status); 1757177050Syongari return (0); 1758177050Syongari} 1759177050Syongari 1760177050Syongari/* 1761177050Syongari * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1762177050Syongari * pointers to the fragment pointers. 1763177050Syongari */ 1764177050Syongaristatic int 1765177050Syongarivr_encap(struct vr_softc *sc, struct mbuf **m_head) 1766177050Syongari{ 1767177050Syongari struct vr_txdesc *txd; 1768177050Syongari struct vr_desc *desc; 1769177050Syongari struct mbuf *m; 1770177050Syongari bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1771177050Syongari uint32_t csum_flags, txctl; 1772177050Syongari int error, i, nsegs, prod, si; 1773177050Syongari int padlen; 1774177050Syongari 1775177050Syongari VR_LOCK_ASSERT(sc); 1776177050Syongari 1777177050Syongari M_ASSERTPKTHDR((*m_head)); 1778177050Syongari 1779177050Syongari /* 1780177050Syongari * Some VIA Rhine wants packet buffers to be longword 1781177050Syongari * aligned, but very often our mbufs aren't. Rather than 1782177050Syongari * waste time trying to decide when to copy and when not 1783177050Syongari * to copy, just do it all the time. 1784177050Syongari */ 1785177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1786177050Syongari m = m_defrag(*m_head, M_DONTWAIT); 1787177050Syongari if (m == NULL) { 1788177050Syongari m_freem(*m_head); 1789177050Syongari *m_head = NULL; 1790177050Syongari return (ENOBUFS); 179141502Swpaul } 1792177050Syongari *m_head = m; 1793177050Syongari } 179441502Swpaul 1795177050Syongari /* 1796177050Syongari * The Rhine chip doesn't auto-pad, so we have to make 1797177050Syongari * sure to pad short frames out to the minimum frame length 1798177050Syongari * ourselves. 1799177050Syongari */ 1800177050Syongari if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1801177050Syongari m = *m_head; 1802177050Syongari padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1803177050Syongari if (M_WRITABLE(m) == 0) { 1804177050Syongari /* Get a writable copy. */ 1805177050Syongari m = m_dup(*m_head, M_DONTWAIT); 1806177050Syongari m_freem(*m_head); 1807177050Syongari if (m == NULL) { 1808177050Syongari *m_head = NULL; 1809177050Syongari return (ENOBUFS); 1810127901Sru } 1811177050Syongari *m_head = m; 181241502Swpaul } 1813177050Syongari if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1814177050Syongari m = m_defrag(m, M_DONTWAIT); 1815177050Syongari if (m == NULL) { 1816177050Syongari m_freem(*m_head); 1817177050Syongari *m_head = NULL; 1818177050Syongari return (ENOBUFS); 1819177050Syongari } 1820177050Syongari } 1821177050Syongari /* 1822177050Syongari * Manually pad short frames, and zero the pad space 1823177050Syongari * to avoid leaking data. 1824177050Syongari */ 1825177050Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1826177050Syongari m->m_pkthdr.len += padlen; 1827177050Syongari m->m_len = m->m_pkthdr.len; 1828177050Syongari *m_head = m; 182941502Swpaul } 183041502Swpaul 1831177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1832177050Syongari txd = &sc->vr_cdata.vr_txdesc[prod]; 1833177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1834177050Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1835177050Syongari if (error == EFBIG) { 1836177050Syongari m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1837177050Syongari if (m == NULL) { 1838177050Syongari m_freem(*m_head); 1839177050Syongari *m_head = NULL; 1840177050Syongari return (ENOBUFS); 1841177050Syongari } 1842177050Syongari *m_head = m; 1843177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1844177050Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1845177050Syongari if (error != 0) { 1846177050Syongari m_freem(*m_head); 1847177050Syongari *m_head = NULL; 1848177050Syongari return (error); 1849177050Syongari } 1850177050Syongari } else if (error != 0) 1851177050Syongari return (error); 1852177050Syongari if (nsegs == 0) { 1853177050Syongari m_freem(*m_head); 1854177050Syongari *m_head = NULL; 1855177050Syongari return (EIO); 1856177050Syongari } 185741502Swpaul 1858177050Syongari /* Check number of available descriptors. */ 1859177050Syongari if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1860177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1861177050Syongari return (ENOBUFS); 1862177050Syongari } 1863131844Sbms 1864177050Syongari txd->tx_m = *m_head; 1865177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1866177050Syongari BUS_DMASYNC_PREWRITE); 1867177050Syongari 1868177050Syongari /* Set checksum offload. */ 1869177050Syongari csum_flags = 0; 1870177050Syongari if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1871177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1872177050Syongari csum_flags |= VR_TXCTL_IPCSUM; 1873177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1874177050Syongari csum_flags |= VR_TXCTL_TCPCSUM; 1875177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1876177050Syongari csum_flags |= VR_TXCTL_UDPCSUM; 1877177050Syongari } 1878177050Syongari 1879177050Syongari /* 1880177050Syongari * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1881177050Syongari * is required for all descriptors regardless of single or 1882177050Syongari * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1883177050Syongari * the first descriptor for a multi-fragmented frames. Without 1884177050Syongari * that VIA Rhine chip generates Tx underrun interrupts and can't 1885177050Syongari * send any frames. 1886177050Syongari */ 1887177050Syongari si = prod; 1888177050Syongari for (i = 0; i < nsegs; i++) { 1889177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1890177050Syongari desc->vr_status = 0; 1891177050Syongari txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1892177050Syongari if (i == 0) 1893177050Syongari txctl |= VR_TXCTL_FIRSTFRAG; 1894177050Syongari desc->vr_ctl = htole32(txctl); 1895177050Syongari desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1896177050Syongari sc->vr_cdata.vr_tx_cnt++; 1897177050Syongari VR_INC(prod, VR_TX_RING_CNT); 1898177050Syongari } 1899177050Syongari /* Update producer index. */ 1900177050Syongari sc->vr_cdata.vr_tx_prod = prod; 1901177050Syongari 1902177050Syongari prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1903177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1904177050Syongari 1905177050Syongari /* 1906177050Syongari * Set EOP on the last desciptor and reuqest Tx completion 1907177050Syongari * interrupt for every VR_TX_INTR_THRESH-th frames. 1908177050Syongari */ 1909177050Syongari VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1910177050Syongari if (sc->vr_cdata.vr_tx_pkts == 0) 1911177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1912177050Syongari else 1913177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1914177050Syongari 1915177050Syongari /* Lastly turn the first descriptor ownership to hardware. */ 1916177050Syongari desc = &sc->vr_rdata.vr_tx_ring[si]; 1917177050Syongari desc->vr_status |= htole32(VR_TXSTAT_OWN); 1918177050Syongari 1919177050Syongari /* Sync descriptors. */ 1920177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1921177050Syongari sc->vr_cdata.vr_tx_ring_map, 1922177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1923177050Syongari 1924177050Syongari return (0); 192541502Swpaul} 192641502Swpaul 1927102336Salfredstatic void 1928131503Sbmsvr_start(struct ifnet *ifp) 192941502Swpaul{ 1930177050Syongari struct vr_softc *sc; 1931131844Sbms 1932177050Syongari sc = ifp->if_softc; 1933131844Sbms VR_LOCK(sc); 1934131844Sbms vr_start_locked(ifp); 1935131844Sbms VR_UNLOCK(sc); 1936131844Sbms} 1937131844Sbms 1938131844Sbmsstatic void 1939131844Sbmsvr_start_locked(struct ifnet *ifp) 1940131844Sbms{ 1941177050Syongari struct vr_softc *sc; 1942177050Syongari struct mbuf *m_head; 1943177050Syongari int enq; 194441502Swpaul 1945177050Syongari sc = ifp->if_softc; 1946177050Syongari 1947177050Syongari VR_LOCK_ASSERT(sc); 1948177050Syongari 1949177050Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1950177050Syongari IFF_DRV_RUNNING || sc->vr_link == 0) 1951127901Sru return; 1952127901Sru 1953177050Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1954177050Syongari sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1955177050Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 195641502Swpaul if (m_head == NULL) 195741502Swpaul break; 1958168813Sphk /* 1959177050Syongari * Pack the data into the transmit ring. If we 1960177050Syongari * don't have room, set the OACTIVE flag and wait 1961177050Syongari * for the NIC to drain the ring. 1962168813Sphk */ 1963177050Syongari if (vr_encap(sc, &m_head)) { 1964177050Syongari if (m_head == NULL) 1965168813Sphk break; 1966177050Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1967177050Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1968177050Syongari break; 1969168813Sphk } 197051583Swpaul 1971177050Syongari enq++; 1972168813Sphk /* 1973168813Sphk * If there's a BPF listener, bounce a copy of this frame 1974168813Sphk * to him. 1975168813Sphk */ 1976177050Syongari ETHER_BPF_MTAP(ifp, m_head); 1977127901Sru } 1978177050Syongari 1979177050Syongari if (enq > 0) { 1980177050Syongari /* Tell the chip to start transmitting. */ 1981177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1982177050Syongari /* Set a timeout in case the chip goes out to lunch. */ 1983177050Syongari sc->vr_watchdog_timer = 5; 1984177050Syongari } 1985131844Sbms} 198641502Swpaul 1987131844Sbmsstatic void 1988131844Sbmsvr_init(void *xsc) 1989131844Sbms{ 1990177050Syongari struct vr_softc *sc; 1991131844Sbms 1992177050Syongari sc = (struct vr_softc *)xsc; 1993131844Sbms VR_LOCK(sc); 1994131844Sbms vr_init_locked(sc); 199567087Swpaul VR_UNLOCK(sc); 199641502Swpaul} 199741502Swpaul 1998102336Salfredstatic void 1999131844Sbmsvr_init_locked(struct vr_softc *sc) 200041502Swpaul{ 2001177050Syongari struct ifnet *ifp; 200251432Swpaul struct mii_data *mii; 2003177050Syongari bus_addr_t addr; 200473963Swpaul int i; 200541502Swpaul 2006131844Sbms VR_LOCK_ASSERT(sc); 200741502Swpaul 2008177050Syongari ifp = sc->vr_ifp; 200951432Swpaul mii = device_get_softc(sc->vr_miibus); 201041502Swpaul 2011131503Sbms /* Cancel pending I/O and free all RX/TX buffers. */ 201241502Swpaul vr_stop(sc); 201341502Swpaul vr_reset(sc); 201441502Swpaul 2015131503Sbms /* Set our station address. */ 201673963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 2017152315Sru CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2018131503Sbms 2019131503Sbms /* Set DMA size. */ 2020101375Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2021101375Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 202273963Swpaul 2023131503Sbms /* 2024101375Ssilby * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2025101108Ssilby * so we must set both. 2026101108Ssilby */ 2027101108Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2028110131Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2029101108Ssilby 2030101108Ssilby VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2031177050Syongari VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2032101108Ssilby 203341502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2034110131Ssilby VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 203541502Swpaul 203641502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2037177050Syongari VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 203841502Swpaul 203941502Swpaul /* Init circular RX list. */ 2040177050Syongari if (vr_rx_ring_init(sc) != 0) { 2041162315Sglebius device_printf(sc->vr_dev, 2042151773Sjhb "initialization failed: no memory for rx buffers\n"); 204341502Swpaul vr_stop(sc); 204441502Swpaul return; 204541502Swpaul } 204641502Swpaul 2047131503Sbms /* Init tx descriptors. */ 2048177050Syongari vr_tx_ring_init(sc); 204941502Swpaul 2050177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2051180552Syongari uint8_t vcam[2] = { 0, 0 }; 2052180552Syongari 2053180552Syongari /* Disable VLAN hardware tag insertion/stripping. */ 2054180552Syongari VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2055180552Syongari /* Disable VLAN hardware filtering. */ 2056180552Syongari VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2057180552Syongari /* Disable all CAM entries. */ 2058180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, 0); 2059180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 0); 2060180552Syongari /* Enable the first VLAN CAM. */ 2061180552Syongari vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2062180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 1); 2063177050Syongari } 206441502Swpaul 206541502Swpaul /* 2066177050Syongari * Set up receive filter. 206741502Swpaul */ 2068177050Syongari vr_set_filter(sc); 206941502Swpaul 207041502Swpaul /* 2071177050Syongari * Load the address of the RX ring. 207241502Swpaul */ 2073177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 2074177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2075177050Syongari /* 2076177050Syongari * Load the address of the TX ring. 2077177050Syongari */ 2078177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 2079177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2080177050Syongari /* Default : full-duplex, no Tx poll. */ 2081177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 208241502Swpaul 2083177050Syongari /* Set flow-control parameters for Rhine III. */ 2084177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 2085177050Syongari /* Rx buffer count available for incoming packet. */ 2086177050Syongari CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT); 2087177050Syongari /* 2088177050Syongari * Tx pause low threshold : 16 free receive buffers 2089177050Syongari * Tx pause XON high threshold : 48 free receive buffers 2090177050Syongari */ 2091177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, 2092177050Syongari VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF); 2093177050Syongari /* Set Tx pause timer. */ 2094177050Syongari CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2095177050Syongari } 2096177050Syongari 209741502Swpaul /* Enable receiver and transmitter. */ 2098177050Syongari CSR_WRITE_1(sc, VR_CR0, 2099177050Syongari VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 210041502Swpaul 2101127901Sru CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2102127901Sru#ifdef DEVICE_POLLING 210341502Swpaul /* 2104127901Sru * Disable interrupts if we are polling. 2105127901Sru */ 2106150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 2107127901Sru CSR_WRITE_2(sc, VR_IMR, 0); 2108131503Sbms else 2109150789Sglebius#endif 2110127901Sru /* 2111177050Syongari * Enable interrupts and disable MII intrs. 211241502Swpaul */ 211341502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2114177050Syongari if (sc->vr_revid > REV_ID_VT6102_A) 2115177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 211641502Swpaul 2117177050Syongari sc->vr_link = 0; 211851432Swpaul mii_mediachg(mii); 211941502Swpaul 2120148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2121148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 212241502Swpaul 2123151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 212441502Swpaul} 212541502Swpaul 212641502Swpaul/* 212741502Swpaul * Set media options. 212841502Swpaul */ 2129102336Salfredstatic int 2130131503Sbmsvr_ifmedia_upd(struct ifnet *ifp) 213141502Swpaul{ 2132177050Syongari struct vr_softc *sc; 2133177050Syongari struct mii_data *mii; 2134177050Syongari struct mii_softc *miisc; 2135177050Syongari int error; 213641502Swpaul 2137177050Syongari sc = ifp->if_softc; 2138177050Syongari VR_LOCK(sc); 2139177050Syongari mii = device_get_softc(sc->vr_miibus); 2140177050Syongari if (mii->mii_instance) { 2141177050Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2142177050Syongari mii_phy_reset(miisc); 2143177050Syongari } 2144177050Syongari error = mii_mediachg(mii); 2145177050Syongari VR_UNLOCK(sc); 214641502Swpaul 2147177050Syongari return (error); 214841502Swpaul} 214941502Swpaul 215041502Swpaul/* 215141502Swpaul * Report current media status. 215241502Swpaul */ 2153102336Salfredstatic void 2154131503Sbmsvr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 215541502Swpaul{ 2156177050Syongari struct vr_softc *sc; 215751432Swpaul struct mii_data *mii; 215841502Swpaul 2159177050Syongari sc = ifp->if_softc; 216051432Swpaul mii = device_get_softc(sc->vr_miibus); 2161133468Sscottl VR_LOCK(sc); 216251432Swpaul mii_pollstat(mii); 2163133468Sscottl VR_UNLOCK(sc); 216451432Swpaul ifmr->ifm_active = mii->mii_media_active; 216551432Swpaul ifmr->ifm_status = mii->mii_media_status; 216641502Swpaul} 216741502Swpaul 2168102336Salfredstatic int 2169131503Sbmsvr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 217041502Swpaul{ 2171177050Syongari struct vr_softc *sc; 2172177050Syongari struct ifreq *ifr; 217351432Swpaul struct mii_data *mii; 2174177050Syongari int error, mask; 217541502Swpaul 2176177050Syongari sc = ifp->if_softc; 2177177050Syongari ifr = (struct ifreq *)data; 2178177050Syongari error = 0; 2179177050Syongari 2180131503Sbms switch (command) { 218141502Swpaul case SIOCSIFFLAGS: 2182131844Sbms VR_LOCK(sc); 218341502Swpaul if (ifp->if_flags & IFF_UP) { 2184177050Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2185177050Syongari if ((ifp->if_flags ^ sc->vr_if_flags) & 2186177050Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2187177050Syongari vr_set_filter(sc); 2188177050Syongari } else { 2189177050Syongari if (sc->vr_detach == 0) 2190177050Syongari vr_init_locked(sc); 2191177050Syongari } 219241502Swpaul } else { 2193148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 219441502Swpaul vr_stop(sc); 219541502Swpaul } 2196177050Syongari sc->vr_if_flags = ifp->if_flags; 2197131844Sbms VR_UNLOCK(sc); 219841502Swpaul break; 219941502Swpaul case SIOCADDMULTI: 220041502Swpaul case SIOCDELMULTI: 2201131518Sbms VR_LOCK(sc); 2202177050Syongari vr_set_filter(sc); 2203131518Sbms VR_UNLOCK(sc); 220441502Swpaul break; 220541502Swpaul case SIOCGIFMEDIA: 220641502Swpaul case SIOCSIFMEDIA: 220751432Swpaul mii = device_get_softc(sc->vr_miibus); 220851432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 220941502Swpaul break; 2210128118Sru case SIOCSIFCAP: 2211177050Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2212150789Sglebius#ifdef DEVICE_POLLING 2213177050Syongari if (mask & IFCAP_POLLING) { 2214177050Syongari if (ifr->ifr_reqcap & IFCAP_POLLING) { 2215177050Syongari error = ether_poll_register(vr_poll, ifp); 2216177050Syongari if (error != 0) 2217177050Syongari break; 2218177050Syongari VR_LOCK(sc); 2219177050Syongari /* Disable interrupts. */ 2220177050Syongari CSR_WRITE_2(sc, VR_IMR, 0x0000); 2221177050Syongari ifp->if_capenable |= IFCAP_POLLING; 2222177050Syongari VR_UNLOCK(sc); 2223177050Syongari } else { 2224177050Syongari error = ether_poll_deregister(ifp); 2225177050Syongari /* Enable interrupts. */ 2226177050Syongari VR_LOCK(sc); 2227177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2228177050Syongari ifp->if_capenable &= ~IFCAP_POLLING; 2229177050Syongari VR_UNLOCK(sc); 2230177050Syongari } 2231150789Sglebius } 2232177050Syongari#endif /* DEVICE_POLLING */ 2233177050Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2234177050Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2235177050Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2236177050Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2237177050Syongari ifp->if_hwassist |= VR_CSUM_FEATURES; 2238177050Syongari else 2239177050Syongari ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2240150789Sglebius } 2241177050Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2242177050Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2243177050Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2244177050Syongari if ((mask & IFCAP_WOL_UCAST) != 0 && 2245177050Syongari (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2246177050Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2247177050Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2248177050Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2249177050Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2250128118Sru break; 225141502Swpaul default: 2252106936Ssam error = ether_ioctl(ifp, command, data); 225341502Swpaul break; 225441502Swpaul } 225541502Swpaul 2256131503Sbms return (error); 225741502Swpaul} 225841502Swpaul 2259102336Salfredstatic void 2260177050Syongarivr_watchdog(struct vr_softc *sc) 226141502Swpaul{ 2262177050Syongari struct ifnet *ifp; 226341502Swpaul 2264177050Syongari VR_LOCK_ASSERT(sc); 2265131844Sbms 2266177050Syongari if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2267177050Syongari return; 2268177050Syongari 2269177050Syongari ifp = sc->vr_ifp; 2270177050Syongari /* 2271177050Syongari * Reclaim first as we don't request interrupt for every packets. 2272177050Syongari */ 2273177050Syongari vr_txeof(sc); 2274177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 2275177050Syongari return; 2276177050Syongari 2277177050Syongari if (sc->vr_link == 0) { 2278177050Syongari if (bootverbose) 2279177050Syongari if_printf(sc->vr_ifp, "watchdog timeout " 2280177050Syongari "(missed link)\n"); 2281177050Syongari ifp->if_oerrors++; 2282177050Syongari vr_init_locked(sc); 2283177050Syongari return; 2284177050Syongari } 2285177050Syongari 228641502Swpaul ifp->if_oerrors++; 2287151773Sjhb if_printf(ifp, "watchdog timeout\n"); 228841502Swpaul 228941502Swpaul vr_stop(sc); 229041502Swpaul vr_reset(sc); 2291131844Sbms vr_init_locked(sc); 2292131518Sbms 2293132986Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2294131844Sbms vr_start_locked(ifp); 2295177050Syongari} 2296131844Sbms 2297177050Syongaristatic void 2298177050Syongarivr_tx_start(struct vr_softc *sc) 2299177050Syongari{ 2300177050Syongari bus_addr_t addr; 2301177050Syongari uint8_t cmd; 2302177050Syongari 2303177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2304177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) { 2305177050Syongari addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2306177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2307177050Syongari cmd |= VR_CR0_TX_ON; 2308177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2309177050Syongari } 2310177050Syongari if (sc->vr_cdata.vr_tx_cnt != 0) { 2311177050Syongari sc->vr_watchdog_timer = 5; 2312177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2313177050Syongari } 231441502Swpaul} 231541502Swpaul 2316177050Syongaristatic void 2317177050Syongarivr_rx_start(struct vr_softc *sc) 2318177050Syongari{ 2319177050Syongari bus_addr_t addr; 2320177050Syongari uint8_t cmd; 2321177050Syongari 2322177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2323177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) { 2324177050Syongari addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2325177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2326177050Syongari cmd |= VR_CR0_RX_ON; 2327177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2328177050Syongari } 2329177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2330177050Syongari} 2331177050Syongari 2332177050Syongaristatic int 2333177050Syongarivr_tx_stop(struct vr_softc *sc) 2334177050Syongari{ 2335177050Syongari int i; 2336177050Syongari uint8_t cmd; 2337177050Syongari 2338177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2339177050Syongari if ((cmd & VR_CR0_TX_ON) != 0) { 2340177050Syongari cmd &= ~VR_CR0_TX_ON; 2341177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2342177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2343177050Syongari DELAY(5); 2344177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2345177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) 2346177050Syongari break; 2347177050Syongari } 2348177050Syongari if (i == 0) 2349177050Syongari return (ETIMEDOUT); 2350177050Syongari } 2351177050Syongari return (0); 2352177050Syongari} 2353177050Syongari 2354177050Syongaristatic int 2355177050Syongarivr_rx_stop(struct vr_softc *sc) 2356177050Syongari{ 2357177050Syongari int i; 2358177050Syongari uint8_t cmd; 2359177050Syongari 2360177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2361177050Syongari if ((cmd & VR_CR0_RX_ON) != 0) { 2362177050Syongari cmd &= ~VR_CR0_RX_ON; 2363177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2364177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2365177050Syongari DELAY(5); 2366177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2367177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) 2368177050Syongari break; 2369177050Syongari } 2370177050Syongari if (i == 0) 2371177050Syongari return (ETIMEDOUT); 2372177050Syongari } 2373177050Syongari return (0); 2374177050Syongari} 2375177050Syongari 237641502Swpaul/* 237741502Swpaul * Stop the adapter and free any mbufs allocated to the 237841502Swpaul * RX and TX lists. 237941502Swpaul */ 2380102336Salfredstatic void 2381131503Sbmsvr_stop(struct vr_softc *sc) 238241502Swpaul{ 2383177050Syongari struct vr_txdesc *txd; 2384177050Syongari struct vr_rxdesc *rxd; 2385177050Syongari struct ifnet *ifp; 2386177050Syongari int i; 238741502Swpaul 2388131518Sbms VR_LOCK_ASSERT(sc); 238967087Swpaul 2390147256Sbrooks ifp = sc->vr_ifp; 2391177050Syongari sc->vr_watchdog_timer = 0; 239241502Swpaul 2393151911Sjhb callout_stop(&sc->vr_stat_callout); 2394148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 239551432Swpaul 2396177050Syongari CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2397177050Syongari if (vr_rx_stop(sc) != 0) 2398177050Syongari device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2399177050Syongari if (vr_tx_stop(sc) != 0) 2400177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2401177050Syongari /* Clear pending interrupts. */ 2402177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 240341502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 240441502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 240541502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 240641502Swpaul 240741502Swpaul /* 2408177050Syongari * Free RX and TX mbufs still in the queues. 240941502Swpaul */ 2410177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 2411177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 2412177050Syongari if (rxd->rx_m != NULL) { 2413177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2414177050Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2415177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2416177050Syongari rxd->rx_dmamap); 2417177050Syongari m_freem(rxd->rx_m); 2418177050Syongari rxd->rx_m = NULL; 2419177050Syongari } 2420177050Syongari } 2421177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 2422177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 2423177050Syongari if (txd->tx_m != NULL) { 2424177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2425177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2426177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2427177050Syongari txd->tx_dmamap); 2428177050Syongari m_freem(txd->tx_m); 2429177050Syongari txd->tx_m = NULL; 2430177050Syongari } 2431177050Syongari } 243241502Swpaul} 243341502Swpaul 243441502Swpaul/* 243541502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 243641502Swpaul * get confused by errant DMAs when rebooting. 243741502Swpaul */ 2438173839Syongaristatic int 2439131503Sbmsvr_shutdown(device_t dev) 244041502Swpaul{ 244141502Swpaul 2442177050Syongari return (vr_suspend(dev)); 2443177050Syongari} 2444173839Syongari 2445177050Syongaristatic int 2446177050Syongarivr_suspend(device_t dev) 2447177050Syongari{ 2448177050Syongari struct vr_softc *sc; 2449177050Syongari 2450177050Syongari sc = device_get_softc(dev); 2451177050Syongari 2452177050Syongari VR_LOCK(sc); 2453177050Syongari vr_stop(sc); 2454177050Syongari vr_setwol(sc); 2455177050Syongari sc->vr_suspended = 1; 2456177050Syongari VR_UNLOCK(sc); 2457177050Syongari 2458173839Syongari return (0); 245941502Swpaul} 2460177050Syongari 2461177050Syongaristatic int 2462177050Syongarivr_resume(device_t dev) 2463177050Syongari{ 2464177050Syongari struct vr_softc *sc; 2465177050Syongari struct ifnet *ifp; 2466177050Syongari 2467177050Syongari sc = device_get_softc(dev); 2468177050Syongari 2469177050Syongari VR_LOCK(sc); 2470177050Syongari ifp = sc->vr_ifp; 2471177050Syongari vr_clrwol(sc); 2472177050Syongari vr_reset(sc); 2473177050Syongari if (ifp->if_flags & IFF_UP) 2474177050Syongari vr_init_locked(sc); 2475177050Syongari 2476177050Syongari sc->vr_suspended = 0; 2477177050Syongari VR_UNLOCK(sc); 2478177050Syongari 2479177050Syongari return (0); 2480177050Syongari} 2481177050Syongari 2482177050Syongaristatic void 2483177050Syongarivr_setwol(struct vr_softc *sc) 2484177050Syongari{ 2485177050Syongari struct ifnet *ifp; 2486177050Syongari int pmc; 2487177050Syongari uint16_t pmstat; 2488177050Syongari uint8_t v; 2489177050Syongari 2490177050Syongari VR_LOCK_ASSERT(sc); 2491177050Syongari 2492177050Syongari if (sc->vr_revid < REV_ID_VT6102_A || 2493177050Syongari pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2494177050Syongari return; 2495177050Syongari 2496177050Syongari ifp = sc->vr_ifp; 2497177050Syongari 2498177050Syongari /* Clear WOL configuration. */ 2499177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2500177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2501177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2502177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2503177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2504177050Syongari /* Newer Rhine III supports two additional patterns. */ 2505177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2506177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2507177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2508177050Syongari } 2509177050Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2510177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2511177050Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2512177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2513177050Syongari /* 2514177050Syongari * It seems that multicast wakeup frames require programming pattern 2515177050Syongari * registers and valid CRC as well as pattern mask for each pattern. 2516177050Syongari * While it's possible to setup such a pattern it would complicate 2517177050Syongari * WOL configuration so ignore multicast wakeup frames. 2518177050Syongari */ 2519177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2520177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2521177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2522177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2523177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2524177050Syongari } 2525177050Syongari 2526177050Syongari /* Put hardware into sleep. */ 2527177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2528177050Syongari v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2529177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2530177050Syongari 2531177050Syongari /* Request PME if WOL is requested. */ 2532177050Syongari pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2533177050Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2534177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2535177050Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2536177050Syongari pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2537177050Syongari} 2538177050Syongari 2539177050Syongaristatic void 2540177050Syongarivr_clrwol(struct vr_softc *sc) 2541177050Syongari{ 2542177050Syongari uint8_t v; 2543177050Syongari 2544177050Syongari VR_LOCK_ASSERT(sc); 2545177050Syongari 2546177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 2547177050Syongari return; 2548177050Syongari 2549177050Syongari /* Take hardware out of sleep. */ 2550177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2551177050Syongari v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2552177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2553177050Syongari 2554177050Syongari /* Clear WOL configuration as WOL may interfere normal operation. */ 2555177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2556177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2557177050Syongari VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2558177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2559177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2560177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2561177050Syongari /* Newer Rhine III supports two additional patterns. */ 2562177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2563177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2564177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2565177050Syongari } 2566177050Syongari} 2567177050Syongari 2568177050Syongaristatic int 2569177050Syongarivr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2570177050Syongari{ 2571177050Syongari struct vr_softc *sc; 2572177050Syongari struct vr_statistics *stat; 2573177050Syongari int error; 2574177050Syongari int result; 2575177050Syongari 2576177050Syongari result = -1; 2577177050Syongari error = sysctl_handle_int(oidp, &result, 0, req); 2578177050Syongari 2579177050Syongari if (error != 0 || req->newptr == NULL) 2580177050Syongari return (error); 2581177050Syongari 2582177050Syongari if (result == 1) { 2583177050Syongari sc = (struct vr_softc *)arg1; 2584177050Syongari stat = &sc->vr_stat; 2585177050Syongari 2586177050Syongari printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2587177050Syongari printf("Outbound good frames : %ju\n", 2588177050Syongari (uintmax_t)stat->tx_ok); 2589177050Syongari printf("Inbound good frames : %ju\n", 2590177050Syongari (uintmax_t)stat->rx_ok); 2591177050Syongari printf("Outbound errors : %u\n", stat->tx_errors); 2592177050Syongari printf("Inbound errors : %u\n", stat->rx_errors); 2593177050Syongari printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2594177050Syongari printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2595177050Syongari printf("Inbound FIFO overflows : %d\n", 2596177050Syongari stat->rx_fifo_overflows); 2597177050Syongari printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2598177050Syongari printf("Inbound frame alignment errors : %u\n", 2599177050Syongari stat->rx_alignment); 2600177050Syongari printf("Inbound giant frames : %u\n", stat->rx_giants); 2601177050Syongari printf("Inbound runt frames : %u\n", stat->rx_runts); 2602177050Syongari printf("Outbound aborted with excessive collisions : %u\n", 2603177050Syongari stat->tx_abort); 2604177050Syongari printf("Outbound collisions : %u\n", stat->tx_collisions); 2605177050Syongari printf("Outbound late collisions : %u\n", 2606177050Syongari stat->tx_late_collisions); 2607177050Syongari printf("Outbound underrun : %u\n", stat->tx_underrun); 2608177050Syongari printf("PCI bus errors : %u\n", stat->bus_errors); 2609177050Syongari printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2610177050Syongari stat->num_restart); 2611177050Syongari } 2612177050Syongari 2613177050Syongari return (error); 2614177050Syongari} 2615