if_vr.c revision 168827
138451Smsmith/*- 238451Smsmith * Copyright (c) 1997, 1998 338451Smsmith * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438451Smsmith * 538451Smsmith * Redistribution and use in source and binary forms, with or without 638451Smsmith * modification, are permitted provided that the following conditions 738451Smsmith * are met: 838451Smsmith * 1. Redistributions of source code must retain the above copyright 938451Smsmith * notice, this list of conditions and the following disclaimer. 1038451Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1138451Smsmith * notice, this list of conditions and the following disclaimer in the 1238451Smsmith * documentation and/or other materials provided with the distribution. 1338451Smsmith * 3. All advertising materials mentioning features or use of this software 1438451Smsmith * must display the following acknowledgement: 1538451Smsmith * This product includes software developed by Bill Paul. 1638451Smsmith * 4. Neither the name of the author nor the names of any co-contributors 1738451Smsmith * may be used to endorse or promote products derived from this software 1838451Smsmith * without specific prior written permission. 1938451Smsmith * 2038451Smsmith * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138451Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238451Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338451Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438451Smsmith * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538451Smsmith * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638451Smsmith * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738451Smsmith * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838451Smsmith * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938451Smsmith * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038451Smsmith * THE POSSIBILITY OF SUCH DAMAGE. 3138451Smsmith */ 3238451Smsmith 3338451Smsmith#include <sys/cdefs.h> 3438451Smsmith__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 168827 2007-04-17 22:59:54Z phk $"); 3538451Smsmith 3638451Smsmith/* 3738451Smsmith * VIA Rhine fast ethernet PCI NIC driver 3884221Sdillon * 3984221Sdillon * Supports various network adapters based on the VIA Rhine 4084221Sdillon * and Rhine II PCI controllers, including the D-Link DFE530TX. 4138451Smsmith * Datasheets are available at http://www.via.com.tw. 4238451Smsmith * 4338451Smsmith * Written by Bill Paul <wpaul@ctr.columbia.edu> 4438451Smsmith * Electrical Engineering Department 4538451Smsmith * Columbia University, New York City 4638451Smsmith */ 4738451Smsmith 4838451Smsmith/* 4938451Smsmith * The VIA Rhine controllers are similar in some respects to the 5038451Smsmith * the DEC tulip chips, except less complicated. The controller 5138451Smsmith * uses an MII bus and an external physical layer interface. The 5238451Smsmith * receiver has a one entry perfect filter and a 64-bit hash table 5338451Smsmith * multicast filter. Transmit and receive descriptors are similar 5438451Smsmith * to the tulip. 5538451Smsmith * 5638451Smsmith * The Rhine has a serious flaw in its transmit DMA mechanism: 5738451Smsmith * transmit buffers must be longword aligned. Unfortunately, 5838451Smsmith * FreeBSD doesn't guarantee that mbufs will be filled in starting 5938451Smsmith * at longword boundaries, so we have to do a buffer copy before 6038451Smsmith * transmission. 6138451Smsmith */ 6238451Smsmith 6338451Smsmith#ifdef HAVE_KERNEL_OPTION_HEADERS 6438451Smsmith#include "opt_device_polling.h" 6538451Smsmith#endif 6638451Smsmith 6738451Smsmith#include <sys/param.h> 6838451Smsmith#include <sys/systm.h> 6938451Smsmith#include <sys/sockio.h> 7038451Smsmith#include <sys/mbuf.h> 7138451Smsmith#include <sys/malloc.h> 7238451Smsmith#include <sys/kernel.h> 7338451Smsmith#include <sys/module.h> 7438451Smsmith#include <sys/socket.h> 7538451Smsmith 7638451Smsmith#include <net/if.h> 7738451Smsmith#include <net/if_arp.h> 7838451Smsmith#include <net/ethernet.h> 7938451Smsmith#include <net/if_dl.h> 8038451Smsmith#include <net/if_media.h> 8138451Smsmith#include <net/if_types.h> 8238451Smsmith 8338451Smsmith#include <net/bpf.h> 8438451Smsmith 8538451Smsmith#include <vm/vm.h> /* for vtophys */ 8638451Smsmith#include <vm/pmap.h> /* for vtophys */ 8738451Smsmith#include <machine/bus.h> 8838451Smsmith#include <machine/resource.h> 8938451Smsmith#include <sys/bus.h> 9038451Smsmith#include <sys/rman.h> 9138451Smsmith 9238451Smsmith#include <dev/mii/mii.h> 9338451Smsmith#include <dev/mii/miivar.h> 9438451Smsmith 9538451Smsmith#include <dev/pci/pcireg.h> 9638451Smsmith#include <dev/pci/pcivar.h> 9738451Smsmith 9838451Smsmith#define VR_USEIOSPACE 9938451Smsmith 10038451Smsmith#include <pci/if_vrreg.h> 10138451Smsmith 10238451SmsmithMODULE_DEPEND(vr, pci, 1, 1, 1); 10338451SmsmithMODULE_DEPEND(vr, ether, 1, 1, 1); 10438451SmsmithMODULE_DEPEND(vr, miibus, 1, 1, 1); 10538451Smsmith 10638451Smsmith/* "device miibus" required. See GENERIC if you get errors here. */ 10738451Smsmith#include "miibus_if.h" 10838451Smsmith 10938451Smsmith#undef VR_USESWSHIFT 11038451Smsmith 111197178Semaste/* 112197178Semaste * Various supported device vendors/types and their names. 11338451Smsmith */ 11492913Sobrienstatic struct vr_type vr_devs[] = { 11538451Smsmith { VIA_VENDORID, VIA_DEVICEID_RHINE, 11638451Smsmith VR_Q_NEEDALIGN, 11738451Smsmith "VIA VT3043 Rhine I 10/100BaseTX" }, 11838451Smsmith { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 11938451Smsmith VR_Q_NEEDALIGN, 12038451Smsmith "VIA VT86C100A Rhine II 10/100BaseTX" }, 12138451Smsmith { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 12238451Smsmith 0, 12338451Smsmith "VIA VT6102 Rhine II 10/100BaseTX" }, 12438451Smsmith { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 12538451Smsmith 0, 12638451Smsmith "VIA VT6105 Rhine III 10/100BaseTX" }, 12738451Smsmith { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 12838451Smsmith VR_Q_CSUM, 12938451Smsmith "VIA VT6105M Rhine III 10/100BaseTX" }, 13038451Smsmith { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 13138451Smsmith VR_Q_NEEDALIGN, 13238451Smsmith "Delta Electronics Rhine II 10/100BaseTX" }, 13338451Smsmith { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 13438451Smsmith VR_Q_NEEDALIGN, 13538451Smsmith "Addtron Technology Rhine II 10/100BaseTX" }, 13638451Smsmith { 0, 0, 0, NULL } 13738451Smsmith}; 13838451Smsmith 13938451Smsmithstatic int vr_probe(device_t); 14038451Smsmithstatic int vr_attach(device_t); 14138451Smsmithstatic int vr_detach(device_t); 14238451Smsmith 14338451Smsmithstatic int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 14438451Smsmith struct mbuf *); 14538451Smsmith 14638451Smsmithstatic void vr_rxeof(struct vr_softc *); 14738451Smsmithstatic void vr_rxeoc(struct vr_softc *); 14838451Smsmithstatic void vr_txeof(struct vr_softc *); 14938451Smsmithstatic void vr_tick(void *); 15038451Smsmithstatic void vr_intr(void *); 15138451Smsmithstatic void vr_start(struct ifnet *); 15238451Smsmithstatic void vr_start_locked(struct ifnet *); 15338451Smsmithstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 15438451Smsmithstatic void vr_init(void *); 15538451Smsmithstatic void vr_init_locked(struct vr_softc *); 15638451Smsmithstatic void vr_stop(struct vr_softc *); 15738451Smsmithstatic void vr_watchdog(struct ifnet *); 15838451Smsmithstatic void vr_shutdown(device_t); 15938451Smsmithstatic int vr_ifmedia_upd(struct ifnet *); 16038451Smsmithstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 16138451Smsmith 16238451Smsmith#ifdef VR_USESWSHIFT 16338451Smsmithstatic void vr_mii_sync(struct vr_softc *); 16438451Smsmithstatic void vr_mii_send(struct vr_softc *, uint32_t, int); 16538451Smsmith#endif 16638451Smsmithstatic int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 16738451Smsmithstatic int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 16838451Smsmithstatic int vr_miibus_readreg(device_t, uint16_t, uint16_t); 16938451Smsmithstatic int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 17038451Smsmithstatic void vr_miibus_statchg(device_t); 17138451Smsmith 17238451Smsmithstatic void vr_setcfg(struct vr_softc *, int); 17338451Smsmithstatic void vr_setmulti(struct vr_softc *); 17438451Smsmithstatic void vr_reset(struct vr_softc *); 17538451Smsmithstatic int vr_list_rx_init(struct vr_softc *); 17638451Smsmithstatic int vr_list_tx_init(struct vr_softc *); 17738451Smsmith 17838451Smsmith#ifdef VR_USEIOSPACE 17938451Smsmith#define VR_RES SYS_RES_IOPORT 18038451Smsmith#define VR_RID VR_PCI_LOIO 18138451Smsmith#else 18238451Smsmith#define VR_RES SYS_RES_MEMORY 18338451Smsmith#define VR_RID VR_PCI_LOMEM 18438451Smsmith#endif 18538451Smsmith 18638451Smsmithstatic device_method_t vr_methods[] = { 18738451Smsmith /* Device interface */ 18838451Smsmith DEVMETHOD(device_probe, vr_probe), 18938451Smsmith DEVMETHOD(device_attach, vr_attach), 19038451Smsmith DEVMETHOD(device_detach, vr_detach), 19138451Smsmith DEVMETHOD(device_shutdown, vr_shutdown), 19238451Smsmith 19338451Smsmith /* bus interface */ 19438451Smsmith DEVMETHOD(bus_print_child, bus_generic_print_child), 19538451Smsmith DEVMETHOD(bus_driver_added, bus_generic_driver_added), 19638451Smsmith 19738451Smsmith /* MII interface */ 19838451Smsmith DEVMETHOD(miibus_readreg, vr_miibus_readreg), 19938451Smsmith DEVMETHOD(miibus_writereg, vr_miibus_writereg), 20038451Smsmith DEVMETHOD(miibus_statchg, vr_miibus_statchg), 20138451Smsmith 20238451Smsmith { 0, 0 } 20338451Smsmith}; 20438451Smsmith 20538451Smsmithstatic driver_t vr_driver = { 20638451Smsmith "vr", 20738451Smsmith vr_methods, 20838451Smsmith sizeof(struct vr_softc) 20938451Smsmith}; 21038451Smsmith 21138451Smsmithstatic devclass_t vr_devclass; 21238451Smsmith 21338451SmsmithDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 21438451SmsmithDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 21538451Smsmith 21638451Smsmith#define VR_SETBIT(sc, reg, x) \ 21738451Smsmith CSR_WRITE_1(sc, reg, \ 21838451Smsmith CSR_READ_1(sc, reg) | (x)) 21938451Smsmith 22038451Smsmith#define VR_CLRBIT(sc, reg, x) \ 22138451Smsmith CSR_WRITE_1(sc, reg, \ 22238451Smsmith CSR_READ_1(sc, reg) & ~(x)) 22338451Smsmith 22438451Smsmith#define VR_SETBIT16(sc, reg, x) \ 22538451Smsmith CSR_WRITE_2(sc, reg, \ 22638451Smsmith CSR_READ_2(sc, reg) | (x)) 22738451Smsmith 22838451Smsmith#define VR_CLRBIT16(sc, reg, x) \ 22938451Smsmith CSR_WRITE_2(sc, reg, \ 230197178Semaste CSR_READ_2(sc, reg) & ~(x)) 23138451Smsmith 23292913Sobrien#define VR_SETBIT32(sc, reg, x) \ 23338451Smsmith CSR_WRITE_4(sc, reg, \ 23438451Smsmith CSR_READ_4(sc, reg) | (x)) 23538451Smsmith 23638451Smsmith#define VR_CLRBIT32(sc, reg, x) \ 23738451Smsmith CSR_WRITE_4(sc, reg, \ 23838451Smsmith CSR_READ_4(sc, reg) & ~(x)) 23938451Smsmith 24038451Smsmith#define SIO_SET(x) \ 24138451Smsmith CSR_WRITE_1(sc, VR_MIICMD, \ 24238451Smsmith CSR_READ_1(sc, VR_MIICMD) | (x)) 24338451Smsmith 24438451Smsmith#define SIO_CLR(x) \ 24538451Smsmith CSR_WRITE_1(sc, VR_MIICMD, \ 24638451Smsmith CSR_READ_1(sc, VR_MIICMD) & ~(x)) 24738451Smsmith 24838451Smsmith#ifdef VR_USESWSHIFT 24938451Smsmith/* 25038451Smsmith * Sync the PHYs by setting data bit and strobing the clock 32 times. 25138451Smsmith */ 25238451Smsmithstatic void 25338451Smsmithvr_mii_sync(struct vr_softc *sc) 25438451Smsmith{ 25538451Smsmith register int i; 25638451Smsmith 25738451Smsmith SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 25838451Smsmith 25938451Smsmith for (i = 0; i < 32; i++) { 26038451Smsmith SIO_SET(VR_MIICMD_CLK); 26138451Smsmith DELAY(1); 26238451Smsmith SIO_CLR(VR_MIICMD_CLK); 26338451Smsmith DELAY(1); 26438451Smsmith } 26538451Smsmith} 26638451Smsmith 26738451Smsmith/* 26838451Smsmith * Clock a series of bits through the MII. 26938451Smsmith */ 27038451Smsmithstatic void 27138451Smsmithvr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 27238451Smsmith{ 27338451Smsmith int i; 27438451Smsmith 27538451Smsmith SIO_CLR(VR_MIICMD_CLK); 27638451Smsmith 27738451Smsmith for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 27838451Smsmith if (bits & i) { 27938451Smsmith SIO_SET(VR_MIICMD_DATAIN); 28038451Smsmith } else { 28138451Smsmith SIO_CLR(VR_MIICMD_DATAIN); 282197178Semaste } 28338451Smsmith DELAY(1); 28438451Smsmith SIO_CLR(VR_MIICMD_CLK); 28538451Smsmith DELAY(1); 28638451Smsmith SIO_SET(VR_MIICMD_CLK); 28738451Smsmith } 28838451Smsmith} 28938451Smsmith#endif 29038451Smsmith 29138451Smsmith/* 29238451Smsmith * Read an PHY register through the MII. 29338451Smsmith */ 29438451Smsmithstatic int 29538451Smsmithvr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 29638451Smsmith#ifdef VR_USESWSHIFT 29738451Smsmith{ 29838451Smsmith int i, ack; 29938451Smsmith 30038451Smsmith /* Set up frame for RX. */ 30138451Smsmith frame->mii_stdelim = VR_MII_STARTDELIM; 30238451Smsmith frame->mii_opcode = VR_MII_READOP; 30338451Smsmith frame->mii_turnaround = 0; 30438451Smsmith frame->mii_data = 0; 30538451Smsmith 30638451Smsmith CSR_WRITE_1(sc, VR_MIICMD, 0); 30738451Smsmith VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 30838451Smsmith 30938451Smsmith /* Turn on data xmit. */ 31038451Smsmith SIO_SET(VR_MIICMD_DIR); 31138451Smsmith 31238451Smsmith vr_mii_sync(sc); 31338451Smsmith 31438451Smsmith /* Send command/address info. */ 315197178Semaste vr_mii_send(sc, frame->mii_stdelim, 2); 316197178Semaste vr_mii_send(sc, frame->mii_opcode, 2); 317197178Semaste vr_mii_send(sc, frame->mii_phyaddr, 5); 318197178Semaste vr_mii_send(sc, frame->mii_regaddr, 5); 319197178Semaste 320197178Semaste /* Idle bit. */ 321197178Semaste SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 32238451Smsmith DELAY(1); 323197178Semaste SIO_SET(VR_MIICMD_CLK); 32438451Smsmith DELAY(1); 32538451Smsmith 32638451Smsmith /* Turn off xmit. */ 32738451Smsmith SIO_CLR(VR_MIICMD_DIR); 32838451Smsmith 32938451Smsmith /* Check for ack */ 33038451Smsmith SIO_CLR(VR_MIICMD_CLK); 33138451Smsmith DELAY(1); 33238451Smsmith ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 33338451Smsmith SIO_SET(VR_MIICMD_CLK); 33438451Smsmith DELAY(1); 33538451Smsmith 33638451Smsmith /* 337197178Semaste * Now try reading data bits. If the ack failed, we still 338197178Semaste * need to clock through 16 cycles to keep the PHY(s) in sync. 339197178Semaste */ 340197178Semaste if (ack) { 341197178Semaste for(i = 0; i < 16; i++) { 342197178Semaste SIO_CLR(VR_MIICMD_CLK); 343197178Semaste DELAY(1); 34438451Smsmith SIO_SET(VR_MIICMD_CLK); 345197178Semaste DELAY(1); 34638451Smsmith } 34738451Smsmith goto fail; 34838451Smsmith } 34938451Smsmith 35038451Smsmith for (i = 0x8000; i; i >>= 1) { 35138451Smsmith SIO_CLR(VR_MIICMD_CLK); 35238451Smsmith DELAY(1); 35338451Smsmith if (!ack) { 35438451Smsmith if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 35538451Smsmith frame->mii_data |= i; 35638451Smsmith DELAY(1); 35738451Smsmith } 35838451Smsmith SIO_SET(VR_MIICMD_CLK); 35938451Smsmith DELAY(1); 36038451Smsmith } 36138451Smsmith 36238451Smsmithfail: 36338451Smsmith SIO_CLR(VR_MIICMD_CLK); 36438451Smsmith DELAY(1); 36538451Smsmith SIO_SET(VR_MIICMD_CLK); 36638451Smsmith DELAY(1); 36738451Smsmith 36838451Smsmith if (ack) 36938451Smsmith return (1); 37038451Smsmith return (0); 37138451Smsmith} 372197178Semaste#else 37338451Smsmith{ 37438451Smsmith int i; 375197178Semaste 37638451Smsmith /* Set the PHY address. */ 37738451Smsmith CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 37838451Smsmith frame->mii_phyaddr); 37938451Smsmith 38038451Smsmith /* Set the register address. */ 38138451Smsmith CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 38238451Smsmith VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 38338451Smsmith 38438451Smsmith for (i = 0; i < 10000; i++) { 38538451Smsmith if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 38638451Smsmith break; 38738451Smsmith DELAY(1); 38838451Smsmith } 38938451Smsmith frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 39038451Smsmith 39138451Smsmith return (0); 39238451Smsmith} 39338451Smsmith#endif 39438451Smsmith 39538451Smsmith 39638451Smsmith/* 39738451Smsmith * Write to a PHY register through the MII. 39838451Smsmith */ 39938451Smsmithstatic int 400193109Smarcelvr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 40138451Smsmith#ifdef VR_USESWSHIFT 40238451Smsmith{ 40338451Smsmith CSR_WRITE_1(sc, VR_MIICMD, 0); 404193109Smarcel VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 405193109Smarcel 406193109Smarcel /* Set up frame for TX. */ 407193109Smarcel frame->mii_stdelim = VR_MII_STARTDELIM; 40838451Smsmith frame->mii_opcode = VR_MII_WRITEOP; 40938451Smsmith frame->mii_turnaround = VR_MII_TURNAROUND; 41038451Smsmith 41138451Smsmith /* Turn on data output. */ 412193109Smarcel SIO_SET(VR_MIICMD_DIR); 41338451Smsmith 41438451Smsmith vr_mii_sync(sc); 41538451Smsmith 41638451Smsmith vr_mii_send(sc, frame->mii_stdelim, 2); 41738451Smsmith vr_mii_send(sc, frame->mii_opcode, 2); 41838451Smsmith vr_mii_send(sc, frame->mii_phyaddr, 5); 41938451Smsmith vr_mii_send(sc, frame->mii_regaddr, 5); 42038451Smsmith vr_mii_send(sc, frame->mii_turnaround, 2); 42138451Smsmith vr_mii_send(sc, frame->mii_data, 16); 42238451Smsmith 42338451Smsmith /* Idle bit. */ 42438451Smsmith SIO_SET(VR_MIICMD_CLK); 42538451Smsmith DELAY(1); 42638451Smsmith SIO_CLR(VR_MIICMD_CLK); 42738451Smsmith DELAY(1); 42838451Smsmith 42938451Smsmith /* Turn off xmit. */ 43038451Smsmith SIO_CLR(VR_MIICMD_DIR); 43138451Smsmith 432193109Smarcel return (0); 433193109Smarcel} 434193109Smarcel#else 435193109Smarcel{ 436193109Smarcel int i; 43738451Smsmith 43838451Smsmith /* Set the PHY address. */ 439 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 440 frame->mii_phyaddr); 441 442 /* Set the register address and data to write. */ 443 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 444 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 445 446 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 447 448 for (i = 0; i < 10000; i++) { 449 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 450 break; 451 DELAY(1); 452 } 453 454 return (0); 455} 456#endif 457 458static int 459vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 460{ 461 struct vr_mii_frame frame; 462 struct vr_softc *sc = device_get_softc(dev); 463 464 switch (sc->vr_revid) { 465 case REV_ID_VT6102_APOLLO: 466 if (phy != 1) { 467 frame.mii_data = 0; 468 goto out; 469 } 470 default: 471 break; 472 } 473 474 bzero((char *)&frame, sizeof(frame)); 475 frame.mii_phyaddr = phy; 476 frame.mii_regaddr = reg; 477 vr_mii_readreg(sc, &frame); 478 479out: 480 return (frame.mii_data); 481} 482 483static int 484vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 485{ 486 struct vr_mii_frame frame; 487 struct vr_softc *sc = device_get_softc(dev); 488 489 switch (sc->vr_revid) { 490 case REV_ID_VT6102_APOLLO: 491 if (phy != 1) 492 return (0); 493 default: 494 break; 495 } 496 497 bzero((char *)&frame, sizeof(frame)); 498 frame.mii_phyaddr = phy; 499 frame.mii_regaddr = reg; 500 frame.mii_data = data; 501 vr_mii_writereg(sc, &frame); 502 503 return (0); 504} 505 506static void 507vr_miibus_statchg(device_t dev) 508{ 509 struct mii_data *mii; 510 struct vr_softc *sc = device_get_softc(dev); 511 512 mii = device_get_softc(sc->vr_miibus); 513 vr_setcfg(sc, mii->mii_media_active); 514} 515 516/* 517 * Program the 64-bit multicast hash filter. 518 */ 519static void 520vr_setmulti(struct vr_softc *sc) 521{ 522 struct ifnet *ifp = sc->vr_ifp; 523 int h = 0; 524 uint32_t hashes[2] = { 0, 0 }; 525 struct ifmultiaddr *ifma; 526 uint8_t rxfilt; 527 int mcnt = 0; 528 529 VR_LOCK_ASSERT(sc); 530 531 rxfilt = CSR_READ_1(sc, VR_RXCFG); 532 533 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 534 rxfilt |= VR_RXCFG_RX_MULTI; 535 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 536 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 537 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 538 return; 539 } 540 541 /* First, zero out all the existing hash bits. */ 542 CSR_WRITE_4(sc, VR_MAR0, 0); 543 CSR_WRITE_4(sc, VR_MAR1, 0); 544 545 /* Now program new ones. */ 546 IF_ADDR_LOCK(ifp); 547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 548 if (ifma->ifma_addr->sa_family != AF_LINK) 549 continue; 550 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 551 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 552 if (h < 32) 553 hashes[0] |= (1 << h); 554 else 555 hashes[1] |= (1 << (h - 32)); 556 mcnt++; 557 } 558 IF_ADDR_UNLOCK(ifp); 559 560 if (mcnt) 561 rxfilt |= VR_RXCFG_RX_MULTI; 562 else 563 rxfilt &= ~VR_RXCFG_RX_MULTI; 564 565 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 566 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 567 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 568} 569 570/* 571 * In order to fiddle with the 572 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 573 * first have to put the transmit and/or receive logic in the idle state. 574 */ 575static void 576vr_setcfg(struct vr_softc *sc, int media) 577{ 578 int restart = 0; 579 580 VR_LOCK_ASSERT(sc); 581 582 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 583 restart = 1; 584 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 585 } 586 587 if ((media & IFM_GMASK) == IFM_FDX) 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 589 else 590 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 591 592 if (restart) 593 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 594} 595 596static void 597vr_reset(struct vr_softc *sc) 598{ 599 register int i; 600 601 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 602 603 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 604 605 for (i = 0; i < VR_TIMEOUT; i++) { 606 DELAY(10); 607 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 608 break; 609 } 610 if (i == VR_TIMEOUT) { 611 if (sc->vr_revid < REV_ID_VT3065_A) 612 device_printf(sc->vr_dev, "reset never completed!\n"); 613 else { 614 /* Use newer force reset command */ 615 device_printf(sc->vr_dev, "Using force reset command.\n"); 616 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 617 } 618 } 619 620 /* Wait a little while for the chip to get its brains in order. */ 621 DELAY(1000); 622} 623 624/* 625 * Probe for a VIA Rhine chip. Check the PCI vendor and device 626 * IDs against our list and return a match or NULL 627 */ 628static struct vr_type * 629vr_match(device_t dev) 630{ 631 struct vr_type *t = vr_devs; 632 633 for (t = vr_devs; t->vr_name != NULL; t++) 634 if ((pci_get_vendor(dev) == t->vr_vid) && 635 (pci_get_device(dev) == t->vr_did)) 636 return (t); 637 return (NULL); 638} 639 640/* 641 * Probe for a VIA Rhine chip. Check the PCI vendor and device 642 * IDs against our list and return a device name if we find a match. 643 */ 644static int 645vr_probe(device_t dev) 646{ 647 struct vr_type *t; 648 649 t = vr_match(dev); 650 if (t != NULL) { 651 device_set_desc(dev, t->vr_name); 652 return (BUS_PROBE_DEFAULT); 653 } 654 return (ENXIO); 655} 656 657/* 658 * Attach the interface. Allocate softc structures, do ifmedia 659 * setup and ethernet/BPF attach. 660 */ 661static int 662vr_attach(dev) 663 device_t dev; 664{ 665 int i; 666 u_char eaddr[ETHER_ADDR_LEN]; 667 struct vr_softc *sc; 668 struct ifnet *ifp; 669 int unit, error = 0, rid; 670 struct vr_type *t; 671 672 sc = device_get_softc(dev); 673 sc->vr_dev = dev; 674 unit = device_get_unit(dev); 675 t = vr_match(dev); 676 KASSERT(t != NULL, ("Lost if_vr device match")); 677 sc->vr_quirks = t->vr_quirks; 678 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 679 680 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 681 MTX_DEF); 682 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 683 684 /* 685 * Map control/status registers. 686 */ 687 pci_enable_busmaster(dev); 688 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 689 690 rid = VR_RID; 691 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 692 693 if (sc->vr_res == NULL) { 694 device_printf(dev, "couldn't map ports/memory\n"); 695 error = ENXIO; 696 goto fail; 697 } 698 699 /* Allocate interrupt */ 700 rid = 0; 701 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 702 RF_SHAREABLE | RF_ACTIVE); 703 704 if (sc->vr_irq == NULL) { 705 device_printf(dev, "couldn't map interrupt\n"); 706 error = ENXIO; 707 goto fail; 708 } 709 710 /* Allocate ifnet structure. */ 711 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 712 if (ifp == NULL) { 713 device_printf(dev, "can not if_alloc()\n"); 714 error = ENOSPC; 715 goto fail; 716 } 717 ifp->if_softc = sc; 718 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 719 ifp->if_mtu = ETHERMTU; 720 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 721 ifp->if_ioctl = vr_ioctl; 722 ifp->if_start = vr_start; 723 ifp->if_watchdog = vr_watchdog; 724 ifp->if_init = vr_init; 725 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 726 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 727 IFQ_SET_READY(&ifp->if_snd); 728 729 if (sc->vr_quirks & VR_Q_CSUM) { 730 ifp->if_hwassist = (CSUM_IP | CSUM_TCP | CSUM_UDP); 731 ifp->if_capabilities |= IFCAP_HWCSUM; 732 } 733 734 ifp->if_capenable = ifp->if_capabilities; 735 if (ifp->if_capenable & IFCAP_TXCSUM) 736 ifp->if_hwassist = (CSUM_IP | CSUM_TCP | CSUM_UDP); 737 else 738 ifp->if_hwassist = 0; 739 740#ifdef DEVICE_POLLING 741 ifp->if_capabilities |= IFCAP_POLLING; 742#endif 743 744 /* 745 * Windows may put the chip in suspend mode when it 746 * shuts down. Be sure to kick it in the head to wake it 747 * up again. 748 */ 749 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 750 751 /* Reset the adapter. */ 752 vr_reset(sc); 753 754 /* 755 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 756 * initialization and disable AUTOPOLL. 757 */ 758 pci_write_config(dev, VR_PCI_MODE, 759 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 760 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 761 762 /* 763 * Get station address. The way the Rhine chips work, 764 * you're not allowed to directly access the EEPROM once 765 * they've been programmed a special way. Consequently, 766 * we need to read the node address from the PAR0 and PAR1 767 * registers. 768 */ 769 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 770 DELAY(200); 771 for (i = 0; i < ETHER_ADDR_LEN; i++) 772 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 773 774 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 775 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 776 777 if (sc->vr_ldata == NULL) { 778 device_printf(dev, "no memory for list buffers!\n"); 779 error = ENXIO; 780 goto fail; 781 } 782 783 /* Do MII setup. */ 784 if (mii_phy_probe(dev, &sc->vr_miibus, 785 vr_ifmedia_upd, vr_ifmedia_sts)) { 786 device_printf(dev, "MII without any phy!\n"); 787 error = ENXIO; 788 goto fail; 789 } 790 791 /* Call MI attach routine. */ 792 ether_ifattach(ifp, eaddr); 793 794 sc->suspended = 0; 795 796 /* Hook interrupt last to avoid having to lock softc */ 797 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 798 NULL, vr_intr, sc, &sc->vr_intrhand); 799 800 if (error) { 801 device_printf(dev, "couldn't set up irq\n"); 802 ether_ifdetach(ifp); 803 goto fail; 804 } 805 806fail: 807 if (error) 808 vr_detach(dev); 809 810 return (error); 811} 812 813/* 814 * Shutdown hardware and free up resources. This can be called any 815 * time after the mutex has been initialized. It is called in both 816 * the error case in attach and the normal detach case so it needs 817 * to be careful about only freeing resources that have actually been 818 * allocated. 819 */ 820static int 821vr_detach(device_t dev) 822{ 823 struct vr_softc *sc = device_get_softc(dev); 824 struct ifnet *ifp = sc->vr_ifp; 825 826 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 827 828#ifdef DEVICE_POLLING 829 if (ifp->if_capenable & IFCAP_POLLING) 830 ether_poll_deregister(ifp); 831#endif 832 833 /* These should only be active if attach succeeded */ 834 if (device_is_attached(dev)) { 835 VR_LOCK(sc); 836 sc->suspended = 1; 837 vr_stop(sc); 838 VR_UNLOCK(sc); 839 callout_drain(&sc->vr_stat_callout); 840 ether_ifdetach(ifp); 841 } 842 if (sc->vr_miibus) 843 device_delete_child(dev, sc->vr_miibus); 844 bus_generic_detach(dev); 845 846 if (sc->vr_intrhand) 847 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 848 if (sc->vr_irq) 849 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 850 if (sc->vr_res) 851 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 852 853 if (ifp) 854 if_free(ifp); 855 856 if (sc->vr_ldata) 857 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 858 859 mtx_destroy(&sc->vr_mtx); 860 861 return (0); 862} 863 864/* 865 * Initialize the transmit descriptors. 866 */ 867static int 868vr_list_tx_init(struct vr_softc *sc) 869{ 870 struct vr_chain_data *cd; 871 struct vr_list_data *ld; 872 int i; 873 874 cd = &sc->vr_cdata; 875 ld = sc->vr_ldata; 876 for (i = 0; i < VR_TX_LIST_CNT; i++) { 877 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 878 if (i == (VR_TX_LIST_CNT - 1)) 879 cd->vr_tx_chain[i].vr_nextdesc = 880 &cd->vr_tx_chain[0]; 881 else 882 cd->vr_tx_chain[i].vr_nextdesc = 883 &cd->vr_tx_chain[i + 1]; 884 } 885 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 886 887 return (0); 888} 889 890 891/* 892 * Initialize the RX descriptors and allocate mbufs for them. Note that 893 * we arrange the descriptors in a closed ring, so that the last descriptor 894 * points back to the first. 895 */ 896static int 897vr_list_rx_init(struct vr_softc *sc) 898{ 899 struct vr_chain_data *cd; 900 struct vr_list_data *ld; 901 int i; 902 903 VR_LOCK_ASSERT(sc); 904 905 cd = &sc->vr_cdata; 906 ld = sc->vr_ldata; 907 908 for (i = 0; i < VR_RX_LIST_CNT; i++) { 909 cd->vr_rx_chain[i].vr_ptr = 910 (struct vr_desc *)&ld->vr_rx_list[i]; 911 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 912 return (ENOBUFS); 913 if (i == (VR_RX_LIST_CNT - 1)) { 914 cd->vr_rx_chain[i].vr_nextdesc = 915 &cd->vr_rx_chain[0]; 916 ld->vr_rx_list[i].vr_next = 917 vtophys(&ld->vr_rx_list[0]); 918 } else { 919 cd->vr_rx_chain[i].vr_nextdesc = 920 &cd->vr_rx_chain[i + 1]; 921 ld->vr_rx_list[i].vr_next = 922 vtophys(&ld->vr_rx_list[i + 1]); 923 } 924 } 925 926 cd->vr_rx_head = &cd->vr_rx_chain[0]; 927 928 return (0); 929} 930 931/* 932 * Initialize an RX descriptor and attach an MBUF cluster. 933 * Note: the length fields are only 11 bits wide, which means the 934 * largest size we can specify is 2047. This is important because 935 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 936 * overflow the field and make a mess. 937 */ 938static int 939vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 940{ 941 struct mbuf *m_new = NULL; 942 943 if (m == NULL) { 944 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 945 if (m_new == NULL) 946 return (ENOBUFS); 947 948 MCLGET(m_new, M_DONTWAIT); 949 if (!(m_new->m_flags & M_EXT)) { 950 m_freem(m_new); 951 return (ENOBUFS); 952 } 953 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 954 } else { 955 m_new = m; 956 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 957 m_new->m_data = m_new->m_ext.ext_buf; 958 } 959 960 m_adj(m_new, sizeof(uint64_t)); 961 962 c->vr_mbuf = m_new; 963 c->vr_ptr->vr_status = VR_RXSTAT; 964 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 965 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 966 967 return (0); 968} 969 970/* 971 * A frame has been uploaded: pass the resulting mbuf chain up to 972 * the higher level protocols. 973 */ 974static void 975vr_rxeof(struct vr_softc *sc) 976{ 977 struct mbuf *m, *m0; 978 struct ifnet *ifp; 979 struct vr_chain_onefrag *cur_rx; 980 int total_len = 0; 981 uint32_t rxstat, rxctl; 982 983 VR_LOCK_ASSERT(sc); 984 ifp = sc->vr_ifp; 985 986 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 987 VR_RXSTAT_OWN)) { 988#ifdef DEVICE_POLLING 989 if (ifp->if_capenable & IFCAP_POLLING) { 990 if (sc->rxcycles <= 0) 991 break; 992 sc->rxcycles--; 993 } 994#endif 995 m0 = NULL; 996 cur_rx = sc->vr_cdata.vr_rx_head; 997 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 998 m = cur_rx->vr_mbuf; 999 1000 /* 1001 * If an error occurs, update stats, clear the 1002 * status word and leave the mbuf cluster in place: 1003 * it should simply get re-used next time this descriptor 1004 * comes up in the ring. 1005 */ 1006 if (rxstat & VR_RXSTAT_RXERR) { 1007 ifp->if_ierrors++; 1008 device_printf(sc->vr_dev, 1009 "rx error (%02x):", rxstat & 0x000000ff); 1010 if (rxstat & VR_RXSTAT_CRCERR) 1011 printf(" crc error"); 1012 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1013 printf(" frame alignment error\n"); 1014 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1015 printf(" FIFO overflow"); 1016 if (rxstat & VR_RXSTAT_GIANT) 1017 printf(" received giant packet"); 1018 if (rxstat & VR_RXSTAT_RUNT) 1019 printf(" received runt packet"); 1020 if (rxstat & VR_RXSTAT_BUSERR) 1021 printf(" system bus error"); 1022 if (rxstat & VR_RXSTAT_BUFFERR) 1023 printf("rx buffer error"); 1024 printf("\n"); 1025 vr_newbuf(sc, cur_rx, m); 1026 continue; 1027 } 1028 1029 /* No errors; receive the packet. */ 1030 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1031 if (ifp->if_capenable & IFCAP_RXCSUM) { 1032 rxctl = cur_rx->vr_ptr->vr_ctl; 1033 if ((rxctl & VR_RXCTL_GOODIP) == VR_RXCTL_GOODIP) 1034 m->m_pkthdr.csum_flags |= 1035 CSUM_IP_CHECKED | CSUM_IP_VALID; 1036 if ((rxctl & VR_RXCTL_GOODTCPUDP)) { 1037 m->m_pkthdr.csum_flags |= 1038 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1039 m->m_pkthdr.csum_data = 0xffff; 1040 } 1041 } 1042 1043 /* 1044 * XXX The VIA Rhine chip includes the CRC with every 1045 * received frame, and there's no way to turn this 1046 * behavior off (at least, I can't find anything in 1047 * the manual that explains how to do it) so we have 1048 * to trim off the CRC manually. 1049 */ 1050 total_len -= ETHER_CRC_LEN; 1051 1052 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1053 NULL); 1054 vr_newbuf(sc, cur_rx, m); 1055 if (m0 == NULL) { 1056 ifp->if_ierrors++; 1057 continue; 1058 } 1059 m = m0; 1060 1061 ifp->if_ipackets++; 1062 VR_UNLOCK(sc); 1063 (*ifp->if_input)(ifp, m); 1064 VR_LOCK(sc); 1065 } 1066} 1067 1068static void 1069vr_rxeoc(struct vr_softc *sc) 1070{ 1071 struct ifnet *ifp = sc->vr_ifp; 1072 int i; 1073 1074 VR_LOCK_ASSERT(sc); 1075 1076 ifp->if_ierrors++; 1077 1078 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1079 DELAY(10000); 1080 1081 /* Wait for receiver to stop */ 1082 for (i = 0x400; 1083 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1084 i--) { 1085 ; 1086 } 1087 1088 if (!i) { 1089 device_printf(sc->vr_dev, "rx shutdown error!\n"); 1090 sc->vr_flags |= VR_F_RESTART; 1091 return; 1092 } 1093 1094 vr_rxeof(sc); 1095 1096 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1097 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1098 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1099} 1100 1101/* 1102 * A frame was downloaded to the chip. It's safe for us to clean up 1103 * the list buffers. 1104 */ 1105static void 1106vr_txeof(struct vr_softc *sc) 1107{ 1108 struct vr_chain *cur_tx; 1109 struct ifnet *ifp = sc->vr_ifp; 1110 1111 VR_LOCK_ASSERT(sc); 1112 1113 /* 1114 * Go through our tx list and free mbufs for those 1115 * frames that have been transmitted. 1116 */ 1117 cur_tx = sc->vr_cdata.vr_tx_cons; 1118 while (cur_tx != sc->vr_cdata.vr_tx_prod) { 1119 uint32_t txstat; 1120 int i; 1121 1122 txstat = cur_tx->vr_ptr->vr_status; 1123 1124 if ((txstat & VR_TXSTAT_ABRT) || 1125 (txstat & VR_TXSTAT_UDF)) { 1126 for (i = 0x400; 1127 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1128 i--) 1129 ; /* Wait for chip to shutdown */ 1130 if (!i) { 1131 device_printf(sc->vr_dev, "tx shutdown timeout\n"); 1132 sc->vr_flags |= VR_F_RESTART; 1133 break; 1134 } 1135 atomic_set_acq_32(&VR_TXOWN(cur_tx), VR_TXSTAT_OWN); 1136 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1137 break; 1138 } 1139 1140 if (txstat & VR_TXSTAT_OWN) 1141 break; 1142 1143 if (txstat & VR_TXSTAT_ERRSUM) { 1144 ifp->if_oerrors++; 1145 if (txstat & VR_TXSTAT_DEFER) 1146 ifp->if_collisions++; 1147 if (txstat & VR_TXSTAT_LATECOLL) 1148 ifp->if_collisions++; 1149 } 1150 1151 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1152 1153 ifp->if_opackets++; 1154 if (cur_tx->vr_mbuf != NULL) 1155 m_freem(cur_tx->vr_mbuf); 1156 cur_tx->vr_mbuf = NULL; 1157 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1158 1159 cur_tx = cur_tx->vr_nextdesc; 1160 } 1161 sc->vr_cdata.vr_tx_cons = cur_tx; 1162 if (cur_tx->vr_mbuf == NULL) 1163 ifp->if_timer = 0; 1164} 1165 1166static void 1167vr_tick(void *xsc) 1168{ 1169 struct vr_softc *sc = xsc; 1170 struct mii_data *mii; 1171 1172 VR_LOCK_ASSERT(sc); 1173 1174 if (sc->vr_flags & VR_F_RESTART) { 1175 device_printf(sc->vr_dev, "restarting\n"); 1176 vr_stop(sc); 1177 vr_reset(sc); 1178 vr_init_locked(sc); 1179 sc->vr_flags &= ~VR_F_RESTART; 1180 } 1181 1182 mii = device_get_softc(sc->vr_miibus); 1183 mii_tick(mii); 1184 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1185} 1186 1187#ifdef DEVICE_POLLING 1188static poll_handler_t vr_poll; 1189static poll_handler_t vr_poll_locked; 1190 1191static void 1192vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1193{ 1194 struct vr_softc *sc = ifp->if_softc; 1195 1196 VR_LOCK(sc); 1197 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1198 vr_poll_locked(ifp, cmd, count); 1199 VR_UNLOCK(sc); 1200} 1201 1202static void 1203vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1204{ 1205 struct vr_softc *sc = ifp->if_softc; 1206 1207 VR_LOCK_ASSERT(sc); 1208 1209 sc->rxcycles = count; 1210 vr_rxeof(sc); 1211 vr_txeof(sc); 1212 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1213 vr_start_locked(ifp); 1214 1215 if (cmd == POLL_AND_CHECK_STATUS) { 1216 uint16_t status; 1217 1218 /* Also check status register. */ 1219 status = CSR_READ_2(sc, VR_ISR); 1220 if (status) 1221 CSR_WRITE_2(sc, VR_ISR, status); 1222 1223 if ((status & VR_INTRS) == 0) 1224 return; 1225 1226 if (status & VR_ISR_RX_DROPPED) { 1227 if_printf(ifp, "rx packet lost\n"); 1228 ifp->if_ierrors++; 1229 } 1230 1231 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1232 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1233 if_printf(ifp, "receive error (%04x)", status); 1234 if (status & VR_ISR_RX_NOBUF) 1235 printf(" no buffers"); 1236 if (status & VR_ISR_RX_OFLOW) 1237 printf(" overflow"); 1238 if (status & VR_ISR_RX_DROPPED) 1239 printf(" packet lost"); 1240 printf("\n"); 1241 vr_rxeoc(sc); 1242 } 1243 1244 if ((status & VR_ISR_BUSERR) || 1245 (status & VR_ISR_TX_UNDERRUN)) { 1246 vr_reset(sc); 1247 vr_init_locked(sc); 1248 return; 1249 } 1250 1251 if ((status & VR_ISR_UDFI) || 1252 (status & VR_ISR_TX_ABRT2) || 1253 (status & VR_ISR_TX_ABRT)) { 1254 ifp->if_oerrors++; 1255 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1256 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1257 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1258 } 1259 } 1260 } 1261} 1262#endif /* DEVICE_POLLING */ 1263 1264static void 1265vr_intr(void *arg) 1266{ 1267 struct vr_softc *sc = arg; 1268 struct ifnet *ifp = sc->vr_ifp; 1269 uint16_t status; 1270 1271 VR_LOCK(sc); 1272 1273 if (sc->suspended) { 1274 /* 1275 * Forcibly disable interrupts. 1276 * XXX: Mobile VIA based platforms may need 1277 * interrupt re-enable on resume. 1278 */ 1279 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1280 goto done_locked; 1281 } 1282 1283#ifdef DEVICE_POLLING 1284 if (ifp->if_capenable & IFCAP_POLLING) 1285 goto done_locked; 1286#endif 1287 1288 /* Suppress unwanted interrupts. */ 1289 if (!(ifp->if_flags & IFF_UP)) { 1290 vr_stop(sc); 1291 goto done_locked; 1292 } 1293 1294 /* Disable interrupts. */ 1295 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1296 1297 for (;;) { 1298 status = CSR_READ_2(sc, VR_ISR); 1299 1300 if (status) 1301 CSR_WRITE_2(sc, VR_ISR, status); 1302 1303 if ((status & VR_INTRS) == 0) 1304 break; 1305 1306 if (status & VR_ISR_RX_OK) 1307 vr_rxeof(sc); 1308 1309 if (status & VR_ISR_RX_DROPPED) { 1310 device_printf(sc->vr_dev, "rx packet lost\n"); 1311 ifp->if_ierrors++; 1312 } 1313 1314 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1315 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1316 device_printf(sc->vr_dev, "receive error (%04x)", status); 1317 if (status & VR_ISR_RX_NOBUF) 1318 printf(" no buffers"); 1319 if (status & VR_ISR_RX_OFLOW) 1320 printf(" overflow"); 1321 if (status & VR_ISR_RX_DROPPED) 1322 printf(" packet lost"); 1323 printf("\n"); 1324 vr_rxeoc(sc); 1325 } 1326 1327 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1328 vr_reset(sc); 1329 vr_init_locked(sc); 1330 break; 1331 } 1332 1333 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1334 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1335 vr_txeof(sc); 1336 if ((status & VR_ISR_UDFI) || 1337 (status & VR_ISR_TX_ABRT2) || 1338 (status & VR_ISR_TX_ABRT)) { 1339 ifp->if_oerrors++; 1340 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1341 VR_SETBIT16(sc, VR_COMMAND, 1342 VR_CMD_TX_ON); 1343 VR_SETBIT16(sc, VR_COMMAND, 1344 VR_CMD_TX_GO); 1345 } 1346 } 1347 } 1348 } 1349 1350 /* Re-enable interrupts. */ 1351 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1352 1353 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1354 vr_start_locked(ifp); 1355 1356done_locked: 1357 VR_UNLOCK(sc); 1358} 1359 1360/* 1361 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1362 * to the mbuf data regions directly in the transmit lists. We also save a 1363 * copy of the pointers since the transmit list fragment pointers are 1364 * physical addresses. 1365 */ 1366 1367static void 1368vr_start(struct ifnet *ifp) 1369{ 1370 struct vr_softc *sc = ifp->if_softc; 1371 1372 VR_LOCK(sc); 1373 vr_start_locked(ifp); 1374 VR_UNLOCK(sc); 1375} 1376 1377static void 1378vr_start_locked(struct ifnet *ifp) 1379{ 1380 struct vr_softc *sc = ifp->if_softc; 1381 struct mbuf *m, *m_head; 1382 struct vr_chain *cur_tx, *n_tx; 1383 struct vr_desc *f = NULL; 1384 uint32_t cval; 1385 1386 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1387 return; 1388 1389 for (cur_tx = sc->vr_cdata.vr_tx_prod; 1390 cur_tx->vr_nextdesc != sc->vr_cdata.vr_tx_cons; ) { 1391 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1392 if (m_head == NULL) 1393 break; 1394 1395 VR_LOCK_ASSERT(sc); 1396 /* 1397 * Some VIA Rhine wants packet buffers to be longword 1398 * aligned, but very often our mbufs aren't. Rather than 1399 * waste time trying to decide when to copy and when not 1400 * to copy, just do it all the time. 1401 */ 1402 if (sc->vr_quirks & VR_Q_NEEDALIGN) { 1403 m = m_defrag(m_head, M_DONTWAIT); 1404 if (m == NULL) { 1405 /* Rollback, send what we were able to encap. */ 1406 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1407 break; 1408 } 1409 m_head = m; 1410 } 1411 1412 /* 1413 * The Rhine chip doesn't auto-pad, so we have to make 1414 * sure to pad short frames out to the minimum frame length 1415 * ourselves. 1416 */ 1417 if (m_head->m_pkthdr.len < VR_MIN_FRAMELEN) { 1418 if (m_head->m_next != NULL) 1419 m_head = m_defrag(m_head, M_DONTWAIT); 1420 m_head->m_pkthdr.len += VR_MIN_FRAMELEN - m_head->m_len; 1421 m_head->m_len = m_head->m_pkthdr.len; 1422 /* XXX: bzero the padding bytes */ 1423 } 1424 1425 n_tx = cur_tx; 1426 for (m = m_head; m != NULL; m = m->m_next) { 1427 if (m->m_len == 0) 1428 continue; 1429 if (n_tx->vr_nextdesc == sc->vr_cdata.vr_tx_cons) { 1430 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1431 sc->vr_cdata.vr_tx_prod = cur_tx; 1432 return; 1433 } 1434 KASSERT(n_tx->vr_mbuf == NULL, ("if_vr_tx overrun")); 1435 1436 f = n_tx->vr_ptr; 1437 f->vr_data = vtophys(mtod(m, caddr_t)); 1438 cval = m->m_len; 1439 cval |= VR_TXCTL_TLINK; 1440 1441 if ((ifp->if_capenable & IFCAP_TXCSUM) && 1442 m_head->m_pkthdr.csum_flags) { 1443 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1444 cval |= VR_TXCTL_IPCSUM; 1445 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1446 cval |= VR_TXCTL_TCPCSUM; 1447 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1448 cval |= VR_TXCTL_UDPCSUM; 1449 } 1450 1451 if (m == m_head) 1452 cval |= VR_TXCTL_FIRSTFRAG; 1453 f->vr_ctl = cval; 1454 f->vr_status = 0; 1455 n_tx = n_tx->vr_nextdesc; 1456 f->vr_next = vtophys(n_tx->vr_ptr); 1457 KASSERT(!(f->vr_next & 0xf), 1458 ("vr_next not 16 byte aligned 0x%x", f->vr_next)); 1459 } 1460 1461 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1462 cur_tx->vr_mbuf = m_head; 1463 atomic_set_acq_32(&VR_TXOWN(cur_tx), VR_TXSTAT_OWN); 1464 1465 /* Tell the chip to start transmitting. */ 1466 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1467 1468 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1469 ifp->if_timer = 5; 1470 1471 /* 1472 * If there's a BPF listener, bounce a copy of this frame 1473 * to him. 1474 */ 1475 BPF_MTAP(ifp, m_head); 1476 cur_tx = n_tx; 1477 } 1478 sc->vr_cdata.vr_tx_prod = cur_tx; 1479} 1480 1481static void 1482vr_init(void *xsc) 1483{ 1484 struct vr_softc *sc = xsc; 1485 1486 VR_LOCK(sc); 1487 vr_init_locked(sc); 1488 VR_UNLOCK(sc); 1489} 1490 1491static void 1492vr_init_locked(struct vr_softc *sc) 1493{ 1494 struct ifnet *ifp = sc->vr_ifp; 1495 struct mii_data *mii; 1496 int i; 1497 1498 VR_LOCK_ASSERT(sc); 1499 1500 mii = device_get_softc(sc->vr_miibus); 1501 1502 /* Cancel pending I/O and free all RX/TX buffers. */ 1503 vr_stop(sc); 1504 vr_reset(sc); 1505 1506 /* Set our station address. */ 1507 for (i = 0; i < ETHER_ADDR_LEN; i++) 1508 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 1509 1510 /* Set DMA size. */ 1511 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1512 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1513 1514 /* 1515 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1516 * so we must set both. 1517 */ 1518 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1519 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1520 1521 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1522 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1523 1524 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1525 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1526 1527 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1528 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1529 1530 /* Init circular RX list. */ 1531 if (vr_list_rx_init(sc) == ENOBUFS) { 1532 device_printf(sc->vr_dev, 1533 "initialization failed: no memory for rx buffers\n"); 1534 vr_stop(sc); 1535 return; 1536 } 1537 1538 /* Init tx descriptors. */ 1539 vr_list_tx_init(sc); 1540 1541 /* If we want promiscuous mode, set the allframes bit. */ 1542 if (ifp->if_flags & IFF_PROMISC) 1543 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1544 else 1545 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1546 1547 /* Set capture broadcast bit to capture broadcast frames. */ 1548 if (ifp->if_flags & IFF_BROADCAST) 1549 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1550 else 1551 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1552 1553 /* 1554 * Program the multicast filter, if necessary. 1555 */ 1556 vr_setmulti(sc); 1557 1558 /* 1559 * Load the address of the RX list. 1560 */ 1561 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1562 1563 /* Enable receiver and transmitter. */ 1564 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1565 VR_CMD_TX_ON|VR_CMD_RX_ON| 1566 VR_CMD_RX_GO); 1567 1568 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1569 1570 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1571#ifdef DEVICE_POLLING 1572 /* 1573 * Disable interrupts if we are polling. 1574 */ 1575 if (ifp->if_capenable & IFCAP_POLLING) 1576 CSR_WRITE_2(sc, VR_IMR, 0); 1577 else 1578#endif 1579 /* 1580 * Enable interrupts. 1581 */ 1582 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1583 1584 mii_mediachg(mii); 1585 1586 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1587 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1588 1589 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1590} 1591 1592/* 1593 * Set media options. 1594 */ 1595static int 1596vr_ifmedia_upd(struct ifnet *ifp) 1597{ 1598 struct vr_softc *sc = ifp->if_softc; 1599 1600 if (ifp->if_flags & IFF_UP) 1601 vr_init(sc); 1602 1603 return (0); 1604} 1605 1606/* 1607 * Report current media status. 1608 */ 1609static void 1610vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1611{ 1612 struct vr_softc *sc = ifp->if_softc; 1613 struct mii_data *mii; 1614 1615 mii = device_get_softc(sc->vr_miibus); 1616 VR_LOCK(sc); 1617 mii_pollstat(mii); 1618 VR_UNLOCK(sc); 1619 ifmr->ifm_active = mii->mii_media_active; 1620 ifmr->ifm_status = mii->mii_media_status; 1621} 1622 1623static int 1624vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1625{ 1626 struct vr_softc *sc = ifp->if_softc; 1627 struct ifreq *ifr = (struct ifreq *) data; 1628 struct mii_data *mii; 1629 int error = 0; 1630 1631 switch (command) { 1632 case SIOCSIFFLAGS: 1633 VR_LOCK(sc); 1634 if (ifp->if_flags & IFF_UP) { 1635 vr_init_locked(sc); 1636 } else { 1637 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1638 vr_stop(sc); 1639 } 1640 VR_UNLOCK(sc); 1641 error = 0; 1642 break; 1643 case SIOCADDMULTI: 1644 case SIOCDELMULTI: 1645 VR_LOCK(sc); 1646 vr_setmulti(sc); 1647 VR_UNLOCK(sc); 1648 error = 0; 1649 break; 1650 case SIOCGIFMEDIA: 1651 case SIOCSIFMEDIA: 1652 mii = device_get_softc(sc->vr_miibus); 1653 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1654 break; 1655 case SIOCSIFCAP: 1656#ifdef DEVICE_POLLING 1657 if (ifr->ifr_reqcap & IFCAP_POLLING && 1658 !(ifp->if_capenable & IFCAP_POLLING)) { 1659 error = ether_poll_register(vr_poll, ifp); 1660 if (error) 1661 return(error); 1662 VR_LOCK(sc); 1663 /* Disable interrupts */ 1664 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1665 ifp->if_capenable |= IFCAP_POLLING; 1666 VR_UNLOCK(sc); 1667 return (error); 1668 1669 } 1670 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1671 ifp->if_capenable & IFCAP_POLLING) { 1672 error = ether_poll_deregister(ifp); 1673 /* Enable interrupts. */ 1674 VR_LOCK(sc); 1675 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1676 ifp->if_capenable &= ~IFCAP_POLLING; 1677 VR_UNLOCK(sc); 1678 return (error); 1679 } 1680#endif /* DEVICE_POLLING */ 1681 ifp->if_capenable = ifr->ifr_reqcap; 1682 if (ifp->if_capenable & IFCAP_TXCSUM) 1683 ifp->if_hwassist = (CSUM_IP | CSUM_TCP | CSUM_UDP); 1684 else 1685 ifp->if_hwassist = 0; 1686 break; 1687 default: 1688 error = ether_ioctl(ifp, command, data); 1689 break; 1690 } 1691 1692 return (error); 1693} 1694 1695static void 1696vr_watchdog(struct ifnet *ifp) 1697{ 1698 struct vr_softc *sc = ifp->if_softc; 1699 1700 VR_LOCK(sc); 1701 1702 ifp->if_oerrors++; 1703 if_printf(ifp, "watchdog timeout\n"); 1704 1705 vr_stop(sc); 1706 vr_reset(sc); 1707 vr_init_locked(sc); 1708 1709 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1710 vr_start_locked(ifp); 1711 1712 VR_UNLOCK(sc); 1713} 1714 1715/* 1716 * Stop the adapter and free any mbufs allocated to the 1717 * RX and TX lists. 1718 */ 1719static void 1720vr_stop(struct vr_softc *sc) 1721{ 1722 register int i; 1723 struct ifnet *ifp; 1724 1725 VR_LOCK_ASSERT(sc); 1726 1727 ifp = sc->vr_ifp; 1728 ifp->if_timer = 0; 1729 1730 callout_stop(&sc->vr_stat_callout); 1731 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1732 1733 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1734 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1735 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1736 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1737 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1738 1739 /* 1740 * Free data in the RX lists. 1741 */ 1742 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1743 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1744 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1745 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1746 } 1747 } 1748 bzero((char *)&sc->vr_ldata->vr_rx_list, 1749 sizeof(sc->vr_ldata->vr_rx_list)); 1750 1751 /* 1752 * Free the TX list buffers. 1753 */ 1754 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1755 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1756 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1757 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1758 } 1759 } 1760 bzero((char *)&sc->vr_ldata->vr_tx_list, 1761 sizeof(sc->vr_ldata->vr_tx_list)); 1762} 1763 1764/* 1765 * Stop all chip I/O so that the kernel's probe routines don't 1766 * get confused by errant DMAs when rebooting. 1767 */ 1768static void 1769vr_shutdown(device_t dev) 1770{ 1771 1772 vr_detach(dev); 1773} 1774