if_vr.c revision 152315
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 152315 2005-11-11 16:04:59Z ru $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48/* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63#ifdef HAVE_KERNEL_OPTION_HEADERS 64#include "opt_device_polling.h" 65#endif 66 67#include <sys/param.h> 68#include <sys/systm.h> 69#include <sys/sockio.h> 70#include <sys/mbuf.h> 71#include <sys/malloc.h> 72#include <sys/kernel.h> 73#include <sys/module.h> 74#include <sys/socket.h> 75 76#include <net/if.h> 77#include <net/if_arp.h> 78#include <net/ethernet.h> 79#include <net/if_dl.h> 80#include <net/if_media.h> 81#include <net/if_types.h> 82 83#include <net/bpf.h> 84 85#include <vm/vm.h> /* for vtophys */ 86#include <vm/pmap.h> /* for vtophys */ 87#include <machine/bus.h> 88#include <machine/resource.h> 89#include <sys/bus.h> 90#include <sys/rman.h> 91 92#include <dev/mii/mii.h> 93#include <dev/mii/miivar.h> 94 95#include <dev/pci/pcireg.h> 96#include <dev/pci/pcivar.h> 97 98#define VR_USEIOSPACE 99 100#include <pci/if_vrreg.h> 101 102MODULE_DEPEND(vr, pci, 1, 1, 1); 103MODULE_DEPEND(vr, ether, 1, 1, 1); 104MODULE_DEPEND(vr, miibus, 1, 1, 1); 105 106/* "device miibus" required. See GENERIC if you get errors here. */ 107#include "miibus_if.h" 108 109#undef VR_USESWSHIFT 110 111/* 112 * Various supported device vendors/types and their names. 113 */ 114static struct vr_type vr_devs[] = { 115 { VIA_VENDORID, VIA_DEVICEID_RHINE, 116 "VIA VT3043 Rhine I 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 118 "VIA VT86C100A Rhine II 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 120 "VIA VT6102 Rhine II 10/100BaseTX" }, 121 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 122 "VIA VT6105 Rhine III 10/100BaseTX" }, 123 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 124 "VIA VT6105M Rhine III 10/100BaseTX" }, 125 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 126 "Delta Electronics Rhine II 10/100BaseTX" }, 127 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 128 "Addtron Technology Rhine II 10/100BaseTX" }, 129 { 0, 0, NULL } 130}; 131 132static int vr_probe(device_t); 133static int vr_attach(device_t); 134static int vr_detach(device_t); 135 136static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 137 struct mbuf *); 138static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 139 140static void vr_rxeof(struct vr_softc *); 141static void vr_rxeoc(struct vr_softc *); 142static void vr_txeof(struct vr_softc *); 143static void vr_tick(void *); 144static void vr_intr(void *); 145static void vr_start(struct ifnet *); 146static void vr_start_locked(struct ifnet *); 147static int vr_ioctl(struct ifnet *, u_long, caddr_t); 148static void vr_init(void *); 149static void vr_init_locked(struct vr_softc *); 150static void vr_stop(struct vr_softc *); 151static void vr_watchdog(struct ifnet *); 152static void vr_shutdown(device_t); 153static int vr_ifmedia_upd(struct ifnet *); 154static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155 156#ifdef VR_USESWSHIFT 157static void vr_mii_sync(struct vr_softc *); 158static void vr_mii_send(struct vr_softc *, uint32_t, int); 159#endif 160static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 161static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 162static int vr_miibus_readreg(device_t, uint16_t, uint16_t); 163static int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 164static void vr_miibus_statchg(device_t); 165 166static void vr_setcfg(struct vr_softc *, int); 167static void vr_setmulti(struct vr_softc *); 168static void vr_reset(struct vr_softc *); 169static int vr_list_rx_init(struct vr_softc *); 170static int vr_list_tx_init(struct vr_softc *); 171 172#ifdef VR_USEIOSPACE 173#define VR_RES SYS_RES_IOPORT 174#define VR_RID VR_PCI_LOIO 175#else 176#define VR_RES SYS_RES_MEMORY 177#define VR_RID VR_PCI_LOMEM 178#endif 179 180static device_method_t vr_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, vr_probe), 183 DEVMETHOD(device_attach, vr_attach), 184 DEVMETHOD(device_detach, vr_detach), 185 DEVMETHOD(device_shutdown, vr_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 193 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 194 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t vr_driver = { 200 "vr", 201 vr_methods, 202 sizeof(struct vr_softc) 203}; 204 205static devclass_t vr_devclass; 206 207DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 208DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 209 210#define VR_SETBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) | (x)) 213 214#define VR_CLRBIT(sc, reg, x) \ 215 CSR_WRITE_1(sc, reg, \ 216 CSR_READ_1(sc, reg) & ~(x)) 217 218#define VR_SETBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) | (x)) 221 222#define VR_CLRBIT16(sc, reg, x) \ 223 CSR_WRITE_2(sc, reg, \ 224 CSR_READ_2(sc, reg) & ~(x)) 225 226#define VR_SETBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define VR_CLRBIT32(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_1(sc, VR_MIICMD, \ 240 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 241 242#ifdef VR_USESWSHIFT 243/* 244 * Sync the PHYs by setting data bit and strobing the clock 32 times. 245 */ 246static void 247vr_mii_sync(struct vr_softc *sc) 248{ 249 register int i; 250 251 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 252 253 for (i = 0; i < 32; i++) { 254 SIO_SET(VR_MIICMD_CLK); 255 DELAY(1); 256 SIO_CLR(VR_MIICMD_CLK); 257 DELAY(1); 258 } 259} 260 261/* 262 * Clock a series of bits through the MII. 263 */ 264static void 265vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 266{ 267 int i; 268 269 SIO_CLR(VR_MIICMD_CLK); 270 271 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 272 if (bits & i) { 273 SIO_SET(VR_MIICMD_DATAIN); 274 } else { 275 SIO_CLR(VR_MIICMD_DATAIN); 276 } 277 DELAY(1); 278 SIO_CLR(VR_MIICMD_CLK); 279 DELAY(1); 280 SIO_SET(VR_MIICMD_CLK); 281 } 282} 283#endif 284 285/* 286 * Read an PHY register through the MII. 287 */ 288static int 289vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 290#ifdef VR_USESWSHIFT 291{ 292 int i, ack; 293 294 /* Set up frame for RX. */ 295 frame->mii_stdelim = VR_MII_STARTDELIM; 296 frame->mii_opcode = VR_MII_READOP; 297 frame->mii_turnaround = 0; 298 frame->mii_data = 0; 299 300 CSR_WRITE_1(sc, VR_MIICMD, 0); 301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302 303 /* Turn on data xmit. */ 304 SIO_SET(VR_MIICMD_DIR); 305 306 vr_mii_sync(sc); 307 308 /* Send command/address info. */ 309 vr_mii_send(sc, frame->mii_stdelim, 2); 310 vr_mii_send(sc, frame->mii_opcode, 2); 311 vr_mii_send(sc, frame->mii_phyaddr, 5); 312 vr_mii_send(sc, frame->mii_regaddr, 5); 313 314 /* Idle bit. */ 315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 316 DELAY(1); 317 SIO_SET(VR_MIICMD_CLK); 318 DELAY(1); 319 320 /* Turn off xmit. */ 321 SIO_CLR(VR_MIICMD_DIR); 322 323 /* Check for ack */ 324 SIO_CLR(VR_MIICMD_CLK); 325 DELAY(1); 326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 327 SIO_SET(VR_MIICMD_CLK); 328 DELAY(1); 329 330 /* 331 * Now try reading data bits. If the ack failed, we still 332 * need to clock through 16 cycles to keep the PHY(s) in sync. 333 */ 334 if (ack) { 335 for(i = 0; i < 16; i++) { 336 SIO_CLR(VR_MIICMD_CLK); 337 DELAY(1); 338 SIO_SET(VR_MIICMD_CLK); 339 DELAY(1); 340 } 341 goto fail; 342 } 343 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_CLR(VR_MIICMD_CLK); 346 DELAY(1); 347 if (!ack) { 348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 349 frame->mii_data |= i; 350 DELAY(1); 351 } 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 356fail: 357 SIO_CLR(VR_MIICMD_CLK); 358 DELAY(1); 359 SIO_SET(VR_MIICMD_CLK); 360 DELAY(1); 361 362 if (ack) 363 return (1); 364 return (0); 365} 366#else 367{ 368 int i; 369 370 /* Set the PHY address. */ 371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 372 frame->mii_phyaddr); 373 374 /* Set the register address. */ 375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 377 378 for (i = 0; i < 10000; i++) { 379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 380 break; 381 DELAY(1); 382 } 383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 384 385 return (0); 386} 387#endif 388 389 390/* 391 * Write to a PHY register through the MII. 392 */ 393static int 394vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 395#ifdef VR_USESWSHIFT 396{ 397 CSR_WRITE_1(sc, VR_MIICMD, 0); 398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 400 /* Set up frame for TX. */ 401 frame->mii_stdelim = VR_MII_STARTDELIM; 402 frame->mii_opcode = VR_MII_WRITEOP; 403 frame->mii_turnaround = VR_MII_TURNAROUND; 404 405 /* Turn on data output. */ 406 SIO_SET(VR_MIICMD_DIR); 407 408 vr_mii_sync(sc); 409 410 vr_mii_send(sc, frame->mii_stdelim, 2); 411 vr_mii_send(sc, frame->mii_opcode, 2); 412 vr_mii_send(sc, frame->mii_phyaddr, 5); 413 vr_mii_send(sc, frame->mii_regaddr, 5); 414 vr_mii_send(sc, frame->mii_turnaround, 2); 415 vr_mii_send(sc, frame->mii_data, 16); 416 417 /* Idle bit. */ 418 SIO_SET(VR_MIICMD_CLK); 419 DELAY(1); 420 SIO_CLR(VR_MIICMD_CLK); 421 DELAY(1); 422 423 /* Turn off xmit. */ 424 SIO_CLR(VR_MIICMD_DIR); 425 426 return (0); 427} 428#else 429{ 430 int i; 431 432 /* Set the PHY address. */ 433 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 434 frame->mii_phyaddr); 435 436 /* Set the register address and data to write. */ 437 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 438 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 439 440 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 441 442 for (i = 0; i < 10000; i++) { 443 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 444 break; 445 DELAY(1); 446 } 447 448 return (0); 449} 450#endif 451 452static int 453vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 454{ 455 struct vr_mii_frame frame; 456 struct vr_softc *sc = device_get_softc(dev); 457 458 switch (sc->vr_revid) { 459 case REV_ID_VT6102_APOLLO: 460 if (phy != 1) { 461 frame.mii_data = 0; 462 goto out; 463 } 464 default: 465 break; 466 } 467 468 bzero((char *)&frame, sizeof(frame)); 469 frame.mii_phyaddr = phy; 470 frame.mii_regaddr = reg; 471 vr_mii_readreg(sc, &frame); 472 473out: 474 return (frame.mii_data); 475} 476 477static int 478vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 479{ 480 struct vr_mii_frame frame; 481 struct vr_softc *sc = device_get_softc(dev); 482 483 switch (sc->vr_revid) { 484 case REV_ID_VT6102_APOLLO: 485 if (phy != 1) 486 return (0); 487 default: 488 break; 489 } 490 491 bzero((char *)&frame, sizeof(frame)); 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 frame.mii_data = data; 495 vr_mii_writereg(sc, &frame); 496 497 return (0); 498} 499 500static void 501vr_miibus_statchg(device_t dev) 502{ 503 struct mii_data *mii; 504 struct vr_softc *sc = device_get_softc(dev); 505 506 mii = device_get_softc(sc->vr_miibus); 507 vr_setcfg(sc, mii->mii_media_active); 508} 509 510/* 511 * Program the 64-bit multicast hash filter. 512 */ 513static void 514vr_setmulti(struct vr_softc *sc) 515{ 516 struct ifnet *ifp = sc->vr_ifp; 517 int h = 0; 518 uint32_t hashes[2] = { 0, 0 }; 519 struct ifmultiaddr *ifma; 520 uint8_t rxfilt; 521 int mcnt = 0; 522 523 VR_LOCK_ASSERT(sc); 524 525 rxfilt = CSR_READ_1(sc, VR_RXCFG); 526 527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 528 rxfilt |= VR_RXCFG_RX_MULTI; 529 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 530 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 531 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 532 return; 533 } 534 535 /* First, zero out all the existing hash bits. */ 536 CSR_WRITE_4(sc, VR_MAR0, 0); 537 CSR_WRITE_4(sc, VR_MAR1, 0); 538 539 /* Now program new ones. */ 540 IF_ADDR_LOCK(ifp); 541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542 if (ifma->ifma_addr->sa_family != AF_LINK) 543 continue; 544 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 545 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 546 if (h < 32) 547 hashes[0] |= (1 << h); 548 else 549 hashes[1] |= (1 << (h - 32)); 550 mcnt++; 551 } 552 IF_ADDR_UNLOCK(ifp); 553 554 if (mcnt) 555 rxfilt |= VR_RXCFG_RX_MULTI; 556 else 557 rxfilt &= ~VR_RXCFG_RX_MULTI; 558 559 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 560 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 561 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 562} 563 564/* 565 * In order to fiddle with the 566 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 567 * first have to put the transmit and/or receive logic in the idle state. 568 */ 569static void 570vr_setcfg(struct vr_softc *sc, int media) 571{ 572 int restart = 0; 573 574 VR_LOCK_ASSERT(sc); 575 576 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 577 restart = 1; 578 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 579 } 580 581 if ((media & IFM_GMASK) == IFM_FDX) 582 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 583 else 584 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 585 586 if (restart) 587 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 588} 589 590static void 591vr_reset(struct vr_softc *sc) 592{ 593 register int i; 594 595 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 596 597 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 598 599 for (i = 0; i < VR_TIMEOUT; i++) { 600 DELAY(10); 601 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 602 break; 603 } 604 if (i == VR_TIMEOUT) { 605 if (sc->vr_revid < REV_ID_VT3065_A) 606 if_printf(sc->vr_ifp, "reset never completed!\n"); 607 else { 608 /* Use newer force reset command */ 609 if_printf(sc->vr_ifp, "Using force reset command.\n"); 610 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 611 } 612 } 613 614 /* Wait a little while for the chip to get its brains in order. */ 615 DELAY(1000); 616} 617 618/* 619 * Probe for a VIA Rhine chip. Check the PCI vendor and device 620 * IDs against our list and return a device name if we find a match. 621 */ 622static int 623vr_probe(device_t dev) 624{ 625 struct vr_type *t = vr_devs; 626 627 while (t->vr_name != NULL) { 628 if ((pci_get_vendor(dev) == t->vr_vid) && 629 (pci_get_device(dev) == t->vr_did)) { 630 device_set_desc(dev, t->vr_name); 631 return (BUS_PROBE_DEFAULT); 632 } 633 t++; 634 } 635 636 return (ENXIO); 637} 638 639/* 640 * Attach the interface. Allocate softc structures, do ifmedia 641 * setup and ethernet/BPF attach. 642 */ 643static int 644vr_attach(dev) 645 device_t dev; 646{ 647 int i; 648 u_char eaddr[ETHER_ADDR_LEN]; 649 struct vr_softc *sc; 650 struct ifnet *ifp; 651 int unit, error = 0, rid; 652 653 sc = device_get_softc(dev); 654 unit = device_get_unit(dev); 655 656 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 657 MTX_DEF); 658 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 659 660 /* 661 * Map control/status registers. 662 */ 663 pci_enable_busmaster(dev); 664 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 665 666 rid = VR_RID; 667 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 668 669 if (sc->vr_res == NULL) { 670 device_printf(dev, "couldn't map ports/memory\n"); 671 error = ENXIO; 672 goto fail; 673 } 674 675 sc->vr_btag = rman_get_bustag(sc->vr_res); 676 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 677 678 /* Allocate interrupt */ 679 rid = 0; 680 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 681 RF_SHAREABLE | RF_ACTIVE); 682 683 if (sc->vr_irq == NULL) { 684 device_printf(dev, "couldn't map interrupt\n"); 685 error = ENXIO; 686 goto fail; 687 } 688 689 /* Allocate ifnet structure. */ 690 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 691 if (ifp == NULL) { 692 device_printf(dev, "can not if_alloc()\n"); 693 error = ENOSPC; 694 goto fail; 695 } 696 ifp->if_softc = sc; 697 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 698 ifp->if_mtu = ETHERMTU; 699 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 700 ifp->if_ioctl = vr_ioctl; 701 ifp->if_start = vr_start; 702 ifp->if_watchdog = vr_watchdog; 703 ifp->if_init = vr_init; 704 ifp->if_baudrate = 10000000; 705 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 706 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 707 IFQ_SET_READY(&ifp->if_snd); 708 ifp->if_capenable = ifp->if_capabilities; 709#ifdef DEVICE_POLLING 710 ifp->if_capabilities |= IFCAP_POLLING; 711#endif 712 713 /* 714 * Windows may put the chip in suspend mode when it 715 * shuts down. Be sure to kick it in the head to wake it 716 * up again. 717 */ 718 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 719 720 /* Reset the adapter. */ 721 vr_reset(sc); 722 723 /* 724 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 725 * initialization and disable AUTOPOLL. 726 */ 727 pci_write_config(dev, VR_PCI_MODE, 728 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 729 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 730 731 /* 732 * Get station address. The way the Rhine chips work, 733 * you're not allowed to directly access the EEPROM once 734 * they've been programmed a special way. Consequently, 735 * we need to read the node address from the PAR0 and PAR1 736 * registers. 737 */ 738 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 739 DELAY(200); 740 for (i = 0; i < ETHER_ADDR_LEN; i++) 741 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 742 743 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 744 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 745 746 if (sc->vr_ldata == NULL) { 747 device_printf(dev, "no memory for list buffers!\n"); 748 error = ENXIO; 749 goto fail; 750 } 751 752 /* Do MII setup. */ 753 if (mii_phy_probe(dev, &sc->vr_miibus, 754 vr_ifmedia_upd, vr_ifmedia_sts)) { 755 device_printf(dev, "MII without any phy!\n"); 756 error = ENXIO; 757 goto fail; 758 } 759 760 /* Call MI attach routine. */ 761 ether_ifattach(ifp, eaddr); 762 763 sc->suspended = 0; 764 765 /* Hook interrupt last to avoid having to lock softc */ 766 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 767 vr_intr, sc, &sc->vr_intrhand); 768 769 if (error) { 770 device_printf(dev, "couldn't set up irq\n"); 771 ether_ifdetach(ifp); 772 goto fail; 773 } 774 775fail: 776 if (error) 777 vr_detach(dev); 778 779 return (error); 780} 781 782/* 783 * Shutdown hardware and free up resources. This can be called any 784 * time after the mutex has been initialized. It is called in both 785 * the error case in attach and the normal detach case so it needs 786 * to be careful about only freeing resources that have actually been 787 * allocated. 788 */ 789static int 790vr_detach(device_t dev) 791{ 792 struct vr_softc *sc = device_get_softc(dev); 793 struct ifnet *ifp = sc->vr_ifp; 794 795 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 796 797#ifdef DEVICE_POLLING 798 if (ifp->if_capenable & IFCAP_POLLING) 799 ether_poll_deregister(ifp); 800#endif 801 802 /* These should only be active if attach succeeded */ 803 if (device_is_attached(dev)) { 804 VR_LOCK(sc); 805 sc->suspended = 1; 806 vr_stop(sc); 807 VR_UNLOCK(sc); 808 callout_drain(&sc->vr_stat_callout); 809 ether_ifdetach(ifp); 810 } 811 if (sc->vr_miibus) 812 device_delete_child(dev, sc->vr_miibus); 813 bus_generic_detach(dev); 814 815 if (sc->vr_intrhand) 816 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 817 if (sc->vr_irq) 818 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 819 if (sc->vr_res) 820 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 821 822 if (ifp) 823 if_free(ifp); 824 825 if (sc->vr_ldata) 826 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 827 828 mtx_destroy(&sc->vr_mtx); 829 830 return (0); 831} 832 833/* 834 * Initialize the transmit descriptors. 835 */ 836static int 837vr_list_tx_init(struct vr_softc *sc) 838{ 839 struct vr_chain_data *cd; 840 struct vr_list_data *ld; 841 int i; 842 843 cd = &sc->vr_cdata; 844 ld = sc->vr_ldata; 845 for (i = 0; i < VR_TX_LIST_CNT; i++) { 846 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 847 if (i == (VR_TX_LIST_CNT - 1)) 848 cd->vr_tx_chain[i].vr_nextdesc = 849 &cd->vr_tx_chain[0]; 850 else 851 cd->vr_tx_chain[i].vr_nextdesc = 852 &cd->vr_tx_chain[i + 1]; 853 } 854 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 855 856 return (0); 857} 858 859 860/* 861 * Initialize the RX descriptors and allocate mbufs for them. Note that 862 * we arrange the descriptors in a closed ring, so that the last descriptor 863 * points back to the first. 864 */ 865static int 866vr_list_rx_init(struct vr_softc *sc) 867{ 868 struct vr_chain_data *cd; 869 struct vr_list_data *ld; 870 int i; 871 872 VR_LOCK_ASSERT(sc); 873 874 cd = &sc->vr_cdata; 875 ld = sc->vr_ldata; 876 877 for (i = 0; i < VR_RX_LIST_CNT; i++) { 878 cd->vr_rx_chain[i].vr_ptr = 879 (struct vr_desc *)&ld->vr_rx_list[i]; 880 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 881 return (ENOBUFS); 882 if (i == (VR_RX_LIST_CNT - 1)) { 883 cd->vr_rx_chain[i].vr_nextdesc = 884 &cd->vr_rx_chain[0]; 885 ld->vr_rx_list[i].vr_next = 886 vtophys(&ld->vr_rx_list[0]); 887 } else { 888 cd->vr_rx_chain[i].vr_nextdesc = 889 &cd->vr_rx_chain[i + 1]; 890 ld->vr_rx_list[i].vr_next = 891 vtophys(&ld->vr_rx_list[i + 1]); 892 } 893 } 894 895 cd->vr_rx_head = &cd->vr_rx_chain[0]; 896 897 return (0); 898} 899 900/* 901 * Initialize an RX descriptor and attach an MBUF cluster. 902 * Note: the length fields are only 11 bits wide, which means the 903 * largest size we can specify is 2047. This is important because 904 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 905 * overflow the field and make a mess. 906 */ 907static int 908vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 909{ 910 struct mbuf *m_new = NULL; 911 912 if (m == NULL) { 913 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 914 if (m_new == NULL) 915 return (ENOBUFS); 916 917 MCLGET(m_new, M_DONTWAIT); 918 if (!(m_new->m_flags & M_EXT)) { 919 m_freem(m_new); 920 return (ENOBUFS); 921 } 922 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 923 } else { 924 m_new = m; 925 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 926 m_new->m_data = m_new->m_ext.ext_buf; 927 } 928 929 m_adj(m_new, sizeof(uint64_t)); 930 931 c->vr_mbuf = m_new; 932 c->vr_ptr->vr_status = VR_RXSTAT; 933 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 934 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 935 936 return (0); 937} 938 939/* 940 * A frame has been uploaded: pass the resulting mbuf chain up to 941 * the higher level protocols. 942 */ 943static void 944vr_rxeof(struct vr_softc *sc) 945{ 946 struct mbuf *m, *m0; 947 struct ifnet *ifp; 948 struct vr_chain_onefrag *cur_rx; 949 int total_len = 0; 950 uint32_t rxstat; 951 952 VR_LOCK_ASSERT(sc); 953 ifp = sc->vr_ifp; 954 955 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 956 VR_RXSTAT_OWN)) { 957#ifdef DEVICE_POLLING 958 if (ifp->if_capenable & IFCAP_POLLING) { 959 if (sc->rxcycles <= 0) 960 break; 961 sc->rxcycles--; 962 } 963#endif 964 m0 = NULL; 965 cur_rx = sc->vr_cdata.vr_rx_head; 966 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 967 m = cur_rx->vr_mbuf; 968 969 /* 970 * If an error occurs, update stats, clear the 971 * status word and leave the mbuf cluster in place: 972 * it should simply get re-used next time this descriptor 973 * comes up in the ring. 974 */ 975 if (rxstat & VR_RXSTAT_RXERR) { 976 ifp->if_ierrors++; 977 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 978 if (rxstat & VR_RXSTAT_CRCERR) 979 printf(" crc error"); 980 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 981 printf(" frame alignment error\n"); 982 if (rxstat & VR_RXSTAT_FIFOOFLOW) 983 printf(" FIFO overflow"); 984 if (rxstat & VR_RXSTAT_GIANT) 985 printf(" received giant packet"); 986 if (rxstat & VR_RXSTAT_RUNT) 987 printf(" received runt packet"); 988 if (rxstat & VR_RXSTAT_BUSERR) 989 printf(" system bus error"); 990 if (rxstat & VR_RXSTAT_BUFFERR) 991 printf("rx buffer error"); 992 printf("\n"); 993 vr_newbuf(sc, cur_rx, m); 994 continue; 995 } 996 997 /* No errors; receive the packet. */ 998 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 999 1000 /* 1001 * XXX The VIA Rhine chip includes the CRC with every 1002 * received frame, and there's no way to turn this 1003 * behavior off (at least, I can't find anything in 1004 * the manual that explains how to do it) so we have 1005 * to trim off the CRC manually. 1006 */ 1007 total_len -= ETHER_CRC_LEN; 1008 1009 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1010 NULL); 1011 vr_newbuf(sc, cur_rx, m); 1012 if (m0 == NULL) { 1013 ifp->if_ierrors++; 1014 continue; 1015 } 1016 m = m0; 1017 1018 ifp->if_ipackets++; 1019 VR_UNLOCK(sc); 1020 (*ifp->if_input)(ifp, m); 1021 VR_LOCK(sc); 1022 } 1023} 1024 1025static void 1026vr_rxeoc(struct vr_softc *sc) 1027{ 1028 struct ifnet *ifp = sc->vr_ifp; 1029 int i; 1030 1031 VR_LOCK_ASSERT(sc); 1032 1033 ifp->if_ierrors++; 1034 1035 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1036 DELAY(10000); 1037 1038 /* Wait for receiver to stop */ 1039 for (i = 0x400; 1040 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1041 i--) { 1042 ; 1043 } 1044 1045 if (!i) { 1046 if_printf(ifp, "rx shutdown error!\n"); 1047 sc->vr_flags |= VR_F_RESTART; 1048 return; 1049 } 1050 1051 vr_rxeof(sc); 1052 1053 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1056} 1057 1058/* 1059 * A frame was downloaded to the chip. It's safe for us to clean up 1060 * the list buffers. 1061 */ 1062static void 1063vr_txeof(struct vr_softc *sc) 1064{ 1065 struct vr_chain *cur_tx; 1066 struct ifnet *ifp = sc->vr_ifp; 1067 1068 VR_LOCK_ASSERT(sc); 1069 1070 /* 1071 * Go through our tx list and free mbufs for those 1072 * frames that have been transmitted. 1073 */ 1074 cur_tx = sc->vr_cdata.vr_tx_cons; 1075 while (cur_tx->vr_mbuf != NULL) { 1076 uint32_t txstat; 1077 int i; 1078 1079 txstat = cur_tx->vr_ptr->vr_status; 1080 1081 if ((txstat & VR_TXSTAT_ABRT) || 1082 (txstat & VR_TXSTAT_UDF)) { 1083 for (i = 0x400; 1084 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1085 i--) 1086 ; /* Wait for chip to shutdown */ 1087 if (!i) { 1088 if_printf(ifp, "tx shutdown timeout\n"); 1089 sc->vr_flags |= VR_F_RESTART; 1090 break; 1091 } 1092 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1093 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1094 break; 1095 } 1096 1097 if (txstat & VR_TXSTAT_OWN) 1098 break; 1099 1100 if (txstat & VR_TXSTAT_ERRSUM) { 1101 ifp->if_oerrors++; 1102 if (txstat & VR_TXSTAT_DEFER) 1103 ifp->if_collisions++; 1104 if (txstat & VR_TXSTAT_LATECOLL) 1105 ifp->if_collisions++; 1106 } 1107 1108 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1109 1110 ifp->if_opackets++; 1111 m_freem(cur_tx->vr_mbuf); 1112 cur_tx->vr_mbuf = NULL; 1113 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1114 1115 cur_tx = cur_tx->vr_nextdesc; 1116 } 1117 sc->vr_cdata.vr_tx_cons = cur_tx; 1118 if (cur_tx->vr_mbuf == NULL) 1119 ifp->if_timer = 0; 1120} 1121 1122static void 1123vr_tick(void *xsc) 1124{ 1125 struct vr_softc *sc = xsc; 1126 struct mii_data *mii; 1127 1128 VR_LOCK_ASSERT(sc); 1129 1130 if (sc->vr_flags & VR_F_RESTART) { 1131 if_printf(sc->vr_ifp, "restarting\n"); 1132 vr_stop(sc); 1133 vr_reset(sc); 1134 vr_init_locked(sc); 1135 sc->vr_flags &= ~VR_F_RESTART; 1136 } 1137 1138 mii = device_get_softc(sc->vr_miibus); 1139 mii_tick(mii); 1140 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1141} 1142 1143#ifdef DEVICE_POLLING 1144static poll_handler_t vr_poll; 1145static poll_handler_t vr_poll_locked; 1146 1147static void 1148vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1149{ 1150 struct vr_softc *sc = ifp->if_softc; 1151 1152 VR_LOCK(sc); 1153 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1154 vr_poll_locked(ifp, cmd, count); 1155 VR_UNLOCK(sc); 1156} 1157 1158static void 1159vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1160{ 1161 struct vr_softc *sc = ifp->if_softc; 1162 1163 VR_LOCK_ASSERT(sc); 1164 1165 sc->rxcycles = count; 1166 vr_rxeof(sc); 1167 vr_txeof(sc); 1168 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1169 vr_start_locked(ifp); 1170 1171 if (cmd == POLL_AND_CHECK_STATUS) { 1172 uint16_t status; 1173 1174 /* Also check status register. */ 1175 status = CSR_READ_2(sc, VR_ISR); 1176 if (status) 1177 CSR_WRITE_2(sc, VR_ISR, status); 1178 1179 if ((status & VR_INTRS) == 0) 1180 return; 1181 1182 if (status & VR_ISR_RX_DROPPED) { 1183 if_printf(ifp, "rx packet lost\n"); 1184 ifp->if_ierrors++; 1185 } 1186 1187 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1188 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1189 if_printf(ifp, "receive error (%04x)", status); 1190 if (status & VR_ISR_RX_NOBUF) 1191 printf(" no buffers"); 1192 if (status & VR_ISR_RX_OFLOW) 1193 printf(" overflow"); 1194 if (status & VR_ISR_RX_DROPPED) 1195 printf(" packet lost"); 1196 printf("\n"); 1197 vr_rxeoc(sc); 1198 } 1199 1200 if ((status & VR_ISR_BUSERR) || 1201 (status & VR_ISR_TX_UNDERRUN)) { 1202 vr_reset(sc); 1203 vr_init_locked(sc); 1204 return; 1205 } 1206 1207 if ((status & VR_ISR_UDFI) || 1208 (status & VR_ISR_TX_ABRT2) || 1209 (status & VR_ISR_TX_ABRT)) { 1210 ifp->if_oerrors++; 1211 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1212 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1213 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1214 } 1215 } 1216 } 1217} 1218#endif /* DEVICE_POLLING */ 1219 1220static void 1221vr_intr(void *arg) 1222{ 1223 struct vr_softc *sc = arg; 1224 struct ifnet *ifp = sc->vr_ifp; 1225 uint16_t status; 1226 1227 VR_LOCK(sc); 1228 1229 if (sc->suspended) { 1230 /* 1231 * Forcibly disable interrupts. 1232 * XXX: Mobile VIA based platforms may need 1233 * interrupt re-enable on resume. 1234 */ 1235 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1236 goto done_locked; 1237 } 1238 1239#ifdef DEVICE_POLLING 1240 if (ifp->if_capenable & IFCAP_POLLING) 1241 goto done_locked; 1242#endif 1243 1244 /* Suppress unwanted interrupts. */ 1245 if (!(ifp->if_flags & IFF_UP)) { 1246 vr_stop(sc); 1247 goto done_locked; 1248 } 1249 1250 /* Disable interrupts. */ 1251 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1252 1253 for (;;) { 1254 status = CSR_READ_2(sc, VR_ISR); 1255 if (status) 1256 CSR_WRITE_2(sc, VR_ISR, status); 1257 1258 if ((status & VR_INTRS) == 0) 1259 break; 1260 1261 if (status & VR_ISR_RX_OK) 1262 vr_rxeof(sc); 1263 1264 if (status & VR_ISR_RX_DROPPED) { 1265 if_printf(ifp, "rx packet lost\n"); 1266 ifp->if_ierrors++; 1267 } 1268 1269 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1270 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1271 if_printf(ifp, "receive error (%04x)", status); 1272 if (status & VR_ISR_RX_NOBUF) 1273 printf(" no buffers"); 1274 if (status & VR_ISR_RX_OFLOW) 1275 printf(" overflow"); 1276 if (status & VR_ISR_RX_DROPPED) 1277 printf(" packet lost"); 1278 printf("\n"); 1279 vr_rxeoc(sc); 1280 } 1281 1282 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1283 vr_reset(sc); 1284 vr_init_locked(sc); 1285 break; 1286 } 1287 1288 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1289 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1290 vr_txeof(sc); 1291 if ((status & VR_ISR_UDFI) || 1292 (status & VR_ISR_TX_ABRT2) || 1293 (status & VR_ISR_TX_ABRT)) { 1294 ifp->if_oerrors++; 1295 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1296 VR_SETBIT16(sc, VR_COMMAND, 1297 VR_CMD_TX_ON); 1298 VR_SETBIT16(sc, VR_COMMAND, 1299 VR_CMD_TX_GO); 1300 } 1301 } 1302 } 1303 } 1304 1305 /* Re-enable interrupts. */ 1306 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1307 1308 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1309 vr_start_locked(ifp); 1310 1311done_locked: 1312 VR_UNLOCK(sc); 1313} 1314 1315/* 1316 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1317 * pointers to the fragment pointers. 1318 */ 1319static int 1320vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1321{ 1322 struct vr_desc *f = NULL; 1323 struct mbuf *m; 1324 1325 VR_LOCK_ASSERT(sc); 1326 /* 1327 * The VIA Rhine wants packet buffers to be longword 1328 * aligned, but very often our mbufs aren't. Rather than 1329 * waste time trying to decide when to copy and when not 1330 * to copy, just do it all the time. 1331 */ 1332 m = m_defrag(m_head, M_DONTWAIT); 1333 if (m == NULL) 1334 return (1); 1335 1336 /* 1337 * The Rhine chip doesn't auto-pad, so we have to make 1338 * sure to pad short frames out to the minimum frame length 1339 * ourselves. 1340 */ 1341 if (m->m_len < VR_MIN_FRAMELEN) { 1342 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1343 m->m_len = m->m_pkthdr.len; 1344 } 1345 1346 c->vr_mbuf = m; 1347 f = c->vr_ptr; 1348 f->vr_data = vtophys(mtod(m, caddr_t)); 1349 f->vr_ctl = m->m_len; 1350 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1351 f->vr_status = 0; 1352 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1353 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1354 1355 return (0); 1356} 1357 1358/* 1359 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1360 * to the mbuf data regions directly in the transmit lists. We also save a 1361 * copy of the pointers since the transmit list fragment pointers are 1362 * physical addresses. 1363 */ 1364 1365static void 1366vr_start(struct ifnet *ifp) 1367{ 1368 struct vr_softc *sc = ifp->if_softc; 1369 1370 VR_LOCK(sc); 1371 vr_start_locked(ifp); 1372 VR_UNLOCK(sc); 1373} 1374 1375static void 1376vr_start_locked(struct ifnet *ifp) 1377{ 1378 struct vr_softc *sc = ifp->if_softc; 1379 struct mbuf *m_head; 1380 struct vr_chain *cur_tx; 1381 1382 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1383 return; 1384 1385 cur_tx = sc->vr_cdata.vr_tx_prod; 1386 while (cur_tx->vr_mbuf == NULL) { 1387 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1388 if (m_head == NULL) 1389 break; 1390 1391 /* Pack the data into the descriptor. */ 1392 if (vr_encap(sc, cur_tx, m_head)) { 1393 /* Rollback, send what we were able to encap. */ 1394 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1395 break; 1396 } 1397 1398 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1399 1400 /* 1401 * If there's a BPF listener, bounce a copy of this frame 1402 * to him. 1403 */ 1404 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1405 1406 cur_tx = cur_tx->vr_nextdesc; 1407 } 1408 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1409 sc->vr_cdata.vr_tx_prod = cur_tx; 1410 1411 /* Tell the chip to start transmitting. */ 1412 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1413 1414 /* Set a timeout in case the chip goes out to lunch. */ 1415 ifp->if_timer = 5; 1416 1417 if (cur_tx->vr_mbuf != NULL) 1418 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1419 } 1420} 1421 1422static void 1423vr_init(void *xsc) 1424{ 1425 struct vr_softc *sc = xsc; 1426 1427 VR_LOCK(sc); 1428 vr_init_locked(sc); 1429 VR_UNLOCK(sc); 1430} 1431 1432static void 1433vr_init_locked(struct vr_softc *sc) 1434{ 1435 struct ifnet *ifp = sc->vr_ifp; 1436 struct mii_data *mii; 1437 int i; 1438 1439 VR_LOCK_ASSERT(sc); 1440 1441 mii = device_get_softc(sc->vr_miibus); 1442 1443 /* Cancel pending I/O and free all RX/TX buffers. */ 1444 vr_stop(sc); 1445 vr_reset(sc); 1446 1447 /* Set our station address. */ 1448 for (i = 0; i < ETHER_ADDR_LEN; i++) 1449 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 1450 1451 /* Set DMA size. */ 1452 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1453 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1454 1455 /* 1456 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1457 * so we must set both. 1458 */ 1459 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1460 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1461 1462 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1463 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1464 1465 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1466 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1467 1468 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1469 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1470 1471 /* Init circular RX list. */ 1472 if (vr_list_rx_init(sc) == ENOBUFS) { 1473 if_printf(ifp, 1474 "initialization failed: no memory for rx buffers\n"); 1475 vr_stop(sc); 1476 return; 1477 } 1478 1479 /* Init tx descriptors. */ 1480 vr_list_tx_init(sc); 1481 1482 /* If we want promiscuous mode, set the allframes bit. */ 1483 if (ifp->if_flags & IFF_PROMISC) 1484 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1485 else 1486 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1487 1488 /* Set capture broadcast bit to capture broadcast frames. */ 1489 if (ifp->if_flags & IFF_BROADCAST) 1490 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1491 else 1492 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1493 1494 /* 1495 * Program the multicast filter, if necessary. 1496 */ 1497 vr_setmulti(sc); 1498 1499 /* 1500 * Load the address of the RX list. 1501 */ 1502 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1503 1504 /* Enable receiver and transmitter. */ 1505 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1506 VR_CMD_TX_ON|VR_CMD_RX_ON| 1507 VR_CMD_RX_GO); 1508 1509 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1510 1511 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1512#ifdef DEVICE_POLLING 1513 /* 1514 * Disable interrupts if we are polling. 1515 */ 1516 if (ifp->if_capenable & IFCAP_POLLING) 1517 CSR_WRITE_2(sc, VR_IMR, 0); 1518 else 1519#endif 1520 /* 1521 * Enable interrupts. 1522 */ 1523 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1524 1525 mii_mediachg(mii); 1526 1527 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1528 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1529 1530 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1531} 1532 1533/* 1534 * Set media options. 1535 */ 1536static int 1537vr_ifmedia_upd(struct ifnet *ifp) 1538{ 1539 struct vr_softc *sc = ifp->if_softc; 1540 1541 if (ifp->if_flags & IFF_UP) 1542 vr_init(sc); 1543 1544 return (0); 1545} 1546 1547/* 1548 * Report current media status. 1549 */ 1550static void 1551vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1552{ 1553 struct vr_softc *sc = ifp->if_softc; 1554 struct mii_data *mii; 1555 1556 mii = device_get_softc(sc->vr_miibus); 1557 VR_LOCK(sc); 1558 mii_pollstat(mii); 1559 VR_UNLOCK(sc); 1560 ifmr->ifm_active = mii->mii_media_active; 1561 ifmr->ifm_status = mii->mii_media_status; 1562} 1563 1564static int 1565vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1566{ 1567 struct vr_softc *sc = ifp->if_softc; 1568 struct ifreq *ifr = (struct ifreq *) data; 1569 struct mii_data *mii; 1570 int error = 0; 1571 1572 switch (command) { 1573 case SIOCSIFFLAGS: 1574 VR_LOCK(sc); 1575 if (ifp->if_flags & IFF_UP) { 1576 vr_init_locked(sc); 1577 } else { 1578 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1579 vr_stop(sc); 1580 } 1581 VR_UNLOCK(sc); 1582 error = 0; 1583 break; 1584 case SIOCADDMULTI: 1585 case SIOCDELMULTI: 1586 VR_LOCK(sc); 1587 vr_setmulti(sc); 1588 VR_UNLOCK(sc); 1589 error = 0; 1590 break; 1591 case SIOCGIFMEDIA: 1592 case SIOCSIFMEDIA: 1593 mii = device_get_softc(sc->vr_miibus); 1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1595 break; 1596 case SIOCSIFCAP: 1597#ifdef DEVICE_POLLING 1598 if (ifr->ifr_reqcap & IFCAP_POLLING && 1599 !(ifp->if_capenable & IFCAP_POLLING)) { 1600 error = ether_poll_register(vr_poll, ifp); 1601 if (error) 1602 return(error); 1603 VR_LOCK(sc); 1604 /* Disable interrupts */ 1605 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1606 ifp->if_capenable |= IFCAP_POLLING; 1607 VR_UNLOCK(sc); 1608 return (error); 1609 1610 } 1611 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1612 ifp->if_capenable & IFCAP_POLLING) { 1613 error = ether_poll_deregister(ifp); 1614 /* Enable interrupts. */ 1615 VR_LOCK(sc); 1616 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1617 ifp->if_capenable &= ~IFCAP_POLLING; 1618 VR_UNLOCK(sc); 1619 return (error); 1620 } 1621#endif /* DEVICE_POLLING */ 1622 break; 1623 default: 1624 error = ether_ioctl(ifp, command, data); 1625 break; 1626 } 1627 1628 return (error); 1629} 1630 1631static void 1632vr_watchdog(struct ifnet *ifp) 1633{ 1634 struct vr_softc *sc = ifp->if_softc; 1635 1636 VR_LOCK(sc); 1637 1638 ifp->if_oerrors++; 1639 if_printf(ifp, "watchdog timeout\n"); 1640 1641 vr_stop(sc); 1642 vr_reset(sc); 1643 vr_init_locked(sc); 1644 1645 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1646 vr_start_locked(ifp); 1647 1648 VR_UNLOCK(sc); 1649} 1650 1651/* 1652 * Stop the adapter and free any mbufs allocated to the 1653 * RX and TX lists. 1654 */ 1655static void 1656vr_stop(struct vr_softc *sc) 1657{ 1658 register int i; 1659 struct ifnet *ifp; 1660 1661 VR_LOCK_ASSERT(sc); 1662 1663 ifp = sc->vr_ifp; 1664 ifp->if_timer = 0; 1665 1666 callout_stop(&sc->vr_stat_callout); 1667 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1668 1669 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1670 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1671 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1672 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1673 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1674 1675 /* 1676 * Free data in the RX lists. 1677 */ 1678 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1679 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1680 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1681 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1682 } 1683 } 1684 bzero((char *)&sc->vr_ldata->vr_rx_list, 1685 sizeof(sc->vr_ldata->vr_rx_list)); 1686 1687 /* 1688 * Free the TX list buffers. 1689 */ 1690 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1691 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1692 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1693 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1694 } 1695 } 1696 bzero((char *)&sc->vr_ldata->vr_tx_list, 1697 sizeof(sc->vr_ldata->vr_tx_list)); 1698} 1699 1700/* 1701 * Stop all chip I/O so that the kernel's probe routines don't 1702 * get confused by errant DMAs when rebooting. 1703 */ 1704static void 1705vr_shutdown(device_t dev) 1706{ 1707 1708 vr_detach(dev); 1709} 1710