if_vr.c revision 129878
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 129878 2004-05-30 20:00:41Z phk $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include <sys/param.h> 63#include <sys/systm.h> 64#include <sys/sockio.h> 65#include <sys/mbuf.h> 66#include <sys/malloc.h> 67#include <sys/kernel.h> 68#include <sys/module.h> 69#include <sys/socket.h> 70 71#include <net/if.h> 72#include <net/if_arp.h> 73#include <net/ethernet.h> 74#include <net/if_dl.h> 75#include <net/if_media.h> 76 77#include <net/bpf.h> 78 79#include <vm/vm.h> /* for vtophys */ 80#include <vm/pmap.h> /* for vtophys */ 81#include <machine/bus_pio.h> 82#include <machine/bus_memio.h> 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <dev/pci/pcireg.h> 92#include <dev/pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, pci, 1, 1, 1); 99MODULE_DEPEND(vr, ether, 1, 1, 1); 100MODULE_DEPEND(vr, miibus, 1, 1, 1); 101 102/* "controller miibus0" required. See GENERIC if you get errors here. */ 103#include "miibus_if.h" 104 105#undef VR_USESWSHIFT 106 107/* 108 * Various supported device vendors/types and their names. 109 */ 110static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 118 "VIA VT6105 Rhine III 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 120 "VIA VT6105M Rhine III 10/100BaseTX" }, 121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 122 "Delta Electronics Rhine II 10/100BaseTX" }, 123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 124 "Addtron Technology Rhine II 10/100BaseTX" }, 125 { 0, 0, NULL } 126}; 127 128static int vr_probe (device_t); 129static int vr_attach (device_t); 130static int vr_detach (device_t); 131 132static int vr_newbuf (struct vr_softc *, 133 struct vr_chain_onefrag *, 134 struct mbuf *); 135static int vr_encap (struct vr_softc *, struct vr_chain *, 136 struct mbuf * ); 137 138static void vr_rxeof (struct vr_softc *); 139static void vr_rxeoc (struct vr_softc *); 140static void vr_txeof (struct vr_softc *); 141static void vr_tick (void *); 142static void vr_intr (void *); 143static void vr_start (struct ifnet *); 144static int vr_ioctl (struct ifnet *, u_long, caddr_t); 145static void vr_init (void *); 146static void vr_stop (struct vr_softc *); 147static void vr_watchdog (struct ifnet *); 148static void vr_shutdown (device_t); 149static int vr_ifmedia_upd (struct ifnet *); 150static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152#ifdef VR_USESWSHIFT 153static void vr_mii_sync (struct vr_softc *); 154static void vr_mii_send (struct vr_softc *, u_int32_t, int); 155#endif 156static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 157static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 158static int vr_miibus_readreg (device_t, int, int); 159static int vr_miibus_writereg (device_t, int, int, int); 160static void vr_miibus_statchg (device_t); 161 162static void vr_setcfg (struct vr_softc *, int); 163static uint32_t vr_mchash (const uint8_t *); 164static void vr_setmulti (struct vr_softc *); 165static void vr_reset (struct vr_softc *); 166static int vr_list_rx_init (struct vr_softc *); 167static int vr_list_tx_init (struct vr_softc *); 168 169#ifdef VR_USEIOSPACE 170#define VR_RES SYS_RES_IOPORT 171#define VR_RID VR_PCI_LOIO 172#else 173#define VR_RES SYS_RES_MEMORY 174#define VR_RID VR_PCI_LOMEM 175#endif 176 177static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200}; 201 202static devclass_t vr_devclass; 203 204DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 205DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207#define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | (x)) 210 211#define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~(x)) 214 215#define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | (x)) 218 219#define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~(x)) 222 223#define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227#define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231#define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | (x)) 234 235#define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 238 239#ifdef VR_USESWSHIFT 240/* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243static void 244vr_mii_sync(sc) 245 struct vr_softc *sc; 246{ 247 register int i; 248 249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 250 251 for (i = 0; i < 32; i++) { 252 SIO_SET(VR_MIICMD_CLK); 253 DELAY(1); 254 SIO_CLR(VR_MIICMD_CLK); 255 DELAY(1); 256 } 257 258 return; 259} 260 261/* 262 * Clock a series of bits through the MII. 263 */ 264static void 265vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269{ 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285} 286#endif 287 288/* 289 * Read an PHY register through the MII. 290 */ 291static int 292vr_mii_readreg(sc, frame) 293 struct vr_softc *sc; 294 struct vr_mii_frame *frame; 295 296#ifdef VR_USESWSHIFT 297{ 298 int i, ack; 299 300 VR_LOCK(sc); 301 302 /* 303 * Set up frame for RX. 304 */ 305 frame->mii_stdelim = VR_MII_STARTDELIM; 306 frame->mii_opcode = VR_MII_READOP; 307 frame->mii_turnaround = 0; 308 frame->mii_data = 0; 309 310 CSR_WRITE_1(sc, VR_MIICMD, 0); 311 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 312 313 /* 314 * Turn on data xmit. 315 */ 316 SIO_SET(VR_MIICMD_DIR); 317 318 vr_mii_sync(sc); 319 320 /* 321 * Send command/address info. 322 */ 323 vr_mii_send(sc, frame->mii_stdelim, 2); 324 vr_mii_send(sc, frame->mii_opcode, 2); 325 vr_mii_send(sc, frame->mii_phyaddr, 5); 326 vr_mii_send(sc, frame->mii_regaddr, 5); 327 328 /* Idle bit */ 329 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 330 DELAY(1); 331 SIO_SET(VR_MIICMD_CLK); 332 DELAY(1); 333 334 /* Turn off xmit. */ 335 SIO_CLR(VR_MIICMD_DIR); 336 337 /* Check for ack */ 338 SIO_CLR(VR_MIICMD_CLK); 339 DELAY(1); 340 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 344 /* 345 * Now try reading data bits. If the ack failed, we still 346 * need to clock through 16 cycles to keep the PHY(s) in sync. 347 */ 348 if (ack) { 349 for(i = 0; i < 16; i++) { 350 SIO_CLR(VR_MIICMD_CLK); 351 DELAY(1); 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 goto fail; 356 } 357 358 for (i = 0x8000; i; i >>= 1) { 359 SIO_CLR(VR_MIICMD_CLK); 360 DELAY(1); 361 if (!ack) { 362 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 363 frame->mii_data |= i; 364 DELAY(1); 365 } 366 SIO_SET(VR_MIICMD_CLK); 367 DELAY(1); 368 } 369 370fail: 371 372 SIO_CLR(VR_MIICMD_CLK); 373 DELAY(1); 374 SIO_SET(VR_MIICMD_CLK); 375 DELAY(1); 376 377 VR_UNLOCK(sc); 378 379 if (ack) 380 return(1); 381 return(0); 382} 383#else 384{ 385 int s, i; 386 387 s = splimp(); 388 389 /* Set the PHY-adress */ 390 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 391 frame->mii_phyaddr); 392 393 /* Set the register-adress */ 394 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 395 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 396 397 for (i = 0; i < 10000; i++) { 398 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 399 break; 400 DELAY(1); 401 } 402 403 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 404 405 (void)splx(s); 406 407 return(0); 408} 409#endif 410 411 412/* 413 * Write to a PHY register through the MII. 414 */ 415static int 416vr_mii_writereg(sc, frame) 417 struct vr_softc *sc; 418 struct vr_mii_frame *frame; 419 420#ifdef VR_USESWSHIFT 421{ 422 VR_LOCK(sc); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 VR_UNLOCK(sc); 461 462 return(0); 463} 464#else 465{ 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489} 490#endif 491 492static int 493vr_miibus_readreg(dev, phy, reg) 494 device_t dev; 495 int phy, reg; 496{ 497 struct vr_softc *sc; 498 struct vr_mii_frame frame; 499 500 sc = device_get_softc(dev); 501 502 switch (sc->vr_revid) { 503 case REV_ID_VT6102_APOLLO: 504 if (phy != 1) 505 return 0; 506 default: 507 break; 508 } 509 510 bzero((char *)&frame, sizeof(frame)); 511 512 frame.mii_phyaddr = phy; 513 frame.mii_regaddr = reg; 514 vr_mii_readreg(sc, &frame); 515 516 return(frame.mii_data); 517} 518 519static int 520vr_miibus_writereg(dev, phy, reg, data) 521 device_t dev; 522 u_int16_t phy, reg, data; 523{ 524 struct vr_softc *sc; 525 struct vr_mii_frame frame; 526 527 sc = device_get_softc(dev); 528 529 switch (sc->vr_revid) { 530 case REV_ID_VT6102_APOLLO: 531 if (phy != 1) 532 return 0; 533 default: 534 break; 535 } 536 537 bzero((char *)&frame, sizeof(frame)); 538 539 frame.mii_phyaddr = phy; 540 frame.mii_regaddr = reg; 541 frame.mii_data = data; 542 543 vr_mii_writereg(sc, &frame); 544 545 return(0); 546} 547 548static void 549vr_miibus_statchg(dev) 550 device_t dev; 551{ 552 struct vr_softc *sc; 553 struct mii_data *mii; 554 555 sc = device_get_softc(dev); 556 VR_LOCK(sc); 557 mii = device_get_softc(sc->vr_miibus); 558 vr_setcfg(sc, mii->mii_media_active); 559 VR_UNLOCK(sc); 560 561 return; 562} 563 564/* 565 * Calculate CRC of a multicast group address, return the lower 6 bits. 566 */ 567static u_int32_t 568vr_mchash(addr) 569 const uint8_t *addr; 570{ 571 uint32_t crc, carry; 572 int idx, bit; 573 uint8_t data; 574 575 /* Compute CRC for the address value. */ 576 crc = 0xFFFFFFFF; /* initial value */ 577 578 for (idx = 0; idx < 6; idx++) { 579 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 580 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 581 crc <<= 1; 582 if (carry) 583 crc = (crc ^ 0x04c11db6) | carry; 584 } 585 } 586 587 /* return the filter bit position */ 588 return((crc >> 26) & 0x0000003F); 589} 590 591/* 592 * Program the 64-bit multicast hash filter. 593 */ 594static void 595vr_setmulti(sc) 596 struct vr_softc *sc; 597{ 598 struct ifnet *ifp; 599 int h = 0; 600 u_int32_t hashes[2] = { 0, 0 }; 601 struct ifmultiaddr *ifma; 602 u_int8_t rxfilt; 603 int mcnt = 0; 604 605 ifp = &sc->arpcom.ac_if; 606 607 rxfilt = CSR_READ_1(sc, VR_RXCFG); 608 609 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 610 rxfilt |= VR_RXCFG_RX_MULTI; 611 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 612 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 613 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 614 return; 615 } 616 617 /* first, zot all the existing hash bits */ 618 CSR_WRITE_4(sc, VR_MAR0, 0); 619 CSR_WRITE_4(sc, VR_MAR1, 0); 620 621 /* now program new ones */ 622 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 623 if (ifma->ifma_addr->sa_family != AF_LINK) 624 continue; 625 h = vr_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 626 if (h < 32) 627 hashes[0] |= (1 << h); 628 else 629 hashes[1] |= (1 << (h - 32)); 630 mcnt++; 631 } 632 633 if (mcnt) 634 rxfilt |= VR_RXCFG_RX_MULTI; 635 else 636 rxfilt &= ~VR_RXCFG_RX_MULTI; 637 638 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 639 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 640 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 641 642 return; 643} 644 645/* 646 * In order to fiddle with the 647 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 648 * first have to put the transmit and/or receive logic in the idle state. 649 */ 650static void 651vr_setcfg(sc, media) 652 struct vr_softc *sc; 653 int media; 654{ 655 int restart = 0; 656 657 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 658 restart = 1; 659 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 660 } 661 662 if ((media & IFM_GMASK) == IFM_FDX) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 664 else 665 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 667 if (restart) 668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 669 670 return; 671} 672 673static void 674vr_reset(sc) 675 struct vr_softc *sc; 676{ 677 register int i; 678 679 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 680 681 for (i = 0; i < VR_TIMEOUT; i++) { 682 DELAY(10); 683 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 684 break; 685 } 686 if (i == VR_TIMEOUT) { 687 if (sc->vr_revid < REV_ID_VT3065_A) 688 printf("vr%d: reset never completed!\n", sc->vr_unit); 689 else { 690 /* Use newer force reset command */ 691 printf("vr%d: Using force reset command.\n", sc->vr_unit); 692 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 693 } 694 } 695 696 /* Wait a little while for the chip to get its brains in order. */ 697 DELAY(1000); 698 699 return; 700} 701 702/* 703 * Probe for a VIA Rhine chip. Check the PCI vendor and device 704 * IDs against our list and return a device name if we find a match. 705 */ 706static int 707vr_probe(dev) 708 device_t dev; 709{ 710 struct vr_type *t; 711 712 t = vr_devs; 713 714 while(t->vr_name != NULL) { 715 if ((pci_get_vendor(dev) == t->vr_vid) && 716 (pci_get_device(dev) == t->vr_did)) { 717 device_set_desc(dev, t->vr_name); 718 return(0); 719 } 720 t++; 721 } 722 723 return(ENXIO); 724} 725 726/* 727 * Attach the interface. Allocate softc structures, do ifmedia 728 * setup and ethernet/BPF attach. 729 */ 730static int 731vr_attach(dev) 732 device_t dev; 733{ 734 int i; 735 u_char eaddr[ETHER_ADDR_LEN]; 736 struct vr_softc *sc; 737 struct ifnet *ifp; 738 int unit, error = 0, rid; 739 740 sc = device_get_softc(dev); 741 unit = device_get_unit(dev); 742 743 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 744 MTX_DEF | MTX_RECURSE); 745#ifndef BURN_BRIDGES 746 /* 747 * Handle power management nonsense. 748 */ 749 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 750 u_int32_t iobase, membase, irq; 751 752 /* Save important PCI config data. */ 753 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 754 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 755 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 756 757 /* Reset the power state. */ 758 printf("vr%d: chip is in D%d power mode " 759 "-- setting to D0\n", unit, 760 pci_get_powerstate(dev)); 761 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 762 763 /* Restore PCI config data. */ 764 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 765 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 766 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 767 } 768#endif 769 /* 770 * Map control/status registers. 771 */ 772 pci_enable_busmaster(dev); 773 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 774 775 rid = VR_RID; 776 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 777 778 if (sc->vr_res == NULL) { 779 printf("vr%d: couldn't map ports/memory\n", unit); 780 error = ENXIO; 781 goto fail; 782 } 783 784 sc->vr_btag = rman_get_bustag(sc->vr_res); 785 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 786 787 /* Allocate interrupt */ 788 rid = 0; 789 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 790 RF_SHAREABLE | RF_ACTIVE); 791 792 if (sc->vr_irq == NULL) { 793 printf("vr%d: couldn't map interrupt\n", unit); 794 error = ENXIO; 795 goto fail; 796 } 797 798 /* 799 * Windows may put the chip in suspend mode when it 800 * shuts down. Be sure to kick it in the head to wake it 801 * up again. 802 */ 803 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 804 805 /* Reset the adapter. */ 806 vr_reset(sc); 807 808 /* 809 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 810 * initialization and disable AUTOPOLL. 811 */ 812 pci_write_config(dev, VR_PCI_MODE, 813 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 814 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 815 816 /* 817 * Get station address. The way the Rhine chips work, 818 * you're not allowed to directly access the EEPROM once 819 * they've been programmed a special way. Consequently, 820 * we need to read the node address from the PAR0 and PAR1 821 * registers. 822 */ 823 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 824 DELAY(200); 825 for (i = 0; i < ETHER_ADDR_LEN; i++) 826 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 827 828 sc->vr_unit = unit; 829 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 830 831 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 832 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 833 834 if (sc->vr_ldata == NULL) { 835 printf("vr%d: no memory for list buffers!\n", unit); 836 error = ENXIO; 837 goto fail; 838 } 839 840 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 841 842 ifp = &sc->arpcom.ac_if; 843 ifp->if_softc = sc; 844 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 845 ifp->if_mtu = ETHERMTU; 846 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 847 ifp->if_ioctl = vr_ioctl; 848 ifp->if_start = vr_start; 849 ifp->if_watchdog = vr_watchdog; 850 ifp->if_init = vr_init; 851 ifp->if_baudrate = 10000000; 852 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 853#ifdef DEVICE_POLLING 854 ifp->if_capabilities |= IFCAP_POLLING; 855#endif 856 ifp->if_capenable = ifp->if_capabilities; 857 858 /* 859 * Do MII setup. 860 */ 861 if (mii_phy_probe(dev, &sc->vr_miibus, 862 vr_ifmedia_upd, vr_ifmedia_sts)) { 863 printf("vr%d: MII without any phy!\n", sc->vr_unit); 864 error = ENXIO; 865 goto fail; 866 } 867 868 callout_handle_init(&sc->vr_stat_ch); 869 870 /* 871 * Call MI attach routine. 872 */ 873 ether_ifattach(ifp, eaddr); 874 875 /* Hook interrupt last to avoid having to lock softc */ 876 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 877 vr_intr, sc, &sc->vr_intrhand); 878 879 if (error) { 880 printf("vr%d: couldn't set up irq\n", unit); 881 ether_ifdetach(ifp); 882 goto fail; 883 } 884 885fail: 886 if (error) 887 vr_detach(dev); 888 889 return(error); 890} 891 892/* 893 * Shutdown hardware and free up resources. This can be called any 894 * time after the mutex has been initialized. It is called in both 895 * the error case in attach and the normal detach case so it needs 896 * to be careful about only freeing resources that have actually been 897 * allocated. 898 */ 899static int 900vr_detach(dev) 901 device_t dev; 902{ 903 struct vr_softc *sc; 904 struct ifnet *ifp; 905 906 sc = device_get_softc(dev); 907 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 908 VR_LOCK(sc); 909 ifp = &sc->arpcom.ac_if; 910 911 /* These should only be active if attach succeeded */ 912 if (device_is_attached(dev)) { 913 vr_stop(sc); 914 ether_ifdetach(ifp); 915 } 916 if (sc->vr_miibus) 917 device_delete_child(dev, sc->vr_miibus); 918 bus_generic_detach(dev); 919 920 if (sc->vr_intrhand) 921 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 922 if (sc->vr_irq) 923 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 924 if (sc->vr_res) 925 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 926 927 if (sc->vr_ldata) 928 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 929 930 VR_UNLOCK(sc); 931 mtx_destroy(&sc->vr_mtx); 932 933 return(0); 934} 935 936/* 937 * Initialize the transmit descriptors. 938 */ 939static int 940vr_list_tx_init(sc) 941 struct vr_softc *sc; 942{ 943 struct vr_chain_data *cd; 944 struct vr_list_data *ld; 945 int i; 946 947 cd = &sc->vr_cdata; 948 ld = sc->vr_ldata; 949 for (i = 0; i < VR_TX_LIST_CNT; i++) { 950 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 951 if (i == (VR_TX_LIST_CNT - 1)) 952 cd->vr_tx_chain[i].vr_nextdesc = 953 &cd->vr_tx_chain[0]; 954 else 955 cd->vr_tx_chain[i].vr_nextdesc = 956 &cd->vr_tx_chain[i + 1]; 957 } 958 959 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 960 961 return(0); 962} 963 964 965/* 966 * Initialize the RX descriptors and allocate mbufs for them. Note that 967 * we arrange the descriptors in a closed ring, so that the last descriptor 968 * points back to the first. 969 */ 970static int 971vr_list_rx_init(sc) 972 struct vr_softc *sc; 973{ 974 struct vr_chain_data *cd; 975 struct vr_list_data *ld; 976 int i; 977 978 cd = &sc->vr_cdata; 979 ld = sc->vr_ldata; 980 981 for (i = 0; i < VR_RX_LIST_CNT; i++) { 982 cd->vr_rx_chain[i].vr_ptr = 983 (struct vr_desc *)&ld->vr_rx_list[i]; 984 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 985 return(ENOBUFS); 986 if (i == (VR_RX_LIST_CNT - 1)) { 987 cd->vr_rx_chain[i].vr_nextdesc = 988 &cd->vr_rx_chain[0]; 989 ld->vr_rx_list[i].vr_next = 990 vtophys(&ld->vr_rx_list[0]); 991 } else { 992 cd->vr_rx_chain[i].vr_nextdesc = 993 &cd->vr_rx_chain[i + 1]; 994 ld->vr_rx_list[i].vr_next = 995 vtophys(&ld->vr_rx_list[i + 1]); 996 } 997 } 998 999 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1000 1001 return(0); 1002} 1003 1004/* 1005 * Initialize an RX descriptor and attach an MBUF cluster. 1006 * Note: the length fields are only 11 bits wide, which means the 1007 * largest size we can specify is 2047. This is important because 1008 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1009 * overflow the field and make a mess. 1010 */ 1011static int 1012vr_newbuf(sc, c, m) 1013 struct vr_softc *sc; 1014 struct vr_chain_onefrag *c; 1015 struct mbuf *m; 1016{ 1017 struct mbuf *m_new = NULL; 1018 1019 if (m == NULL) { 1020 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1021 if (m_new == NULL) 1022 return(ENOBUFS); 1023 1024 MCLGET(m_new, M_DONTWAIT); 1025 if (!(m_new->m_flags & M_EXT)) { 1026 m_freem(m_new); 1027 return(ENOBUFS); 1028 } 1029 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1030 } else { 1031 m_new = m; 1032 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1033 m_new->m_data = m_new->m_ext.ext_buf; 1034 } 1035 1036 m_adj(m_new, sizeof(u_int64_t)); 1037 1038 c->vr_mbuf = m_new; 1039 c->vr_ptr->vr_status = VR_RXSTAT; 1040 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1041 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1042 1043 return(0); 1044} 1045 1046/* 1047 * A frame has been uploaded: pass the resulting mbuf chain up to 1048 * the higher level protocols. 1049 */ 1050static void 1051vr_rxeof(sc) 1052 struct vr_softc *sc; 1053{ 1054 struct mbuf *m, *m0; 1055 struct ifnet *ifp; 1056 struct vr_chain_onefrag *cur_rx; 1057 int total_len = 0; 1058 u_int32_t rxstat; 1059 1060 VR_LOCK_ASSERT(sc); 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1065 VR_RXSTAT_OWN)) { 1066#ifdef DEVICE_POLLING 1067 if (ifp->if_flags & IFF_POLLING) { 1068 if (sc->rxcycles <= 0) 1069 break; 1070 sc->rxcycles--; 1071 } 1072#endif /* DEVICE_POLLING */ 1073 m0 = NULL; 1074 cur_rx = sc->vr_cdata.vr_rx_head; 1075 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1076 m = cur_rx->vr_mbuf; 1077 1078 /* 1079 * If an error occurs, update stats, clear the 1080 * status word and leave the mbuf cluster in place: 1081 * it should simply get re-used next time this descriptor 1082 * comes up in the ring. 1083 */ 1084 if (rxstat & VR_RXSTAT_RXERR) { 1085 ifp->if_ierrors++; 1086 printf("vr%d: rx error (%02x):", 1087 sc->vr_unit, rxstat & 0x000000ff); 1088 if (rxstat & VR_RXSTAT_CRCERR) 1089 printf(" crc error"); 1090 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1091 printf(" frame alignment error\n"); 1092 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1093 printf(" FIFO overflow"); 1094 if (rxstat & VR_RXSTAT_GIANT) 1095 printf(" received giant packet"); 1096 if (rxstat & VR_RXSTAT_RUNT) 1097 printf(" received runt packet"); 1098 if (rxstat & VR_RXSTAT_BUSERR) 1099 printf(" system bus error"); 1100 if (rxstat & VR_RXSTAT_BUFFERR) 1101 printf("rx buffer error"); 1102 printf("\n"); 1103 vr_newbuf(sc, cur_rx, m); 1104 continue; 1105 } 1106 1107 /* No errors; receive the packet. */ 1108 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1109 1110 /* 1111 * XXX The VIA Rhine chip includes the CRC with every 1112 * received frame, and there's no way to turn this 1113 * behavior off (at least, I can't find anything in 1114 * the manual that explains how to do it) so we have 1115 * to trim off the CRC manually. 1116 */ 1117 total_len -= ETHER_CRC_LEN; 1118 1119 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1120 NULL); 1121 vr_newbuf(sc, cur_rx, m); 1122 if (m0 == NULL) { 1123 ifp->if_ierrors++; 1124 continue; 1125 } 1126 m = m0; 1127 1128 ifp->if_ipackets++; 1129 VR_UNLOCK(sc); 1130 (*ifp->if_input)(ifp, m); 1131 VR_LOCK(sc); 1132 } 1133 1134 return; 1135} 1136 1137static void 1138vr_rxeoc(sc) 1139 struct vr_softc *sc; 1140{ 1141 struct ifnet *ifp; 1142 int i; 1143 1144 ifp = &sc->arpcom.ac_if; 1145 1146 ifp->if_ierrors++; 1147 1148 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1149 DELAY(10000); 1150 1151 for (i = 0x400; 1152 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1153 i--) 1154 ; /* Wait for receiver to stop */ 1155 1156 if (!i) { 1157 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1158 sc->vr_flags |= VR_F_RESTART; 1159 return; 1160 } 1161 1162 vr_rxeof(sc); 1163 1164 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1165 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1166 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1167 1168 return; 1169} 1170 1171/* 1172 * A frame was downloaded to the chip. It's safe for us to clean up 1173 * the list buffers. 1174 */ 1175 1176static void 1177vr_txeof(sc) 1178 struct vr_softc *sc; 1179{ 1180 struct vr_chain *cur_tx; 1181 struct ifnet *ifp; 1182 1183 ifp = &sc->arpcom.ac_if; 1184 1185 /* 1186 * Go through our tx list and free mbufs for those 1187 * frames that have been transmitted. 1188 */ 1189 cur_tx = sc->vr_cdata.vr_tx_cons; 1190 while (cur_tx->vr_mbuf != NULL) { 1191 u_int32_t txstat; 1192 int i; 1193 1194 txstat = cur_tx->vr_ptr->vr_status; 1195 1196 if ((txstat & VR_TXSTAT_ABRT) || 1197 (txstat & VR_TXSTAT_UDF)) { 1198 for (i = 0x400; 1199 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1200 i--) 1201 ; /* Wait for chip to shutdown */ 1202 if (!i) { 1203 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1204 sc->vr_flags |= VR_F_RESTART; 1205 break; 1206 } 1207 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1208 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1209 break; 1210 } 1211 1212 if (txstat & VR_TXSTAT_OWN) 1213 break; 1214 1215 if (txstat & VR_TXSTAT_ERRSUM) { 1216 ifp->if_oerrors++; 1217 if (txstat & VR_TXSTAT_DEFER) 1218 ifp->if_collisions++; 1219 if (txstat & VR_TXSTAT_LATECOLL) 1220 ifp->if_collisions++; 1221 } 1222 1223 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1224 1225 ifp->if_opackets++; 1226 m_freem(cur_tx->vr_mbuf); 1227 cur_tx->vr_mbuf = NULL; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 1230 cur_tx = cur_tx->vr_nextdesc; 1231 } 1232 sc->vr_cdata.vr_tx_cons = cur_tx; 1233 if (cur_tx->vr_mbuf == NULL) 1234 ifp->if_timer = 0; 1235} 1236 1237static void 1238vr_tick(xsc) 1239 void *xsc; 1240{ 1241 struct vr_softc *sc; 1242 struct mii_data *mii; 1243 1244 sc = xsc; 1245 VR_LOCK(sc); 1246 if (sc->vr_flags & VR_F_RESTART) { 1247 printf("vr%d: restarting\n", sc->vr_unit); 1248 vr_stop(sc); 1249 vr_reset(sc); 1250 vr_init(sc); 1251 sc->vr_flags &= ~VR_F_RESTART; 1252 } 1253 1254 mii = device_get_softc(sc->vr_miibus); 1255 mii_tick(mii); 1256 1257 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1258 1259 VR_UNLOCK(sc); 1260 1261 return; 1262} 1263 1264#ifdef DEVICE_POLLING 1265static poll_handler_t vr_poll; 1266 1267static void 1268vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1269{ 1270 struct vr_softc *sc = ifp->if_softc; 1271 1272 VR_LOCK(sc); 1273 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1274 ether_poll_deregister(ifp); 1275 cmd = POLL_DEREGISTER; 1276 } 1277 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1278 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1279 goto done; 1280 } 1281 1282 sc->rxcycles = count; 1283 vr_rxeof(sc); 1284 vr_txeof(sc); 1285 if (ifp->if_snd.ifq_head != NULL) 1286 vr_start(ifp); 1287 1288 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1289 u_int16_t status; 1290 1291 status = CSR_READ_2(sc, VR_ISR); 1292 if (status) 1293 CSR_WRITE_2(sc, VR_ISR, status); 1294 1295 if ((status & VR_INTRS) == 0) 1296 goto done; 1297 1298 if (status & VR_ISR_RX_DROPPED) { 1299 printf("vr%d: rx packet lost\n", sc->vr_unit); 1300 ifp->if_ierrors++; 1301 } 1302 1303 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1304 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1305 printf("vr%d: receive error (%04x)", 1306 sc->vr_unit, status); 1307 if (status & VR_ISR_RX_NOBUF) 1308 printf(" no buffers"); 1309 if (status & VR_ISR_RX_OFLOW) 1310 printf(" overflow"); 1311 if (status & VR_ISR_RX_DROPPED) 1312 printf(" packet lost"); 1313 printf("\n"); 1314 vr_rxeoc(sc); 1315 } 1316 1317 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1318 vr_reset(sc); 1319 vr_init(sc); 1320 goto done; 1321 } 1322 1323 if ((status & VR_ISR_UDFI) || 1324 (status & VR_ISR_TX_ABRT2) || 1325 (status & VR_ISR_TX_ABRT)) { 1326 ifp->if_oerrors++; 1327 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1328 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1329 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1330 } 1331 } 1332 } 1333 1334done: 1335 VR_UNLOCK(sc); 1336 1337} 1338#endif /* DEVICE_POLLING */ 1339 1340static void 1341vr_intr(arg) 1342 void *arg; 1343{ 1344 struct vr_softc *sc; 1345 struct ifnet *ifp; 1346 u_int16_t status; 1347 1348 sc = arg; 1349 VR_LOCK(sc); 1350 ifp = &sc->arpcom.ac_if; 1351 1352#ifdef DEVICE_POLLING 1353 if (ifp->if_flags & IFF_POLLING) 1354 goto done; 1355 if ((ifp->if_capenable & IFCAP_POLLING) && 1356 ether_poll_register(vr_poll, ifp)) { /* ok, disable interrupts */ 1357 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1358 vr_poll(ifp, 0, 1); 1359 goto done; 1360 } 1361#endif /* DEVICE_POLLING */ 1362 1363 /* Supress unwanted interrupts. */ 1364 if (!(ifp->if_flags & IFF_UP)) { 1365 vr_stop(sc); 1366 VR_UNLOCK(sc); 1367 return; 1368 } 1369 1370 /* Disable interrupts. */ 1371 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1372 1373 for (;;) { 1374 1375 status = CSR_READ_2(sc, VR_ISR); 1376 if (status) 1377 CSR_WRITE_2(sc, VR_ISR, status); 1378 1379 if ((status & VR_INTRS) == 0) 1380 break; 1381 1382 if (status & VR_ISR_RX_OK) 1383 vr_rxeof(sc); 1384 1385 if (status & VR_ISR_RX_DROPPED) { 1386 printf("vr%d: rx packet lost\n", sc->vr_unit); 1387 ifp->if_ierrors++; 1388 } 1389 1390 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1391 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1392 printf("vr%d: receive error (%04x)", 1393 sc->vr_unit, status); 1394 if (status & VR_ISR_RX_NOBUF) 1395 printf(" no buffers"); 1396 if (status & VR_ISR_RX_OFLOW) 1397 printf(" overflow"); 1398 if (status & VR_ISR_RX_DROPPED) 1399 printf(" packet lost"); 1400 printf("\n"); 1401 vr_rxeoc(sc); 1402 } 1403 1404 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1405 vr_reset(sc); 1406 vr_init(sc); 1407 break; 1408 } 1409 1410 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1411 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1412 vr_txeof(sc); 1413 if ((status & VR_ISR_UDFI) || 1414 (status & VR_ISR_TX_ABRT2) || 1415 (status & VR_ISR_TX_ABRT)) { 1416 ifp->if_oerrors++; 1417 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1418 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1419 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1420 } 1421 } 1422 } 1423 1424 } 1425 1426 /* Re-enable interrupts. */ 1427 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1428 1429 if (ifp->if_snd.ifq_head != NULL) { 1430 vr_start(ifp); 1431 } 1432 1433#ifdef DEVICE_POLLING 1434done: 1435#endif /* DEVICE_POLLING */ 1436 VR_UNLOCK(sc); 1437 1438 return; 1439} 1440 1441/* 1442 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1443 * pointers to the fragment pointers. 1444 */ 1445static int 1446vr_encap(sc, c, m_head) 1447 struct vr_softc *sc; 1448 struct vr_chain *c; 1449 struct mbuf *m_head; 1450{ 1451 struct vr_desc *f = NULL; 1452 struct mbuf *m; 1453 1454 /* 1455 * The VIA Rhine wants packet buffers to be longword 1456 * aligned, but very often our mbufs aren't. Rather than 1457 * waste time trying to decide when to copy and when not 1458 * to copy, just do it all the time. 1459 */ 1460 m = m_defrag(m_head, M_DONTWAIT); 1461 if (m == NULL) { 1462 return(1); 1463 } 1464 1465 /* 1466 * The Rhine chip doesn't auto-pad, so we have to make 1467 * sure to pad short frames out to the minimum frame length 1468 * ourselves. 1469 */ 1470 if (m->m_len < VR_MIN_FRAMELEN) { 1471 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1472 m->m_len = m->m_pkthdr.len; 1473 } 1474 1475 c->vr_mbuf = m; 1476 f = c->vr_ptr; 1477 f->vr_data = vtophys(mtod(m, caddr_t)); 1478 f->vr_ctl = m->m_len; 1479 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1480 f->vr_status = 0; 1481 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1482 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1483 1484 return(0); 1485} 1486 1487/* 1488 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1489 * to the mbuf data regions directly in the transmit lists. We also save a 1490 * copy of the pointers since the transmit list fragment pointers are 1491 * physical addresses. 1492 */ 1493 1494static void 1495vr_start(ifp) 1496 struct ifnet *ifp; 1497{ 1498 struct vr_softc *sc; 1499 struct mbuf *m_head; 1500 struct vr_chain *cur_tx; 1501 1502 if (ifp->if_flags & IFF_OACTIVE) 1503 return; 1504 1505 sc = ifp->if_softc; 1506 1507 VR_LOCK(sc); 1508 1509 cur_tx = sc->vr_cdata.vr_tx_prod; 1510 while (cur_tx->vr_mbuf == NULL) { 1511 IF_DEQUEUE(&ifp->if_snd, m_head); 1512 if (m_head == NULL) 1513 break; 1514 1515 /* Pack the data into the descriptor. */ 1516 if (vr_encap(sc, cur_tx, m_head)) { 1517 /* Rollback, send what we were able to encap. */ 1518 IF_PREPEND(&ifp->if_snd, m_head); 1519 break; 1520 } 1521 1522 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1523 1524 /* 1525 * If there's a BPF listener, bounce a copy of this frame 1526 * to him. 1527 */ 1528 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1529 1530 cur_tx = cur_tx->vr_nextdesc; 1531 } 1532 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1533 sc->vr_cdata.vr_tx_prod = cur_tx; 1534 1535 /* Tell the chip to start transmitting. */ 1536 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1537 1538 /* Set a timeout in case the chip goes out to lunch. */ 1539 ifp->if_timer = 5; 1540 1541 if (cur_tx->vr_mbuf != NULL) 1542 ifp->if_flags |= IFF_OACTIVE; 1543 } 1544 1545 VR_UNLOCK(sc); 1546 1547 return; 1548} 1549 1550static void 1551vr_init(xsc) 1552 void *xsc; 1553{ 1554 struct vr_softc *sc = xsc; 1555 struct ifnet *ifp = &sc->arpcom.ac_if; 1556 struct mii_data *mii; 1557 int i; 1558 1559 VR_LOCK(sc); 1560 1561 mii = device_get_softc(sc->vr_miibus); 1562 1563 /* 1564 * Cancel pending I/O and free all RX/TX buffers. 1565 */ 1566 vr_stop(sc); 1567 vr_reset(sc); 1568 1569 /* 1570 * Set our station address. 1571 */ 1572 for (i = 0; i < ETHER_ADDR_LEN; i++) 1573 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1574 1575 /* Set DMA size */ 1576 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1577 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1578 1579 /* 1580 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1581 * so we must set both. 1582 */ 1583 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1584 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1585 1586 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1587 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1588 1589 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1590 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1591 1592 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1593 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1594 1595 /* Init circular RX list. */ 1596 if (vr_list_rx_init(sc) == ENOBUFS) { 1597 printf("vr%d: initialization failed: no " 1598 "memory for rx buffers\n", sc->vr_unit); 1599 vr_stop(sc); 1600 VR_UNLOCK(sc); 1601 return; 1602 } 1603 1604 /* 1605 * Init tx descriptors. 1606 */ 1607 vr_list_tx_init(sc); 1608 1609 /* If we want promiscuous mode, set the allframes bit. */ 1610 if (ifp->if_flags & IFF_PROMISC) 1611 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1612 else 1613 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1614 1615 /* Set capture broadcast bit to capture broadcast frames. */ 1616 if (ifp->if_flags & IFF_BROADCAST) 1617 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1618 else 1619 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1620 1621 /* 1622 * Program the multicast filter, if necessary. 1623 */ 1624 vr_setmulti(sc); 1625 1626 /* 1627 * Load the address of the RX list. 1628 */ 1629 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1630 1631 /* Enable receiver and transmitter. */ 1632 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1633 VR_CMD_TX_ON|VR_CMD_RX_ON| 1634 VR_CMD_RX_GO); 1635 1636 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1637 1638 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1639#ifdef DEVICE_POLLING 1640 /* 1641 * Disable interrupts if we are polling. 1642 */ 1643 if (ifp->if_flags & IFF_POLLING) 1644 CSR_WRITE_2(sc, VR_IMR, 0); 1645 else 1646#endif /* DEVICE_POLLING */ 1647 /* 1648 * Enable interrupts. 1649 */ 1650 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1651 1652 mii_mediachg(mii); 1653 1654 ifp->if_flags |= IFF_RUNNING; 1655 ifp->if_flags &= ~IFF_OACTIVE; 1656 1657 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1658 1659 VR_UNLOCK(sc); 1660 1661 return; 1662} 1663 1664/* 1665 * Set media options. 1666 */ 1667static int 1668vr_ifmedia_upd(ifp) 1669 struct ifnet *ifp; 1670{ 1671 struct vr_softc *sc; 1672 1673 sc = ifp->if_softc; 1674 1675 if (ifp->if_flags & IFF_UP) 1676 vr_init(sc); 1677 1678 return(0); 1679} 1680 1681/* 1682 * Report current media status. 1683 */ 1684static void 1685vr_ifmedia_sts(ifp, ifmr) 1686 struct ifnet *ifp; 1687 struct ifmediareq *ifmr; 1688{ 1689 struct vr_softc *sc; 1690 struct mii_data *mii; 1691 1692 sc = ifp->if_softc; 1693 mii = device_get_softc(sc->vr_miibus); 1694 mii_pollstat(mii); 1695 ifmr->ifm_active = mii->mii_media_active; 1696 ifmr->ifm_status = mii->mii_media_status; 1697 1698 return; 1699} 1700 1701static int 1702vr_ioctl(ifp, command, data) 1703 struct ifnet *ifp; 1704 u_long command; 1705 caddr_t data; 1706{ 1707 struct vr_softc *sc = ifp->if_softc; 1708 struct ifreq *ifr = (struct ifreq *) data; 1709 struct mii_data *mii; 1710 int error = 0; 1711 1712 VR_LOCK(sc); 1713 1714 switch(command) { 1715 case SIOCSIFFLAGS: 1716 if (ifp->if_flags & IFF_UP) { 1717 vr_init(sc); 1718 } else { 1719 if (ifp->if_flags & IFF_RUNNING) 1720 vr_stop(sc); 1721 } 1722 error = 0; 1723 break; 1724 case SIOCADDMULTI: 1725 case SIOCDELMULTI: 1726 vr_setmulti(sc); 1727 error = 0; 1728 break; 1729 case SIOCGIFMEDIA: 1730 case SIOCSIFMEDIA: 1731 mii = device_get_softc(sc->vr_miibus); 1732 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1733 break; 1734 case SIOCSIFCAP: 1735 ifp->if_capenable = ifr->ifr_reqcap; 1736 break; 1737 default: 1738 error = ether_ioctl(ifp, command, data); 1739 break; 1740 } 1741 1742 VR_UNLOCK(sc); 1743 1744 return(error); 1745} 1746 1747static void 1748vr_watchdog(ifp) 1749 struct ifnet *ifp; 1750{ 1751 struct vr_softc *sc; 1752 1753 sc = ifp->if_softc; 1754 1755 VR_LOCK(sc); 1756 ifp->if_oerrors++; 1757 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1758 1759 vr_stop(sc); 1760 vr_reset(sc); 1761 vr_init(sc); 1762 1763 if (ifp->if_snd.ifq_head != NULL) 1764 vr_start(ifp); 1765 1766 VR_UNLOCK(sc); 1767 1768 return; 1769} 1770 1771/* 1772 * Stop the adapter and free any mbufs allocated to the 1773 * RX and TX lists. 1774 */ 1775static void 1776vr_stop(sc) 1777 struct vr_softc *sc; 1778{ 1779 register int i; 1780 struct ifnet *ifp; 1781 1782 VR_LOCK(sc); 1783 1784 ifp = &sc->arpcom.ac_if; 1785 ifp->if_timer = 0; 1786 1787 untimeout(vr_tick, sc, sc->vr_stat_ch); 1788 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1789#ifdef DEVICE_POLLING 1790 ether_poll_deregister(ifp); 1791#endif /* DEVICE_POLLING */ 1792 1793 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1794 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1795 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1796 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1797 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1798 1799 /* 1800 * Free data in the RX lists. 1801 */ 1802 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1803 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1804 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1805 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1806 } 1807 } 1808 bzero((char *)&sc->vr_ldata->vr_rx_list, 1809 sizeof(sc->vr_ldata->vr_rx_list)); 1810 1811 /* 1812 * Free the TX list buffers. 1813 */ 1814 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1815 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1816 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1817 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1818 } 1819 } 1820 1821 bzero((char *)&sc->vr_ldata->vr_tx_list, 1822 sizeof(sc->vr_ldata->vr_tx_list)); 1823 1824 VR_UNLOCK(sc); 1825 1826 return; 1827} 1828 1829/* 1830 * Stop all chip I/O so that the kernel's probe routines don't 1831 * get confused by errant DMAs when rebooting. 1832 */ 1833static void 1834vr_shutdown(dev) 1835 device_t dev; 1836{ 1837 struct vr_softc *sc; 1838 1839 sc = device_get_softc(dev); 1840 1841 vr_stop(sc); 1842 1843 return; 1844} 1845