nicvf_queues.c revision 296601
1/* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/vnic/nicvf_queues.c 296601 2016-03-10 05:23:46Z zbb $ 27 * 28 */ 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/vnic/nicvf_queues.c 296601 2016-03-10 05:23:46Z zbb $"); 31 32#include "opt_inet.h" 33#include "opt_inet6.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bitset.h> 38#include <sys/bitstring.h> 39#include <sys/buf_ring.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/kernel.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/pciio.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/sockio.h> 50#include <sys/socket.h> 51#include <sys/stdatomic.h> 52#include <sys/cpuset.h> 53#include <sys/lock.h> 54#include <sys/mutex.h> 55#include <sys/smp.h> 56#include <sys/taskqueue.h> 57 58#include <vm/vm.h> 59#include <vm/pmap.h> 60 61#include <machine/bus.h> 62#include <machine/vmparam.h> 63 64#include <net/ethernet.h> 65#include <net/if.h> 66#include <net/if_var.h> 67#include <net/if_media.h> 68#include <net/ifq.h> 69 70#include <netinet/in_systm.h> 71#include <netinet/in.h> 72#include <netinet/if_ether.h> 73#include <netinet/ip.h> 74#include <netinet/ip6.h> 75#include <netinet/sctp.h> 76#include <netinet/tcp.h> 77#include <netinet/tcp_lro.h> 78#include <netinet/udp.h> 79 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcivar.h> 82 83#include "thunder_bgx.h" 84#include "nic_reg.h" 85#include "nic.h" 86#include "q_struct.h" 87#include "nicvf_queues.h" 88 89#define DEBUG 90#undef DEBUG 91 92#ifdef DEBUG 93#define dprintf(dev, fmt, ...) device_printf(dev, fmt, ##__VA_ARGS__) 94#else 95#define dprintf(dev, fmt, ...) 96#endif 97 98MALLOC_DECLARE(M_NICVF); 99 100static void nicvf_free_snd_queue(struct nicvf *, struct snd_queue *); 101static struct mbuf * nicvf_get_rcv_mbuf(struct nicvf *, struct cqe_rx_t *); 102static void nicvf_sq_disable(struct nicvf *, int); 103static void nicvf_sq_enable(struct nicvf *, struct snd_queue *, int); 104static void nicvf_put_sq_desc(struct snd_queue *, int); 105static void nicvf_cmp_queue_config(struct nicvf *, struct queue_set *, int, 106 boolean_t); 107static void nicvf_sq_free_used_descs(struct nicvf *, struct snd_queue *, int); 108 109static void nicvf_rbdr_task(void *, int); 110static void nicvf_rbdr_task_nowait(void *, int); 111 112struct rbuf_info { 113 bus_dma_tag_t dmat; 114 bus_dmamap_t dmap; 115 struct mbuf * mbuf; 116}; 117 118#define GET_RBUF_INFO(x) ((struct rbuf_info *)((x) - NICVF_RCV_BUF_ALIGN_BYTES)) 119 120/* Poll a register for a specific value */ 121static int nicvf_poll_reg(struct nicvf *nic, int qidx, 122 uint64_t reg, int bit_pos, int bits, int val) 123{ 124 uint64_t bit_mask; 125 uint64_t reg_val; 126 int timeout = 10; 127 128 bit_mask = (1UL << bits) - 1; 129 bit_mask = (bit_mask << bit_pos); 130 131 while (timeout) { 132 reg_val = nicvf_queue_reg_read(nic, reg, qidx); 133 if (((reg_val & bit_mask) >> bit_pos) == val) 134 return (0); 135 136 DELAY(1000); 137 timeout--; 138 } 139 device_printf(nic->dev, "Poll on reg 0x%lx failed\n", reg); 140 return (ETIMEDOUT); 141} 142 143/* Callback for bus_dmamap_load() */ 144static void 145nicvf_dmamap_q_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 146{ 147 bus_addr_t *paddr; 148 149 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 150 paddr = arg; 151 *paddr = segs->ds_addr; 152} 153 154/* Allocate memory for a queue's descriptors */ 155static int 156nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem, 157 int q_len, int desc_size, int align_bytes) 158{ 159 int err, err_dmat; 160 161 /* Create DMA tag first */ 162 err = bus_dma_tag_create( 163 bus_get_dma_tag(nic->dev), /* parent tag */ 164 align_bytes, /* alignment */ 165 0, /* boundary */ 166 BUS_SPACE_MAXADDR, /* lowaddr */ 167 BUS_SPACE_MAXADDR, /* highaddr */ 168 NULL, NULL, /* filtfunc, filtfuncarg */ 169 (q_len * desc_size), /* maxsize */ 170 1, /* nsegments */ 171 (q_len * desc_size), /* maxsegsize */ 172 0, /* flags */ 173 NULL, NULL, /* lockfunc, lockfuncarg */ 174 &dmem->dmat); /* dmat */ 175 176 if (err != 0) { 177 device_printf(nic->dev, 178 "Failed to create busdma tag for descriptors ring\n"); 179 return (err); 180 } 181 182 /* Allocate segment of continuous DMA safe memory */ 183 err = bus_dmamem_alloc( 184 dmem->dmat, /* DMA tag */ 185 &dmem->base, /* virtual address */ 186 (BUS_DMA_NOWAIT | BUS_DMA_ZERO), /* flags */ 187 &dmem->dmap); /* DMA map */ 188 if (err != 0) { 189 device_printf(nic->dev, "Failed to allocate DMA safe memory for" 190 "descriptors ring\n"); 191 goto dmamem_fail; 192 } 193 194 err = bus_dmamap_load( 195 dmem->dmat, 196 dmem->dmap, 197 dmem->base, 198 (q_len * desc_size), /* allocation size */ 199 nicvf_dmamap_q_cb, /* map to DMA address cb. */ 200 &dmem->phys_base, /* physical address */ 201 BUS_DMA_NOWAIT); 202 if (err != 0) { 203 device_printf(nic->dev, 204 "Cannot load DMA map of descriptors ring\n"); 205 goto dmamap_fail; 206 } 207 208 dmem->q_len = q_len; 209 dmem->size = (desc_size * q_len); 210 211 return (0); 212 213dmamap_fail: 214 bus_dmamem_free(dmem->dmat, dmem->base, dmem->dmap); 215 dmem->phys_base = 0; 216dmamem_fail: 217 err_dmat = bus_dma_tag_destroy(dmem->dmat); 218 dmem->base = NULL; 219 KASSERT(err_dmat == 0, 220 ("%s: Trying to destroy BUSY DMA tag", __func__)); 221 222 return (err); 223} 224 225/* Free queue's descriptor memory */ 226static void 227nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem) 228{ 229 int err; 230 231 if ((dmem == NULL) || (dmem->base == NULL)) 232 return; 233 234 /* Unload a map */ 235 bus_dmamap_sync(dmem->dmat, dmem->dmap, BUS_DMASYNC_POSTREAD); 236 bus_dmamap_unload(dmem->dmat, dmem->dmap); 237 /* Free DMA memory */ 238 bus_dmamem_free(dmem->dmat, dmem->base, dmem->dmap); 239 /* Destroy DMA tag */ 240 err = bus_dma_tag_destroy(dmem->dmat); 241 242 KASSERT(err == 0, 243 ("%s: Trying to destroy BUSY DMA tag", __func__)); 244 245 dmem->phys_base = 0; 246 dmem->base = NULL; 247} 248 249/* 250 * Allocate buffer for packet reception 251 * HW returns memory address where packet is DMA'ed but not a pointer 252 * into RBDR ring, so save buffer address at the start of fragment and 253 * align the start address to a cache aligned address 254 */ 255static __inline int 256nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr, 257 bus_dmamap_t dmap, int mflags, uint32_t buf_len, bus_addr_t *rbuf) 258{ 259 struct mbuf *mbuf; 260 struct rbuf_info *rinfo; 261 bus_dma_segment_t segs[1]; 262 int nsegs; 263 int err; 264 265 mbuf = m_getjcl(mflags, MT_DATA, M_PKTHDR, MCLBYTES); 266 if (mbuf == NULL) 267 return (ENOMEM); 268 269 /* 270 * The length is equal to the actual length + one 128b line 271 * used as a room for rbuf_info structure. 272 */ 273 mbuf->m_len = mbuf->m_pkthdr.len = buf_len; 274 275 err = bus_dmamap_load_mbuf_sg(rbdr->rbdr_buff_dmat, dmap, mbuf, segs, 276 &nsegs, BUS_DMA_NOWAIT); 277 if (err != 0) { 278 device_printf(nic->dev, 279 "Failed to map mbuf into DMA visible memory, err: %d\n", 280 err); 281 m_freem(mbuf); 282 bus_dmamap_destroy(rbdr->rbdr_buff_dmat, dmap); 283 return (err); 284 } 285 if (nsegs != 1) 286 panic("Unexpected number of DMA segments for RB: %d", nsegs); 287 /* 288 * Now use the room for rbuf_info structure 289 * and adjust mbuf data and length. 290 */ 291 rinfo = (struct rbuf_info *)mbuf->m_data; 292 m_adj(mbuf, NICVF_RCV_BUF_ALIGN_BYTES); 293 294 rinfo->dmat = rbdr->rbdr_buff_dmat; 295 rinfo->dmap = dmap; 296 rinfo->mbuf = mbuf; 297 298 *rbuf = segs[0].ds_addr + NICVF_RCV_BUF_ALIGN_BYTES; 299 300 return (0); 301} 302 303/* Retrieve mbuf for received packet */ 304static struct mbuf * 305nicvf_rb_ptr_to_mbuf(struct nicvf *nic, bus_addr_t rb_ptr) 306{ 307 struct mbuf *mbuf; 308 struct rbuf_info *rinfo; 309 310 /* Get buffer start address and alignment offset */ 311 rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(rb_ptr)); 312 313 /* Now retrieve mbuf to give to stack */ 314 mbuf = rinfo->mbuf; 315 if (__predict_false(mbuf == NULL)) { 316 panic("%s: Received packet fragment with NULL mbuf", 317 device_get_nameunit(nic->dev)); 318 } 319 /* 320 * Clear the mbuf in the descriptor to indicate 321 * that this slot is processed and free to use. 322 */ 323 rinfo->mbuf = NULL; 324 325 bus_dmamap_sync(rinfo->dmat, rinfo->dmap, BUS_DMASYNC_POSTREAD); 326 bus_dmamap_unload(rinfo->dmat, rinfo->dmap); 327 328 return (mbuf); 329} 330 331/* Allocate RBDR ring and populate receive buffers */ 332static int 333nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr, int ring_len, 334 int buf_size, int qidx) 335{ 336 bus_dmamap_t dmap; 337 bus_addr_t rbuf; 338 struct rbdr_entry_t *desc; 339 int idx; 340 int err; 341 342 /* Allocate rbdr descriptors ring */ 343 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len, 344 sizeof(struct rbdr_entry_t), NICVF_RCV_BUF_ALIGN_BYTES); 345 if (err != 0) { 346 device_printf(nic->dev, 347 "Failed to create RBDR descriptors ring\n"); 348 return (err); 349 } 350 351 rbdr->desc = rbdr->dmem.base; 352 /* 353 * Buffer size has to be in multiples of 128 bytes. 354 * Make room for metadata of size of one line (128 bytes). 355 */ 356 rbdr->dma_size = buf_size - NICVF_RCV_BUF_ALIGN_BYTES; 357 rbdr->enable = TRUE; 358 rbdr->thresh = RBDR_THRESH; 359 rbdr->nic = nic; 360 rbdr->idx = qidx; 361 362 /* 363 * Create DMA tag for Rx buffers. 364 * Each map created using this tag is intended to store Rx payload for 365 * one fragment and one header structure containing rbuf_info (thus 366 * additional 128 byte line since RB must be a multiple of 128 byte 367 * cache line). 368 */ 369 if (buf_size > MCLBYTES) { 370 device_printf(nic->dev, 371 "Buffer size to large for mbuf cluster\n"); 372 return (EINVAL); 373 } 374 err = bus_dma_tag_create( 375 bus_get_dma_tag(nic->dev), /* parent tag */ 376 NICVF_RCV_BUF_ALIGN_BYTES, /* alignment */ 377 0, /* boundary */ 378 DMAP_MAX_PHYSADDR, /* lowaddr */ 379 DMAP_MIN_PHYSADDR, /* highaddr */ 380 NULL, NULL, /* filtfunc, filtfuncarg */ 381 roundup2(buf_size, MCLBYTES), /* maxsize */ 382 1, /* nsegments */ 383 roundup2(buf_size, MCLBYTES), /* maxsegsize */ 384 0, /* flags */ 385 NULL, NULL, /* lockfunc, lockfuncarg */ 386 &rbdr->rbdr_buff_dmat); /* dmat */ 387 388 if (err != 0) { 389 device_printf(nic->dev, 390 "Failed to create busdma tag for RBDR buffers\n"); 391 return (err); 392 } 393 394 rbdr->rbdr_buff_dmaps = malloc(sizeof(*rbdr->rbdr_buff_dmaps) * 395 ring_len, M_NICVF, (M_WAITOK | M_ZERO)); 396 397 for (idx = 0; idx < ring_len; idx++) { 398 err = bus_dmamap_create(rbdr->rbdr_buff_dmat, 0, &dmap); 399 if (err != 0) { 400 device_printf(nic->dev, 401 "Failed to create DMA map for RB\n"); 402 return (err); 403 } 404 rbdr->rbdr_buff_dmaps[idx] = dmap; 405 406 err = nicvf_alloc_rcv_buffer(nic, rbdr, dmap, M_WAITOK, 407 DMA_BUFFER_LEN, &rbuf); 408 if (err != 0) 409 return (err); 410 411 desc = GET_RBDR_DESC(rbdr, idx); 412 desc->buf_addr = (rbuf >> NICVF_RCV_BUF_ALIGN); 413 } 414 415 /* Allocate taskqueue */ 416 TASK_INIT(&rbdr->rbdr_task, 0, nicvf_rbdr_task, rbdr); 417 TASK_INIT(&rbdr->rbdr_task_nowait, 0, nicvf_rbdr_task_nowait, rbdr); 418 rbdr->rbdr_taskq = taskqueue_create_fast("nicvf_rbdr_taskq", M_WAITOK, 419 taskqueue_thread_enqueue, &rbdr->rbdr_taskq); 420 taskqueue_start_threads(&rbdr->rbdr_taskq, 1, PI_NET, "%s: rbdr_taskq", 421 device_get_nameunit(nic->dev)); 422 423 return (0); 424} 425 426/* Free RBDR ring and its receive buffers */ 427static void 428nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) 429{ 430 struct mbuf *mbuf; 431 struct queue_set *qs; 432 struct rbdr_entry_t *desc; 433 struct rbuf_info *rinfo; 434 bus_addr_t buf_addr; 435 int head, tail, idx; 436 int err; 437 438 qs = nic->qs; 439 440 if ((qs == NULL) || (rbdr == NULL)) 441 return; 442 443 rbdr->enable = FALSE; 444 if (rbdr->rbdr_taskq != NULL) { 445 /* Remove tasks */ 446 while (taskqueue_cancel(rbdr->rbdr_taskq, 447 &rbdr->rbdr_task_nowait, NULL) != 0) { 448 /* Finish the nowait task first */ 449 taskqueue_drain(rbdr->rbdr_taskq, 450 &rbdr->rbdr_task_nowait); 451 } 452 taskqueue_free(rbdr->rbdr_taskq); 453 rbdr->rbdr_taskq = NULL; 454 455 while (taskqueue_cancel(taskqueue_thread, 456 &rbdr->rbdr_task, NULL) != 0) { 457 /* Now finish the sleepable task */ 458 taskqueue_drain(taskqueue_thread, &rbdr->rbdr_task); 459 } 460 } 461 462 /* 463 * Free all of the memory under the RB descriptors. 464 * There are assumptions here: 465 * 1. Corresponding RBDR is disabled 466 * - it is safe to operate using head and tail indexes 467 * 2. All bffers that were received are properly freed by 468 * the receive handler 469 * - there is no need to unload DMA map and free MBUF for other 470 * descriptors than unused ones 471 */ 472 if (rbdr->rbdr_buff_dmat != NULL) { 473 head = rbdr->head; 474 tail = rbdr->tail; 475 while (head != tail) { 476 desc = GET_RBDR_DESC(rbdr, head); 477 buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; 478 rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(buf_addr)); 479 bus_dmamap_unload(rbdr->rbdr_buff_dmat, rinfo->dmap); 480 mbuf = rinfo->mbuf; 481 /* This will destroy everything including rinfo! */ 482 m_freem(mbuf); 483 head++; 484 head &= (rbdr->dmem.q_len - 1); 485 } 486 /* Free tail descriptor */ 487 desc = GET_RBDR_DESC(rbdr, tail); 488 buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; 489 rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(buf_addr)); 490 bus_dmamap_unload(rbdr->rbdr_buff_dmat, rinfo->dmap); 491 mbuf = rinfo->mbuf; 492 /* This will destroy everything including rinfo! */ 493 m_freem(mbuf); 494 495 /* Destroy DMA maps */ 496 for (idx = 0; idx < qs->rbdr_len; idx++) { 497 if (rbdr->rbdr_buff_dmaps[idx] == NULL) 498 continue; 499 err = bus_dmamap_destroy(rbdr->rbdr_buff_dmat, 500 rbdr->rbdr_buff_dmaps[idx]); 501 KASSERT(err == 0, 502 ("%s: Could not destroy DMA map for RB, desc: %d", 503 __func__, idx)); 504 rbdr->rbdr_buff_dmaps[idx] = NULL; 505 } 506 507 /* Now destroy the tag */ 508 err = bus_dma_tag_destroy(rbdr->rbdr_buff_dmat); 509 KASSERT(err == 0, 510 ("%s: Trying to destroy BUSY DMA tag", __func__)); 511 512 rbdr->head = 0; 513 rbdr->tail = 0; 514 } 515 516 /* Free RBDR ring */ 517 nicvf_free_q_desc_mem(nic, &rbdr->dmem); 518} 519 520/* 521 * Refill receive buffer descriptors with new buffers. 522 */ 523static int 524nicvf_refill_rbdr(struct rbdr *rbdr, int mflags) 525{ 526 struct nicvf *nic; 527 struct queue_set *qs; 528 int rbdr_idx; 529 int tail, qcount; 530 int refill_rb_cnt; 531 struct rbdr_entry_t *desc; 532 bus_dmamap_t dmap; 533 bus_addr_t rbuf; 534 boolean_t rb_alloc_fail; 535 int new_rb; 536 537 rb_alloc_fail = TRUE; 538 new_rb = 0; 539 nic = rbdr->nic; 540 qs = nic->qs; 541 rbdr_idx = rbdr->idx; 542 543 /* Check if it's enabled */ 544 if (!rbdr->enable) 545 return (0); 546 547 /* Get no of desc's to be refilled */ 548 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx); 549 qcount &= 0x7FFFF; 550 /* Doorbell can be ringed with a max of ring size minus 1 */ 551 if (qcount >= (qs->rbdr_len - 1)) { 552 rb_alloc_fail = FALSE; 553 goto out; 554 } else 555 refill_rb_cnt = qs->rbdr_len - qcount - 1; 556 557 /* Start filling descs from tail */ 558 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3; 559 while (refill_rb_cnt) { 560 tail++; 561 tail &= (rbdr->dmem.q_len - 1); 562 563 dmap = rbdr->rbdr_buff_dmaps[tail]; 564 if (nicvf_alloc_rcv_buffer(nic, rbdr, dmap, mflags, 565 DMA_BUFFER_LEN, &rbuf)) { 566 /* Something went wrong. Resign */ 567 break; 568 } 569 desc = GET_RBDR_DESC(rbdr, tail); 570 desc->buf_addr = (rbuf >> NICVF_RCV_BUF_ALIGN); 571 refill_rb_cnt--; 572 new_rb++; 573 } 574 575 /* make sure all memory stores are done before ringing doorbell */ 576 wmb(); 577 578 /* Check if buffer allocation failed */ 579 if (refill_rb_cnt == 0) 580 rb_alloc_fail = FALSE; 581 582 /* Notify HW */ 583 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, 584 rbdr_idx, new_rb); 585out: 586 if (!rb_alloc_fail) { 587 /* 588 * Re-enable RBDR interrupts only 589 * if buffer allocation is success. 590 */ 591 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx); 592 593 return (0); 594 } 595 596 return (ENOMEM); 597} 598 599/* Refill RBs even if sleep is needed to reclaim memory */ 600static void 601nicvf_rbdr_task(void *arg, int pending) 602{ 603 struct rbdr *rbdr; 604 int err; 605 606 rbdr = (struct rbdr *)arg; 607 608 err = nicvf_refill_rbdr(rbdr, M_WAITOK); 609 if (__predict_false(err != 0)) { 610 panic("%s: Failed to refill RBs even when sleep enabled", 611 __func__); 612 } 613} 614 615/* Refill RBs as soon as possible without waiting */ 616static void 617nicvf_rbdr_task_nowait(void *arg, int pending) 618{ 619 struct rbdr *rbdr; 620 int err; 621 622 rbdr = (struct rbdr *)arg; 623 624 err = nicvf_refill_rbdr(rbdr, M_NOWAIT); 625 if (err != 0) { 626 /* 627 * Schedule another, sleepable kernel thread 628 * that will for sure refill the buffers. 629 */ 630 taskqueue_enqueue(taskqueue_thread, &rbdr->rbdr_task); 631 } 632} 633 634static int 635nicvf_rcv_pkt_handler(struct nicvf *nic, struct cmp_queue *cq, 636 struct cqe_rx_t *cqe_rx, int cqe_type) 637{ 638 struct mbuf *mbuf; 639 struct rcv_queue *rq; 640 int rq_idx; 641 int err = 0; 642 643 rq_idx = cqe_rx->rq_idx; 644 rq = &nic->qs->rq[rq_idx]; 645 646 /* Check for errors */ 647 err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx); 648 if (err && !cqe_rx->rb_cnt) 649 return (0); 650 651 mbuf = nicvf_get_rcv_mbuf(nic, cqe_rx); 652 if (mbuf == NULL) { 653 dprintf(nic->dev, "Packet not received\n"); 654 return (0); 655 } 656 657 /* If error packet */ 658 if (err != 0) { 659 m_freem(mbuf); 660 return (0); 661 } 662 663 if (rq->lro_enabled && 664 ((cqe_rx->l3_type == L3TYPE_IPV4) && (cqe_rx->l4_type == L4TYPE_TCP)) && 665 (mbuf->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 666 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) { 667 /* 668 * At this point it is known that there are no errors in the 669 * packet. Attempt to LRO enqueue. Send to stack if no resources 670 * or enqueue error. 671 */ 672 if ((rq->lro.lro_cnt != 0) && 673 (tcp_lro_rx(&rq->lro, mbuf, 0) == 0)) 674 return (0); 675 } 676 /* 677 * Push this packet to the stack later to avoid 678 * unlocking completion task in the middle of work. 679 */ 680 err = buf_ring_enqueue(cq->rx_br, mbuf); 681 if (err != 0) { 682 /* 683 * Failed to enqueue this mbuf. 684 * We don't drop it, just schedule another task. 685 */ 686 return (err); 687 } 688 689 return (0); 690} 691 692static int 693nicvf_snd_pkt_handler(struct nicvf *nic, struct cmp_queue *cq, 694 struct cqe_send_t *cqe_tx, int cqe_type) 695{ 696 bus_dmamap_t dmap; 697 struct mbuf *mbuf; 698 struct snd_queue *sq; 699 struct sq_hdr_subdesc *hdr; 700 701 mbuf = NULL; 702 sq = &nic->qs->sq[cqe_tx->sq_idx]; 703 /* Avoid blocking here since we hold a non-sleepable NICVF_CMP_LOCK */ 704 if (NICVF_TX_TRYLOCK(sq) == 0) 705 return (EAGAIN); 706 707 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); 708 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { 709 NICVF_TX_UNLOCK(sq); 710 return (0); 711 } 712 713 dprintf(nic->dev, 714 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n", 715 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, 716 cqe_tx->sqe_ptr, hdr->subdesc_cnt); 717 718 dmap = (bus_dmamap_t)sq->snd_buff[cqe_tx->sqe_ptr].dmap; 719 bus_dmamap_unload(sq->snd_buff_dmat, dmap); 720 721 mbuf = (struct mbuf *)sq->snd_buff[cqe_tx->sqe_ptr].mbuf; 722 if (mbuf != NULL) { 723 m_freem(mbuf); 724 sq->snd_buff[cqe_tx->sqe_ptr].mbuf = NULL; 725 } 726 727 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx); 728 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 729 730 NICVF_TX_UNLOCK(sq); 731 return (0); 732} 733 734static int 735nicvf_cq_intr_handler(struct nicvf *nic, uint8_t cq_idx) 736{ 737 struct mbuf *mbuf; 738 struct ifnet *ifp; 739 int processed_cqe, work_done = 0, tx_done = 0; 740 int cqe_count, cqe_head; 741 struct queue_set *qs = nic->qs; 742 struct cmp_queue *cq = &qs->cq[cq_idx]; 743 struct rcv_queue *rq; 744 struct cqe_rx_t *cq_desc; 745 struct lro_ctrl *lro; 746 struct lro_entry *queued; 747 int rq_idx; 748 int cmp_err; 749 750 NICVF_CMP_LOCK(cq); 751 cmp_err = 0; 752 processed_cqe = 0; 753 /* Get no of valid CQ entries to process */ 754 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); 755 cqe_count &= CQ_CQE_COUNT; 756 if (cqe_count == 0) 757 goto out; 758 759 /* Get head of the valid CQ entries */ 760 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; 761 cqe_head &= 0xFFFF; 762 763 dprintf(nic->dev, "%s CQ%d cqe_count %d cqe_head %d\n", 764 __func__, cq_idx, cqe_count, cqe_head); 765 while (processed_cqe < cqe_count) { 766 /* Get the CQ descriptor */ 767 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); 768 cqe_head++; 769 cqe_head &= (cq->dmem.q_len - 1); 770 /* Prefetch next CQ descriptor */ 771 __builtin_prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); 772 773 dprintf(nic->dev, "CQ%d cq_desc->cqe_type %d\n", cq_idx, 774 cq_desc->cqe_type); 775 switch (cq_desc->cqe_type) { 776 case CQE_TYPE_RX: 777 cmp_err = nicvf_rcv_pkt_handler(nic, cq, cq_desc, 778 CQE_TYPE_RX); 779 if (__predict_false(cmp_err != 0)) { 780 /* 781 * Ups. Cannot finish now. 782 * Let's try again later. 783 */ 784 goto done; 785 } 786 work_done++; 787 break; 788 case CQE_TYPE_SEND: 789 cmp_err = nicvf_snd_pkt_handler(nic, cq, 790 (void *)cq_desc, CQE_TYPE_SEND); 791 if (__predict_false(cmp_err != 0)) { 792 /* 793 * Ups. Cannot finish now. 794 * Let's try again later. 795 */ 796 goto done; 797 } 798 799 tx_done++; 800 break; 801 case CQE_TYPE_INVALID: 802 case CQE_TYPE_RX_SPLIT: 803 case CQE_TYPE_RX_TCP: 804 case CQE_TYPE_SEND_PTP: 805 /* Ignore for now */ 806 break; 807 } 808 processed_cqe++; 809 } 810done: 811 dprintf(nic->dev, 812 "%s CQ%d processed_cqe %d work_done %d\n", 813 __func__, cq_idx, processed_cqe, work_done); 814 815 /* Ring doorbell to inform H/W to reuse processed CQEs */ 816 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, cq_idx, processed_cqe); 817 818 if ((tx_done > 0) && 819 ((if_getdrvflags(nic->ifp) & IFF_DRV_RUNNING) != 0)) { 820 /* Reenable TXQ if its stopped earlier due to SQ full */ 821 if_setdrvflagbits(nic->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 822 } 823out: 824 /* 825 * Flush any outstanding LRO work 826 */ 827 rq_idx = cq_idx; 828 rq = &nic->qs->rq[rq_idx]; 829 lro = &rq->lro; 830 while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) { 831 SLIST_REMOVE_HEAD(&lro->lro_active, next); 832 tcp_lro_flush(lro, queued); 833 } 834 835 NICVF_CMP_UNLOCK(cq); 836 837 ifp = nic->ifp; 838 /* Push received MBUFs to the stack */ 839 while (!buf_ring_empty(cq->rx_br)) { 840 mbuf = buf_ring_dequeue_mc(cq->rx_br); 841 if (__predict_true(mbuf != NULL)) 842 (*ifp->if_input)(ifp, mbuf); 843 } 844 845 return (cmp_err); 846} 847 848/* 849 * Qset error interrupt handler 850 * 851 * As of now only CQ errors are handled 852 */ 853static void 854nicvf_qs_err_task(void *arg, int pending) 855{ 856 struct nicvf *nic; 857 struct queue_set *qs; 858 int qidx; 859 uint64_t status; 860 boolean_t enable = TRUE; 861 862 nic = (struct nicvf *)arg; 863 qs = nic->qs; 864 865 /* Deactivate network interface */ 866 if_setdrvflagbits(nic->ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 867 868 /* Check if it is CQ err */ 869 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 870 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, 871 qidx); 872 if ((status & CQ_ERR_MASK) == 0) 873 continue; 874 /* Process already queued CQEs and reconfig CQ */ 875 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 876 nicvf_sq_disable(nic, qidx); 877 (void)nicvf_cq_intr_handler(nic, qidx); 878 nicvf_cmp_queue_config(nic, qs, qidx, enable); 879 nicvf_sq_free_used_descs(nic, &qs->sq[qidx], qidx); 880 nicvf_sq_enable(nic, &qs->sq[qidx], qidx); 881 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 882 } 883 884 if_setdrvflagbits(nic->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 885 /* Re-enable Qset error interrupt */ 886 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 887} 888 889static void 890nicvf_cmp_task(void *arg, int pending) 891{ 892 struct cmp_queue *cq; 893 struct nicvf *nic; 894 int cmp_err; 895 896 cq = (struct cmp_queue *)arg; 897 nic = cq->nic; 898 899 /* Handle CQ descriptors */ 900 cmp_err = nicvf_cq_intr_handler(nic, cq->idx); 901 if (__predict_false(cmp_err != 0)) { 902 /* 903 * Schedule another thread here since we did not 904 * process the entire CQ due to Tx or Rx CQ parse error. 905 */ 906 taskqueue_enqueue(cq->cmp_taskq, &cq->cmp_task); 907 908 } 909 910 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->idx); 911 /* Reenable interrupt (previously disabled in nicvf_intr_handler() */ 912 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->idx); 913 914} 915 916/* Initialize completion queue */ 917static int 918nicvf_init_cmp_queue(struct nicvf *nic, struct cmp_queue *cq, int q_len, 919 int qidx) 920{ 921 int err; 922 923 /* Initizalize lock */ 924 snprintf(cq->mtx_name, sizeof(cq->mtx_name), "%s: CQ(%d) lock", 925 device_get_nameunit(nic->dev), qidx); 926 mtx_init(&cq->mtx, cq->mtx_name, NULL, MTX_DEF); 927 928 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE, 929 NICVF_CQ_BASE_ALIGN_BYTES); 930 931 if (err != 0) { 932 device_printf(nic->dev, 933 "Could not allocate DMA memory for CQ\n"); 934 return (err); 935 } 936 937 cq->desc = cq->dmem.base; 938 cq->thresh = pass1_silicon(nic->dev) ? 0 : CMP_QUEUE_CQE_THRESH; 939 cq->nic = nic; 940 cq->idx = qidx; 941 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1; 942 943 cq->rx_br = buf_ring_alloc(CMP_QUEUE_LEN * 8, M_DEVBUF, M_WAITOK, 944 &cq->mtx); 945 946 /* Allocate taskqueue */ 947 TASK_INIT(&cq->cmp_task, 0, nicvf_cmp_task, cq); 948 cq->cmp_taskq = taskqueue_create_fast("nicvf_cmp_taskq", M_WAITOK, 949 taskqueue_thread_enqueue, &cq->cmp_taskq); 950 taskqueue_start_threads(&cq->cmp_taskq, 1, PI_NET, "%s: cmp_taskq(%d)", 951 device_get_nameunit(nic->dev), qidx); 952 953 return (0); 954} 955 956static void 957nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq) 958{ 959 960 if (cq == NULL) 961 return; 962 /* 963 * The completion queue itself should be disabled by now 964 * (ref. nicvf_snd_queue_config()). 965 * Ensure that it is safe to disable it or panic. 966 */ 967 if (cq->enable) 968 panic("%s: Trying to free working CQ(%d)", __func__, cq->idx); 969 970 if (cq->cmp_taskq != NULL) { 971 /* Remove task */ 972 while (taskqueue_cancel(cq->cmp_taskq, &cq->cmp_task, NULL) != 0) 973 taskqueue_drain(cq->cmp_taskq, &cq->cmp_task); 974 975 taskqueue_free(cq->cmp_taskq); 976 cq->cmp_taskq = NULL; 977 } 978 /* 979 * Completion interrupt will possibly enable interrupts again 980 * so disable interrupting now after we finished processing 981 * completion task. It is safe to do so since the corresponding CQ 982 * was already disabled. 983 */ 984 nicvf_disable_intr(nic, NICVF_INTR_CQ, cq->idx); 985 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->idx); 986 987 NICVF_CMP_LOCK(cq); 988 nicvf_free_q_desc_mem(nic, &cq->dmem); 989 drbr_free(cq->rx_br, M_DEVBUF); 990 NICVF_CMP_UNLOCK(cq); 991 mtx_destroy(&cq->mtx); 992 memset(cq->mtx_name, 0, sizeof(cq->mtx_name)); 993} 994 995static void 996nicvf_snd_task(void *arg, int pending) 997{ 998 struct snd_queue *sq = (struct snd_queue *)arg; 999 struct mbuf *mbuf; 1000 1001 NICVF_TX_LOCK(sq); 1002 while (1) { 1003 mbuf = drbr_dequeue(NULL, sq->br); 1004 if (mbuf == NULL) 1005 break; 1006 1007 if (nicvf_tx_mbuf_locked(sq, mbuf) != 0) { 1008 /* XXX ARM64TODO: Increase Tx drop counter */ 1009 m_freem(mbuf); 1010 break; 1011 } 1012 } 1013 NICVF_TX_UNLOCK(sq); 1014} 1015 1016/* Initialize transmit queue */ 1017static int 1018nicvf_init_snd_queue(struct nicvf *nic, struct snd_queue *sq, int q_len, 1019 int qidx) 1020{ 1021 size_t i; 1022 int err; 1023 1024 /* Initizalize TX lock for this queue */ 1025 snprintf(sq->mtx_name, sizeof(sq->mtx_name), "%s: SQ(%d) lock", 1026 device_get_nameunit(nic->dev), qidx); 1027 mtx_init(&sq->mtx, sq->mtx_name, NULL, MTX_DEF); 1028 1029 NICVF_TX_LOCK(sq); 1030 /* Allocate buffer ring */ 1031 sq->br = buf_ring_alloc(q_len / MIN_SQ_DESC_PER_PKT_XMIT, M_DEVBUF, 1032 M_NOWAIT, &sq->mtx); 1033 if (sq->br == NULL) { 1034 device_printf(nic->dev, 1035 "ERROR: Could not set up buf ring for SQ(%d)\n", qidx); 1036 err = ENOMEM; 1037 goto error; 1038 } 1039 1040 /* Allocate DMA memory for Tx descriptors */ 1041 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE, 1042 NICVF_SQ_BASE_ALIGN_BYTES); 1043 if (err != 0) { 1044 device_printf(nic->dev, 1045 "Could not allocate DMA memory for SQ\n"); 1046 goto error; 1047 } 1048 1049 sq->desc = sq->dmem.base; 1050 sq->head = sq->tail = 0; 1051 atomic_store_rel_int(&sq->free_cnt, q_len - 1); 1052 sq->thresh = SND_QUEUE_THRESH; 1053 sq->idx = qidx; 1054 sq->nic = nic; 1055 1056 /* 1057 * Allocate DMA maps for Tx buffers 1058 */ 1059 1060 /* Create DMA tag first */ 1061 err = bus_dma_tag_create( 1062 bus_get_dma_tag(nic->dev), /* parent tag */ 1063 1, /* alignment */ 1064 0, /* boundary */ 1065 BUS_SPACE_MAXADDR, /* lowaddr */ 1066 BUS_SPACE_MAXADDR, /* highaddr */ 1067 NULL, NULL, /* filtfunc, filtfuncarg */ 1068 NICVF_TSO_MAXSIZE, /* maxsize */ 1069 NICVF_TSO_NSEGS, /* nsegments */ 1070 MCLBYTES, /* maxsegsize */ 1071 0, /* flags */ 1072 NULL, NULL, /* lockfunc, lockfuncarg */ 1073 &sq->snd_buff_dmat); /* dmat */ 1074 1075 if (err != 0) { 1076 device_printf(nic->dev, 1077 "Failed to create busdma tag for Tx buffers\n"); 1078 goto error; 1079 } 1080 1081 /* Allocate send buffers array */ 1082 sq->snd_buff = malloc(sizeof(*sq->snd_buff) * q_len, M_NICVF, 1083 (M_NOWAIT | M_ZERO)); 1084 if (sq->snd_buff == NULL) { 1085 device_printf(nic->dev, 1086 "Could not allocate memory for Tx buffers array\n"); 1087 err = ENOMEM; 1088 goto error; 1089 } 1090 1091 /* Now populate maps */ 1092 for (i = 0; i < q_len; i++) { 1093 err = bus_dmamap_create(sq->snd_buff_dmat, 0, 1094 &sq->snd_buff[i].dmap); 1095 if (err != 0) { 1096 device_printf(nic->dev, 1097 "Failed to create DMA maps for Tx buffers\n"); 1098 goto error; 1099 } 1100 } 1101 NICVF_TX_UNLOCK(sq); 1102 1103 /* Allocate taskqueue */ 1104 TASK_INIT(&sq->snd_task, 0, nicvf_snd_task, sq); 1105 sq->snd_taskq = taskqueue_create_fast("nicvf_snd_taskq", M_WAITOK, 1106 taskqueue_thread_enqueue, &sq->snd_taskq); 1107 taskqueue_start_threads(&sq->snd_taskq, 1, PI_NET, "%s: snd_taskq(%d)", 1108 device_get_nameunit(nic->dev), qidx); 1109 1110 return (0); 1111error: 1112 NICVF_TX_UNLOCK(sq); 1113 return (err); 1114} 1115 1116static void 1117nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) 1118{ 1119 struct queue_set *qs = nic->qs; 1120 size_t i; 1121 int err; 1122 1123 if (sq == NULL) 1124 return; 1125 1126 if (sq->snd_taskq != NULL) { 1127 /* Remove task */ 1128 while (taskqueue_cancel(sq->snd_taskq, &sq->snd_task, NULL) != 0) 1129 taskqueue_drain(sq->snd_taskq, &sq->snd_task); 1130 1131 taskqueue_free(sq->snd_taskq); 1132 sq->snd_taskq = NULL; 1133 } 1134 1135 NICVF_TX_LOCK(sq); 1136 if (sq->snd_buff_dmat != NULL) { 1137 if (sq->snd_buff != NULL) { 1138 for (i = 0; i < qs->sq_len; i++) { 1139 m_freem(sq->snd_buff[i].mbuf); 1140 sq->snd_buff[i].mbuf = NULL; 1141 1142 bus_dmamap_unload(sq->snd_buff_dmat, 1143 sq->snd_buff[i].dmap); 1144 err = bus_dmamap_destroy(sq->snd_buff_dmat, 1145 sq->snd_buff[i].dmap); 1146 /* 1147 * If bus_dmamap_destroy fails it can cause 1148 * random panic later if the tag is also 1149 * destroyed in the process. 1150 */ 1151 KASSERT(err == 0, 1152 ("%s: Could not destroy DMA map for SQ", 1153 __func__)); 1154 } 1155 } 1156 1157 free(sq->snd_buff, M_NICVF); 1158 1159 err = bus_dma_tag_destroy(sq->snd_buff_dmat); 1160 KASSERT(err == 0, 1161 ("%s: Trying to destroy BUSY DMA tag", __func__)); 1162 } 1163 1164 /* Free private driver ring for this send queue */ 1165 if (sq->br != NULL) 1166 drbr_free(sq->br, M_DEVBUF); 1167 1168 if (sq->dmem.base != NULL) 1169 nicvf_free_q_desc_mem(nic, &sq->dmem); 1170 1171 NICVF_TX_UNLOCK(sq); 1172 /* Destroy Tx lock */ 1173 mtx_destroy(&sq->mtx); 1174 memset(sq->mtx_name, 0, sizeof(sq->mtx_name)); 1175} 1176 1177static void 1178nicvf_reclaim_snd_queue(struct nicvf *nic, struct queue_set *qs, int qidx) 1179{ 1180 1181 /* Disable send queue */ 1182 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0); 1183 /* Check if SQ is stopped */ 1184 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01)) 1185 return; 1186 /* Reset send queue */ 1187 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 1188} 1189 1190static void 1191nicvf_reclaim_rcv_queue(struct nicvf *nic, struct queue_set *qs, int qidx) 1192{ 1193 union nic_mbx mbx = {}; 1194 1195 /* Make sure all packets in the pipeline are written back into mem */ 1196 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC; 1197 nicvf_send_msg_to_pf(nic, &mbx); 1198} 1199 1200static void 1201nicvf_reclaim_cmp_queue(struct nicvf *nic, struct queue_set *qs, int qidx) 1202{ 1203 1204 /* Disable timer threshold (doesn't get reset upon CQ reset */ 1205 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0); 1206 /* Disable completion queue */ 1207 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0); 1208 /* Reset completion queue */ 1209 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 1210} 1211 1212static void 1213nicvf_reclaim_rbdr(struct nicvf *nic, struct rbdr *rbdr, int qidx) 1214{ 1215 uint64_t tmp, fifo_state; 1216 int timeout = 10; 1217 1218 /* Save head and tail pointers for feeing up buffers */ 1219 rbdr->head = 1220 nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_HEAD, qidx) >> 3; 1221 rbdr->tail = 1222 nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, qidx) >> 3; 1223 1224 /* 1225 * If RBDR FIFO is in 'FAIL' state then do a reset first 1226 * before relaiming. 1227 */ 1228 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); 1229 if (((fifo_state >> 62) & 0x03) == 0x3) { 1230 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 1231 qidx, NICVF_RBDR_RESET); 1232 } 1233 1234 /* Disable RBDR */ 1235 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0); 1236 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 1237 return; 1238 while (1) { 1239 tmp = nicvf_queue_reg_read(nic, 1240 NIC_QSET_RBDR_0_1_PREFETCH_STATUS, qidx); 1241 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF)) 1242 break; 1243 1244 DELAY(1000); 1245 timeout--; 1246 if (!timeout) { 1247 device_printf(nic->dev, 1248 "Failed polling on prefetch status\n"); 1249 return; 1250 } 1251 } 1252 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 1253 NICVF_RBDR_RESET); 1254 1255 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02)) 1256 return; 1257 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00); 1258 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 1259 return; 1260} 1261 1262/* Configures receive queue */ 1263static void 1264nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, 1265 int qidx, bool enable) 1266{ 1267 union nic_mbx mbx = {}; 1268 struct rcv_queue *rq; 1269 struct rq_cfg rq_cfg; 1270 struct ifnet *ifp; 1271 struct lro_ctrl *lro; 1272 1273 ifp = nic->ifp; 1274 1275 rq = &qs->rq[qidx]; 1276 rq->enable = enable; 1277 1278 lro = &rq->lro; 1279 1280 /* Disable receive queue */ 1281 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0); 1282 1283 if (!rq->enable) { 1284 nicvf_reclaim_rcv_queue(nic, qs, qidx); 1285 /* Free LRO memory */ 1286 tcp_lro_free(lro); 1287 rq->lro_enabled = FALSE; 1288 return; 1289 } 1290 1291 /* Configure LRO if enabled */ 1292 rq->lro_enabled = FALSE; 1293 if ((if_getcapenable(ifp) & IFCAP_LRO) != 0) { 1294 if (tcp_lro_init(lro) != 0) { 1295 device_printf(nic->dev, 1296 "Failed to initialize LRO for RXQ%d\n", qidx); 1297 } else { 1298 rq->lro_enabled = TRUE; 1299 lro->ifp = nic->ifp; 1300 } 1301 } 1302 1303 rq->cq_qs = qs->vnic_id; 1304 rq->cq_idx = qidx; 1305 rq->start_rbdr_qs = qs->vnic_id; 1306 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1; 1307 rq->cont_rbdr_qs = qs->vnic_id; 1308 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1; 1309 /* all writes of RBDR data to be loaded into L2 Cache as well*/ 1310 rq->caching = 1; 1311 1312 /* Send a mailbox msg to PF to config RQ */ 1313 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG; 1314 mbx.rq.qs_num = qs->vnic_id; 1315 mbx.rq.rq_num = qidx; 1316 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) | 1317 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) | 1318 (rq->cont_qs_rbdr_idx << 8) | (rq->start_rbdr_qs << 1) | 1319 (rq->start_qs_rbdr_idx); 1320 nicvf_send_msg_to_pf(nic, &mbx); 1321 1322 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG; 1323 mbx.rq.cfg = (1UL << 63) | (1UL << 62) | (qs->vnic_id << 0); 1324 nicvf_send_msg_to_pf(nic, &mbx); 1325 1326 /* 1327 * RQ drop config 1328 * Enable CQ drop to reserve sufficient CQEs for all tx packets 1329 */ 1330 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG; 1331 mbx.rq.cfg = (1UL << 62) | (RQ_CQ_DROP << 8); 1332 nicvf_send_msg_to_pf(nic, &mbx); 1333 1334 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00); 1335 1336 /* Enable Receive queue */ 1337 rq_cfg.ena = 1; 1338 rq_cfg.tcp_ena = 0; 1339 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 1340 *(uint64_t *)&rq_cfg); 1341} 1342 1343/* Configures completion queue */ 1344static void 1345nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, 1346 int qidx, boolean_t enable) 1347{ 1348 struct cmp_queue *cq; 1349 struct cq_cfg cq_cfg; 1350 1351 cq = &qs->cq[qidx]; 1352 cq->enable = enable; 1353 1354 if (!cq->enable) { 1355 nicvf_reclaim_cmp_queue(nic, qs, qidx); 1356 return; 1357 } 1358 1359 /* Reset completion queue */ 1360 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 1361 1362 /* Set completion queue base address */ 1363 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE, qidx, 1364 (uint64_t)(cq->dmem.phys_base)); 1365 1366 /* Enable Completion queue */ 1367 cq_cfg.ena = 1; 1368 cq_cfg.reset = 0; 1369 cq_cfg.caching = 0; 1370 cq_cfg.qsize = CMP_QSIZE; 1371 cq_cfg.avg_con = 0; 1372 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(uint64_t *)&cq_cfg); 1373 1374 /* Set threshold value for interrupt generation */ 1375 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh); 1376 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 1377 nic->cq_coalesce_usecs); 1378} 1379 1380/* Configures transmit queue */ 1381static void 1382nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, 1383 boolean_t enable) 1384{ 1385 union nic_mbx mbx = {}; 1386 struct snd_queue *sq; 1387 struct sq_cfg sq_cfg; 1388 1389 sq = &qs->sq[qidx]; 1390 sq->enable = enable; 1391 1392 if (!sq->enable) { 1393 nicvf_reclaim_snd_queue(nic, qs, qidx); 1394 return; 1395 } 1396 1397 /* Reset send queue */ 1398 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 1399 1400 sq->cq_qs = qs->vnic_id; 1401 sq->cq_idx = qidx; 1402 1403 /* Send a mailbox msg to PF to config SQ */ 1404 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG; 1405 mbx.sq.qs_num = qs->vnic_id; 1406 mbx.sq.sq_num = qidx; 1407 mbx.sq.sqs_mode = nic->sqs_mode; 1408 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx; 1409 nicvf_send_msg_to_pf(nic, &mbx); 1410 1411 /* Set queue base address */ 1412 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, qidx, 1413 (uint64_t)(sq->dmem.phys_base)); 1414 1415 /* Enable send queue & set queue size */ 1416 sq_cfg.ena = 1; 1417 sq_cfg.reset = 0; 1418 sq_cfg.ldwb = 0; 1419 sq_cfg.qsize = SND_QSIZE; 1420 sq_cfg.tstmp_bgx_intf = 0; 1421 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(uint64_t *)&sq_cfg); 1422 1423 /* Set threshold value for interrupt generation */ 1424 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh); 1425} 1426 1427/* Configures receive buffer descriptor ring */ 1428static void 1429nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs, int qidx, 1430 boolean_t enable) 1431{ 1432 struct rbdr *rbdr; 1433 struct rbdr_cfg rbdr_cfg; 1434 1435 rbdr = &qs->rbdr[qidx]; 1436 nicvf_reclaim_rbdr(nic, rbdr, qidx); 1437 if (!enable) 1438 return; 1439 1440 /* Set descriptor base address */ 1441 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE, qidx, 1442 (uint64_t)(rbdr->dmem.phys_base)); 1443 1444 /* Enable RBDR & set queue size */ 1445 /* Buffer size should be in multiples of 128 bytes */ 1446 rbdr_cfg.ena = 1; 1447 rbdr_cfg.reset = 0; 1448 rbdr_cfg.ldwb = 0; 1449 rbdr_cfg.qsize = RBDR_SIZE; 1450 rbdr_cfg.avg_con = 0; 1451 rbdr_cfg.lines = rbdr->dma_size / 128; 1452 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 1453 *(uint64_t *)&rbdr_cfg); 1454 1455 /* Notify HW */ 1456 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, qidx, 1457 qs->rbdr_len - 1); 1458 1459 /* Set threshold value for interrupt generation */ 1460 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH, qidx, 1461 rbdr->thresh - 1); 1462} 1463 1464/* Requests PF to assign and enable Qset */ 1465void 1466nicvf_qset_config(struct nicvf *nic, boolean_t enable) 1467{ 1468 union nic_mbx mbx = {}; 1469 struct queue_set *qs; 1470 struct qs_cfg *qs_cfg; 1471 1472 qs = nic->qs; 1473 if (qs == NULL) { 1474 device_printf(nic->dev, 1475 "Qset is still not allocated, don't init queues\n"); 1476 return; 1477 } 1478 1479 qs->enable = enable; 1480 qs->vnic_id = nic->vf_id; 1481 1482 /* Send a mailbox msg to PF to config Qset */ 1483 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG; 1484 mbx.qs.num = qs->vnic_id; 1485 1486 mbx.qs.cfg = 0; 1487 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg; 1488 if (qs->enable) { 1489 qs_cfg->ena = 1; 1490 qs_cfg->vnic = qs->vnic_id; 1491 } 1492 nicvf_send_msg_to_pf(nic, &mbx); 1493} 1494 1495static void 1496nicvf_free_resources(struct nicvf *nic) 1497{ 1498 int qidx; 1499 struct queue_set *qs; 1500 1501 qs = nic->qs; 1502 /* 1503 * Remove QS error task first since it has to be dead 1504 * to safely free completion queue tasks. 1505 */ 1506 if (qs->qs_err_taskq != NULL) { 1507 /* Shut down QS error tasks */ 1508 while (taskqueue_cancel(qs->qs_err_taskq, 1509 &qs->qs_err_task, NULL) != 0) { 1510 taskqueue_drain(qs->qs_err_taskq, &qs->qs_err_task); 1511 1512 } 1513 taskqueue_free(qs->qs_err_taskq); 1514 qs->qs_err_taskq = NULL; 1515 } 1516 /* Free receive buffer descriptor ring */ 1517 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1518 nicvf_free_rbdr(nic, &qs->rbdr[qidx]); 1519 1520 /* Free completion queue */ 1521 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1522 nicvf_free_cmp_queue(nic, &qs->cq[qidx]); 1523 1524 /* Free send queue */ 1525 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1526 nicvf_free_snd_queue(nic, &qs->sq[qidx]); 1527} 1528 1529static int 1530nicvf_alloc_resources(struct nicvf *nic) 1531{ 1532 struct queue_set *qs = nic->qs; 1533 int qidx; 1534 1535 /* Alloc receive buffer descriptor ring */ 1536 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1537 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len, 1538 DMA_BUFFER_LEN, qidx)) 1539 goto alloc_fail; 1540 } 1541 1542 /* Alloc send queue */ 1543 for (qidx = 0; qidx < qs->sq_cnt; qidx++) { 1544 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len, qidx)) 1545 goto alloc_fail; 1546 } 1547 1548 /* Alloc completion queue */ 1549 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1550 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len, qidx)) 1551 goto alloc_fail; 1552 } 1553 1554 /* Allocate QS error taskqueue */ 1555 TASK_INIT(&qs->qs_err_task, 0, nicvf_qs_err_task, nic); 1556 qs->qs_err_taskq = taskqueue_create_fast("nicvf_qs_err_taskq", M_WAITOK, 1557 taskqueue_thread_enqueue, &qs->qs_err_taskq); 1558 taskqueue_start_threads(&qs->qs_err_taskq, 1, PI_NET, "%s: qs_taskq", 1559 device_get_nameunit(nic->dev)); 1560 1561 return (0); 1562alloc_fail: 1563 nicvf_free_resources(nic); 1564 return (ENOMEM); 1565} 1566 1567int 1568nicvf_set_qset_resources(struct nicvf *nic) 1569{ 1570 struct queue_set *qs; 1571 1572 qs = malloc(sizeof(*qs), M_NICVF, (M_ZERO | M_WAITOK)); 1573 nic->qs = qs; 1574 1575 /* Set count of each queue */ 1576 qs->rbdr_cnt = RBDR_CNT; 1577 /* With no RSS we stay with single RQ */ 1578 qs->rq_cnt = 1; 1579 1580 qs->sq_cnt = SND_QUEUE_CNT; 1581 qs->cq_cnt = CMP_QUEUE_CNT; 1582 1583 /* Set queue lengths */ 1584 qs->rbdr_len = RCV_BUF_COUNT; 1585 qs->sq_len = SND_QUEUE_LEN; 1586 qs->cq_len = CMP_QUEUE_LEN; 1587 1588 nic->rx_queues = qs->rq_cnt; 1589 nic->tx_queues = qs->sq_cnt; 1590 1591 return (0); 1592} 1593 1594int 1595nicvf_config_data_transfer(struct nicvf *nic, boolean_t enable) 1596{ 1597 boolean_t disable = FALSE; 1598 struct queue_set *qs; 1599 int qidx; 1600 1601 qs = nic->qs; 1602 if (qs == NULL) 1603 return (0); 1604 1605 if (enable) { 1606 if (nicvf_alloc_resources(nic) != 0) 1607 return (ENOMEM); 1608 1609 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1610 nicvf_snd_queue_config(nic, qs, qidx, enable); 1611 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1612 nicvf_cmp_queue_config(nic, qs, qidx, enable); 1613 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1614 nicvf_rbdr_config(nic, qs, qidx, enable); 1615 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1616 nicvf_rcv_queue_config(nic, qs, qidx, enable); 1617 } else { 1618 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1619 nicvf_rcv_queue_config(nic, qs, qidx, disable); 1620 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1621 nicvf_rbdr_config(nic, qs, qidx, disable); 1622 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1623 nicvf_snd_queue_config(nic, qs, qidx, disable); 1624 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1625 nicvf_cmp_queue_config(nic, qs, qidx, disable); 1626 1627 nicvf_free_resources(nic); 1628 } 1629 1630 return (0); 1631} 1632 1633/* 1634 * Get a free desc from SQ 1635 * returns descriptor ponter & descriptor number 1636 */ 1637static __inline int 1638nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt) 1639{ 1640 int qentry; 1641 1642 qentry = sq->tail; 1643 atomic_subtract_int(&sq->free_cnt, desc_cnt); 1644 sq->tail += desc_cnt; 1645 sq->tail &= (sq->dmem.q_len - 1); 1646 1647 return (qentry); 1648} 1649 1650/* Free descriptor back to SQ for future use */ 1651static void 1652nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt) 1653{ 1654 1655 atomic_add_int(&sq->free_cnt, desc_cnt); 1656 sq->head += desc_cnt; 1657 sq->head &= (sq->dmem.q_len - 1); 1658} 1659 1660static __inline int 1661nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry) 1662{ 1663 qentry++; 1664 qentry &= (sq->dmem.q_len - 1); 1665 return (qentry); 1666} 1667 1668static void 1669nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx) 1670{ 1671 uint64_t sq_cfg; 1672 1673 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1674 sq_cfg |= NICVF_SQ_EN; 1675 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1676 /* Ring doorbell so that H/W restarts processing SQEs */ 1677 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0); 1678} 1679 1680static void 1681nicvf_sq_disable(struct nicvf *nic, int qidx) 1682{ 1683 uint64_t sq_cfg; 1684 1685 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1686 sq_cfg &= ~NICVF_SQ_EN; 1687 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1688} 1689 1690static void 1691nicvf_sq_free_used_descs(struct nicvf *nic, struct snd_queue *sq, int qidx) 1692{ 1693 uint64_t head, tail; 1694 struct snd_buff *snd_buff; 1695 struct sq_hdr_subdesc *hdr; 1696 1697 NICVF_TX_LOCK(sq); 1698 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4; 1699 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4; 1700 while (sq->head != head) { 1701 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); 1702 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { 1703 nicvf_put_sq_desc(sq, 1); 1704 continue; 1705 } 1706 snd_buff = &sq->snd_buff[sq->head]; 1707 if (snd_buff->mbuf != NULL) { 1708 bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); 1709 m_freem(snd_buff->mbuf); 1710 sq->snd_buff[sq->head].mbuf = NULL; 1711 } 1712 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 1713 } 1714 NICVF_TX_UNLOCK(sq); 1715} 1716 1717/* 1718 * Add SQ HEADER subdescriptor. 1719 * First subdescriptor for every send descriptor. 1720 */ 1721static __inline int 1722nicvf_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, 1723 int subdesc_cnt, struct mbuf *mbuf, int len) 1724{ 1725 struct nicvf *nic; 1726 struct sq_hdr_subdesc *hdr; 1727 struct ether_vlan_header *eh; 1728#ifdef INET 1729 struct ip *ip; 1730 struct tcphdr *th; 1731#endif 1732 uint16_t etype; 1733 int ehdrlen, iphlen, poff; 1734 1735 nic = sq->nic; 1736 1737 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1738 sq->snd_buff[qentry].mbuf = mbuf; 1739 1740 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1741 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1742 /* Enable notification via CQE after processing SQE */ 1743 hdr->post_cqe = 1; 1744 /* No of subdescriptors following this */ 1745 hdr->subdesc_cnt = subdesc_cnt; 1746 hdr->tot_len = len; 1747 1748 eh = mtod(mbuf, struct ether_vlan_header *); 1749 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 1750 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1751 etype = ntohs(eh->evl_proto); 1752 } else { 1753 ehdrlen = ETHER_HDR_LEN; 1754 etype = ntohs(eh->evl_encap_proto); 1755 } 1756 1757 switch (etype) { 1758#ifdef INET6 1759 case ETHERTYPE_IPV6: 1760 /* ARM64TODO: Add support for IPv6 */ 1761 hdr->csum_l3 = 0; 1762 sq->snd_buff[qentry].mbuf = NULL; 1763 return (ENXIO); 1764#endif 1765#ifdef INET 1766 case ETHERTYPE_IP: 1767 if (mbuf->m_len < ehdrlen + sizeof(struct ip)) { 1768 mbuf = m_pullup(mbuf, ehdrlen + sizeof(struct ip)); 1769 sq->snd_buff[qentry].mbuf = mbuf; 1770 if (mbuf == NULL) 1771 return (ENOBUFS); 1772 } 1773 1774 ip = (struct ip *)(mbuf->m_data + ehdrlen); 1775 ip->ip_sum = 0; 1776 iphlen = ip->ip_hl << 2; 1777 poff = ehdrlen + iphlen; 1778 1779 if (mbuf->m_pkthdr.csum_flags != 0) { 1780 hdr->csum_l3 = 1; /* Enable IP csum calculation */ 1781 switch (ip->ip_p) { 1782 case IPPROTO_TCP: 1783 if ((mbuf->m_pkthdr.csum_flags & CSUM_TCP) == 0) 1784 break; 1785 1786 if (mbuf->m_len < (poff + sizeof(struct tcphdr))) { 1787 mbuf = m_pullup(mbuf, poff + sizeof(struct tcphdr)); 1788 sq->snd_buff[qentry].mbuf = mbuf; 1789 if (mbuf == NULL) 1790 return (ENOBUFS); 1791 } 1792 hdr->csum_l4 = SEND_L4_CSUM_TCP; 1793 break; 1794 case IPPROTO_UDP: 1795 if ((mbuf->m_pkthdr.csum_flags & CSUM_UDP) == 0) 1796 break; 1797 1798 if (mbuf->m_len < (poff + sizeof(struct udphdr))) { 1799 mbuf = m_pullup(mbuf, poff + sizeof(struct udphdr)); 1800 sq->snd_buff[qentry].mbuf = mbuf; 1801 if (mbuf == NULL) 1802 return (ENOBUFS); 1803 } 1804 hdr->csum_l4 = SEND_L4_CSUM_UDP; 1805 break; 1806 case IPPROTO_SCTP: 1807 if ((mbuf->m_pkthdr.csum_flags & CSUM_SCTP) == 0) 1808 break; 1809 1810 if (mbuf->m_len < (poff + sizeof(struct sctphdr))) { 1811 mbuf = m_pullup(mbuf, poff + sizeof(struct sctphdr)); 1812 sq->snd_buff[qentry].mbuf = mbuf; 1813 if (mbuf == NULL) 1814 return (ENOBUFS); 1815 } 1816 hdr->csum_l4 = SEND_L4_CSUM_SCTP; 1817 break; 1818 default: 1819 break; 1820 } 1821 hdr->l3_offset = ehdrlen; 1822 hdr->l4_offset = ehdrlen + iphlen; 1823 } 1824 1825 if ((mbuf->m_pkthdr.tso_segsz != 0) && nic->hw_tso) { 1826 /* 1827 * Extract ip again as m_data could have been modified. 1828 */ 1829 ip = (struct ip *)(mbuf->m_data + ehdrlen); 1830 th = (struct tcphdr *)((caddr_t)ip + iphlen); 1831 1832 hdr->tso = 1; 1833 hdr->tso_start = ehdrlen + iphlen + (th->th_off * 4); 1834 hdr->tso_max_paysize = mbuf->m_pkthdr.tso_segsz; 1835 hdr->inner_l3_offset = ehdrlen - 2; 1836 nic->drv_stats.tx_tso++; 1837 } 1838 break; 1839#endif 1840 default: 1841 hdr->csum_l3 = 0; 1842 } 1843 1844 return (0); 1845} 1846 1847/* 1848 * SQ GATHER subdescriptor 1849 * Must follow HDR descriptor 1850 */ 1851static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, 1852 int size, uint64_t data) 1853{ 1854 struct sq_gather_subdesc *gather; 1855 1856 qentry &= (sq->dmem.q_len - 1); 1857 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry); 1858 1859 memset(gather, 0, SND_QUEUE_DESC_SIZE); 1860 gather->subdesc_type = SQ_DESC_TYPE_GATHER; 1861 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD; 1862 gather->size = size; 1863 gather->addr = data; 1864} 1865 1866/* Put an mbuf to a SQ for packet transfer. */ 1867int 1868nicvf_tx_mbuf_locked(struct snd_queue *sq, struct mbuf *mbuf) 1869{ 1870 bus_dma_segment_t segs[256]; 1871 struct nicvf *nic; 1872 struct snd_buff *snd_buff; 1873 size_t seg; 1874 int nsegs, qentry; 1875 int subdesc_cnt; 1876 int err; 1877 1878 NICVF_TX_LOCK_ASSERT(sq); 1879 1880 if (sq->free_cnt == 0) 1881 return (ENOBUFS); 1882 1883 snd_buff = &sq->snd_buff[sq->tail]; 1884 1885 err = bus_dmamap_load_mbuf_sg(sq->snd_buff_dmat, snd_buff->dmap, 1886 mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1887 if (err != 0) { 1888 /* ARM64TODO: Add mbuf defragmenting if we lack maps */ 1889 return (err); 1890 } 1891 1892 /* Set how many subdescriptors is required */ 1893 nic = sq->nic; 1894 if (mbuf->m_pkthdr.tso_segsz != 0 && nic->hw_tso) 1895 subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; 1896 else 1897 subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT + nsegs - 1; 1898 1899 if (subdesc_cnt > sq->free_cnt) { 1900 /* ARM64TODO: Add mbuf defragmentation if we lack descriptors */ 1901 bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); 1902 return (ENOBUFS); 1903 } 1904 1905 qentry = nicvf_get_sq_desc(sq, subdesc_cnt); 1906 1907 /* Add SQ header subdesc */ 1908 err = nicvf_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, mbuf, 1909 mbuf->m_pkthdr.len); 1910 if (err != 0) { 1911 bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); 1912 return (err); 1913 } 1914 1915 /* Add SQ gather subdescs */ 1916 for (seg = 0; seg < nsegs; seg++) { 1917 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1918 nicvf_sq_add_gather_subdesc(sq, qentry, segs[seg].ds_len, 1919 segs[seg].ds_addr); 1920 } 1921 1922 /* make sure all memory stores are done before ringing doorbell */ 1923 bus_dmamap_sync(sq->dmem.dmat, sq->dmem.dmap, BUS_DMASYNC_PREWRITE); 1924 1925 dprintf(sq->nic->dev, "%s: sq->idx: %d, subdesc_cnt: %d\n", 1926 __func__, sq->idx, subdesc_cnt); 1927 /* Inform HW to xmit new packet */ 1928 nicvf_queue_reg_write(sq->nic, NIC_QSET_SQ_0_7_DOOR, 1929 sq->idx, subdesc_cnt); 1930 return (0); 1931} 1932 1933static __inline u_int 1934frag_num(u_int i) 1935{ 1936#if BYTE_ORDER == BIG_ENDIAN 1937 return ((i & ~3) + 3 - (i & 3)); 1938#else 1939 return (i); 1940#endif 1941} 1942 1943/* Returns MBUF for a received packet */ 1944struct mbuf * 1945nicvf_get_rcv_mbuf(struct nicvf *nic, struct cqe_rx_t *cqe_rx) 1946{ 1947 int frag; 1948 int payload_len = 0; 1949 struct mbuf *mbuf; 1950 struct mbuf *mbuf_frag; 1951 uint16_t *rb_lens = NULL; 1952 uint64_t *rb_ptrs = NULL; 1953 1954 mbuf = NULL; 1955 rb_lens = (uint16_t *)((uint8_t *)cqe_rx + (3 * sizeof(uint64_t))); 1956 rb_ptrs = (uint64_t *)((uint8_t *)cqe_rx + (6 * sizeof(uint64_t))); 1957 1958 dprintf(nic->dev, "%s rb_cnt %d rb0_ptr %lx rb0_sz %d\n", 1959 __func__, cqe_rx->rb_cnt, cqe_rx->rb0_ptr, cqe_rx->rb0_sz); 1960 1961 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) { 1962 payload_len = rb_lens[frag_num(frag)]; 1963 if (frag == 0) { 1964 /* First fragment */ 1965 mbuf = nicvf_rb_ptr_to_mbuf(nic, 1966 (*rb_ptrs - cqe_rx->align_pad)); 1967 mbuf->m_len = payload_len; 1968 mbuf->m_data += cqe_rx->align_pad; 1969 if_setrcvif(mbuf, nic->ifp); 1970 } else { 1971 /* Add fragments */ 1972 mbuf_frag = nicvf_rb_ptr_to_mbuf(nic, *rb_ptrs); 1973 m_append(mbuf, payload_len, mbuf_frag->m_data); 1974 m_freem(mbuf_frag); 1975 } 1976 /* Next buffer pointer */ 1977 rb_ptrs++; 1978 } 1979 1980 if (__predict_true(mbuf != NULL)) { 1981 m_fixhdr(mbuf); 1982 mbuf->m_pkthdr.flowid = cqe_rx->rq_idx; 1983 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE); 1984 if (__predict_true((if_getcapenable(nic->ifp) & IFCAP_RXCSUM) != 0)) { 1985 /* 1986 * HW by default verifies IP & TCP/UDP/SCTP checksums 1987 */ 1988 1989 /* XXX: Do we need to include IP with options too? */ 1990 if (__predict_true(cqe_rx->l3_type == L3TYPE_IPV4 || 1991 cqe_rx->l3_type == L3TYPE_IPV6)) { 1992 mbuf->m_pkthdr.csum_flags = 1993 (CSUM_IP_CHECKED | CSUM_IP_VALID); 1994 } 1995 if (cqe_rx->l4_type == L4TYPE_TCP || 1996 cqe_rx->l4_type == L4TYPE_UDP || 1997 cqe_rx->l4_type == L4TYPE_SCTP) { 1998 mbuf->m_pkthdr.csum_flags |= 1999 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2000 mbuf->m_pkthdr.csum_data = htons(0xffff); 2001 } 2002 } 2003 } 2004 2005 return (mbuf); 2006} 2007 2008/* Enable interrupt */ 2009void 2010nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) 2011{ 2012 uint64_t reg_val; 2013 2014 reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); 2015 2016 switch (int_type) { 2017 case NICVF_INTR_CQ: 2018 reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); 2019 break; 2020 case NICVF_INTR_SQ: 2021 reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); 2022 break; 2023 case NICVF_INTR_RBDR: 2024 reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); 2025 break; 2026 case NICVF_INTR_PKT_DROP: 2027 reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); 2028 break; 2029 case NICVF_INTR_TCP_TIMER: 2030 reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); 2031 break; 2032 case NICVF_INTR_MBOX: 2033 reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); 2034 break; 2035 case NICVF_INTR_QS_ERR: 2036 reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); 2037 break; 2038 default: 2039 device_printf(nic->dev, 2040 "Failed to enable interrupt: unknown type\n"); 2041 break; 2042 } 2043 2044 nicvf_reg_write(nic, NIC_VF_ENA_W1S, reg_val); 2045} 2046 2047/* Disable interrupt */ 2048void 2049nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx) 2050{ 2051 uint64_t reg_val = 0; 2052 2053 switch (int_type) { 2054 case NICVF_INTR_CQ: 2055 reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); 2056 break; 2057 case NICVF_INTR_SQ: 2058 reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); 2059 break; 2060 case NICVF_INTR_RBDR: 2061 reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); 2062 break; 2063 case NICVF_INTR_PKT_DROP: 2064 reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); 2065 break; 2066 case NICVF_INTR_TCP_TIMER: 2067 reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); 2068 break; 2069 case NICVF_INTR_MBOX: 2070 reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); 2071 break; 2072 case NICVF_INTR_QS_ERR: 2073 reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); 2074 break; 2075 default: 2076 device_printf(nic->dev, 2077 "Failed to disable interrupt: unknown type\n"); 2078 break; 2079 } 2080 2081 nicvf_reg_write(nic, NIC_VF_ENA_W1C, reg_val); 2082} 2083 2084/* Clear interrupt */ 2085void 2086nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx) 2087{ 2088 uint64_t reg_val = 0; 2089 2090 switch (int_type) { 2091 case NICVF_INTR_CQ: 2092 reg_val = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); 2093 break; 2094 case NICVF_INTR_SQ: 2095 reg_val = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); 2096 break; 2097 case NICVF_INTR_RBDR: 2098 reg_val = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); 2099 break; 2100 case NICVF_INTR_PKT_DROP: 2101 reg_val = (1UL << NICVF_INTR_PKT_DROP_SHIFT); 2102 break; 2103 case NICVF_INTR_TCP_TIMER: 2104 reg_val = (1UL << NICVF_INTR_TCP_TIMER_SHIFT); 2105 break; 2106 case NICVF_INTR_MBOX: 2107 reg_val = (1UL << NICVF_INTR_MBOX_SHIFT); 2108 break; 2109 case NICVF_INTR_QS_ERR: 2110 reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); 2111 break; 2112 default: 2113 device_printf(nic->dev, 2114 "Failed to clear interrupt: unknown type\n"); 2115 break; 2116 } 2117 2118 nicvf_reg_write(nic, NIC_VF_INT, reg_val); 2119} 2120 2121/* Check if interrupt is enabled */ 2122int 2123nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx) 2124{ 2125 uint64_t reg_val; 2126 uint64_t mask = 0xff; 2127 2128 reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); 2129 2130 switch (int_type) { 2131 case NICVF_INTR_CQ: 2132 mask = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); 2133 break; 2134 case NICVF_INTR_SQ: 2135 mask = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); 2136 break; 2137 case NICVF_INTR_RBDR: 2138 mask = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); 2139 break; 2140 case NICVF_INTR_PKT_DROP: 2141 mask = NICVF_INTR_PKT_DROP_MASK; 2142 break; 2143 case NICVF_INTR_TCP_TIMER: 2144 mask = NICVF_INTR_TCP_TIMER_MASK; 2145 break; 2146 case NICVF_INTR_MBOX: 2147 mask = NICVF_INTR_MBOX_MASK; 2148 break; 2149 case NICVF_INTR_QS_ERR: 2150 mask = NICVF_INTR_QS_ERR_MASK; 2151 break; 2152 default: 2153 device_printf(nic->dev, 2154 "Failed to check interrupt enable: unknown type\n"); 2155 break; 2156 } 2157 2158 return (reg_val & mask); 2159} 2160 2161void 2162nicvf_update_rq_stats(struct nicvf *nic, int rq_idx) 2163{ 2164 struct rcv_queue *rq; 2165 2166#define GET_RQ_STATS(reg) \ 2167 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\ 2168 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 2169 2170 rq = &nic->qs->rq[rq_idx]; 2171 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS); 2172 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS); 2173} 2174 2175void 2176nicvf_update_sq_stats(struct nicvf *nic, int sq_idx) 2177{ 2178 struct snd_queue *sq; 2179 2180#define GET_SQ_STATS(reg) \ 2181 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\ 2182 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 2183 2184 sq = &nic->qs->sq[sq_idx]; 2185 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS); 2186 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS); 2187} 2188 2189/* Check for errors in the receive cmp.queue entry */ 2190int 2191nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cmp_queue *cq, 2192 struct cqe_rx_t *cqe_rx) 2193{ 2194 struct nicvf_hw_stats *stats = &nic->hw_stats; 2195 struct nicvf_drv_stats *drv_stats = &nic->drv_stats; 2196 2197 if (!cqe_rx->err_level && !cqe_rx->err_opcode) { 2198 drv_stats->rx_frames_ok++; 2199 return (0); 2200 } 2201 2202 switch (cqe_rx->err_opcode) { 2203 case CQ_RX_ERROP_RE_PARTIAL: 2204 stats->rx_bgx_truncated_pkts++; 2205 break; 2206 case CQ_RX_ERROP_RE_JABBER: 2207 stats->rx_jabber_errs++; 2208 break; 2209 case CQ_RX_ERROP_RE_FCS: 2210 stats->rx_fcs_errs++; 2211 break; 2212 case CQ_RX_ERROP_RE_RX_CTL: 2213 stats->rx_bgx_errs++; 2214 break; 2215 case CQ_RX_ERROP_PREL2_ERR: 2216 stats->rx_prel2_errs++; 2217 break; 2218 case CQ_RX_ERROP_L2_MAL: 2219 stats->rx_l2_hdr_malformed++; 2220 break; 2221 case CQ_RX_ERROP_L2_OVERSIZE: 2222 stats->rx_oversize++; 2223 break; 2224 case CQ_RX_ERROP_L2_UNDERSIZE: 2225 stats->rx_undersize++; 2226 break; 2227 case CQ_RX_ERROP_L2_LENMISM: 2228 stats->rx_l2_len_mismatch++; 2229 break; 2230 case CQ_RX_ERROP_L2_PCLP: 2231 stats->rx_l2_pclp++; 2232 break; 2233 case CQ_RX_ERROP_IP_NOT: 2234 stats->rx_ip_ver_errs++; 2235 break; 2236 case CQ_RX_ERROP_IP_CSUM_ERR: 2237 stats->rx_ip_csum_errs++; 2238 break; 2239 case CQ_RX_ERROP_IP_MAL: 2240 stats->rx_ip_hdr_malformed++; 2241 break; 2242 case CQ_RX_ERROP_IP_MALD: 2243 stats->rx_ip_payload_malformed++; 2244 break; 2245 case CQ_RX_ERROP_IP_HOP: 2246 stats->rx_ip_ttl_errs++; 2247 break; 2248 case CQ_RX_ERROP_L3_PCLP: 2249 stats->rx_l3_pclp++; 2250 break; 2251 case CQ_RX_ERROP_L4_MAL: 2252 stats->rx_l4_malformed++; 2253 break; 2254 case CQ_RX_ERROP_L4_CHK: 2255 stats->rx_l4_csum_errs++; 2256 break; 2257 case CQ_RX_ERROP_UDP_LEN: 2258 stats->rx_udp_len_errs++; 2259 break; 2260 case CQ_RX_ERROP_L4_PORT: 2261 stats->rx_l4_port_errs++; 2262 break; 2263 case CQ_RX_ERROP_TCP_FLAG: 2264 stats->rx_tcp_flag_errs++; 2265 break; 2266 case CQ_RX_ERROP_TCP_OFFSET: 2267 stats->rx_tcp_offset_errs++; 2268 break; 2269 case CQ_RX_ERROP_L4_PCLP: 2270 stats->rx_l4_pclp++; 2271 break; 2272 case CQ_RX_ERROP_RBDR_TRUNC: 2273 stats->rx_truncated_pkts++; 2274 break; 2275 } 2276 2277 return (1); 2278} 2279 2280/* Check for errors in the send cmp.queue entry */ 2281int 2282nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cmp_queue *cq, 2283 struct cqe_send_t *cqe_tx) 2284{ 2285 struct cmp_queue_stats *stats = &cq->stats; 2286 2287 switch (cqe_tx->send_status) { 2288 case CQ_TX_ERROP_GOOD: 2289 stats->tx.good++; 2290 return (0); 2291 case CQ_TX_ERROP_DESC_FAULT: 2292 stats->tx.desc_fault++; 2293 break; 2294 case CQ_TX_ERROP_HDR_CONS_ERR: 2295 stats->tx.hdr_cons_err++; 2296 break; 2297 case CQ_TX_ERROP_SUBDC_ERR: 2298 stats->tx.subdesc_err++; 2299 break; 2300 case CQ_TX_ERROP_IMM_SIZE_OFLOW: 2301 stats->tx.imm_size_oflow++; 2302 break; 2303 case CQ_TX_ERROP_DATA_SEQUENCE_ERR: 2304 stats->tx.data_seq_err++; 2305 break; 2306 case CQ_TX_ERROP_MEM_SEQUENCE_ERR: 2307 stats->tx.mem_seq_err++; 2308 break; 2309 case CQ_TX_ERROP_LOCK_VIOL: 2310 stats->tx.lock_viol++; 2311 break; 2312 case CQ_TX_ERROP_DATA_FAULT: 2313 stats->tx.data_fault++; 2314 break; 2315 case CQ_TX_ERROP_TSTMP_CONFLICT: 2316 stats->tx.tstmp_conflict++; 2317 break; 2318 case CQ_TX_ERROP_TSTMP_TIMEOUT: 2319 stats->tx.tstmp_timeout++; 2320 break; 2321 case CQ_TX_ERROP_MEM_FAULT: 2322 stats->tx.mem_fault++; 2323 break; 2324 case CQ_TX_ERROP_CK_OVERLAP: 2325 stats->tx.csum_overlap++; 2326 break; 2327 case CQ_TX_ERROP_CK_OFLOW: 2328 stats->tx.csum_overflow++; 2329 break; 2330 } 2331 2332 return (1); 2333} 2334