nic_main.c revision 297457
1/* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/vnic/nic_main.c 297457 2016-03-31 16:44:32Z zbb $ 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/vnic/nic_main.c 297457 2016-03-31 16:44:32Z zbb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bitset.h> 36#include <sys/bitstring.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/pciio.h> 44#include <sys/pcpu.h> 45#include <sys/proc.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/cpuset.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_media.h> 55 56#include <machine/bus.h> 57#include <machine/_inttypes.h> 58 59#include <dev/pci/pcireg.h> 60#include <dev/pci/pcivar.h> 61 62#include <sys/dnv.h> 63#include <sys/nv.h> 64#ifdef PCI_IOV 65#include <sys/iov_schema.h> 66#include <dev/pci/pci_iov.h> 67#endif 68 69#include "thunder_bgx.h" 70#include "nic_reg.h" 71#include "nic.h" 72#include "q_struct.h" 73 74#define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" 75 76#define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) 77 78#define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) 79#define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) 80#define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) 81 82/* Structure to be used by the SR-IOV for VF configuration schemas */ 83struct nicvf_info { 84 boolean_t vf_enabled; 85 int vf_flags; 86}; 87 88struct nicpf { 89 device_t dev; 90 uint8_t node; 91 u_int flags; 92 uint8_t num_vf_en; /* No of VF enabled */ 93 struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; 94 struct resource * reg_base; /* Register start address */ 95 struct pkind_cfg pkind; 96 uint8_t vf_lmac_map[MAX_LMAC]; 97 boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; 98 99 struct callout check_link; 100 struct mtx check_link_mtx; 101 102 uint8_t link[MAX_LMAC]; 103 uint8_t duplex[MAX_LMAC]; 104 uint32_t speed[MAX_LMAC]; 105 uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; 106 uint16_t rss_ind_tbl_size; 107 108 /* MSI-X */ 109 boolean_t msix_enabled; 110 uint8_t num_vec; 111 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; 112 struct resource * msix_table_res; 113}; 114 115static int nicpf_probe(device_t); 116static int nicpf_attach(device_t); 117static int nicpf_detach(device_t); 118 119#ifdef PCI_IOV 120static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); 121static void nicpf_iov_uninit(device_t); 122static int nicpf_iov_add_vf(device_t, uint16_t, const nvlist_t *); 123#endif 124 125static device_method_t nicpf_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, nicpf_probe), 128 DEVMETHOD(device_attach, nicpf_attach), 129 DEVMETHOD(device_detach, nicpf_detach), 130 /* PCI SR-IOV interface */ 131#ifdef PCI_IOV 132 DEVMETHOD(pci_iov_init, nicpf_iov_init), 133 DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), 134 DEVMETHOD(pci_iov_add_vf, nicpf_iov_add_vf), 135#endif 136 DEVMETHOD_END, 137}; 138 139static driver_t nicpf_driver = { 140 "vnicpf", 141 nicpf_methods, 142 sizeof(struct nicpf), 143}; 144 145static devclass_t nicpf_devclass; 146 147DRIVER_MODULE(nicpf, pci, nicpf_driver, nicpf_devclass, 0, 0); 148MODULE_DEPEND(nicpf, pci, 1, 1, 1); 149MODULE_DEPEND(nicpf, ether, 1, 1, 1); 150MODULE_DEPEND(nicpf, thunder_bgx, 1, 1, 1); 151 152static int nicpf_alloc_res(struct nicpf *); 153static void nicpf_free_res(struct nicpf *); 154static void nic_set_lmac_vf_mapping(struct nicpf *); 155static void nic_init_hw(struct nicpf *); 156static int nic_sriov_init(device_t, struct nicpf *); 157static void nic_poll_for_link(void *); 158static int nic_register_interrupts(struct nicpf *); 159static void nic_unregister_interrupts(struct nicpf *); 160 161/* 162 * Device interface 163 */ 164static int 165nicpf_probe(device_t dev) 166{ 167 uint16_t vendor_id; 168 uint16_t device_id; 169 170 vendor_id = pci_get_vendor(dev); 171 device_id = pci_get_device(dev); 172 173 if (vendor_id == PCI_VENDOR_ID_CAVIUM && 174 device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { 175 device_set_desc(dev, VNIC_PF_DEVSTR); 176 return (BUS_PROBE_DEFAULT); 177 } 178 179 return (ENXIO); 180} 181 182static int 183nicpf_attach(device_t dev) 184{ 185 struct nicpf *nic; 186 int err; 187 188 nic = device_get_softc(dev); 189 nic->dev = dev; 190 191 /* Enable bus mastering */ 192 pci_enable_busmaster(dev); 193 194 /* Allocate PCI resources */ 195 err = nicpf_alloc_res(nic); 196 if (err != 0) { 197 device_printf(dev, "Could not allocate PCI resources\n"); 198 return (err); 199 } 200 201 nic->node = nic_get_node_id(nic->reg_base); 202 203 /* Enable Traffic Network Switch (TNS) bypass mode by default */ 204 nic->flags &= ~NIC_TNS_ENABLED; 205 nic_set_lmac_vf_mapping(nic); 206 207 /* Initialize hardware */ 208 nic_init_hw(nic); 209 210 /* Set RSS TBL size for each VF */ 211 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 212 213 /* Setup interrupts */ 214 err = nic_register_interrupts(nic); 215 if (err != 0) 216 goto err_free_res; 217 218 /* Configure SRIOV */ 219 err = nic_sriov_init(dev, nic); 220 if (err != 0) 221 goto err_free_intr; 222 223 if (nic->flags & NIC_TNS_ENABLED) 224 return (0); 225 226 mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); 227 /* Register physical link status poll callout */ 228 callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); 229 mtx_lock(&nic->check_link_mtx); 230 nic_poll_for_link(nic); 231 mtx_unlock(&nic->check_link_mtx); 232 233 return (0); 234 235err_free_intr: 236 nic_unregister_interrupts(nic); 237err_free_res: 238 nicpf_free_res(nic); 239 pci_disable_busmaster(dev); 240 241 return (err); 242} 243 244static int 245nicpf_detach(device_t dev) 246{ 247 struct nicpf *nic; 248 249 nic = device_get_softc(dev); 250 251 callout_drain(&nic->check_link); 252 mtx_destroy(&nic->check_link_mtx); 253 254 nic_unregister_interrupts(nic); 255 nicpf_free_res(nic); 256 pci_disable_busmaster(dev); 257 258 return (0); 259} 260 261/* 262 * SR-IOV interface 263 */ 264#ifdef PCI_IOV 265static int 266nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 267{ 268 struct nicpf *nic; 269 270 nic = device_get_softc(dev); 271 272 if (num_vfs == 0) 273 return (ENXIO); 274 275 nic->flags |= NIC_SRIOV_ENABLED; 276 277 return (0); 278} 279 280static void 281nicpf_iov_uninit(device_t dev) 282{ 283 284 /* ARM64TODO: Implement this function */ 285} 286 287static int 288nicpf_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 289{ 290 const void *mac; 291 struct nicpf *nic; 292 size_t size; 293 int bgx, lmac; 294 295 nic = device_get_softc(dev); 296 297 if ((nic->flags & NIC_SRIOV_ENABLED) == 0) 298 return (ENXIO); 299 300 if (vfnum > (nic->num_vf_en - 1)) 301 return (EINVAL); 302 303 if (nvlist_exists_binary(params, "mac-addr") != 0) { 304 mac = nvlist_get_binary(params, "mac-addr", &size); 305 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 306 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 307 bgx_set_lmac_mac(nic->node, bgx, lmac, mac); 308 } 309 310 return (0); 311} 312#endif 313 314/* 315 * Helper routines 316 */ 317static int 318nicpf_alloc_res(struct nicpf *nic) 319{ 320 device_t dev; 321 int rid; 322 323 dev = nic->dev; 324 325 rid = VNIC_PF_REG_RID; 326 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 327 RF_ACTIVE); 328 if (nic->reg_base == NULL) { 329 /* For verbose output print some more details */ 330 if (bootverbose) { 331 device_printf(dev, 332 "Could not allocate registers memory\n"); 333 } 334 return (ENXIO); 335 } 336 337 return (0); 338} 339 340static void 341nicpf_free_res(struct nicpf *nic) 342{ 343 device_t dev; 344 345 dev = nic->dev; 346 347 if (nic->reg_base != NULL) { 348 bus_release_resource(dev, SYS_RES_MEMORY, 349 rman_get_rid(nic->reg_base), nic->reg_base); 350 } 351} 352 353/* Register read/write APIs */ 354static __inline void 355nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, 356 uint64_t val) 357{ 358 359 bus_write_8(nic->reg_base, offset, val); 360} 361 362static __inline uint64_t 363nic_reg_read(struct nicpf *nic, uint64_t offset) 364{ 365 uint64_t val; 366 367 val = bus_read_8(nic->reg_base, offset); 368 return (val); 369} 370 371/* PF -> VF mailbox communication APIs */ 372static void 373nic_enable_mbx_intr(struct nicpf *nic) 374{ 375 376 /* Enable mailbox interrupt for all 128 VFs */ 377 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); 378 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); 379} 380 381static void 382nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 383{ 384 385 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); 386} 387 388static uint64_t 389nic_get_mbx_addr(int vf) 390{ 391 392 return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); 393} 394 395/* 396 * Send a mailbox message to VF 397 * @vf: vf to which this message to be sent 398 * @mbx: Message to be sent 399 */ 400static void 401nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 402{ 403 bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); 404 uint64_t *msg = (uint64_t *)mbx; 405 406 /* 407 * In first revision HW, mbox interrupt is triggerred 408 * when PF writes to MBOX(1), in next revisions when 409 * PF writes to MBOX(0) 410 */ 411 if (pass1_silicon(nic->dev)) { 412 nic_reg_write(nic, mbx_addr + 0, msg[0]); 413 nic_reg_write(nic, mbx_addr + 8, msg[1]); 414 } else { 415 nic_reg_write(nic, mbx_addr + 8, msg[1]); 416 nic_reg_write(nic, mbx_addr + 0, msg[0]); 417 } 418} 419 420/* 421 * Responds to VF's READY message with VF's 422 * ID, node, MAC address e.t.c 423 * @vf: VF which sent READY message 424 */ 425static void 426nic_mbx_send_ready(struct nicpf *nic, int vf) 427{ 428 union nic_mbx mbx = {}; 429 int bgx_idx, lmac; 430 const char *mac; 431 432 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 433 mbx.nic_cfg.vf_id = vf; 434 435 if (nic->flags & NIC_TNS_ENABLED) 436 mbx.nic_cfg.tns_mode = NIC_TNS_MODE; 437 else 438 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 439 440 if (vf < MAX_LMAC) { 441 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 442 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 443 444 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 445 if (mac) { 446 memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, 447 ETHER_ADDR_LEN); 448 } 449 } 450 mbx.nic_cfg.node_id = nic->node; 451 452 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; 453 454 nic_send_msg_to_vf(nic, vf, &mbx); 455} 456 457/* 458 * ACKs VF's mailbox message 459 * @vf: VF to which ACK to be sent 460 */ 461static void 462nic_mbx_send_ack(struct nicpf *nic, int vf) 463{ 464 union nic_mbx mbx = {}; 465 466 mbx.msg.msg = NIC_MBOX_MSG_ACK; 467 nic_send_msg_to_vf(nic, vf, &mbx); 468} 469 470/* 471 * NACKs VF's mailbox message that PF is not able to 472 * complete the action 473 * @vf: VF to which ACK to be sent 474 */ 475static void 476nic_mbx_send_nack(struct nicpf *nic, int vf) 477{ 478 union nic_mbx mbx = {}; 479 480 mbx.msg.msg = NIC_MBOX_MSG_NACK; 481 nic_send_msg_to_vf(nic, vf, &mbx); 482} 483 484/* 485 * Flush all in flight receive packets to memory and 486 * bring down an active RQ 487 */ 488static int 489nic_rcv_queue_sw_sync(struct nicpf *nic) 490{ 491 uint16_t timeout = ~0x00; 492 493 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 494 /* Wait till sync cycle is finished */ 495 while (timeout) { 496 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 497 break; 498 timeout--; 499 } 500 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 501 if (!timeout) { 502 device_printf(nic->dev, "Receive queue software sync failed\n"); 503 return (ETIMEDOUT); 504 } 505 return (0); 506} 507 508/* Get BGX Rx/Tx stats and respond to VF's request */ 509static void 510nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 511{ 512 int bgx_idx, lmac; 513 union nic_mbx mbx = {}; 514 515 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 516 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 517 518 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 519 mbx.bgx_stats.vf_id = bgx->vf_id; 520 mbx.bgx_stats.rx = bgx->rx; 521 mbx.bgx_stats.idx = bgx->idx; 522 if (bgx->rx != 0) { 523 mbx.bgx_stats.stats = 524 bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); 525 } else { 526 mbx.bgx_stats.stats = 527 bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); 528 } 529 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 530} 531 532/* Update hardware min/max frame size */ 533static int 534nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 535{ 536 537 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { 538 device_printf(nic->dev, 539 "Invalid MTU setting from VF%d rejected, " 540 "should be between %d and %d\n", 541 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); 542 return (EINVAL); 543 } 544 new_frs += ETHER_HDR_LEN; 545 if (new_frs <= nic->pkind.maxlen) 546 return (0); 547 548 nic->pkind.maxlen = new_frs; 549 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); 550 return (0); 551} 552 553/* Set minimum transmit packet size */ 554static void 555nic_set_tx_pkt_pad(struct nicpf *nic, int size) 556{ 557 int lmac; 558 uint64_t lmac_cfg; 559 560 /* Max value that can be set is 60 */ 561 if (size > 60) 562 size = 60; 563 564 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { 565 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 566 lmac_cfg &= ~(0xF << 2); 567 lmac_cfg |= ((size / 4) << 2); 568 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 569 } 570} 571 572/* 573 * Function to check number of LMACs present and set VF::LMAC mapping. 574 * Mapping will be used while initializing channels. 575 */ 576static void 577nic_set_lmac_vf_mapping(struct nicpf *nic) 578{ 579 unsigned bgx_map = bgx_get_map(nic->node); 580 int bgx, next_bgx_lmac = 0; 581 int lmac, lmac_cnt = 0; 582 uint64_t lmac_credit; 583 584 nic->num_vf_en = 0; 585 if (nic->flags & NIC_TNS_ENABLED) { 586 nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; 587 return; 588 } 589 590 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { 591 if ((bgx_map & (1 << bgx)) == 0) 592 continue; 593 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 594 for (lmac = 0; lmac < lmac_cnt; lmac++) 595 nic->vf_lmac_map[next_bgx_lmac++] = 596 NIC_SET_VF_LMAC_MAP(bgx, lmac); 597 nic->num_vf_en += lmac_cnt; 598 599 /* Program LMAC credits */ 600 lmac_credit = (1UL << 1); /* channel credit enable */ 601 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 602 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 603 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 604 NIC_HW_MAX_FRS) / 16) << 12); 605 lmac = bgx * MAX_LMAC_PER_BGX; 606 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { 607 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 608 lmac_credit); 609 } 610 } 611} 612 613#define TNS_PORT0_BLOCK 6 614#define TNS_PORT1_BLOCK 7 615#define BGX0_BLOCK 8 616#define BGX1_BLOCK 9 617 618static void 619nic_init_hw(struct nicpf *nic) 620{ 621 int i; 622 623 /* Enable NIC HW block */ 624 nic_reg_write(nic, NIC_PF_CFG, 0x3); 625 626 /* Enable backpressure */ 627 nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); 628 629 if (nic->flags & NIC_TNS_ENABLED) { 630 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 631 (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); 632 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 633 (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); 634 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 635 (1UL << 63) | TNS_PORT0_BLOCK); 636 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 637 (1UL << 63) | TNS_PORT1_BLOCK); 638 639 } else { 640 /* Disable TNS mode on both interfaces */ 641 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 642 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 643 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 644 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 645 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 646 (1UL << 63) | BGX0_BLOCK); 647 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 648 (1UL << 63) | BGX1_BLOCK); 649 } 650 651 /* PKIND configuration */ 652 nic->pkind.minlen = 0; 653 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; 654 nic->pkind.lenerr_en = 1; 655 nic->pkind.rx_hdr = 0; 656 nic->pkind.hdr_sl = 0; 657 658 for (i = 0; i < NIC_MAX_PKIND; i++) { 659 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 660 *(uint64_t *)&nic->pkind); 661 } 662 663 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 664 665 /* Timer config */ 666 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 667 668 /* Enable VLAN ethertype matching and stripping */ 669 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 670 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); 671} 672 673/* Channel parse index configuration */ 674static void 675nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 676{ 677 uint32_t vnic, bgx, lmac, chan; 678 uint32_t padd, cpi_count = 0; 679 uint64_t cpi_base, cpi, rssi_base, rssi; 680 uint8_t qset, rq_idx = 0; 681 682 vnic = cfg->vf_id; 683 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 684 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 685 686 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 687 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); 688 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); 689 690 /* Rx channel configuration */ 691 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 692 (1UL << 63) | (vnic << 0)); 693 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 694 ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); 695 696 if (cfg->cpi_alg == CPI_ALG_NONE) 697 cpi_count = 1; 698 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 699 cpi_count = 8; 700 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 701 cpi_count = 16; 702 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 703 cpi_count = NIC_MAX_CPI_PER_LMAC; 704 705 /* RSS Qset, Qidx mapping */ 706 qset = cfg->vf_id; 707 rssi = rssi_base; 708 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 709 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 710 (qset << 3) | rq_idx); 711 rq_idx++; 712 } 713 714 rssi = 0; 715 cpi = cpi_base; 716 for (; cpi < (cpi_base + cpi_count); cpi++) { 717 /* Determine port to channel adder */ 718 if (cfg->cpi_alg != CPI_ALG_DIFF) 719 padd = cpi % cpi_count; 720 else 721 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 722 723 /* Leave RSS_SIZE as '0' to disable RSS */ 724 if (pass1_silicon(nic->dev)) { 725 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 726 (vnic << 24) | (padd << 16) | (rssi_base + rssi)); 727 } else { 728 /* Set MPI_ALG to '0' to disable MCAM parsing */ 729 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 730 (padd << 16)); 731 /* MPI index is same as CPI if MPI_ALG is not enabled */ 732 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), 733 (vnic << 24) | (rssi_base + rssi)); 734 } 735 736 if ((rssi + 1) >= cfg->rq_cnt) 737 continue; 738 739 if (cfg->cpi_alg == CPI_ALG_VLAN) 740 rssi++; 741 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 742 rssi = ((cpi - cpi_base) & 0xe) >> 1; 743 else if (cfg->cpi_alg == CPI_ALG_DIFF) 744 rssi = ((cpi - cpi_base) & 0x38) >> 3; 745 } 746 nic->cpi_base[cfg->vf_id] = cpi_base; 747} 748 749/* 750 * 4 level transmit side scheduler configutation 751 * for TNS bypass mode 752 * 753 * Sample configuration for SQ0 754 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 755 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 756 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 757 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 758 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 759 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 760 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 761 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 762 */ 763static void 764nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) 765{ 766 uint32_t bgx, lmac, chan; 767 uint32_t tl2, tl3, tl4; 768 uint32_t rr_quantum; 769 uint8_t sq_idx = sq->sq_num; 770 uint8_t pqs_vnic; 771 772 pqs_vnic = vnic; 773 774 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 775 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 776 777 /* 24 bytes for FCS, IPG and preamble */ 778 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 779 780 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); 781 tl4 += sq_idx; 782 783 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); 784 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 785 ((uint64_t)vnic << NIC_QS_ID_SHIFT) | 786 ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); 787 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 788 ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); 789 790 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 791 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 792 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 793 /* Enable backpressure on the channel */ 794 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 795 796 tl2 = tl3 >> 2; 797 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 798 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 799 /* No priorities as of now */ 800 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 801} 802 803static int 804nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 805{ 806 int bgx_idx, lmac_idx; 807 808 if (lbk->vf_id > MAX_LMAC) 809 return (ENXIO); 810 811 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 812 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 813 814 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 815 816 return (0); 817} 818 819/* Interrupt handler to handle mailbox messages from VFs */ 820static void 821nic_handle_mbx_intr(struct nicpf *nic, int vf) 822{ 823 union nic_mbx mbx = {}; 824 uint64_t *mbx_data; 825 uint64_t mbx_addr; 826 uint64_t reg_addr; 827 uint64_t cfg; 828 int bgx, lmac; 829 int i; 830 int ret = 0; 831 832 nic->mbx_lock[vf] = TRUE; 833 834 mbx_addr = nic_get_mbx_addr(vf); 835 mbx_data = (uint64_t *)&mbx; 836 837 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 838 *mbx_data = nic_reg_read(nic, mbx_addr); 839 mbx_data++; 840 mbx_addr += sizeof(uint64_t); 841 } 842 843 switch (mbx.msg.msg) { 844 case NIC_MBOX_MSG_READY: 845 nic_mbx_send_ready(nic, vf); 846 if (vf < MAX_LMAC) { 847 nic->link[vf] = 0; 848 nic->duplex[vf] = 0; 849 nic->speed[vf] = 0; 850 } 851 ret = 1; 852 break; 853 case NIC_MBOX_MSG_QS_CFG: 854 reg_addr = NIC_PF_QSET_0_127_CFG | 855 (mbx.qs.num << NIC_QS_ID_SHIFT); 856 cfg = mbx.qs.cfg; 857 nic_reg_write(nic, reg_addr, cfg); 858 break; 859 case NIC_MBOX_MSG_RQ_CFG: 860 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 861 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 862 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 863 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 864 break; 865 case NIC_MBOX_MSG_RQ_BP_CFG: 866 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 867 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 868 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 869 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 870 break; 871 case NIC_MBOX_MSG_RQ_SW_SYNC: 872 ret = nic_rcv_queue_sw_sync(nic); 873 break; 874 case NIC_MBOX_MSG_RQ_DROP_CFG: 875 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 876 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 877 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 878 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 879 break; 880 case NIC_MBOX_MSG_SQ_CFG: 881 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 882 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 883 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 884 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 885 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 886 break; 887 case NIC_MBOX_MSG_SET_MAC: 888 lmac = mbx.mac.vf_id; 889 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 890 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 891 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 892 break; 893 case NIC_MBOX_MSG_SET_MAX_FRS: 894 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); 895 break; 896 case NIC_MBOX_MSG_CPI_CFG: 897 nic_config_cpi(nic, &mbx.cpi_cfg); 898 break; 899 case NIC_MBOX_MSG_CFG_DONE: 900 /* Last message of VF config msg sequence */ 901 nic->vf_info[vf].vf_enabled = TRUE; 902 goto unlock; 903 case NIC_MBOX_MSG_SHUTDOWN: 904 /* First msg in VF teardown sequence */ 905 nic->vf_info[vf].vf_enabled = FALSE; 906 break; 907 case NIC_MBOX_MSG_BGX_STATS: 908 nic_get_bgx_stats(nic, &mbx.bgx_stats); 909 goto unlock; 910 case NIC_MBOX_MSG_LOOPBACK: 911 ret = nic_config_loopback(nic, &mbx.lbk); 912 break; 913 default: 914 device_printf(nic->dev, 915 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 916 break; 917 } 918 919 if (ret == 0) 920 nic_mbx_send_ack(nic, vf); 921 else if (mbx.msg.msg != NIC_MBOX_MSG_READY) 922 nic_mbx_send_nack(nic, vf); 923unlock: 924 nic->mbx_lock[vf] = FALSE; 925} 926 927static void 928nic_mbx_intr_handler(struct nicpf *nic, int mbx) 929{ 930 uint64_t intr; 931 uint8_t vf, vf_per_mbx_reg = 64; 932 933 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 934 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 935 if (intr & (1UL << vf)) { 936 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 937 nic_clear_mbx_intr(nic, vf, mbx); 938 } 939 } 940} 941 942static void 943nic_mbx0_intr_handler (void *arg) 944{ 945 struct nicpf *nic = (struct nicpf *)arg; 946 947 nic_mbx_intr_handler(nic, 0); 948} 949 950static void 951nic_mbx1_intr_handler (void *arg) 952{ 953 struct nicpf *nic = (struct nicpf *)arg; 954 955 nic_mbx_intr_handler(nic, 1); 956} 957 958static int 959nic_enable_msix(struct nicpf *nic) 960{ 961 struct pci_devinfo *dinfo; 962 int rid, count; 963 int ret; 964 965 dinfo = device_get_ivars(nic->dev); 966 rid = dinfo->cfg.msix.msix_table_bar; 967 nic->msix_table_res = 968 bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 969 if (nic->msix_table_res == NULL) { 970 device_printf(nic->dev, 971 "Could not allocate memory for MSI-X table\n"); 972 return (ENXIO); 973 } 974 975 count = nic->num_vec = NIC_PF_MSIX_VECTORS; 976 977 ret = pci_alloc_msix(nic->dev, &count); 978 if ((ret != 0) || (count != nic->num_vec)) { 979 device_printf(nic->dev, 980 "Request for #%d msix vectors failed, error: %d\n", 981 nic->num_vec, ret); 982 return (ret); 983 } 984 985 nic->msix_enabled = 1; 986 return (0); 987} 988 989static void 990nic_disable_msix(struct nicpf *nic) 991{ 992 if (nic->msix_enabled) { 993 pci_release_msi(nic->dev); 994 nic->msix_enabled = 0; 995 nic->num_vec = 0; 996 } 997} 998 999static void 1000nic_free_all_interrupts(struct nicpf *nic) 1001{ 1002 int irq; 1003 1004 for (irq = 0; irq < nic->num_vec; irq++) { 1005 if (nic->msix_entries[irq].irq_res == NULL) 1006 continue; 1007 if (nic->msix_entries[irq].handle != NULL) { 1008 bus_teardown_intr(nic->dev, 1009 nic->msix_entries[irq].irq_res, 1010 nic->msix_entries[irq].handle); 1011 } 1012 1013 bus_release_resource(nic->dev, SYS_RES_IRQ, irq, 1014 nic->msix_entries[irq].irq_res); 1015 } 1016} 1017 1018static int 1019nic_register_interrupts(struct nicpf *nic) 1020{ 1021 int irq, rid; 1022 int ret; 1023 1024 /* Enable MSI-X */ 1025 ret = nic_enable_msix(nic); 1026 if (ret != 0) 1027 return (ret); 1028 1029 /* Register mailbox interrupt handlers */ 1030 irq = NIC_PF_INTR_ID_MBOX0; 1031 rid = irq + 1; 1032 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1033 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1034 if (nic->msix_entries[irq].irq_res == NULL) { 1035 ret = ENXIO; 1036 goto fail; 1037 } 1038 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1039 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, 1040 &nic->msix_entries[irq].handle); 1041 if (ret != 0) 1042 goto fail; 1043 1044 irq = NIC_PF_INTR_ID_MBOX1; 1045 rid = irq + 1; 1046 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1047 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1048 if (nic->msix_entries[irq].irq_res == NULL) { 1049 ret = ENXIO; 1050 goto fail; 1051 } 1052 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1053 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, 1054 &nic->msix_entries[irq].handle); 1055 if (ret != 0) 1056 goto fail; 1057 1058 /* Enable mailbox interrupt */ 1059 nic_enable_mbx_intr(nic); 1060 return (0); 1061 1062fail: 1063 nic_free_all_interrupts(nic); 1064 return (ret); 1065} 1066 1067static void 1068nic_unregister_interrupts(struct nicpf *nic) 1069{ 1070 1071 nic_free_all_interrupts(nic); 1072 nic_disable_msix(nic); 1073} 1074 1075static int nic_sriov_init(device_t dev, struct nicpf *nic) 1076{ 1077#ifdef PCI_IOV 1078 nvlist_t *pf_schema, *vf_schema; 1079 int iov_pos; 1080 int err; 1081 uint16_t total_vf_cnt; 1082 1083 err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 1084 if (err != 0) { 1085 device_printf(dev, 1086 "SR-IOV capability is not found in PCIe config space\n"); 1087 return (err); 1088 } 1089 /* Fix-up the number of enabled VFs */ 1090 total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); 1091 if (total_vf_cnt == 0) 1092 return (ENXIO); 1093 1094 /* Attach SR-IOV */ 1095 pf_schema = pci_iov_schema_alloc_node(); 1096 vf_schema = pci_iov_schema_alloc_node(); 1097 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 1098 /* 1099 * All VFs can change their MACs. 1100 * This flag will be ignored but we set it just for the record. 1101 */ 1102 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 1103 IOV_SCHEMA_HASDEFAULT, TRUE); 1104 1105 err = pci_iov_attach(dev, pf_schema, vf_schema); 1106 if (err != 0) { 1107 device_printf(dev, 1108 "Failed to initialize SR-IOV (error=%d)\n", 1109 err); 1110 return (err); 1111 } 1112#endif 1113 return (0); 1114} 1115 1116/* 1117 * Poll for BGX LMAC link status and update corresponding VF 1118 * if there is a change, valid only if internal L2 switch 1119 * is not present otherwise VF link is always treated as up 1120 */ 1121static void 1122nic_poll_for_link(void *arg) 1123{ 1124 union nic_mbx mbx = {}; 1125 struct nicpf *nic; 1126 struct bgx_link_status link; 1127 uint8_t vf, bgx, lmac; 1128 1129 nic = (struct nicpf *)arg; 1130 1131 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1132 1133 for (vf = 0; vf < nic->num_vf_en; vf++) { 1134 /* Poll only if VF is UP */ 1135 if (!nic->vf_info[vf].vf_enabled) 1136 continue; 1137 1138 /* Get BGX, LMAC indices for the VF */ 1139 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1140 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1141 /* Get interface link status */ 1142 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1143 1144 /* Inform VF only if link status changed */ 1145 if (nic->link[vf] == link.link_up) 1146 continue; 1147 1148 if (!nic->mbx_lock[vf]) { 1149 nic->link[vf] = link.link_up; 1150 nic->duplex[vf] = link.duplex; 1151 nic->speed[vf] = link.speed; 1152 1153 /* Send a mbox message to VF with current link status */ 1154 mbx.link_status.link_up = link.link_up; 1155 mbx.link_status.duplex = link.duplex; 1156 mbx.link_status.speed = link.speed; 1157 nic_send_msg_to_vf(nic, vf, &mbx); 1158 } 1159 } 1160 callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); 1161} 1162