nic_main.c revision 296037
1/* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/vnic/nic_main.c 296037 2016-02-25 14:26:13Z zbb $ 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/vnic/nic_main.c 296037 2016-02-25 14:26:13Z zbb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bitset.h> 36#include <sys/bitstring.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/pciio.h> 44#include <sys/pcpu.h> 45#include <sys/proc.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/cpuset.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_media.h> 55 56#include <machine/bus.h> 57#include <machine/_inttypes.h> 58 59#include <dev/pci/pcireg.h> 60#include <dev/pci/pcivar.h> 61 62#include <sys/dnv.h> 63#include <sys/nv.h> 64#ifdef PCI_IOV 65#include <sys/iov_schema.h> 66#include <dev/pci/pci_iov.h> 67#endif 68 69#include "thunder_bgx.h" 70#include "nic_reg.h" 71#include "nic.h" 72#include "q_struct.h" 73 74#define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" 75 76#define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) 77 78#define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) 79#define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) 80#define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) 81 82/* Structure to be used by the SR-IOV for VF configuration schemas */ 83struct nicvf_info { 84 boolean_t vf_enabled; 85 int vf_flags; 86}; 87 88struct nicpf { 89 device_t dev; 90 uint8_t node; 91 u_int flags; 92 uint8_t num_vf_en; /* No of VF enabled */ 93 struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; 94 struct resource * reg_base; /* Register start address */ 95 struct pkind_cfg pkind; 96 uint8_t vf_lmac_map[MAX_LMAC]; 97 boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; 98 99 struct callout check_link; 100 struct mtx check_link_mtx; 101 102 uint8_t link[MAX_LMAC]; 103 uint8_t duplex[MAX_LMAC]; 104 uint32_t speed[MAX_LMAC]; 105 uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; 106 uint16_t rss_ind_tbl_size; 107 108 /* MSI-X */ 109 boolean_t msix_enabled; 110 uint8_t num_vec; 111 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; 112 struct resource * msix_table_res; 113}; 114 115static int nicpf_probe(device_t); 116static int nicpf_attach(device_t); 117static int nicpf_detach(device_t); 118 119#ifdef PCI_IOV 120static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); 121static void nicpf_iov_uninit(device_t); 122static int nicpf_iov_addr_vf(device_t, uint16_t, const nvlist_t *); 123#endif 124 125static device_method_t nicpf_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, nicpf_probe), 128 DEVMETHOD(device_attach, nicpf_attach), 129 DEVMETHOD(device_detach, nicpf_detach), 130 /* PCI SR-IOV interface */ 131#ifdef PCI_IOV 132 DEVMETHOD(pci_iov_init, nicpf_iov_init), 133 DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), 134 DEVMETHOD(pci_iov_add_vf, nicpf_iov_addr_vf), 135#endif 136 DEVMETHOD_END, 137}; 138 139static driver_t nicpf_driver = { 140 "vnicpf", 141 nicpf_methods, 142 sizeof(struct nicpf), 143}; 144 145static devclass_t nicpf_devclass; 146 147DRIVER_MODULE(nicpf, pci, nicpf_driver, nicpf_devclass, 0, 0); 148MODULE_DEPEND(nicpf, pci, 1, 1, 1); 149MODULE_DEPEND(nicpf, ether, 1, 1, 1); 150MODULE_DEPEND(nicpf, thunder_bgx, 1, 1, 1); 151 152static int nicpf_alloc_res(struct nicpf *); 153static void nicpf_free_res(struct nicpf *); 154static void nic_set_lmac_vf_mapping(struct nicpf *); 155static void nic_init_hw(struct nicpf *); 156static int nic_sriov_init(device_t, struct nicpf *); 157static void nic_poll_for_link(void *); 158static int nic_register_interrupts(struct nicpf *); 159static void nic_unregister_interrupts(struct nicpf *); 160 161/* 162 * Device interface 163 */ 164static int 165nicpf_probe(device_t dev) 166{ 167 uint16_t vendor_id; 168 uint16_t device_id; 169 170 vendor_id = pci_get_vendor(dev); 171 device_id = pci_get_device(dev); 172 173 if (vendor_id == PCI_VENDOR_ID_CAVIUM && 174 device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { 175 device_set_desc(dev, VNIC_PF_DEVSTR); 176 return (BUS_PROBE_DEFAULT); 177 } 178 179 return (ENXIO); 180} 181 182static int 183nicpf_attach(device_t dev) 184{ 185 struct nicpf *nic; 186 int err; 187 188 nic = device_get_softc(dev); 189 nic->dev = dev; 190 191 /* Enable bus mastering */ 192 pci_enable_busmaster(dev); 193 194 /* Allocate PCI resources */ 195 err = nicpf_alloc_res(nic); 196 if (err != 0) { 197 device_printf(dev, "Could not allocate PCI resources\n"); 198 return (err); 199 } 200 201 nic->node = nic_get_node_id(nic->reg_base); 202 203 /* Enable Traffic Network Switch (TNS) bypass mode by default */ 204 nic->flags &= ~NIC_TNS_ENABLED; 205 nic_set_lmac_vf_mapping(nic); 206 207 /* Initialize hardware */ 208 nic_init_hw(nic); 209 210 /* Set RSS TBL size for each VF */ 211 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 212 213 /* Setup interrupts */ 214 err = nic_register_interrupts(nic); 215 if (err != 0) 216 goto err_free_res; 217 218 /* Configure SRIOV */ 219 err = nic_sriov_init(dev, nic); 220 if (err != 0) 221 goto err_free_intr; 222 223 if (nic->flags & NIC_TNS_ENABLED) 224 return (0); 225 226 mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); 227 /* Register physical link status poll callout */ 228 callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); 229 mtx_lock(&nic->check_link_mtx); 230 nic_poll_for_link(nic); 231 mtx_unlock(&nic->check_link_mtx); 232 233 return (0); 234 235err_free_intr: 236 nic_unregister_interrupts(nic); 237err_free_res: 238 nicpf_free_res(nic); 239 pci_disable_busmaster(dev); 240 241 return (err); 242} 243 244static int 245nicpf_detach(device_t dev) 246{ 247 struct nicpf *nic; 248 249 nic = device_get_softc(dev); 250 251 callout_drain(&nic->check_link); 252 mtx_destroy(&nic->check_link_mtx); 253 254 nic_unregister_interrupts(nic); 255 nicpf_free_res(nic); 256 pci_disable_busmaster(dev); 257 258 return (0); 259} 260 261/* 262 * SR-IOV interface 263 */ 264#ifdef PCI_IOV 265static int 266nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 267{ 268 struct nicpf *nic; 269 270 nic = device_get_softc(dev); 271 272 nic->num_vf_en = 0; 273 if (num_vfs == 0) 274 return (ENXIO); 275 if (num_vfs > MAX_NUM_VFS_SUPPORTED) 276 return (EINVAL); 277 278 /* 279 * Just set variables here. 280 * The number of VFs will be written to configuration 281 * space later in PCI_ADD_VF(). 282 */ 283 nic->num_vf_en = num_vfs; 284 nic->flags |= NIC_SRIOV_ENABLED; 285 286 return (0); 287} 288 289static void 290nicpf_iov_uninit(device_t dev) 291{ 292 293 /* ARM64TODO: Implement this function */ 294} 295 296static int 297nicpf_iov_addr_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 298{ 299 const void *mac; 300 struct nicpf *nic; 301 size_t size; 302 int bgx, lmac; 303 304 nic = device_get_softc(dev); 305 306 if ((nic->flags & NIC_SRIOV_ENABLED) == 0) 307 return (ENXIO); 308 309 if (nvlist_exists_binary(params, "mac-addr") != 0) { 310 mac = nvlist_get_binary(params, "mac-addr", &size); 311 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 312 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 313 bgx_set_lmac_mac(nic->node, bgx, lmac, mac); 314 } 315 316 return (0); 317} 318#endif 319 320/* 321 * Helper routines 322 */ 323static int 324nicpf_alloc_res(struct nicpf *nic) 325{ 326 device_t dev; 327 int rid; 328 329 dev = nic->dev; 330 331 rid = VNIC_PF_REG_RID; 332 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 333 RF_ACTIVE); 334 if (nic->reg_base == NULL) { 335 /* For verbose output print some more details */ 336 if (bootverbose) { 337 device_printf(dev, 338 "Could not allocate registers memory\n"); 339 } 340 return (ENXIO); 341 } 342 343 return (0); 344} 345 346static void 347nicpf_free_res(struct nicpf *nic) 348{ 349 device_t dev; 350 351 dev = nic->dev; 352 353 if (nic->reg_base != NULL) { 354 bus_release_resource(dev, SYS_RES_MEMORY, 355 rman_get_rid(nic->reg_base), nic->reg_base); 356 } 357} 358 359/* Register read/write APIs */ 360static __inline void 361nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, 362 uint64_t val) 363{ 364 365 bus_write_8(nic->reg_base, offset, val); 366} 367 368static __inline uint64_t 369nic_reg_read(struct nicpf *nic, uint64_t offset) 370{ 371 uint64_t val; 372 373 val = bus_read_8(nic->reg_base, offset); 374 return (val); 375} 376 377/* PF -> VF mailbox communication APIs */ 378static void 379nic_enable_mbx_intr(struct nicpf *nic) 380{ 381 382 /* Enable mailbox interrupt for all 128 VFs */ 383 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); 384 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); 385} 386 387static void 388nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 389{ 390 391 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); 392} 393 394static uint64_t 395nic_get_mbx_addr(int vf) 396{ 397 398 return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); 399} 400 401/* 402 * Send a mailbox message to VF 403 * @vf: vf to which this message to be sent 404 * @mbx: Message to be sent 405 */ 406static void 407nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 408{ 409 bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); 410 uint64_t *msg = (uint64_t *)mbx; 411 412 /* 413 * In first revision HW, mbox interrupt is triggerred 414 * when PF writes to MBOX(1), in next revisions when 415 * PF writes to MBOX(0) 416 */ 417 if (pass1_silicon(nic->dev)) { 418 nic_reg_write(nic, mbx_addr + 0, msg[0]); 419 nic_reg_write(nic, mbx_addr + 8, msg[1]); 420 } else { 421 nic_reg_write(nic, mbx_addr + 8, msg[1]); 422 nic_reg_write(nic, mbx_addr + 0, msg[0]); 423 } 424} 425 426/* 427 * Responds to VF's READY message with VF's 428 * ID, node, MAC address e.t.c 429 * @vf: VF which sent READY message 430 */ 431static void 432nic_mbx_send_ready(struct nicpf *nic, int vf) 433{ 434 union nic_mbx mbx = {}; 435 int bgx_idx, lmac; 436 const char *mac; 437 438 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 439 mbx.nic_cfg.vf_id = vf; 440 441 if (nic->flags & NIC_TNS_ENABLED) 442 mbx.nic_cfg.tns_mode = NIC_TNS_MODE; 443 else 444 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 445 446 if (vf < MAX_LMAC) { 447 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 448 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 449 450 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 451 if (mac) { 452 memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, 453 ETHER_ADDR_LEN); 454 } 455 } 456 mbx.nic_cfg.node_id = nic->node; 457 458 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; 459 460 nic_send_msg_to_vf(nic, vf, &mbx); 461} 462 463/* 464 * ACKs VF's mailbox message 465 * @vf: VF to which ACK to be sent 466 */ 467static void 468nic_mbx_send_ack(struct nicpf *nic, int vf) 469{ 470 union nic_mbx mbx = {}; 471 472 mbx.msg.msg = NIC_MBOX_MSG_ACK; 473 nic_send_msg_to_vf(nic, vf, &mbx); 474} 475 476/* 477 * NACKs VF's mailbox message that PF is not able to 478 * complete the action 479 * @vf: VF to which ACK to be sent 480 */ 481static void 482nic_mbx_send_nack(struct nicpf *nic, int vf) 483{ 484 union nic_mbx mbx = {}; 485 486 mbx.msg.msg = NIC_MBOX_MSG_NACK; 487 nic_send_msg_to_vf(nic, vf, &mbx); 488} 489 490/* 491 * Flush all in flight receive packets to memory and 492 * bring down an active RQ 493 */ 494static int 495nic_rcv_queue_sw_sync(struct nicpf *nic) 496{ 497 uint16_t timeout = ~0x00; 498 499 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 500 /* Wait till sync cycle is finished */ 501 while (timeout) { 502 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 503 break; 504 timeout--; 505 } 506 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 507 if (!timeout) { 508 device_printf(nic->dev, "Receive queue software sync failed\n"); 509 return (ETIMEDOUT); 510 } 511 return (0); 512} 513 514/* Get BGX Rx/Tx stats and respond to VF's request */ 515static void 516nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 517{ 518 int bgx_idx, lmac; 519 union nic_mbx mbx = {}; 520 521 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 522 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 523 524 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 525 mbx.bgx_stats.vf_id = bgx->vf_id; 526 mbx.bgx_stats.rx = bgx->rx; 527 mbx.bgx_stats.idx = bgx->idx; 528 if (bgx->rx != 0) { 529 mbx.bgx_stats.stats = 530 bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); 531 } else { 532 mbx.bgx_stats.stats = 533 bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); 534 } 535 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 536} 537 538/* Update hardware min/max frame size */ 539static int 540nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 541{ 542 543 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { 544 device_printf(nic->dev, 545 "Invalid MTU setting from VF%d rejected, " 546 "should be between %d and %d\n", 547 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); 548 return (EINVAL); 549 } 550 new_frs += ETHER_HDR_LEN; 551 if (new_frs <= nic->pkind.maxlen) 552 return (0); 553 554 nic->pkind.maxlen = new_frs; 555 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); 556 return (0); 557} 558 559/* Set minimum transmit packet size */ 560static void 561nic_set_tx_pkt_pad(struct nicpf *nic, int size) 562{ 563 int lmac; 564 uint64_t lmac_cfg; 565 566 /* Max value that can be set is 60 */ 567 if (size > 60) 568 size = 60; 569 570 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { 571 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 572 lmac_cfg &= ~(0xF << 2); 573 lmac_cfg |= ((size / 4) << 2); 574 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 575 } 576} 577 578/* 579 * Function to check number of LMACs present and set VF::LMAC mapping. 580 * Mapping will be used while initializing channels. 581 */ 582static void 583nic_set_lmac_vf_mapping(struct nicpf *nic) 584{ 585 unsigned bgx_map = bgx_get_map(nic->node); 586 int bgx, next_bgx_lmac = 0; 587 int lmac, lmac_cnt = 0; 588 uint64_t lmac_credit; 589 590 nic->num_vf_en = 0; 591 if (nic->flags & NIC_TNS_ENABLED) { 592 nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; 593 return; 594 } 595 596 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { 597 if ((bgx_map & (1 << bgx)) == 0) 598 continue; 599 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 600 for (lmac = 0; lmac < lmac_cnt; lmac++) 601 nic->vf_lmac_map[next_bgx_lmac++] = 602 NIC_SET_VF_LMAC_MAP(bgx, lmac); 603 nic->num_vf_en += lmac_cnt; 604 605 /* Program LMAC credits */ 606 lmac_credit = (1UL << 1); /* channel credit enable */ 607 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 608 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 609 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 610 NIC_HW_MAX_FRS) / 16) << 12); 611 lmac = bgx * MAX_LMAC_PER_BGX; 612 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { 613 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 614 lmac_credit); 615 } 616 } 617} 618 619#define TNS_PORT0_BLOCK 6 620#define TNS_PORT1_BLOCK 7 621#define BGX0_BLOCK 8 622#define BGX1_BLOCK 9 623 624static void 625nic_init_hw(struct nicpf *nic) 626{ 627 int i; 628 629 /* Enable NIC HW block */ 630 nic_reg_write(nic, NIC_PF_CFG, 0x3); 631 632 /* Enable backpressure */ 633 nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); 634 635 if (nic->flags & NIC_TNS_ENABLED) { 636 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 637 (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); 638 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 639 (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); 640 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 641 (1UL << 63) | TNS_PORT0_BLOCK); 642 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 643 (1UL << 63) | TNS_PORT1_BLOCK); 644 645 } else { 646 /* Disable TNS mode on both interfaces */ 647 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 648 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 649 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 650 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 651 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 652 (1UL << 63) | BGX0_BLOCK); 653 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 654 (1UL << 63) | BGX1_BLOCK); 655 } 656 657 /* PKIND configuration */ 658 nic->pkind.minlen = 0; 659 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; 660 nic->pkind.lenerr_en = 1; 661 nic->pkind.rx_hdr = 0; 662 nic->pkind.hdr_sl = 0; 663 664 for (i = 0; i < NIC_MAX_PKIND; i++) { 665 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 666 *(uint64_t *)&nic->pkind); 667 } 668 669 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 670 671 /* Timer config */ 672 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 673 674 /* Enable VLAN ethertype matching and stripping */ 675 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 676 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); 677} 678 679/* Channel parse index configuration */ 680static void 681nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 682{ 683 uint32_t vnic, bgx, lmac, chan; 684 uint32_t padd, cpi_count = 0; 685 uint64_t cpi_base, cpi, rssi_base, rssi; 686 uint8_t qset, rq_idx = 0; 687 688 vnic = cfg->vf_id; 689 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 690 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 691 692 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 693 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); 694 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); 695 696 /* Rx channel configuration */ 697 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 698 (1UL << 63) | (vnic << 0)); 699 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 700 ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); 701 702 if (cfg->cpi_alg == CPI_ALG_NONE) 703 cpi_count = 1; 704 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 705 cpi_count = 8; 706 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 707 cpi_count = 16; 708 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 709 cpi_count = NIC_MAX_CPI_PER_LMAC; 710 711 /* RSS Qset, Qidx mapping */ 712 qset = cfg->vf_id; 713 rssi = rssi_base; 714 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 715 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 716 (qset << 3) | rq_idx); 717 rq_idx++; 718 } 719 720 rssi = 0; 721 cpi = cpi_base; 722 for (; cpi < (cpi_base + cpi_count); cpi++) { 723 /* Determine port to channel adder */ 724 if (cfg->cpi_alg != CPI_ALG_DIFF) 725 padd = cpi % cpi_count; 726 else 727 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 728 729 /* Leave RSS_SIZE as '0' to disable RSS */ 730 if (pass1_silicon(nic->dev)) { 731 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 732 (vnic << 24) | (padd << 16) | (rssi_base + rssi)); 733 } else { 734 /* Set MPI_ALG to '0' to disable MCAM parsing */ 735 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 736 (padd << 16)); 737 /* MPI index is same as CPI if MPI_ALG is not enabled */ 738 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), 739 (vnic << 24) | (rssi_base + rssi)); 740 } 741 742 if ((rssi + 1) >= cfg->rq_cnt) 743 continue; 744 745 if (cfg->cpi_alg == CPI_ALG_VLAN) 746 rssi++; 747 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 748 rssi = ((cpi - cpi_base) & 0xe) >> 1; 749 else if (cfg->cpi_alg == CPI_ALG_DIFF) 750 rssi = ((cpi - cpi_base) & 0x38) >> 3; 751 } 752 nic->cpi_base[cfg->vf_id] = cpi_base; 753} 754 755/* 756 * 4 level transmit side scheduler configutation 757 * for TNS bypass mode 758 * 759 * Sample configuration for SQ0 760 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 761 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 762 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 763 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 764 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 765 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 766 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 767 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 768 */ 769static void 770nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) 771{ 772 uint32_t bgx, lmac, chan; 773 uint32_t tl2, tl3, tl4; 774 uint32_t rr_quantum; 775 uint8_t sq_idx = sq->sq_num; 776 uint8_t pqs_vnic; 777 778 pqs_vnic = vnic; 779 780 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 781 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 782 783 /* 24 bytes for FCS, IPG and preamble */ 784 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 785 786 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); 787 tl4 += sq_idx; 788 789 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); 790 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 791 ((uint64_t)vnic << NIC_QS_ID_SHIFT) | 792 ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); 793 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 794 ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); 795 796 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 797 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 798 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 799 /* Enable backpressure on the channel */ 800 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 801 802 tl2 = tl3 >> 2; 803 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 804 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 805 /* No priorities as of now */ 806 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 807} 808 809static int 810nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 811{ 812 int bgx_idx, lmac_idx; 813 814 if (lbk->vf_id > MAX_LMAC) 815 return (ENXIO); 816 817 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 818 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 819 820 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 821 822 return (0); 823} 824 825/* Interrupt handler to handle mailbox messages from VFs */ 826static void 827nic_handle_mbx_intr(struct nicpf *nic, int vf) 828{ 829 union nic_mbx mbx = {}; 830 uint64_t *mbx_data; 831 uint64_t mbx_addr; 832 uint64_t reg_addr; 833 uint64_t cfg; 834 int bgx, lmac; 835 int i; 836 int ret = 0; 837 838 nic->mbx_lock[vf] = TRUE; 839 840 mbx_addr = nic_get_mbx_addr(vf); 841 mbx_data = (uint64_t *)&mbx; 842 843 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 844 *mbx_data = nic_reg_read(nic, mbx_addr); 845 mbx_data++; 846 mbx_addr += sizeof(uint64_t); 847 } 848 849 switch (mbx.msg.msg) { 850 case NIC_MBOX_MSG_READY: 851 nic_mbx_send_ready(nic, vf); 852 if (vf < MAX_LMAC) { 853 nic->link[vf] = 0; 854 nic->duplex[vf] = 0; 855 nic->speed[vf] = 0; 856 } 857 ret = 1; 858 break; 859 case NIC_MBOX_MSG_QS_CFG: 860 reg_addr = NIC_PF_QSET_0_127_CFG | 861 (mbx.qs.num << NIC_QS_ID_SHIFT); 862 cfg = mbx.qs.cfg; 863 nic_reg_write(nic, reg_addr, cfg); 864 break; 865 case NIC_MBOX_MSG_RQ_CFG: 866 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 867 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 868 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 869 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 870 break; 871 case NIC_MBOX_MSG_RQ_BP_CFG: 872 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 873 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 874 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 875 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 876 break; 877 case NIC_MBOX_MSG_RQ_SW_SYNC: 878 ret = nic_rcv_queue_sw_sync(nic); 879 break; 880 case NIC_MBOX_MSG_RQ_DROP_CFG: 881 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 882 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 883 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 884 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 885 break; 886 case NIC_MBOX_MSG_SQ_CFG: 887 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 888 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 889 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 890 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 891 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 892 break; 893 case NIC_MBOX_MSG_SET_MAC: 894 lmac = mbx.mac.vf_id; 895 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 896 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 897 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 898 break; 899 case NIC_MBOX_MSG_SET_MAX_FRS: 900 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); 901 break; 902 case NIC_MBOX_MSG_CPI_CFG: 903 nic_config_cpi(nic, &mbx.cpi_cfg); 904 break; 905 case NIC_MBOX_MSG_CFG_DONE: 906 /* Last message of VF config msg sequence */ 907 nic->vf_info[vf].vf_enabled = TRUE; 908 goto unlock; 909 case NIC_MBOX_MSG_SHUTDOWN: 910 /* First msg in VF teardown sequence */ 911 nic->vf_info[vf].vf_enabled = FALSE; 912 break; 913 case NIC_MBOX_MSG_BGX_STATS: 914 nic_get_bgx_stats(nic, &mbx.bgx_stats); 915 goto unlock; 916 case NIC_MBOX_MSG_LOOPBACK: 917 ret = nic_config_loopback(nic, &mbx.lbk); 918 break; 919 default: 920 device_printf(nic->dev, 921 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 922 break; 923 } 924 925 if (ret == 0) 926 nic_mbx_send_ack(nic, vf); 927 else if (mbx.msg.msg != NIC_MBOX_MSG_READY) 928 nic_mbx_send_nack(nic, vf); 929unlock: 930 nic->mbx_lock[vf] = FALSE; 931} 932 933static void 934nic_mbx_intr_handler(struct nicpf *nic, int mbx) 935{ 936 uint64_t intr; 937 uint8_t vf, vf_per_mbx_reg = 64; 938 939 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 940 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 941 if (intr & (1UL << vf)) { 942 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 943 nic_clear_mbx_intr(nic, vf, mbx); 944 } 945 } 946} 947 948static void 949nic_mbx0_intr_handler (void *arg) 950{ 951 struct nicpf *nic = (struct nicpf *)arg; 952 953 nic_mbx_intr_handler(nic, 0); 954} 955 956static void 957nic_mbx1_intr_handler (void *arg) 958{ 959 struct nicpf *nic = (struct nicpf *)arg; 960 961 nic_mbx_intr_handler(nic, 1); 962} 963 964static int 965nic_enable_msix(struct nicpf *nic) 966{ 967 struct pci_devinfo *dinfo; 968 int rid, count; 969 int ret; 970 971 dinfo = device_get_ivars(nic->dev); 972 rid = dinfo->cfg.msix.msix_table_bar; 973 nic->msix_table_res = 974 bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 975 if (nic->msix_table_res == NULL) { 976 device_printf(nic->dev, 977 "Could not allocate memory for MSI-X table\n"); 978 return (ENXIO); 979 } 980 981 count = nic->num_vec = NIC_PF_MSIX_VECTORS; 982 983 ret = pci_alloc_msix(nic->dev, &count); 984 if ((ret != 0) || (count != nic->num_vec)) { 985 device_printf(nic->dev, 986 "Request for #%d msix vectors failed, error: %d\n", 987 nic->num_vec, ret); 988 return (ret); 989 } 990 991 nic->msix_enabled = 1; 992 return (0); 993} 994 995static void 996nic_disable_msix(struct nicpf *nic) 997{ 998 if (nic->msix_enabled) { 999 pci_release_msi(nic->dev); 1000 nic->msix_enabled = 0; 1001 nic->num_vec = 0; 1002 } 1003} 1004 1005static void 1006nic_free_all_interrupts(struct nicpf *nic) 1007{ 1008 int irq; 1009 1010 for (irq = 0; irq < nic->num_vec; irq++) { 1011 if (nic->msix_entries[irq].irq_res == NULL) 1012 continue; 1013 if (nic->msix_entries[irq].handle != NULL) { 1014 bus_teardown_intr(nic->dev, 1015 nic->msix_entries[irq].irq_res, 1016 nic->msix_entries[irq].handle); 1017 } 1018 1019 bus_release_resource(nic->dev, SYS_RES_IRQ, irq, 1020 nic->msix_entries[irq].irq_res); 1021 } 1022} 1023 1024static int 1025nic_register_interrupts(struct nicpf *nic) 1026{ 1027 int irq, rid; 1028 int ret; 1029 1030 /* Enable MSI-X */ 1031 ret = nic_enable_msix(nic); 1032 if (ret != 0) 1033 return (ret); 1034 1035 /* Register mailbox interrupt handlers */ 1036 irq = NIC_PF_INTR_ID_MBOX0; 1037 rid = irq + 1; 1038 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1039 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1040 if (nic->msix_entries[irq].irq_res == NULL) { 1041 ret = ENXIO; 1042 goto fail; 1043 } 1044 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1045 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, 1046 &nic->msix_entries[irq].handle); 1047 if (ret != 0) 1048 goto fail; 1049 1050 irq = NIC_PF_INTR_ID_MBOX1; 1051 rid = irq + 1; 1052 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1053 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1054 if (nic->msix_entries[irq].irq_res == NULL) { 1055 ret = ENXIO; 1056 goto fail; 1057 } 1058 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1059 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, 1060 &nic->msix_entries[irq].handle); 1061 if (ret != 0) 1062 goto fail; 1063 1064 /* Enable mailbox interrupt */ 1065 nic_enable_mbx_intr(nic); 1066 return (0); 1067 1068fail: 1069 nic_free_all_interrupts(nic); 1070 return (ret); 1071} 1072 1073static void 1074nic_unregister_interrupts(struct nicpf *nic) 1075{ 1076 1077 nic_free_all_interrupts(nic); 1078 nic_disable_msix(nic); 1079} 1080 1081static int nic_sriov_init(device_t dev, struct nicpf *nic) 1082{ 1083#ifdef PCI_IOV 1084 nvlist_t *pf_schema, *vf_schema; 1085 int iov_pos; 1086 int err; 1087 uint16_t total_vf_cnt; 1088 1089 err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 1090 if (err != 0) { 1091 device_printf(dev, 1092 "SR-IOV capability is not found in PCIe config space\n"); 1093 return (err); 1094 } 1095 /* Fix-up the number of enabled VFs */ 1096 total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); 1097 if (total_vf_cnt < nic->num_vf_en) 1098 nic->num_vf_en = total_vf_cnt; 1099 1100 if (total_vf_cnt == 0) 1101 return (0); 1102 1103 /* Attach SR-IOV */ 1104 pf_schema = pci_iov_schema_alloc_node(); 1105 vf_schema = pci_iov_schema_alloc_node(); 1106 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 1107 /* 1108 * All VFs can change their MACs. 1109 * This flag will be ignored but we set it just for the record. 1110 */ 1111 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 1112 IOV_SCHEMA_HASDEFAULT, TRUE); 1113 1114 err = pci_iov_attach(dev, pf_schema, vf_schema); 1115 if (err != 0) { 1116 device_printf(dev, 1117 "Failed to initialize SR-IOV (error=%d)\n", 1118 err); 1119 nic->num_vf_en = 0; 1120 return (err); 1121 } 1122#endif 1123 return (0); 1124} 1125 1126/* 1127 * Poll for BGX LMAC link status and update corresponding VF 1128 * if there is a change, valid only if internal L2 switch 1129 * is not present otherwise VF link is always treated as up 1130 */ 1131static void 1132nic_poll_for_link(void *arg) 1133{ 1134 union nic_mbx mbx = {}; 1135 struct nicpf *nic; 1136 struct bgx_link_status link; 1137 uint8_t vf, bgx, lmac; 1138 1139 nic = (struct nicpf *)arg; 1140 1141 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1142 1143 for (vf = 0; vf < nic->num_vf_en; vf++) { 1144 /* Poll only if VF is UP */ 1145 if (!nic->vf_info[vf].vf_enabled) 1146 continue; 1147 1148 /* Get BGX, LMAC indices for the VF */ 1149 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1150 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1151 /* Get interface link status */ 1152 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1153 1154 /* Inform VF only if link status changed */ 1155 if (nic->link[vf] == link.link_up) 1156 continue; 1157 1158 if (!nic->mbx_lock[vf]) { 1159 nic->link[vf] = link.link_up; 1160 nic->duplex[vf] = link.duplex; 1161 nic->speed[vf] = link.speed; 1162 1163 /* Send a mbox message to VF with current link status */ 1164 mbx.link_status.link_up = link.link_up; 1165 mbx.link_status.duplex = link.duplex; 1166 mbx.link_status.speed = link.speed; 1167 nic_send_msg_to_vf(nic, vf, &mbx); 1168 } 1169 } 1170 callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); 1171} 1172