1192873Sweongyo/* $FreeBSD$ */ 2192873Sweongyo 3192873Sweongyo/*- 4192873Sweongyo * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 5192873Sweongyo * 6192873Sweongyo * Permission to use, copy, modify, and distribute this software for any 7192873Sweongyo * purpose with or without fee is hereby granted, provided that the above 8192873Sweongyo * copyright notice and this permission notice appear in all copies. 9192873Sweongyo * 10192873Sweongyo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11192873Sweongyo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12192873Sweongyo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13192873Sweongyo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14192873Sweongyo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15192873Sweongyo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16192873Sweongyo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17192873Sweongyo */ 18192873Sweongyo 19192873Sweongyo#define URTW_CONFIG_INDEX 0 20192873Sweongyo#define URTW_IFACE_INDEX 0 21192873Sweongyo 22192873Sweongyo/* for 8187 */ 23192873Sweongyo#define URTW_MAC0 0x0000 /* 1 byte */ 24192873Sweongyo#define URTW_MAC1 0x0001 /* 1 byte */ 25192873Sweongyo#define URTW_MAC2 0x0002 /* 1 byte */ 26192873Sweongyo#define URTW_MAC3 0x0003 /* 1 byte */ 27192873Sweongyo#define URTW_MAC4 0x0004 /* 1 byte */ 28192873Sweongyo#define URTW_MAC5 0x0005 /* 1 byte */ 29198194Sweongyo#define URTW_MAR 0x0008 /* 6 byte */ 30198194Sweongyo#define URTW_RXFIFO_CNT 0x0010 /* 1 byte */ 31198194Sweongyo#define URTW_TXFIFO_CNT 0x0012 /* 1 byte */ 32198194Sweongyo#define URTW_BQREQ 0x0013 /* 1 byte */ 33198194Sweongyo#define URTW_TSFT 0x0018 /* 6 byte */ 34198194Sweongyo#define URTW_TLPDA 0x0020 /* 4 byte */ 35198194Sweongyo#define URTW_TNPDA 0x0024 /* 4 byte */ 36198194Sweongyo#define URTW_THPDA 0x0028 /* 4 byte */ 37192873Sweongyo#define URTW_BRSR 0x002c /* 2 byte */ 38192873Sweongyo#define URTW_BRSR_MBR_8185 (0x0fff) 39198194Sweongyo#define URTW_8187B_EIFS 0x002d /* 1 byte for 8187B */ 40192873Sweongyo#define URTW_BSSID 0x002e /* 6 byte */ 41198194Sweongyo#define URTW_BRSR_8187B 0x0034 /* 2 byte for 8187B */ 42198194Sweongyo#define URTW_RESP_RATE 0x0034 /* 1 byte for 8187L */ 43192873Sweongyo#define URTW_RESP_MAX_RATE_SHIFT (4) 44192873Sweongyo#define URTW_RESP_MIN_RATE_SHIFT (0) 45192873Sweongyo#define URTW_EIFS 0x0035 /* 1 byte */ 46192873Sweongyo#define URTW_CMD 0x0037 /* 1 byte */ 47192873Sweongyo#define URTW_CMD_TX_ENABLE (0x4) 48192873Sweongyo#define URTW_CMD_RX_ENABLE (0x8) 49192873Sweongyo#define URTW_CMD_RST (0x10) 50198194Sweongyo#define URTW_INTR_MASK 0x003c /* 2 byte */ 51198194Sweongyo#define URTW_INTR_STATUS 0x003e /* 2 byte */ 52192873Sweongyo#define URTW_TX_CONF 0x0040 /* 4 byte */ 53192873Sweongyo#define URTW_TX_LOOPBACK_SHIFT (17) 54192873Sweongyo#define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT) 55192873Sweongyo#define URTW_TX_LOOPBACK_MAC (1 << URTW_TX_LOOPBACK_SHIFT) 56192873Sweongyo#define URTW_TX_LOOPBACK_BASEBAND (2 << URTW_TX_LOOPBACK_SHIFT) 57192873Sweongyo#define URTW_TX_LOOPBACK_CONTINUE (3 << URTW_TX_LOOPBACK_SHIFT) 58192873Sweongyo#define URTW_TX_LOOPBACK_MASK (0x60000) 59192873Sweongyo#define URTW_TX_DPRETRY_MASK (0xff00) 60192873Sweongyo#define URTW_TX_RTSRETRY_MASK (0xff) 61192873Sweongyo#define URTW_TX_DPRETRY_SHIFT (0) 62192873Sweongyo#define URTW_TX_RTSRETRY_SHIFT (8) 63192873Sweongyo#define URTW_TX_NOCRC (0x10000) 64192873Sweongyo#define URTW_TX_MXDMA_MASK (0xe00000) 65192873Sweongyo#define URTW_TX_MXDMA_1024 (6 << URTW_TX_MXDMA_SHIFT) 66192873Sweongyo#define URTW_TX_MXDMA_2048 (7 << URTW_TX_MXDMA_SHIFT) 67192873Sweongyo#define URTW_TX_MXDMA_SHIFT (21) 68192873Sweongyo#define URTW_TX_DISCW (1 << 20) 69192873Sweongyo#define URTW_TX_SWPLCPLEN (1 << 24) 70198194Sweongyo#define URTW_TX_R8187vD (5 << 25) 71198194Sweongyo#define URTW_TX_R8187vD_B (6 << 25) 72198194Sweongyo#define URTW_TX_HWMASK (7 << 25) 73192873Sweongyo#define URTW_TX_DISREQQSIZE (1 << 28) 74192873Sweongyo#define URTW_TX_HW_SEQNUM (1 << 30) 75258780Seadler#define URTW_TX_CWMIN (1U << 31) 76192873Sweongyo#define URTW_TX_NOICV (0x80000) 77192873Sweongyo#define URTW_RX 0x0044 /* 4 byte */ 78192873Sweongyo#define URTW_RX_9356SEL (1 << 6) 79192873Sweongyo#define URTW_RX_FILTER_MASK \ 80192873Sweongyo (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \ 81192873Sweongyo URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \ 82192873Sweongyo URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG | \ 83192873Sweongyo (1 << 21) | \ 84192873Sweongyo URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID) 85192873Sweongyo#define URTW_RX_FILTER_ALLMAC (0x00000001) 86192873Sweongyo#define URTW_RX_FILTER_NICMAC (0x00000002) 87192873Sweongyo#define URTW_RX_FILTER_MCAST (0x00000004) 88192873Sweongyo#define URTW_RX_FILTER_BCAST (0x00000008) 89192873Sweongyo#define URTW_RX_FILTER_CRCERR (0x00000020) 90192873Sweongyo#define URTW_RX_FILTER_ICVERR (0x00001000) 91192873Sweongyo#define URTW_RX_FILTER_DATA (0x00040000) 92192873Sweongyo#define URTW_RX_FILTER_CTL (0x00080000) 93192873Sweongyo#define URTW_RX_FILTER_MNG (0x00100000) 94192873Sweongyo#define URTW_RX_FILTER_PWR (0x00400000) 95192873Sweongyo#define URTW_RX_CHECK_BSSID (0x00800000) 96192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_MASK ((1 << 13) | (1 << 14) | (1 << 15)) 97192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_SHIFT (13) 98192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_128 (3) 99192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_256 (4) 100192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_512 (5) 101192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_1024 (6) 102192873Sweongyo#define URTW_RX_FIFO_THRESHOLD_NONE (7 << URTW_RX_FIFO_THRESHOLD_SHIFT) 103192873Sweongyo#define URTW_RX_AUTORESETPHY (1 << URTW_RX_AUTORESETPHY_SHIFT) 104192873Sweongyo#define URTW_RX_AUTORESETPHY_SHIFT (28) 105192873Sweongyo#define URTW_MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 106192873Sweongyo#define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT) 107192873Sweongyo#define URTW_MAX_RX_DMA_1024 (6) 108192873Sweongyo#define URTW_MAX_RX_DMA_SHIFT (10) 109258780Seadler#define URTW_RCR_ONLYERLPKT (1U << 31) 110192873Sweongyo#define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ 111198194Sweongyo#define URTW_INT_TBDA 0x004c /* 4 byte */ 112192873Sweongyo#define URTW_EPROM_CMD 0x0050 /* 1 byte */ 113192873Sweongyo#define URTW_EPROM_CMD_NORMAL (0x0) 114192873Sweongyo#define URTW_EPROM_CMD_NORMAL_MODE \ 115192873Sweongyo (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT) 116192873Sweongyo#define URTW_EPROM_CMD_LOAD (0x1) 117192873Sweongyo#define URTW_EPROM_CMD_PROGRAM (0x2) 118192873Sweongyo#define URTW_EPROM_CMD_PROGRAM_MODE \ 119192873Sweongyo (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT) 120192873Sweongyo#define URTW_EPROM_CMD_CONFIG (0x3) 121192873Sweongyo#define URTW_EPROM_CMD_SHIFT (6) 122192873Sweongyo#define URTW_EPROM_CMD_MASK ((1 << 7) | (1 << 6)) 123192873Sweongyo#define URTW_EPROM_READBIT (0x1) 124192873Sweongyo#define URTW_EPROM_WRITEBIT (0x2) 125192873Sweongyo#define URTW_EPROM_CK (0x4) 126192873Sweongyo#define URTW_EPROM_CS (0x8) 127198194Sweongyo#define URTW_CONFIG0 0x0051 /* 1 byte */ 128192873Sweongyo#define URTW_CONFIG1 0x0052 /* 1 byte */ 129192873Sweongyo#define URTW_CONFIG2 0x0053 /* 1 byte */ 130192873Sweongyo#define URTW_ANAPARAM 0x0054 /* 4 byte */ 131192873Sweongyo#define URTW_8225_ANAPARAM_ON (0xa0000a59) 132192873Sweongyo#define URTW_8225_ANAPARAM_OFF (0xa00beb59) 133192873Sweongyo#define URTW_8187B_8225_ANAPARAM_ON (0x45090658) 134192873Sweongyo#define URTW_8187B_8225_ANAPARAM_OFF (0x55480658) 135192873Sweongyo#define URTW_MSR 0x0058 /* 1 byte */ 136192873Sweongyo#define URTW_MSR_LINK_MASK ((1 << 2) | (1 << 3)) 137192873Sweongyo#define URTW_MSR_LINK_SHIFT (2) 138192873Sweongyo#define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT) 139192873Sweongyo#define URTW_MSR_LINK_ADHOC (1 << URTW_MSR_LINK_SHIFT) 140192873Sweongyo#define URTW_MSR_LINK_STA (2 << URTW_MSR_LINK_SHIFT) 141192873Sweongyo#define URTW_MSR_LINK_HOSTAP (3 << URTW_MSR_LINK_SHIFT) 142192873Sweongyo#define URTW_MSR_LINK_ENEDCA (1 << 4) 143192873Sweongyo#define URTW_CONFIG3 0x0059 /* 1 byte */ 144192873Sweongyo#define URTW_CONFIG3_ANAPARAM_WRITE (0x40) 145192873Sweongyo#define URTW_CONFIG3_GNT_SELECT (0x80) 146192873Sweongyo#define URTW_CONFIG3_ANAPARAM_W_SHIFT (6) 147192873Sweongyo#define URTW_CONFIG4 0x005a /* 1 byte */ 148192873Sweongyo#define URTW_CONFIG4_VCOOFF (1 << 7) 149192873Sweongyo#define URTW_TESTR 0x005b /* 1 byte */ 150192873Sweongyo#define URTW_PSR 0x005e /* 1 byte */ 151198194Sweongyo#define URTW_SECURITY 0x005f /* 1 byte */ 152192873Sweongyo#define URTW_ANAPARAM2 0x0060 /* 4 byte */ 153192873Sweongyo#define URTW_8225_ANAPARAM2_ON (0x860c7312) 154192873Sweongyo#define URTW_8225_ANAPARAM2_OFF (0x840dec11) 155192873Sweongyo#define URTW_8187B_8225_ANAPARAM2_ON (0x727f3f52) 156192873Sweongyo#define URTW_8187B_8225_ANAPARAM2_OFF (0x72003f50) 157192873Sweongyo#define URTW_BEACON_INTERVAL 0x0070 /* 2 byte */ 158192873Sweongyo#define URTW_ATIM_WND 0x0072 /* 2 byte */ 159192873Sweongyo#define URTW_BEACON_INTERVAL_TIME 0x0074 /* 2 byte */ 160192873Sweongyo#define URTW_ATIM_TR_ITV 0x0076 /* 2 byte */ 161198194Sweongyo#define URTW_PHY_DELAY 0x0078 /* 1 byte */ 162192873Sweongyo#define URTW_CARRIER_SCOUNT 0x0079 /* 1 byte */ 163192873Sweongyo#define URTW_PHY_MAGIC1 0x007c /* 1 byte */ 164192873Sweongyo#define URTW_PHY_MAGIC2 0x007d /* 1 byte */ 165192873Sweongyo#define URTW_PHY_MAGIC3 0x007e /* 1 byte */ 166192873Sweongyo#define URTW_PHY_MAGIC4 0x007f /* 1 byte */ 167192873Sweongyo#define URTW_RF_PINS_OUTPUT 0x0080 /* 2 byte */ 168192873Sweongyo#define URTW_RF_PINS_OUTPUT_MAGIC1 (0x3a0) 169192873Sweongyo#define URTW_BB_HOST_BANG_CLK (1 << 1) 170192873Sweongyo#define URTW_BB_HOST_BANG_EN (1 << 2) 171192873Sweongyo#define URTW_BB_HOST_BANG_RW (1 << 3) 172192873Sweongyo#define URTW_RF_PINS_ENABLE 0x0082 /* 2 byte */ 173192873Sweongyo#define URTW_RF_PINS_SELECT 0x0084 /* 2 byte */ 174192873Sweongyo#define URTW_ADDR_MAGIC1 0x0085 /* broken? */ 175192873Sweongyo#define URTW_RF_PINS_INPUT 0x0086 /* 2 byte */ 176192873Sweongyo#define URTW_RF_PINS_MAGIC1 (0xfff3) 177192873Sweongyo#define URTW_RF_PINS_MAGIC2 (0xfff0) 178192873Sweongyo#define URTW_RF_PINS_MAGIC3 (0x0007) 179192873Sweongyo#define URTW_RF_PINS_MAGIC4 (0xf) 180192873Sweongyo#define URTW_RF_PINS_MAGIC5 (0x0080) 181192873Sweongyo#define URTW_RF_PARA 0x0088 /* 4 byte */ 182192873Sweongyo#define URTW_RF_TIMING 0x008c /* 4 byte */ 183192873Sweongyo#define URTW_GP_ENABLE 0x0090 /* 1 byte */ 184192873Sweongyo#define URTW_GP_ENABLE_DATA_MAGIC1 (0x1) 185192873Sweongyo#define URTW_GPIO 0x0091 /* 1 byte */ 186192873Sweongyo#define URTW_GPIO_DATA_MAGIC1 (0x1) 187192873Sweongyo#define URTW_HSSI_PARA 0x0094 /* 4 byte */ 188192873Sweongyo#define URTW_TX_AGC_CTL 0x009c /* 1 byte */ 189192873Sweongyo#define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1) 190192873Sweongyo#define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2) 191192873Sweongyo#define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4) 192192873Sweongyo#define URTW_TX_GAIN_CCK 0x009d /* 1 byte */ 193192873Sweongyo#define URTW_TX_GAIN_OFDM 0x009e /* 1 byte */ 194192873Sweongyo#define URTW_TX_ANTENNA 0x009f /* 1 byte */ 195192873Sweongyo#define URTW_WPA_CONFIG 0x00b0 /* 1 byte */ 196192873Sweongyo#define URTW_SIFS 0x00b4 /* 1 byte */ 197192873Sweongyo#define URTW_DIFS 0x00b5 /* 1 byte */ 198192873Sweongyo#define URTW_SLOT 0x00b6 /* 1 byte */ 199192873Sweongyo#define URTW_CW_CONF 0x00bc /* 1 byte */ 200192873Sweongyo#define URTW_CW_CONF_PERPACKET_RETRY (0x2) 201192873Sweongyo#define URTW_CW_CONF_PERPACKET_CW (0x1) 202192873Sweongyo#define URTW_CW_VAL 0x00bd /* 1 byte */ 203192873Sweongyo#define URTW_RATE_FALLBACK 0x00be /* 1 byte */ 204192873Sweongyo#define URTW_RATE_FALLBACK_ENABLE (0x80) 205192873Sweongyo#define URTW_ACM_CONTROL 0x00bf /* 1 byte */ 206198194Sweongyo#define URTW_CONFIG5 0x00d8 /* 1 byte */ 207198194Sweongyo#define URTW_TXDMA_POLLING 0x00d9 /* 1 byte */ 208198194Sweongyo#define URTW_CWR 0x00dc /* 2 byte */ 209198194Sweongyo#define URTW_RETRY_CTR 0x00de /* 1 byte */ 210192873Sweongyo#define URTW_INT_MIG 0x00e2 /* 2 byte */ 211198194Sweongyo#define URTW_RDSAR 0x00e4 /* 4 byte */ 212192873Sweongyo#define URTW_TID_AC_MAP 0x00e8 /* 2 byte */ 213192873Sweongyo#define URTW_ANAPARAM3 0x00ee /* 1 byte */ 214192873Sweongyo#define URTW_8187B_8225_ANAPARAM3_ON (0x0) 215192873Sweongyo#define URTW_8187B_8225_ANAPARAM3_OFF (0x0) 216198194Sweongyo#define URTW_8187B_AC_VO 0x00f0 /* 4 byte for 8187B */ 217198194Sweongyo#define URTW_FEMR 0x00f4 /* 2 byte */ 218198194Sweongyo#define URTW_8187B_AC_VI 0x00f4 /* 4 byte for 8187B */ 219198194Sweongyo#define URTW_8187B_AC_BE 0x00f8 /* 4 byte for 8187B */ 220198194Sweongyo#define URTW_TALLY_CNT 0x00fa /* 2 byte */ 221192873Sweongyo#define URTW_TALLY_SEL 0x00fc /* 1 byte */ 222198194Sweongyo#define URTW_8187B_AC_BK 0x00fc /* 4 byte for 8187B */ 223192873Sweongyo#define URTW_ADDR_MAGIC2 0x00fe /* 2 byte */ 224192873Sweongyo#define URTW_ADDR_MAGIC3 0x00ff /* 1 byte */ 225192873Sweongyo 226192873Sweongyo/* for 8225 */ 227192873Sweongyo#define URTW_8225_ADDR_0_MAGIC 0x0 228192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC1 (0x1b7) 229192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC2 (0x0b7) 230192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC3 (0x127) 231192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC4 (0x027) 232192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC5 (0x22f) 233192873Sweongyo#define URTW_8225_ADDR_0_DATA_MAGIC6 (0x2bf) 234192873Sweongyo#define URTW_8225_ADDR_1_MAGIC 0x1 235192873Sweongyo#define URTW_8225_ADDR_2_MAGIC 0x2 236192873Sweongyo#define URTW_8225_ADDR_2_DATA_MAGIC1 (0xc4d) 237192873Sweongyo#define URTW_8225_ADDR_2_DATA_MAGIC2 (0x44d) 238192873Sweongyo#define URTW_8225_ADDR_3_MAGIC 0x3 239192873Sweongyo#define URTW_8225_ADDR_3_DATA_MAGIC1 (0x2) 240192873Sweongyo#define URTW_8225_ADDR_5_MAGIC 0x5 241192873Sweongyo#define URTW_8225_ADDR_5_DATA_MAGIC1 (0x4) 242192873Sweongyo#define URTW_8225_ADDR_6_MAGIC 0x6 243192873Sweongyo#define URTW_8225_ADDR_6_DATA_MAGIC1 (0xe6) 244192873Sweongyo#define URTW_8225_ADDR_6_DATA_MAGIC2 (0x80) 245192873Sweongyo#define URTW_8225_ADDR_7_MAGIC 0x7 246192873Sweongyo#define URTW_8225_ADDR_8_MAGIC 0x8 247192873Sweongyo#define URTW_8225_ADDR_8_DATA_MAGIC1 (0x588) 248192873Sweongyo#define URTW_8225_ADDR_9_MAGIC 0x9 249192873Sweongyo#define URTW_8225_ADDR_9_DATA_MAGIC1 (0x700) 250192873Sweongyo#define URTW_8225_ADDR_C_MAGIC 0xc 251192873Sweongyo#define URTW_8225_ADDR_C_DATA_MAGIC1 (0x850) 252192873Sweongyo#define URTW_8225_ADDR_C_DATA_MAGIC2 (0x050) 253192873Sweongyo 254192873Sweongyo/* for EEPROM */ 255198194Sweongyo#define URTW_EPROM_CHANPLAN 0x03 256300753Savos#define URTW_EPROM_CHANPLAN_BY_HW (0x80) 257192873Sweongyo#define URTW_EPROM_TXPW_BASE 0x05 258192873Sweongyo#define URTW_EPROM_RFCHIPID 0x06 259192873Sweongyo#define URTW_EPROM_RFCHIPID_RTL8225U (5) 260192873Sweongyo#define URTW_EPROM_RFCHIPID_RTL8225Z2 (6) 261192873Sweongyo#define URTW_EPROM_MACADDR 0x07 262192873Sweongyo#define URTW_EPROM_TXPW0 0x16 263192873Sweongyo#define URTW_EPROM_TXPW2 0x1b 264192873Sweongyo#define URTW_EPROM_TXPW1 0x3d 265192873Sweongyo#define URTW_EPROM_SWREV 0x3f 266192873Sweongyo#define URTW_EPROM_CID_MASK (0xff) 267192873Sweongyo#define URTW_EPROM_CID_RSVD0 (0x00) 268192873Sweongyo#define URTW_EPROM_CID_RSVD1 (0xff) 269192873Sweongyo#define URTW_EPROM_CID_ALPHA0 (0x01) 270192873Sweongyo#define URTW_EPROM_CID_SERCOMM_PS (0x02) 271192873Sweongyo#define URTW_EPROM_CID_HW_LED (0x03) 272192873Sweongyo 273192873Sweongyo/* LED */ 274192873Sweongyo#define URTW_CID_DEFAULT 0 275192873Sweongyo#define URTW_CID_8187_ALPHA0 1 276192873Sweongyo#define URTW_CID_8187_SERCOMM_PS 2 277192873Sweongyo#define URTW_CID_8187_HW_LED 3 278192873Sweongyo#define URTW_SW_LED_MODE0 0 279192873Sweongyo#define URTW_SW_LED_MODE1 1 280192873Sweongyo#define URTW_SW_LED_MODE2 2 281192873Sweongyo#define URTW_SW_LED_MODE3 3 282192873Sweongyo#define URTW_HW_LED 4 283192873Sweongyo#define URTW_LED_CTL_POWER_ON 0 284192873Sweongyo#define URTW_LED_CTL_LINK 2 285192873Sweongyo#define URTW_LED_CTL_TX 4 286192873Sweongyo#define URTW_LED_PIN_GPIO0 0 287192873Sweongyo#define URTW_LED_PIN_LED0 1 288192873Sweongyo#define URTW_LED_PIN_LED1 2 289192873Sweongyo#define URTW_LED_UNKNOWN 0 290192873Sweongyo#define URTW_LED_ON 1 291192873Sweongyo#define URTW_LED_OFF 2 292192873Sweongyo#define URTW_LED_BLINK_NORMAL 3 293192873Sweongyo#define URTW_LED_BLINK_SLOWLY 4 294192873Sweongyo#define URTW_LED_POWER_ON_BLINK 5 295192873Sweongyo#define URTW_LED_SCAN_BLINK 6 296192873Sweongyo#define URTW_LED_NO_LINK_BLINK 7 297192873Sweongyo#define URTW_LED_BLINK_CM3 8 298192873Sweongyo 299192873Sweongyo/* for extra area */ 300192873Sweongyo#define URTW_EPROM_DISABLE 0 301192873Sweongyo#define URTW_EPROM_ENABLE 1 302192873Sweongyo#define URTW_EPROM_DELAY 10 303192873Sweongyo#define URTW_8187_GETREGS_REQ 5 304192873Sweongyo#define URTW_8187_SETREGS_REQ 5 305192873Sweongyo#define URTW_8225_RF_MAX_SENS 6 306192873Sweongyo#define URTW_8225_RF_DEF_SENS 4 307192873Sweongyo#define URTW_DEFAULT_RTS_RETRY 7 308192873Sweongyo#define URTW_DEFAULT_TX_RETRY 7 309192873Sweongyo#define URTW_DEFAULT_RTS_THRESHOLD 2342U 310192873Sweongyo 311198194Sweongyo#define URTW_ASIFS_TIME 10 312198194Sweongyo#define URTW_ACKCTS_LEN 14 /* len for ACK and CTS */ 313198194Sweongyo 314192873Sweongyostruct urtw_8187b_rxhdr { 315198194Sweongyo uint32_t flag; 316198194Sweongyo#define URTW_RX_FLAG_LEN /* 0 ~ 11 bits */ 317198194Sweongyo#define URTW_RX_FLAG_ICV_ERR (1 << 12) 318198194Sweongyo#define URTW_RX_FLAG_CRC32_ERR (1 << 13) 319198194Sweongyo#define URTW_RX_FLAG_PM (1 << 14) 320198194Sweongyo#define URTW_RX_FLAG_RX_ERR (1 << 15) 321198194Sweongyo#define URTW_RX_FLAG_BCAST (1 << 16) 322198194Sweongyo#define URTW_RX_FLAG_PAM (1 << 17) 323198194Sweongyo#define URTW_RX_FLAG_MCAST (1 << 18) 324198194Sweongyo#define URTW_RX_FLAG_QOS (1 << 19) /* only for RTL8187B */ 325198194Sweongyo#define URTW_RX_FLAG_RXRATE /* 20 ~ 23 bits */ 326198194Sweongyo#define URTW_RX_FLAG_RXRATE_SHIFT 20 327198194Sweongyo#define URTW_RX_FLAG_TRSW (1 << 24) /* only for RTL8187B */ 328198194Sweongyo#define URTW_RX_FLAG_SPLCP (1 << 25) 329198194Sweongyo#define URTW_RX_FLAG_FOF (1 << 26) 330198194Sweongyo#define URTW_RX_FLAG_DMA_FAIL (1 << 27) 331198194Sweongyo#define URTW_RX_FLAG_LAST (1 << 28) 332198194Sweongyo#define URTW_RX_FLAG_FIRST (1 << 29) 333198194Sweongyo#define URTW_RX_FLAG_EOR (1 << 30) 334258780Seadler#define URTW_RX_FLAG_OWN (1U << 31) 335192873Sweongyo uint64_t mactime; 336198194Sweongyo uint8_t noise; 337192873Sweongyo uint8_t rssi; 338198194Sweongyo#define URTW_RX_RSSI /* 0 ~ 6 bits */ 339198194Sweongyo#define URTW_RX_RSSI_MASK 0x3f 340198194Sweongyo#define URTW_RX_ANTENNA (1 << 7) 341192873Sweongyo uint8_t agc; 342198194Sweongyo uint8_t flag2; 343198194Sweongyo#define URTW_RX_FLAG2_DECRYPTED (1 << 0) 344198194Sweongyo#define URTW_RX_FLAG2_WAKUP (1 << 1) 345198194Sweongyo#define URTW_RX_FLAG2_SHIFT (1 << 2) 346198194Sweongyo#define URTW_RX_FLAG2_RSVD0 /* 3 ~ 7 bits */ 347198194Sweongyo uint16_t flag3; 348198194Sweongyo#define URTW_RX_FLAG3_NUMMCSI /* 0 ~ 3 bits */ 349198194Sweongyo#define URTW_RX_FLAG3_SNR_L2E /* 4 ~ 9 bits */ 350198194Sweongyo#define URTW_RX_FLAG3_CFO_BIAS /* 10 ~ 15 bits */ 351192873Sweongyo int8_t pwdb; 352192873Sweongyo uint8_t fot; 353192873Sweongyo} __packed; 354192873Sweongyo 355192873Sweongyostruct urtw_8187b_txhdr { 356198194Sweongyo uint32_t flag; 357198194Sweongyo#define URTW_TX_FLAG_PKTLEN /* 0 ~ 11 bits */ 358198194Sweongyo#define URTW_TX_FLAG_RSVD0 /* 12 ~ 14 bits */ 359198194Sweongyo#define URTW_TX_FLAG_NO_ENC (1 << 15) 360198194Sweongyo#define URTW_TX_FLAG_SPLCP (1 << 16) 361198194Sweongyo#define URTW_TX_FLAG_MOREFRAG (1 << 17) 362198194Sweongyo#define URTW_TX_FLAG_CTS (1 << 18) 363198194Sweongyo#define URTW_TX_FLAG_RTSRATE /* 19 ~ 22 bits */ 364198194Sweongyo#define URTW_TX_FLAG_RTSRATE_SHIFT 19 365198194Sweongyo#define URTW_TX_FLAG_RTS (1 << 23) 366198194Sweongyo#define URTW_TX_FLAG_TXRATE /* 24 ~ 27 bits */ 367198194Sweongyo#define URTW_TX_FLAG_TXRATE_SHIFT 24 368198194Sweongyo#define URTW_TX_FLAG_LAST (1 << 28) 369198194Sweongyo#define URTW_TX_FLAG_FIRST (1 << 29) 370198194Sweongyo#define URTW_TX_FLAG_DMA (1 << 30) 371258780Seadler#define URTW_TX_FLAG_OWN (1U << 31) 372198194Sweongyo uint16_t rtsdur; 373192873Sweongyo uint16_t len; 374198194Sweongyo#define URTW_TX_LEN /* 0 ~ 14 bits */ 375198194Sweongyo#define URTW_TX_LEN_EXT (1 << 15) 376198194Sweongyo uint32_t bufaddr; 377198194Sweongyo uint16_t flag1; 378198194Sweongyo#define URTW_TX_FLAG1_RXLEN /* 0 ~ 11 bits */ 379198194Sweongyo#define URTW_TX_FLAG1_RSVD0 /* 12 ~ 14 bits */ 380198194Sweongyo#define URTW_TX_FLAG1_MICCAL (1 << 15) 381198194Sweongyo uint16_t txdur; 382198194Sweongyo uint32_t nextdescaddr; 383198194Sweongyo uint8_t rtsagc; 384198194Sweongyo uint8_t retry; 385198194Sweongyo uint16_t flag2; 386198194Sweongyo#define URTW_TX_FLAG2_RTDB (1 << 0) 387198194Sweongyo#define URTW_TX_FLAG2_NOACM (1 << 1) 388198194Sweongyo#define URTW_TX_FLAG2_PIFS (1 << 2) 389198194Sweongyo#define URTW_TX_FLAG2_RSVD0 /* 3 ~ 6 bits */ 390198194Sweongyo#define URTW_TX_FLAG2_RTSRATEFALLBACK /* 7 ~ 10 bits */ 391198194Sweongyo#define URTW_TX_FLAG2_RATEFALLBACK /* 11 ~ 15 bits */ 392198194Sweongyo uint16_t delaybound; 393198194Sweongyo uint16_t flag3; 394198194Sweongyo#define URTW_TX_FLAG3_RSVD0 /* 0 ~ 3 bits */ 395198194Sweongyo#define URTW_TX_FLAG3_AGC /* 4 ~ 11 bits */ 396198194Sweongyo#define URTW_TX_FLAG3_ANTENNA (1 << 12) 397198194Sweongyo#define URTW_TX_FLAG3_SPC /* 13 ~ 14 bits */ 398198194Sweongyo#define URTW_TX_FLAG3_RSVD1 (1 << 15) 399198194Sweongyo uint32_t flag4; 400198194Sweongyo#define URTW_TX_FLAG4_LENADJUST /* 0 ~ 1 bits */ 401198194Sweongyo#define URTW_TX_FLAG4_RSVD0 (1 << 2) 402198194Sweongyo#define URTW_TX_FLAG4_TPCDESEN (1 << 3) 403198194Sweongyo#define URTW_TX_FLAG4_TPCPOLARITY /* 4 ~ 5 bits */ 404198194Sweongyo#define URTW_TX_FLAG4_TPCEN (1 << 6) 405198194Sweongyo#define URTW_TX_FLAG4_PTEN (1 << 7) 406198194Sweongyo#define URTW_TX_FLAG4_BCKEY /* 8 ~ 13 bits */ 407198194Sweongyo#define URTW_TX_FLAG4_ENBCKEY (1 << 14) 408198194Sweongyo#define URTW_TX_FLAG4_ENPMPD (1 << 15) 409198194Sweongyo#define URTW_TX_FLAG4_FRAGQSZ /* 16 ~ 31 bits */ 410198194Sweongyo} __packed; 411198194Sweongyo 412198194Sweongyostruct urtw_8187l_rxhdr { 413198194Sweongyo uint32_t flag; 414198194Sweongyo uint8_t noise; 415198194Sweongyo uint8_t rssi; 416198194Sweongyo#define URTW_RX_8187L_RSSI /* 0 ~ 6 bits */ 417198194Sweongyo#define URTW_RX_8187L_RSSI_MASK 0x3f 418198194Sweongyo#define URTW_RX_8187L_ANTENNA (1 << 7) 419198194Sweongyo uint8_t agc; 420198194Sweongyo uint8_t flag2; 421198194Sweongyo#define URTW_RX_8187L_DECRYPTED (1 << 0) 422198194Sweongyo#define URTW_RX_8187L_WAKEUP (1 << 1) 423198194Sweongyo#define URTW_RX_8187L_SHIFT (1 << 2) 424198194Sweongyo#define URTW_RX_8187L_RSVD0 /* 3 ~ 7 bits */ 425198194Sweongyo uint64_t mactime; 426198194Sweongyo} __packed; 427198194Sweongyo 428198194Sweongyostruct urtw_8187l_txhdr { 429198194Sweongyo uint32_t flag; 430198194Sweongyo uint16_t rtsdur; 431198194Sweongyo uint16_t len; 432192873Sweongyo uint32_t retry; 433192873Sweongyo} __packed; 434