if_rsureg.h revision 287894
1/*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17 * $FreeBSD: head/sys/dev/usb/wlan/if_rsureg.h 287894 2015-09-17 03:08:02Z adrian $ 18 */ 19 20/* USB Requests. */ 21#define R92S_REQ_REGS 0x05 22 23/* 24 * MAC registers. 25 */ 26#define R92S_SYSCFG 0x0000 27#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 28#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 29#define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 30#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 31#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 32#define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 33#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 34#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 35#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 36#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 37#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 38#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 39#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 40#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 41#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 42#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 43 44#define R92S_CMDCTRL 0x0040 45#define R92S_CR (R92S_CMDCTRL + 0x000) 46#define R92S_TCR (R92S_CMDCTRL + 0x004) 47#define R92S_RCR (R92S_CMDCTRL + 0x008) 48 49#define R92S_MACIDSETTING 0x0050 50#define R92S_MACID (R92S_MACIDSETTING + 0x000) 51 52#define R92S_GP 0x01e0 53#define R92S_GPIO_CTRL (R92S_GP + 0x00c) 54#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 55#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 56 57#define R92S_IOCMD_CTRL 0x0370 58#define R92S_IOCMD_DATA 0x0374 59 60#define R92S_USB_HRPWM 0xfe58 61 62/* Bits for R92S_SYS_FUNC_EN. */ 63#define R92S_FEN_CPUEN 0x0400 64 65/* Bits for R92S_PMC_FSM. */ 66#define R92S_PMC_FSM_CUT_M 0x000f8000 67#define R92S_PMC_FSM_CUT_S 15 68 69/* Bits for R92S_SYS_CLKR. */ 70#define R92S_SYS_CLKSEL 0x0001 71#define R92S_SYS_PS_CLKSEL 0x0002 72#define R92S_SYS_CPU_CLKSEL 0x0004 73#define R92S_MAC_CLK_EN 0x0800 74#define R92S_SYS_CLK_EN 0x1000 75#define R92S_SWHW_SEL 0x4000 76#define R92S_FWHW_SEL 0x8000 77 78/* Bits for R92S_EE_9346CR. */ 79#define R92S_9356SEL 0x10 80#define R92S_EEPROM_EN 0x20 81 82/* Bits for R92S_AFE_MISC. */ 83#define R92S_AFE_MISC_BGEN 0x01 84#define R92S_AFE_MISC_MBEN 0x02 85#define R92S_AFE_MISC_I32_EN 0x08 86 87/* Bits for R92S_SPS1_CTRL. */ 88#define R92S_SPS1_LDEN 0x01 89#define R92S_SPS1_SWEN 0x02 90 91/* Bits for R92S_LDOA15_CTRL. */ 92#define R92S_LDA15_EN 0x01 93 94/* Bits for R92S_LDOV12D_CTRL. */ 95#define R92S_LDV12_EN 0x01 96 97/* Bits for R92C_EFUSE_CTRL. */ 98#define R92S_EFUSE_CTRL_DATA_M 0x000000ff 99#define R92S_EFUSE_CTRL_DATA_S 0 100#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 101#define R92S_EFUSE_CTRL_ADDR_S 8 102#define R92S_EFUSE_CTRL_VALID 0x80000000 103 104/* Bits for R92S_CR. */ 105#define R92S_CR_TXDMA_EN 0x10 106 107/* Bits for R92S_TCR. */ 108#define R92S_TCR_IMEM_CODE_DONE 0x01 109#define R92S_TCR_IMEM_CHK_RPT 0x02 110#define R92S_TCR_EMEM_CODE_DONE 0x04 111#define R92S_TCR_EMEM_CHK_RPT 0x08 112#define R92S_TCR_DMEM_CODE_DONE 0x10 113#define R92S_TCR_IMEM_RDY 0x20 114#define R92S_TCR_FWRDY 0x80 115 116/* Bits for R92S_GPIO_IO_SEL. */ 117#define R92S_GPIO_WPS 0x10 118 119/* Bits for R92S_MAC_PINMUX_CTRL. */ 120#define R92S_GPIOSEL_GPIO_M 0x03 121#define R92S_GPIOSEL_GPIO_S 0 122#define R92S_GPIOSEL_GPIO_JTAG 0 123#define R92S_GPIOSEL_GPIO_PHYDBG 1 124#define R92S_GPIOSEL_GPIO_BT 2 125#define R92S_GPIOSEL_GPIO_WLANDBG 3 126#define R92S_GPIOMUX_EN 0x08 127 128/* Bits for R92S_IOCMD_CTRL. */ 129#define R92S_IOCMD_CLASS_M 0xff000000 130#define R92S_IOCMD_CLASS_S 24 131#define R92S_IOCMD_CLASS_BB_RF 0xf0 132#define R92S_IOCMD_VALUE_M 0x00ffff00 133#define R92S_IOCMD_VALUE_S 8 134#define R92S_IOCMD_INDEX_M 0x000000ff 135#define R92S_IOCMD_INDEX_S 0 136#define R92S_IOCMD_INDEX_BB_READ 0 137#define R92S_IOCMD_INDEX_BB_WRITE 1 138#define R92S_IOCMD_INDEX_RF_READ 2 139#define R92S_IOCMD_INDEX_RF_WRITE 3 140 141/* Bits for R92S_USB_HRPWM. */ 142#define R92S_USB_HRPWM_PS_ALL_ON 0x04 143#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 144 145/* 146 * Macros to access subfields in registers. 147 */ 148/* Mask and Shift (getter). */ 149#define MS(val, field) \ 150 (((val) & field##_M) >> field##_S) 151 152/* Shift and Mask (setter). */ 153#define SM(field, val) \ 154 (((val) << field##_S) & field##_M) 155 156/* Rewrite. */ 157#define RW(var, field, val) \ 158 (((var) & ~field##_M) | SM(field, val)) 159 160/* 161 * Firmware image header. 162 */ 163struct r92s_fw_priv { 164 /* QWORD0 */ 165 uint16_t signature; 166 uint8_t hci_sel; 167#define R92S_HCI_SEL_PCIE 0x01 168#define R92S_HCI_SEL_USB 0x02 169#define R92S_HCI_SEL_SDIO 0x04 170#define R92S_HCI_SEL_8172 0x10 171#define R92S_HCI_SEL_AP 0x80 172 173 uint8_t chip_version; 174 uint16_t custid; 175 uint8_t rf_config; 176 uint8_t nendpoints; 177 /* QWORD1 */ 178 uint32_t regulatory; 179 uint8_t rfintfs; 180 uint8_t def_nettype; 181 uint8_t turbo_mode; 182 uint8_t lowpower_mode; 183 /* QWORD2 */ 184 uint8_t lbk_mode; 185 uint8_t mp_mode; 186 uint8_t vcs_type; 187#define R92S_VCS_TYPE_DISABLE 0 188#define R92S_VCS_TYPE_ENABLE 1 189#define R92S_VCS_TYPE_AUTO 2 190 191 uint8_t vcs_mode; 192#define R92S_VCS_MODE_NONE 0 193#define R92S_VCS_MODE_RTS_CTS 1 194#define R92S_VCS_MODE_CTS2SELF 2 195 196 uint32_t reserved1; 197 /* QWORD3 */ 198 uint8_t qos_en; 199 uint8_t bw40_en; 200 uint8_t amsdu2ampdu_en; 201 uint8_t ampdu_en; 202 uint8_t rc_offload; 203 uint8_t agg_offload; 204 uint16_t reserved2; 205 /* QWORD4 */ 206 uint8_t beacon_offload; 207 uint8_t mlme_offload; 208 uint8_t hwpc_offload; 209 uint8_t tcpcsum_offload; 210 uint8_t tcp_offload; 211 uint8_t ps_offload; 212 uint8_t wwlan_offload; 213 uint8_t reserved3; 214 /* QWORD5 */ 215 uint16_t tcp_tx_len; 216 uint16_t tcp_rx_len; 217 uint32_t reserved4; 218} __packed; 219 220struct r92s_fw_hdr { 221 uint16_t signature; 222 uint16_t version; 223 uint32_t dmemsz; 224 uint32_t imemsz; 225 uint32_t sramsz; 226 uint32_t privsz; 227 uint16_t efuse_addr; 228 uint16_t h2c_resp_addr; 229 uint32_t svnrev; 230 uint8_t month; 231 uint8_t day; 232 uint8_t hour; 233 uint8_t minute; 234 struct r92s_fw_priv priv; 235} __packed; 236 237/* Structure for FW commands and FW events notifications. */ 238struct r92s_fw_cmd_hdr { 239 uint16_t len; 240 uint8_t code; 241 uint8_t seq; 242#define R92S_FW_CMD_MORE 0x80 243 244 uint32_t reserved; 245} __packed; 246 247/* FW commands codes. */ 248#define R92S_CMD_READ_MACREG 0 249#define R92S_CMD_WRITE_MACREG 1 250#define R92S_CMD_READ_BBREG 2 251#define R92S_CMD_WRITE_BBREG 3 252#define R92S_CMD_READ_RFREG 4 253#define R92S_CMD_WRITE_RFREG 5 254#define R92S_CMD_READ_EEPROM 6 255#define R92S_CMD_WRITE_EEPROM 7 256#define R92S_CMD_READ_EFUSE 8 257#define R92S_CMD_WRITE_EFUSE 9 258#define R92S_CMD_READ_CAM 10 259#define R92S_CMD_WRITE_CAM 11 260#define R92S_CMD_SET_BCNITV 12 261#define R92S_CMD_SET_MBIDCFG 13 262#define R92S_CMD_JOIN_BSS 14 263#define R92S_CMD_DISCONNECT 15 264#define R92S_CMD_CREATE_BSS 16 265#define R92S_CMD_SET_OPMODE 17 266#define R92S_CMD_SITE_SURVEY 18 267#define R92S_CMD_SET_AUTH 19 268#define R92S_CMD_SET_KEY 20 269#define R92S_CMD_SET_STA_KEY 21 270#define R92S_CMD_SET_ASSOC_STA 22 271#define R92S_CMD_DEL_ASSOC_STA 23 272#define R92S_CMD_SET_STAPWRSTATE 24 273#define R92S_CMD_SET_BASIC_RATE 25 274#define R92S_CMD_GET_BASIC_RATE 26 275#define R92S_CMD_SET_DATA_RATE 27 276#define R92S_CMD_GET_DATA_RATE 28 277#define R92S_CMD_SET_PHY_INFO 29 278#define R92S_CMD_GET_PHY_INFO 30 279#define R92S_CMD_SET_PHY 31 280#define R92S_CMD_GET_PHY 32 281#define R92S_CMD_READ_RSSI 33 282#define R92S_CMD_READ_GAIN 34 283#define R92S_CMD_SET_ATIM 35 284#define R92S_CMD_SET_PWR_MODE 36 285#define R92S_CMD_JOIN_BSS_RPT 37 286#define R92S_CMD_SET_RA_TABLE 38 287#define R92S_CMD_GET_RA_TABLE 39 288#define R92S_CMD_GET_CCX_REPORT 40 289#define R92S_CMD_GET_DTM_REPORT 41 290#define R92S_CMD_GET_TXRATE_STATS 42 291#define R92S_CMD_SET_USB_SUSPEND 43 292#define R92S_CMD_SET_H2C_LBK 44 293#define R92S_CMD_ADDBA_REQ 45 294#define R92S_CMD_SET_CHANNEL 46 295#define R92S_CMD_SET_TXPOWER 47 296#define R92S_CMD_SWITCH_ANTENNA 48 297#define R92S_CMD_SET_CRYSTAL_CAL 49 298#define R92S_CMD_SET_SINGLE_CARRIER_TX 50 299#define R92S_CMD_SET_SINGLE_TONE_TX 51 300#define R92S_CMD_SET_CARRIER_SUPPR_TX 52 301#define R92S_CMD_SET_CONTINUOUS_TX 53 302#define R92S_CMD_SWITCH_BANDWIDTH 54 303#define R92S_CMD_TX_BEACON 55 304#define R92S_CMD_SET_POWER_TRACKING 56 305#define R92S_CMD_AMSDU_TO_AMPDU 57 306#define R92S_CMD_SET_MAC_ADDRESS 58 307#define R92S_CMD_GET_H2C_LBK 59 308#define R92S_CMD_SET_PBREQ_IE 60 309#define R92S_CMD_SET_ASSOCREQ_IE 61 310#define R92S_CMD_SET_PBRESP_IE 62 311#define R92S_CMD_SET_ASSOCRESP_IE 63 312#define R92S_CMD_GET_CURDATARATE 64 313#define R92S_CMD_GET_TXRETRY_CNT 65 314#define R92S_CMD_GET_RXRETRY_CNT 66 315#define R92S_CMD_GET_BCNOK_CNT 67 316#define R92S_CMD_GET_BCNERR_CNT 68 317#define R92S_CMD_GET_CURTXPWR_LEVEL 69 318#define R92S_CMD_SET_DIG 70 319#define R92S_CMD_SET_RA 71 320#define R92S_CMD_SET_PT 72 321#define R92S_CMD_READ_TSSI 73 322 323/* FW events notifications codes. */ 324#define R92S_EVT_READ_MACREG 0 325#define R92S_EVT_READ_BBREG 1 326#define R92S_EVT_READ_RFREG 2 327#define R92S_EVT_READ_EEPROM 3 328#define R92S_EVT_READ_EFUSE 4 329#define R92S_EVT_READ_CAM 5 330#define R92S_EVT_GET_BASICRATE 6 331#define R92S_EVT_GET_DATARATE 7 332#define R92S_EVT_SURVEY 8 333#define R92S_EVT_SURVEY_DONE 9 334#define R92S_EVT_JOIN_BSS 10 335#define R92S_EVT_ADD_STA 11 336#define R92S_EVT_DEL_STA 12 337#define R92S_EVT_ATIM_DONE 13 338#define R92S_EVT_TX_REPORT 14 339#define R92S_EVT_CCX_REPORT 15 340#define R92S_EVT_DTM_REPORT 16 341#define R92S_EVT_TXRATE_STATS 17 342#define R92S_EVT_C2H_LBK 18 343#define R92S_EVT_FWDBG 19 344#define R92S_EVT_C2H_FEEDBACK 20 345#define R92S_EVT_ADDBA 21 346#define R92S_EVT_C2H_BCN 22 347#define R92S_EVT_PWR_STATE 23 348#define R92S_EVT_WPS_PBC 24 349#define R92S_EVT_ADDBA_REQ_REPORT 25 350 351/* Structure for R92S_CMD_SITE_SURVEY. */ 352struct r92s_fw_cmd_sitesurvey { 353 uint32_t active; 354 uint32_t limit; 355 uint32_t ssidlen; 356 uint8_t ssid[32 + 1]; 357} __packed; 358 359/* Structure for R92S_CMD_SET_AUTH. */ 360struct r92s_fw_cmd_auth { 361 uint8_t mode; 362#define R92S_AUTHMODE_OPEN 0 363#define R92S_AUTHMODE_SHARED 1 364#define R92S_AUTHMODE_WPA 2 365 366 uint8_t dot1x; 367} __packed; 368 369/* Structure for R92S_CMD_SET_KEY. */ 370struct r92s_fw_cmd_set_key { 371 uint8_t algo; 372#define R92S_KEY_ALGO_NONE 0 373#define R92S_KEY_ALGO_WEP40 1 374#define R92S_KEY_ALGO_TKIP 2 375#define R92S_KEY_ALGO_TKIP_MMIC 3 376#define R92S_KEY_ALGO_AES 4 377#define R92S_KEY_ALGO_WEP104 5 378 379 uint8_t id; 380 uint8_t grpkey; 381 uint8_t key[16]; 382} __packed; 383 384/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 385/* NDIS_802_11_SSID. */ 386struct ndis_802_11_ssid { 387 uint32_t ssidlen; 388 uint8_t ssid[32]; 389} __packed; 390 391/* NDIS_802_11_CONFIGURATION_FH. */ 392struct ndis_802_11_configuration_fh { 393 uint32_t len; 394 uint32_t hoppattern; 395 uint32_t hopset; 396 uint32_t dwelltime; 397} __packed; 398 399/* NDIS_802_11_CONFIGURATION. */ 400struct ndis_802_11_configuration { 401 uint32_t len; 402 uint32_t bintval; 403 uint32_t atim; 404 uint32_t dsconfig; 405 struct ndis_802_11_configuration_fh fhconfig; 406} __packed; 407 408/* NDIS_WLAN_BSSID_EX. */ 409struct ndis_wlan_bssid_ex { 410 uint32_t len; 411 uint8_t macaddr[IEEE80211_ADDR_LEN]; 412 uint8_t reserved[2]; 413 struct ndis_802_11_ssid ssid; 414 uint32_t privacy; 415 int32_t rssi; 416 uint32_t networktype; 417#define NDIS802_11FH 0 418#define NDIS802_11DS 1 419#define NDIS802_11OFDM5 2 420#define NDIS802_11OFDM24 3 421#define NDIS802_11AUTOMODE 4 422 423 struct ndis_802_11_configuration config; 424 uint32_t inframode; 425#define NDIS802_11IBSS 0 426#define NDIS802_11INFRASTRUCTURE 1 427#define NDIS802_11AUTOUNKNOWN 2 428#define NDIS802_11MONITOR 3 429#define NDIS802_11APMODE 4 430 431 uint8_t supprates[16]; 432 uint32_t ieslen; 433 /* Followed by ``ieslen'' bytes. */ 434} __packed; 435 436/* NDIS_802_11_FIXED_IEs. */ 437struct ndis_802_11_fixed_ies { 438 uint8_t tstamp[8]; 439 uint16_t bintval; 440 uint16_t capabilities; 441} __packed; 442 443/* Structure for R92S_CMD_SET_PWR_MODE. */ 444struct r92s_set_pwr_mode { 445 uint8_t mode; 446#define R92S_PS_MODE_ACTIVE 0 447#define R92S_PS_MODE_MIN 1 448#define R92S_PS_MODE_MAX 2 449#define R92S_PS_MODE_DTIM 3 450#define R92S_PS_MODE_VOIP 4 451#define R92S_PS_MODE_UAPSD_WMM 5 452#define R92S_PS_MODE_UAPSD 6 453#define R92S_PS_MODE_IBSS 7 454#define R92S_PS_MODE_WWLAN 8 455#define R92S_PS_MODE_RADIOOFF 9 456#define R92S_PS_MODE_DISABLE 10 457 458 uint8_t low_traffic_en; 459 uint8_t lpnav_en; 460 uint8_t rf_low_snr_en; 461 uint8_t dps_en; 462 uint8_t bcn_rx_en; 463 uint8_t bcn_pass_cnt; 464 uint8_t bcn_to; 465 uint16_t bcn_itv; 466 uint8_t app_itv; 467 uint8_t awake_bcn_itv; 468 uint8_t smart_ps; 469 uint8_t bcn_pass_time; 470} __packed; 471 472/* Structure for event R92S_EVENT_JOIN_BSS. */ 473struct r92s_event_join_bss { 474 uint32_t next; 475 uint32_t prev; 476 uint32_t networktype; 477 uint32_t fixed; 478 uint32_t lastscanned; 479 uint32_t associd; 480 uint32_t join_res; 481 struct ndis_wlan_bssid_ex bss; 482} __packed; 483 484#define R92S_MACID_BSS 5 485 486/* Rx MAC descriptor. */ 487struct r92s_rx_stat { 488 uint32_t rxdw0; 489#define R92S_RXDW0_PKTLEN_M 0x00003fff 490#define R92S_RXDW0_PKTLEN_S 0 491#define R92S_RXDW0_CRCERR 0x00004000 492#define R92S_RXDW0_INFOSZ_M 0x000f0000 493#define R92S_RXDW0_INFOSZ_S 16 494#define R92S_RXDW0_QOS 0x00800000 495#define R92S_RXDW0_SHIFT_M 0x03000000 496#define R92S_RXDW0_SHIFT_S 24 497#define R92S_RXDW0_DECRYPTED 0x08000000 498 499 uint32_t rxdw1; 500#define R92S_RXDW1_MOREFRAG 0x08000000 501 502 uint32_t rxdw2; 503#define R92S_RXDW2_FRAG_M 0x0000f000 504#define R92S_RXDW2_FRAG_S 12 505#define R92S_RXDW2_PKTCNT_M 0x00ff0000 506#define R92S_RXDW2_PKTCNT_S 16 507 508 uint32_t rxdw3; 509#define R92S_RXDW3_RATE_M 0x0000003f 510#define R92S_RXDW3_RATE_S 0 511#define R92S_RXDW3_TCPCHKRPT 0x00000800 512#define R92S_RXDW3_IPCHKRPT 0x00001000 513#define R92S_RXDW3_TCPCHKVALID 0x00002000 514#define R92S_RXDW3_HTC 0x00004000 515 516 uint32_t rxdw4; 517 uint32_t rxdw5; 518} __packed __aligned(4); 519 520/* Rx PHY descriptor. */ 521struct r92s_rx_phystat { 522 uint32_t phydw0; 523 uint32_t phydw1; 524 uint32_t phydw2; 525 uint32_t phydw3; 526 uint32_t phydw4; 527 uint32_t phydw5; 528 uint32_t phydw6; 529 uint32_t phydw7; 530} __packed __aligned(4); 531 532/* Rx PHY CCK descriptor. */ 533struct r92s_rx_cck { 534 uint8_t adc_pwdb[4]; 535 uint8_t sq_rpt; 536 uint8_t agc_rpt; 537} __packed; 538 539/* Tx MAC descriptor. */ 540struct r92s_tx_desc { 541 uint32_t txdw0; 542#define R92S_TXDW0_PKTLEN_M 0x0000ffff 543#define R92S_TXDW0_PKTLEN_S 0 544#define R92S_TXDW0_OFFSET_M 0x00ff0000 545#define R92S_TXDW0_OFFSET_S 16 546#define R92S_TXDW0_TYPE_M 0x03000000 547#define R92S_TXDW0_TYPE_S 24 548#define R92S_TXDW0_LSG 0x04000000 549#define R92S_TXDW0_FSG 0x08000000 550#define R92S_TXDW0_LINIP 0x10000000 551#define R92S_TXDW0_OWN 0x80000000 552 553 uint32_t txdw1; 554#define R92S_TXDW1_MACID_M 0x0000001f 555#define R92S_TXDW1_MACID_S 0 556#define R92S_TXDW1_MOREDATA 0x00000020 557#define R92S_TXDW1_MOREFRAG 0x00000040 558#define R92S_TXDW1_QSEL_M 0x00001f00 559#define R92S_TXDW1_QSEL_S 8 560#define R92S_TXDW1_QSEL_BE 0x03 561#define R92S_TXDW1_QSEL_H2C 0x1f 562#define R92S_TXDW1_NONQOS 0x00010000 563#define R92S_TXDW1_KEYIDX_M 0x00060000 564#define R92S_TXDW1_KEYIDX_S 17 565#define R92S_TXDW1_CIPHER_M 0x00c00000 566#define R92S_TXDW1_CIPHER_S 22 567#define R92S_TXDW1_CIPHER_WEP 1 568#define R92S_TXDW1_CIPHER_TKIP 2 569#define R92S_TXDW1_CIPHER_AES 3 570#define R92S_TXDW1_HWPC 0x80000000 571 572 uint32_t txdw2; 573#define R92S_TXDW2_BMCAST 0x00000080 574#define R92S_TXDW2_AGGEN 0x20000000 575#define R92S_TXDW2_BK 0x40000000 576 577 uint32_t txdw3; 578#define R92S_TXDW3_SEQ_M 0x0fff0000 579#define R92S_TXDW3_SEQ_S 16 580#define R92S_TXDW3_FRAG_M 0xf0000000 581#define R92S_TXDW3_FRAG_S 28 582 583 uint32_t txdw4; 584#define R92S_TXDW4_TXBW 0x00040000 585 586 uint32_t txdw5; 587#define R92S_TXDW5_DISFB 0x00008000 588 589 uint16_t ipchksum; 590 uint16_t tcpchksum; 591 592 uint16_t txbufsize; 593 uint16_t reserved1; 594} __packed __aligned(4); 595 596 597/* 598 * Driver definitions. 599 */ 600#define RSU_RX_LIST_COUNT 100 601#define RSU_TX_LIST_COUNT 32 602 603#define RSU_HOST_CMD_RING_COUNT 32 604 605#define RSU_RXBUFSZ (8 * 1024) 606#define RSU_TXBUFSZ \ 607 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 608 609#define RSU_TX_TIMEOUT 5000 /* ms */ 610#define RSU_CMD_TIMEOUT 2000 /* ms */ 611 612/* Queue ids (used by soft only). */ 613#define RSU_QID_BCN 0 614#define RSU_QID_MGT 1 615#define RSU_QID_BMC 2 616#define RSU_QID_VO 3 617#define RSU_QID_VI 4 618#define RSU_QID_BE 5 619#define RSU_QID_BK 6 620#define RSU_QID_RXOFF 7 621#define RSU_QID_H2C 8 622#define RSU_QID_C2H 9 623 624/* Map AC to queue id. */ 625static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 626 RSU_QID_BE, 627 RSU_QID_BK, 628 RSU_QID_VI, 629 RSU_QID_VO 630}; 631 632/* Pipe index to endpoint address mapping. */ 633static const uint8_t r92s_epaddr[] = 634 { 0x83, 0x04, 0x06, 0x0d, 635 0x05, 0x07, 636 0x89, 0x0a, 0x0b, 0x0c }; 637 638/* Queue id to pipe index mapping for 4 endpoints configurations. */ 639static const uint8_t rsu_qid2idx_4ep[] = 640 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 641 642/* Queue id to pipe index mapping for 6 endpoints configurations. */ 643static const uint8_t rsu_qid2idx_6ep[] = 644 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 645 646/* Queue id to pipe index mapping for 11 endpoints configurations. */ 647static const uint8_t rsu_qid2idx_11ep[] = 648 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 649 650struct rsu_rx_radiotap_header { 651 struct ieee80211_radiotap_header wr_ihdr; 652 uint8_t wr_flags; 653 uint8_t wr_rate; 654 uint16_t wr_chan_freq; 655 uint16_t wr_chan_flags; 656 uint8_t wr_dbm_antsignal; 657} __packed __aligned(8); 658 659#define RSU_RX_RADIOTAP_PRESENT \ 660 (1 << IEEE80211_RADIOTAP_FLAGS | \ 661 1 << IEEE80211_RADIOTAP_RATE | \ 662 1 << IEEE80211_RADIOTAP_CHANNEL | \ 663 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 664 665struct rsu_tx_radiotap_header { 666 struct ieee80211_radiotap_header wt_ihdr; 667 uint8_t wt_flags; 668 uint16_t wt_chan_freq; 669 uint16_t wt_chan_flags; 670} __packed __aligned(8); 671 672#define RSU_TX_RADIOTAP_PRESENT \ 673 (1 << IEEE80211_RADIOTAP_FLAGS | \ 674 1 << IEEE80211_RADIOTAP_CHANNEL) 675 676struct rsu_softc; 677 678struct rsu_host_cmd { 679 void (*cb)(struct rsu_softc *, void *); 680 uint8_t data[256]; 681}; 682 683struct rsu_cmd_newstate { 684 enum ieee80211_state state; 685 int arg; 686}; 687 688struct rsu_cmd_key { 689 struct ieee80211_key key; 690}; 691 692struct rsu_host_cmd_ring { 693 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; 694 int cur; 695 int next; 696 int queued; 697}; 698 699enum { 700 RSU_BULK_RX, 701 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 702 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 703 RSU_N_TRANSFER, 704}; 705 706struct rsu_data { 707 struct rsu_softc *sc; 708 uint8_t *buf; 709 uint16_t buflen; 710 struct mbuf *m; 711 struct ieee80211_node *ni; 712 STAILQ_ENTRY(rsu_data) next; 713}; 714 715struct rsu_vap { 716 struct ieee80211vap vap; 717 struct ieee80211_beacon_offsets bo; 718 719 int (*newstate)(struct ieee80211vap *, 720 enum ieee80211_state, int); 721}; 722#define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 723 724#define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 725#define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 726#define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 727 728struct rsu_softc { 729 struct ieee80211com sc_ic; 730 struct mbufq sc_snd; 731 device_t sc_dev; 732 struct usb_device *sc_udev; 733 int (*sc_newstate)(struct ieee80211com *, 734 enum ieee80211_state, int); 735 struct usbd_interface *sc_iface; 736 struct timeout_task calib_task; 737 const uint8_t *qid2idx; 738 struct mtx sc_mtx; 739 int sc_ht; 740 int sc_nendpoints; 741 742 u_int sc_running:1, 743 sc_calibrating:1, 744 sc_scan_pass:1; 745 u_int cut; 746 struct rsu_host_cmd_ring cmdq; 747 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 748 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 749 struct rsu_data *fwcmd_data; 750 uint8_t cmd_seq; 751 uint8_t rom[128]; 752 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 753 754 STAILQ_HEAD(, rsu_data) sc_rx_active; 755 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 756 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 757 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 758 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 759 760 union { 761 struct rsu_rx_radiotap_header th; 762 uint8_t pad[64]; 763 } sc_rxtapu; 764#define sc_rxtap sc_rxtapu.th 765 int sc_rxtap_len; 766 767 union { 768 struct rsu_tx_radiotap_header th; 769 uint8_t pad[64]; 770 } sc_txtapu; 771#define sc_txtap sc_txtapu.th 772 int sc_txtap_len; 773}; 774